JP2013055502A - Serial communication circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to perform skew adjustment with the use of the received symbols at the time of return from a low power consumption mode, and to perform a quick return to a normal communication state.SOLUTION: A serial communication circuit comprises: a physical layer receiving circuit which reproduces a clock from a serial reception signal of a plurality of coded lanes, reproduces a reception symbol for every lane, converts the reception symbols of the plurality of lanes decoded after byte align and SP conversion into the reception symbols synchronized with the same clock, and outputs the converted symbols; and an inter-lane skew adjustment circuit which adjusts a symbol skew among lanes relative to the reception symbols of the plurality of lanes. The serial communication circuit detects a prescribed detection reference symbol from the reception symbol for every lane, starts counting of a detection signal in response to the detection signal by a counter circuit, and adjusts an inter-lane symbol skew by delaying the reception symbols of the plurality of lanes output from the physical layer receiving circuit by a delay amount corresponding to a selection signal of a count value.

Description

  The present invention relates to a serial communication circuit applied to, for example, a high-speed serial communication circuit such as a PCI Express standard.

  For example, Patent Document 1 discloses a byte skew compensation method in a serial communication circuit compliant with the PCI Express standard and a physical layer receiver for this. The byte skew compensation method disclosed in Patent Document 1 determines whether or not received data is a training sequence. When the received data is a training sequence, a reference to a comma symbol is used using the training sequence. Setting alignment points for each of the lanes and, if the received data is not a training sequence, shifting the alignment points by adding or deleting skip symbols for each of the lanes. Therefore, it is possible to effectively compensate for the byte skew despite the addition or deletion of the skip symbol.

  Further, for example, in Patent Document 2, even when the number of symbols differs for each lane, reception that can perform skew adjustment between divided data strings corresponding to each lane by simple processing. An apparatus is disclosed. The receiving device disclosed in Patent Document 2 is an elastic device that generates a processed divided data sequence by performing a process of adjusting the number of symbols of the received divided data sequence to one or more corresponding to each of a plurality of lanes. A buffer and a skew adjustment circuit that adjusts a skew between the processed divided data strings, and the skew adjustment circuit is provided corresponding to each of the plurality of lanes and is a first symbol in the processed divided data string And determining the end of the symbol in each processed divided data sequence based on the determination result of the determination circuit, and the skew between the processed divided data sequences based on the timing at which the end is detected It is characterized by making adjustments.

  In a serial communication system that conforms to the PCI Express standard and transfers high-speed serial data divided into a plurality of lanes, a skew occurs in the delay of the transfer lane, and therefore the receiver needs to adjust the skew.

  FIG. 7A is a timing chart before skew adjustment in the conventional high-speed serial communication circuit disclosed in Patent Document 1, and FIG. 7B is a timing chart after skew adjustment. In Patent Document 1, a skew adjustment method at the time of link training or normal communication is carried out. As shown in FIG. 7, the skew at the time of return from a state in which communication is temporarily stopped in a low power consumption mode or the like. When readjustment is necessary, there is a possibility of misadjustment with the above method alone. When such a situation occurs, it takes a long time to return because it repeats reception errors and retransmissions and then returns. There was a point.

  FIG. 10A is a timing chart before skew adjustment in the conventional high-speed serial communication circuit disclosed in Patent Document 2, and FIG. 6 is a timing chart when the inter-lay skew adjustment is performed using the current skew adjustment value after the inter-skew adjustment. FIG. 14A is a timing chart before skew adjustment when only the counter value is controlled in the high-speed serial communication circuit according to the related art, and FIG. 14B is a skew adjustment previously performed in that case. FIG. 10 is a timing chart when the inter-lay skew adjustment is performed using the current skew adjustment value after the inter-lay skew adjustment is performed. FIG. The method according to Patent Document 2 is a method capable of skew adjustment regardless of the internal state. However, as shown in FIGS. 10 and 14, after skew adjustment, effective data (symbols not in an ordered set) is stored in a subsequent circuit. There was a problem that there was a possibility of duplicate output.

  An object of the present invention is to provide a serial communication circuit that solves the above-described problems, can perform skew adjustment with the received symbol when returning from the low power consumption mode, and can quickly return to the normal communication state. It is to provide.

Serial communication circuit according to the present invention,
A clock is recovered from serial received signals of a plurality of lanes encoded by a predetermined encoding method, and received symbols are recovered from the serial received signal for each lane using the recovered clock. After byte alignment and serial / parallel conversion for the received symbols for each lane, the received symbols are decoded by a decoding method corresponding to the above encoding method and stored in an elastic buffer, and the received symbols of a plurality of lanes are stored by the elastic buffer. A physical layer receiving circuit that converts the received symbol synchronized with the same clock and outputs the received symbol;
A serial communication circuit comprising an inter-lane skew adjustment circuit that adjusts a symbol skew between lanes for received symbols of a plurality of lanes output from the physical layer reception circuit,
The inter-lane skew adjustment circuit is
A detection circuit that detects a predetermined detection reference symbol that can be changed according to a control state for each lane from the received symbol, and outputs a detection signal;
A counter circuit that starts counting the detection signal in response to the detection signal, outputs a counter value of the count, and stops counting when the detection signal is detected in all lanes;
The counter value output from the counter circuit is used as a selection signal, and symbols between lanes are delayed by a delay amount corresponding to the selection signal with respect to the reception symbols of a plurality of lanes output from the physical layer reception circuit. And a signal delay selection circuit for adjusting skew.

  According to the serial communication circuit of the present invention, since the detected symbol in the control state can be changed, an optimum skew adjustment method in that state becomes possible. For example, the skew adjustment is performed on the received symbol when returning from the low power consumption mode. And can quickly return to the normal communication state. In particular, when it is necessary to readjust the skew when returning from the power saving mode, the skew can be adjusted at high speed without performing link retraining.

It is a block diagram which shows the structure of the whole physical layer of the receiving part of the high-speed serial communication circuit which concerns on the 1st Embodiment of this invention. FIG. 2 is a block diagram illustrating a circuit configuration for one lane of the inter-lane skew adjustment circuit 6 of FIG. 1. It is a block diagram which shows the circuit structure for 1 lane of the skew adjustment circuit 6 between lanes in the high-speed serial communication circuit based on the 2nd Embodiment of this invention. It is a block diagram which shows the circuit structure for 1 lane of the skew adjustment circuit 6 between lanes in the high-speed serial communication circuit based on the 3rd Embodiment of this invention. It is a block diagram which shows the circuit structure for 1 lane of the skew adjustment circuit 6 between lanes in the high-speed serial communication circuit based on the 4th Embodiment of this invention. It is a figure which shows the FTS ordered set used in the high-speed serial communication circuit which concerns on each embodiment of this invention. It is a figure which shows the SKP ordered set used in the high-speed serial communication circuit which concerns on each embodiment of this invention. (A) is a timing chart before skew adjustment in the conventional high-speed serial communication circuit, and (b) is a timing chart after the skew adjustment. (A) is a timing chart before skew adjustment in the high-speed serial communication circuit according to the first embodiment, and (b) is a timing chart after skew adjustment based on continuous FTS, COM, and SKP standards in that case. . It is a state transition diagram of the control state machine 10 (LTSMSM (Link Training and Status Machine)) based on the PCI Express standard used in the high-speed serial communication circuit according to each embodiment of the present invention. (A) is a timing chart before skew adjustment in the high-speed serial communication circuit according to the prior art, and (b) in this case, after skew adjustment between the skews with the previously skew-adjusted value, this time skew-adjusted value 6 is a timing chart when adjusting skew between the rows. (A) is a timing chart before skew adjustment in the high-speed serial communication circuit according to the first embodiment, and (b) is a skew of this time after skew adjustment with a previously skew adjusted value in that case. FIG. 10 is a timing chart when adjusting the inter-lay skew with the adjusted value. FIG. (A) is a timing chart before skew adjustment in the high-speed serial communication circuit according to the second embodiment, and (b) is a skew of the current time after adjusting skew between lays with a previously skew adjusted value in that case. FIG. 10 is a timing chart when adjusting the inter-lay skew with the adjusted value. FIG. (A) is a timing chart before skew adjustment when the high-speed serial communication circuit according to the third embodiment is controlled only by a counter value, and (b) is a timing chart between skews with a previously skew-adjusted value in that case. FIG. 10 is a timing chart when the inter-lay skew adjustment is performed using the current skew adjustment value after the skew adjustment. FIG. (A) is a timing chart before skew adjustment when controlled by a detection signal and a counter value in the high-speed serial communication circuit according to the third embodiment, and (b) is a value obtained by previously adjusting skew in that case. FIG. 10 is a timing chart when the inter-lay skew adjustment is performed using the skew adjustment value of this time after the inter-lay skew adjustment. FIG. (A) is a timing chart before skew adjustment when only the counter value is controlled in the high-speed serial communication circuit according to the prior art, and (b) is an inter-lay skew adjustment with a previously skew-adjusted value in that case. 9 is a timing chart when the inter-lay skew adjustment is performed using the current skew adjustment value. It is a flowchart which shows the skew adjustment process which shows operation | movement of the receiving part of the high-speed serial communication circuit which concerns on 1st Embodiment. 10 is a flowchart showing a skew adjustment process showing the operation of the receiving unit of the high-speed serial communication circuit according to the second embodiment. 10 is a flowchart showing a skew adjustment process showing the operation of the receiving unit of the high-speed serial communication circuit according to the third embodiment. 5 is a selection table of the multiplexer 34 in FIG. 4, showing selection data for a selection signal.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

First embodiment.
FIG. 1 is a block diagram showing the configuration of the entire physical layer of the receiving unit of the high-speed serial communication circuit according to the first embodiment of the present invention. In FIG. 1, the receiving unit of the high-speed serial communication circuit according to the present embodiment can perform skew adjustment with the received symbol when returning from the low power consumption mode, and quickly returns to the normal communication state. For this purpose, an inter-lane skew adjustment circuit 6 is provided.

In FIG. 1, the reception unit of the high-speed serial communication circuit according to the present embodiment includes a physical layer reception circuit 50 and an inter-lane skew adjustment circuit 6. Here, the physical layer receiving circuit 50
(A) For example, a received signal receiver 1 that receives and amplifies an 8B10B-encoded serial differential reception signal received via a differential signal transmission path of four lanes, converts the amplified signal into a single-ended signal, and outputs the signal. -1 to 1-4,
(B) a clock recovery circuit 2-1 to 2-4 for recovering a clock from the converted single-ended signal and for recovering and outputting a received symbol of high-speed data based on the recovered clock;
(C) Byte-aligned SP (serial parallel) converters 3-1 to 3- that align the received symbols of high-speed data in units of bytes using a recovered clock and perform serial / parallel conversion to output parallel received symbols. 4 and
(D) 10B8B converters 4-1 to 4-4 for performing 10B8B decoding conversion on the parallel received symbols using the recovered clock and outputting the converted parallel received symbols;
(E) Temporarily storing the parallel received symbols after conversion, converting the clock rate from the recovered clock to the same processing unit clock, and converting the received symbols of parallel data synchronized with the processing unit clock to inter-lane skew Elastic buffers 5-1 to 5-4 for outputting to the adjustment circuit 6 are provided.
Further, the inter-lane skew adjustment circuit 6 performs skew adjustment on the received symbol when returning from the low power consumption mode based on the state information from the control state machine 10 and quickly returns to the normal communication state.

FIG. 2 is a block diagram showing a circuit configuration for one lane of the inter-lane skew adjustment circuit 6 of FIG. In FIG. 2, the circuit for one lane of the inter-lane skew adjustment circuit 6 is
(A) Based on the state information from the control state machine 10, for example, a predetermined reference symbol, which will be described later in detail, is detected from an 8-bit received symbol, and the detection signal is used as the AND of the counter circuit 13 and all-lane detection determination circuit 12. A reference symbol detection circuit 11 for outputting to the input terminal of the gate;
(B) All lanes provided with AND gates that perform a logical product on the detection signals of the lane and the detection signals of all other lanes and output the result signals to the counter circuit 13 as detection completion signals of all lanes. A detection determination circuit 12;
(C) a counter circuit 13 that counts the detection signals of the lane and outputs the counter value to the selection signal generator 14 as the counter value when all lane detection is completed when the detection completion signal is generated for all lanes;
(D) a selection signal generator 14 provided with a delay type flip-flop that delays storage of the counter value at the completion of detection of all lanes for a predetermined period and outputs it to the multiplexer 26 as a selection signal;
(E) For example, the signal delay selection circuit 20 is configured to output an 8-bit reception symbol after delaying a delay time indicated by the selection signal among a plurality of predetermined delay times.

  The signal delay selection circuit 20 delays an input received symbol, and includes five delay flip-flops 21 to 25 connected in cascade with each other and an input received symbol (data d0) based on the selection signal. And a multiplexer 26 that selects and outputs one of the output symbols (data d1 to d5) from each of the delay flip-flops 21 to 25. Here, the delay times differ between the data d0 to d5.

  FIG. 9 is a state transition diagram of a control state machine 10 (for example, using LTSSM (Link Training and Status Machine)) conforming to the PCI Express standard used in the high-speed serial communication circuit according to each embodiment of the present invention ( For example, refer nonpatent literature 1 and 2.). The LTSSM is a state machine that performs state management such as link initialization, training, and recovery from an error. The state machine has each state shown in FIG. 9 and changes state as shown in FIG.

  FIG. 6A is a diagram showing an FTS ordered set used in the high-speed serial communication circuit according to each embodiment of the present invention. As shown in FIG. 6A, the FTS ordered set is composed of one COM (comma) symbol and three FTS (Fast Training Sequence) symbols. Here, the COM symbol is used at the head of each ordered set, and the receiving side can detect the ordered set by the COM symbol. The FTS ordered set is used when a transition is made from the L0s state in the power saving mode (low power consumption mode) (which means a state in which serial communication is temporarily stopped) to the full-on L0 state.

  FIG. 6B is a diagram showing an SKP ordered set used in the high-speed serial communication circuit according to each embodiment of the present invention. As shown in FIG. 6B, the SKP ordered set is composed of one COM symbol and three SKP (skip) symbols. Here, the SKP ordered set is used for the purpose of absorbing a clock frequency difference.

  FIG. 8A is a timing chart before skew adjustment in the high-speed serial communication circuit according to the first embodiment, and FIG. 8B is a diagram after skew adjustment based on continuous FTS, COM, and SKP standards in that case. It is a timing chart. In the inter-lane skew adjustment circuit 6 of FIG. 2, the reference symbol detection circuit 11 changes the detected symbol based on the state information from the control state machine 10. For example, the FTS ordered set (FIG. 6A) received in the return sequence from the L0s state in the power saving mode, the “FTS symbol”, the “COM symbol”, and the “SKP symbol” in the SKP ordered set (FIG. 6B). Detect continuity. When these symbols are continuously detected, a detection signal is output. On the other hand, the counter circuit 13 starts counting the input detection signal, counts up every cycle, and stops detecting when all the lanes are detected (reception of the detection completion signal for all the lanes). The counter value is accumulated by the selection signal generator 14 and used as a selection signal of the signal delay selection circuit 20. For example, as shown in FIG. 8, the lane skew adjustment is completed by the operation.

  FIG. 11A is a timing chart before skew adjustment in the high-speed serial communication circuit according to the first embodiment, and FIG. 11B is a graph after skew adjustment is performed with a previously skew adjusted value in that case. FIG. 6 is a timing chart when the skew adjustment between the lays is performed using the skew adjustment value of this time. As shown in FIG. 11, after detecting the FTS symbol, the COM symbol, and the SKP symbol in each lane, the detection signal is raised, and when it is detected in all the lanes, it is lowered. When the detection signal is at a high level (hereinafter referred to as H level), the count of the counter circuit 13 is increased. In the waveform of FIG. 11, the selection signal for lane 0 (selecting the delay amount for skew adjustment) changes from 2 to 3 upon completion of detection in all lanes (timing t11 in FIG. 11). For this reason, the SKP symbol is repeated, but the SKP symbol is ignored in the subsequent processing, so there is no particular influence.

  FIG. 15 is a flowchart showing a skew adjustment process showing the operation of the receiving unit of the high-speed serial communication circuit according to the first embodiment. As shown in FIG. 15, if the control state is link training in step S1, the COM symbol is set as a detection reference symbol (step S2), and if it is the return state from the L0s state in the power saving mode, FTS, COM, and SKP are set as detection reference symbols. (Step S3). When the reference symbol is detected in step S4, the detection signal is raised and output, the counter value CNT of the counter circuit 13 is initialized to 0, and then started. When the reference symbol is detected in the lane, the counter value CNT of the counter circuit 13 is incremented by 1 (step S7), and when the reference symbol is detected in all lanes (YES in step S6), the counter circuits 13 of all lanes are stopped. Then, the counter value is loaded as a selection signal (step S8), the delay value of the lane is changed by the selection signal (step S9), and the received symbol after skew adjustment is output from the signal delay selection circuit 20 to complete the skew adjustment. (Step S10).

  In the prior art, there was a possibility of incorrect skew adjustment when returning from the L0s state in the power saving mode, and there was a possibility that valid data would be duplicated and output to the processing circuit in the subsequent stage (possibility of communication interruption thereby). Since the skew is adjusted based on the received symbol at an earlier stage, the possibility is eliminated. That is, since the detected symbol in the control state can be changed, an optimum skew adjustment method in the control state is possible.

Second embodiment.
FIG. 3 is a block diagram showing a circuit configuration for one lane of the inter-lane skew adjustment circuit 6 in the high-speed serial communication circuit according to the second embodiment of the present invention. The circuit configuration in FIG. 1 is the same as in the second embodiment. In the second embodiment, compared to the first embodiment of FIG. 2, the reference symbol detection circuit 11 is based on the state information from the control state machine 10, for example, from a received symbol of 8 bits. In addition to detecting a symbol and generating a detection signal, it is characterized in that symbol increase / decrease information is generated and output to the counter circuit 13.

  In FIG. 3, the reference symbol detection circuit 11 can change the detection reference symbol based on the state information from the control state machine 10. For example, when returning from the power saving mode L0s state, a sequence of “FTS symbol”, “COM symbol”, and “SKP symbol” is detected. When the continuation of these symbols is detected, a detection signal is output. Further, since the SKP ordered set of COM symbols and SKP symbols is used, the SKP symbols may be added or deleted in the elastic buffers 5-1 to 5-4 in order to absorb the clock frequency difference of the transmitting and receiving devices. If the information uses a PIPE (PHY Interface for the PCI Express Architecture) interface (which defines an interface between a physical layer LSI and an upper layer (for example, a MAC layer)), a COM symbol is received. Since the SKP symbol increase / decrease information is sent simultaneously with the timing, the information is output to the counter circuit 13. The counter circuit 13 starts counting with the detection signal. At this time, if the SKP symbol is deleted, +1 is added. If the SKP symbol is added, -1 is added (that is, +1 is subtracted), and the count is incremented for each cycle to detect all lanes. Is stopped, the counter value is accumulated and used as a selection signal for the delay selection circuit. This operation completes the lane skew adjustment.

  FIG. 12A is a timing chart before skew adjustment in the high-speed serial communication circuit according to the second embodiment, and FIG. 12B is a graph after skew adjustment is performed using the previously skew-adjusted value in that case. FIG. 6 is a timing chart when the skew adjustment between the lays is performed using the skew adjustment value of this time. As apparent from FIG. 12, since the SKP symbol is deleted in lane 0, the counter value after the detection signal rises starts from +1 and starts counting.

  FIG. 16 is a flowchart showing a skew adjustment process showing the operation of the receiving unit of the high-speed serial communication circuit according to the second embodiment. In FIG. 16, if the control state is link training in step S1, the COM symbol is used as a detection reference symbol, and if it is the return state from the L0s state in the power saving mode, FTS, COM, and SKP are used as detection reference symbols. In other cases, only adjustment based on the symbol increase / decrease information of the SKP ordered set is performed (step S11). When the reference symbol is detected in step S4, a detection signal is output and counting of the counter circuit 13 is started. At that time, if there is SKP deletion, the initial value of the counter value CNT is incremented by +1 (step S14), and if there is SKP addition, the initial value is incremented by -1 (that is, subtracted by 1) and started. When the reference symbols have been detected in all lanes (step S6), the counter circuits 13 of all lanes are stopped and the values are loaded as selection signals (step S8), and the delay interest of the lanes is changed by the selection signals ( Step S9) The received symbol after skew adjustment is output from the signal delay selection circuit 20, and the skew adjustment is completed (Step S10).

  In the prior art, there is a possibility of erroneous skew adjustment and a possibility of valid data being duplicated and output to a subsequent processing circuit when returning from the L0s state in the power saving mode, but the received symbol at an earlier stage is used as a reference. Since the skew is adjusted, the possibility disappears. Furthermore, even when the addition or deletion of symbols is adjusted in the elastic buffers 5-1 to 5-4 of the physical layer receiving circuit in FIG. 1, it corresponds to the increase / decrease of the SKP symbols, and is more accurate than the prior art. You can adjust skew.

Third embodiment.
FIG. 4 is a block diagram showing a circuit configuration for one lane of the inter-lane skew adjustment circuit 6 in the high-speed serial communication circuit according to the third embodiment of the present invention. Note that the circuit configuration of FIG. 1 is the same in the third embodiment. Compared to the second embodiment of FIG. 3, the third embodiment divides received two symbols (16 bits) into one symbol (8 bits) × 2 columns instead of the signal delay selection circuit 20. And a signal delay selection circuit 30 for performing signal delay selection. In other words, this embodiment is characterized in that two symbols (16 bits) are simultaneously interfaced with the physical layer receiving circuit 50, and is also defined in the above-described PIPE interface. That is, the physical layer reception circuit 50 is configured to output two reception symbols in one cycle, and the inter-lane skew adjustment circuit 6 performs skew adjustment on the reception symbols.

  In FIG. 4, the signal delay selection circuit 30 includes three delay flip-flops 31 to 33 that are cascade-connected to each other and three that are cascade-connected to each other to delay two input received symbols. Based on the delay flip-flops 41 to 43 and the selection signal, the received symbols (data d00, d05) to be input and the output symbols (data d10, d15; data d20, d20) from the delay flip-flops 31 to 43 are input. d25; data d30, d35) and a multiplexer 34 that selects and outputs any one pair of symbols. Here, each pair of data d00 and d05, data d10 and d15, data d20 and d25, and data d30 and d35 have different delay times.

  In FIG. 4, the reference symbol detection circuit 11 detects the continuity of the received FTS symbol, COM symbol, and SKP symbol when returning from the L0s state in the power saving mode. When these symbols are continuously detected, a detection signal is output. Further, since the SKP ordered set of COM symbols and SKP symbols is used, the SKP symbols may be added or deleted in the elastic buffers 5-1 to 5-4 in order to absorb the clock frequency difference of the transmitting and receiving devices. If the above PIPE interface is used, the information is sent to the counter circuit 13 because the SKP symbol increase / decrease information is sent simultaneously with the timing of receiving the COM symbol. The counter circuit 13 starts counting with the detection signal. At this time, if the SKP symbol is deleted, the counter value CNT is incremented by +0.5, and if the SKP symbol is added, it is incremented by −0.5 (ie, subtracted by +0.5). It counts up every cycle and stops when detection of all the lanes is completed. The counter value is accumulated by the selection signal generator 14 and used as a selection signal of the signal delay selection circuit 30.

  FIG. 18 is a selection table of the multiplexer 34 of FIG. 4 and shows selection data for the selection signal. In FIG. 18, for example, if the selection signal is 1.0, the data d10 and d15 are selected and output. As is apparent from FIG. 18, in this embodiment, the unit of the selection signal is 0.5, and the data selection method is as shown in FIG. 18, and the lane skew adjustment is completed by the operation.

  FIG. 13A (a) is a timing chart before skew adjustment when only the counter value is controlled in the high-speed serial communication circuit according to the third embodiment, and FIG. 13A (b) is a graph in which skew adjustment has been performed previously. FIG. 10 is a timing chart when the inter-lay skew adjustment is performed using the current skew adjustment value after the inter-lay skew adjustment is performed. FIG. FIG. 13B (a) is a timing chart before skew adjustment when controlled by the detection signal and the counter value in the high-speed serial communication circuit according to the third embodiment, and FIG. 13B (b) 6 is a timing chart when the inter-lay skew adjustment is performed using the current skew adjustment value after the inter-lay skew adjustment is performed using the skew adjustment value. As apparent from FIGS. 13A and 13B, in lane 0, continuous detection of FTS, COM, and SKP can be detected at two symbol breaks, and the SKP symbol is deleted and input in the SKP ordered set. The counter value starts counting from a value increased by +0.5, and counts up every cycle. Since the detection signals of all the lanes are output at timing t13 in FIG. 13B, the counter value is loaded into the multiplexer 34 of the signal delay selection circuit 30 as a selection signal.

  FIG. 17 is a flowchart showing a skew adjustment process showing the operation of the receiving unit of the high-speed serial communication circuit according to the third embodiment. In FIG. 17, if the control state is link training in step S1, the COM symbol is set as a detection reference symbol, and if it is the return state from the L0s state in the power saving mode, FTS, COM, and SKP are set as detection reference symbols. In other cases, only adjustment based on the symbol increase / decrease information of the SKP ordered set is performed (step S11). When the reference symbol is detected (YES in step S4), a detection signal is output and counting of the counter circuit 13 is started. In step S15, if the final detection position is the first symbol (there is a fraction in the middle), the counter value CNT is incremented by +0.5 (step S16). At that time, the increase / decrease of the SKP symbol is checked in step S17. If the SKP symbol is deleted, the initial value of the counter value CNT is added by +0.5 (step S19). If the SKP symbol is added, -0.5 is added (that is, +0.5 is subtracted). (Step S18) and counting is started. When the reference symbols have been detected in all the lanes (YES in step S6), all the counter circuits 13 are stopped and the values are loaded as selection signals (step S8), and the delay interest of the lanes is changed by the selection signals ( Step S9) The received symbol after skew adjustment is output from the signal delay selection circuit 20, and the skew adjustment is completed (Step S10).

  In the prior art, the physical layer receiving circuit is configured using a 1-symbol interface, but may be configured using a 2-symbol interface as in the present embodiment. In this case, as in the first and second embodiments, the skew adjustment is performed based on the received symbol at an earlier stage, so there is no possibility of erroneous adjustment or duplicate output in FIG. That is, since the detected symbol in the control state can be changed, an optimum skew adjustment method in the control state is possible. In the present embodiment, skew adjustment is also possible when the physical layer receiving circuit 50 is interfaced with two symbols in one cycle. If the reception rate of the external reception signal is the same, data in one cycle is doubled. Since the interface frequency can be halved, it is easy to mount the circuit.

  The third embodiment is applied to the second embodiment, but the present invention is not limited to this, and may be applied to the first embodiment.

Fourth embodiment.
FIG. 5 is a block diagram showing a circuit configuration of one lane of the inter-lane skew adjustment circuit 6 in the high-speed serial communication circuit according to the fourth embodiment of the present invention. Note that the circuit configuration of FIG. 1 is the same in the fourth embodiment. Compared to the second embodiment, the fourth embodiment is characterized in that the reference symbol detection circuit 11 detects a received symbol based on the detection reference symbol from the register 10A of the CPU. Other configurations and operations are the same as those in the second embodiment. In this embodiment, the same effects as in the second embodiment are obtained, and the detection reference symbol can be arbitrarily set and changed by the CPU. Therefore, the skew can be adjusted in more detail by dynamically changing from the CPU. . In particular, skew adjustment is possible with an arbitrary symbol or symbol string. It is also possible to support different standard communication systems with the same hardware. The configuration of the fourth embodiment can be applied to the configurations of the first to third embodiments.

  In the above embodiment, when transmitting a serial signal, 8B10B encoding conversion is performed and transmitted, and 10B8B decoding conversion is performed on the receiving side. However, other encoding and decoding for high-speed serial communication are performed. A conversion method may be used.

  In the third and fourth embodiments, the counter circuit 13 counts based on the detection signal and the symbol increase / decrease information. However, the present invention is not limited to this, and the counter circuit 13 may count based only on the detection signal. Good.

  As described above in detail, according to the serial communication circuit according to the present invention, since the detected symbol in the control state can be changed, an optimum skew adjustment method in that state is possible, for example, when returning from the low power consumption mode. Skew adjustment can be performed on the received symbol, and quick return to the normal communication state can be performed. In particular, when it is necessary to readjust the skew when returning from the power saving mode, the skew can be adjusted at high speed without performing link retraining.

1-1 to 1-4: Received signal receiver,
2-1 to 2-4 ... clock recovery circuit,
3-1 to 3-4 Byte-aligned SP (serial parallel) converter,
4-1 to 4-4... 10B8B converter,
5-1 to 5-4. Elastic buffer,
6 ... Inter-lane skew adjustment circuit,
10: Control state machine,
10A: CPU register,
11: Reference symbol detection circuit,
12 ... All-lane detection determination circuit,
13: Counter circuit,
14 ... Selection signal generator,
20, 30... Signal delay selection circuit,
21-25, 31-33, 41-43 ... delay type flip-flops,
26, 34 ... Multiplexer,
50: Physical layer receiving circuit.

JP 2006-202281 A JP 2008-172657 A

PCI-SIG, "PCI Express Base Specification Revision 2.0", PCI-SIG, December 2006. Arai Nobutaka et al., “Introduction to Revised PCI Express, Basic Knowledge and Practice of High-Speed Serial Interface”, Denpa Shimbun, June 20, 2008

Claims (9)

A clock is recovered from serial received signals of a plurality of lanes encoded by a predetermined encoding method, and received symbols are recovered from the serial received signal for each lane using the recovered clock. After byte alignment and serial / parallel conversion for the received symbols for each lane, the received symbols are decoded by a decoding method corresponding to the above encoding method and stored in an elastic buffer, and the received symbols of a plurality of lanes are stored by the elastic buffer. A physical layer receiving circuit that converts the received symbol synchronized with the same clock and outputs the received symbol;
A serial communication circuit comprising an inter-lane skew adjustment circuit that adjusts a symbol skew between lanes for received symbols of a plurality of lanes output from the physical layer reception circuit,
The inter-lane skew adjustment circuit is
A detection circuit that detects a predetermined detection reference symbol that can be changed according to a control state for each lane from the received symbol, and outputs a detection signal;
A counter circuit that starts counting the detection signal in response to the detection signal, outputs a counter value of the count, and stops counting when the detection signal is detected in all lanes;
The counter value output from the counter circuit is used as a selection signal, and symbols between lanes are delayed by a delay amount corresponding to the selection signal with respect to the reception symbols of a plurality of lanes output from the physical layer reception circuit. A serial communication circuit comprising a signal delay selection circuit for adjusting skew. The detection circuit further detects symbol increase / decrease information from the received symbol and outputs it to the counter circuit,
The counter circuit starts counting the detection signal in response to the detection signal, increases / decreases the count value of the count based on the symbol increase / decrease information, and then outputs the count value of the count to all lanes. 2. The serial communication circuit according to claim 1, wherein the counting is stopped when the detection signal is detected.   The inter-lane skew adjustment circuit adjusts the symbol skew between the lanes in a return sequence when returning from a low power consumption mode state in which communication is temporarily stopped. 2. The serial communication circuit according to 2.   The state of the low power consumption mode is the L0s state defined in the PCI Express standard, and the inter-lane skew adjustment circuit receives the “FTS symbol” in the FTS ordered set and SKP ordered set received in the return sequence. 4. The serial communication circuit according to claim 3, wherein a symbol skew between lanes is adjusted based on a series of “COM symbols” and “SKP symbols”.   5. The serial communication circuit according to claim 4, wherein the inter-lane skew adjustment circuit adjusts the symbol skew between lanes when an SKP symbol is added in an SKP ordered set.   5. The serial communication circuit according to claim 4, wherein the inter-lane skew adjustment circuit adjusts symbol skew between lanes when SKP symbols are deleted in an SKP ordered set.   7. The physical layer receiving circuit is configured to output two symbols of received symbols in one cycle, and the inter-lane skew adjusting circuit adjusts skew with respect to the received symbols. The serial communication circuit as described in any one of them.   The serial communication circuit according to any one of claims 1 to 7, further comprising means for arbitrarily setting the detection reference symbol.   The serial communication circuit according to claim 1, wherein the encoding method is an 8B10B encoding / conversion method.

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