JP2013048333A - Image processor, image processing method and image processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inexpensively provide a multi-eye camera system which synchronously outputs an image.SOLUTION: A plurality of memories respectively hold image data outputted from a plurality of CMOS sensors which are synchronously driven on the basis of one clock signal. A delay detection circuit detects delay of image data outputted from the plurality of CMOS sensors. A synchronization signal generation circuit generates a signal for instructing the plurality of memories to output the image data so that the plurality of pieces of image data, which are held in the plurality of memories, are simultaneously outputted on the basis of the delay of the image data, which is detected by the delay detection circuit. This technology can be applied to a multi-eye camera.

Description

  The present technology relates to an image processing device, an image processing method, and an image processing system, and in particular, an image processing device and an image processing that enable a multi-lens camera system that outputs images synchronously to be configured at a lower cost. The present invention relates to a method and an image processing system.

  Conventionally, the GenLock method and the frame synchronizer method are known as methods for synchronizing video signals output from a plurality of cameras.

  The GenLock method is a method in which a plurality of cameras are operated synchronously with a reference signal output from a synchronization signal generator.For example, in a stereo camera, the exposure time is calculated together with the driving of a plurality of image sensors and signal processing units. There is a technique of synchronizing (see, for example, Patent Document 1).

  On the other hand, in the frame synchronizer method, video signals output asynchronously from a plurality of cameras are temporarily held in a frame memory, and the video signals held in the respective frame memories are simultaneously received by a reference signal output from a synchronization signal generator. This is a technique for outputting. As a technique using this method, for example, an image processing system has been proposed in which frame images taken at the same time taken by a plurality of cameras are compared to self-diagnose the soundness of the cameras (for example, Patent Document 2).

  In general, a camera having a terminal for inputting a reference signal is used in a GenLock system camera system. However, such a camera is not common and is expensive, and constitutes a multi-lens camera system that performs synchronous operation. However, it was costly.

  On the other hand, since a general camera can be used in the frame synchronizer type camera system, the cost can be reduced in this respect compared with the GenLock type camera system.

JP 2000-341719 A Japanese Patent Laid-Open No. 2001-211466

  However, since the frame synchronizer system camera system requires a frame memory, it is still expensive.

  The present technology has been made in view of such a situation, and makes it possible to configure a multi-lens camera system that outputs images synchronously at a lower cost.

  An image processing device according to an aspect of the present technology includes a plurality of memories each holding image data output from a plurality of solid-state imaging devices that are driven synchronously based on one clock signal, and a plurality of the solid-state imaging devices. A detection unit that detects a delay of each of the output image data, and simultaneously outputs each of the image data held in a plurality of the memories based on the delay of the image data detected by the detection unit And a signal generator for generating a signal for instructing the plurality of memories to output the image data.

  The image processing apparatus further includes a sending unit that broadcasts a command for outputting the image data to the plurality of solid-state imaging devices, and the detection unit includes a plurality of the solid-state imaging devices based on the command. It is possible to detect a delay of each of the image data output from the imaging device substantially simultaneously.

  The image processing apparatus further includes one clock signal generation unit that generates the clock signal and at least one reset signal generation unit that generates a reset signal for resetting the plurality of solid-state imaging devices. Can do.

  The solid-state imaging device may be configured as a CMOS (Complementary Metal Oxide Semiconductor) image sensor.

  An image processing method according to an aspect of the present technology is an image processing method of an image processing apparatus including a plurality of memories that respectively hold image data output from a plurality of solid-state imaging devices that are driven synchronously based on one clock signal. The image processing device detects delays of the image data output from the plurality of solid-state imaging devices, and is stored in the plurality of memories based on the detected delays of the image data. Generating a signal instructing the plurality of memories to output the image data so as to simultaneously output the image data.

  An image processing system according to an aspect of the present technology includes a plurality of cameras and an image output device that outputs image data output from the plurality of cameras to an image processing device that performs predetermined image processing in synchronization with each other. In the image processing system, the plurality of cameras each include a solid-state imaging device that is driven in synchronization based on one clock signal, and the image output device outputs the images output from the plurality of solid-state imaging devices. Based on the delay of the image data detected by the detection unit, a detection unit that detects a delay of each of the image data output from the plurality of solid-state imaging devices, a plurality of memories each holding data Instructing the plurality of memories to output the image data so that the respective image data held in the plurality of memories are simultaneously output. And a signal generator for generating a signal.

  In one aspect of the present technology, a delay of each image data output from a plurality of solid-state imaging devices is detected, and each image data held in a plurality of memories based on the detected delay of the image data So as to output the image data to a plurality of memories.

  According to one aspect of the present technology, a multi-lens camera system that outputs images synchronously can be configured at a lower cost.

It is a block diagram showing an example of functional composition of an embodiment of an imaging device as an image processing device to which this art is applied. It is a flowchart explaining an image output synchronous process. It is a figure explaining the detection of the delay of image data. It is a figure explaining the structure at the time of using memory as FIFO. It is a block diagram showing an example of functional composition of an embodiment of an image processing system to which this art is applied.

Hereinafter, embodiments of the present technology will be described with reference to the drawings. The description will be given in the following order.
1. 1. Configuration of imaging apparatus to which the present technology is applied 2. Image output synchronization processing Configuration of image processing system to which this technology is applied

<1. Configuration of imaging apparatus to which the present technology is applied>
FIG. 1 shows a configuration of an embodiment of an imaging apparatus as an image processing apparatus to which the present technology is applied.

  The imaging device 11 in FIG. 1 is configured as a so-called multi-lens camera that simultaneously acquires a plurality of images and performs predetermined image processing on the images.

  1 includes lenses 31-1 to 31-N, CMOS (Complementary Metal Oxide Semiconductor) image sensors 32-1 to 32-N, a reset signal generation circuit 33, a clock signal generation circuit 34, and a control command transmission circuit. 35, a small-capacity memory 36, a delay detection circuit 37, a synchronization signal generation circuit 38, an image processing unit 39, and a CPU 40.

  CMOS image sensors 32-1 to 32-N (hereinafter referred to as CMOS sensors 32-1 to 32-N) as solid-state imaging devices each include an image sensor and an A / D (Analog / Digital) conversion unit, and are basically configured. It consists of a digital circuit. The CMOS sensors 32-1 to 32-N receive the light from the lenses 31-1 to 31-N and perform photoelectric conversion to image a subject, and A / D convert the obtained analog image signal. The CMOS sensors 32-1 to 32-N supply digital image data obtained as a result of A / D conversion to the small-capacity memories 36-1 to 36-N.

  The CMOS sensors 32-1 to 32 -N are simultaneously reset by a reset signal from the reset signal generation circuit 33 and are driven in synchronization with the clock signal from the clock signal generation circuit 34.

  In the following, when it is not necessary to distinguish the CMOS sensors 32-1 to 32 -N, they are simply referred to as the CMOS sensor 32, and other configurations in the imaging device 11 are similarly handled.

  The reset signal generation circuit 33 generates a reset signal for resetting the CMOS sensor 32 and supplies the reset signal to the CMOS sensor 32.

  The clock signal generation circuit 34 generates a clock signal for synchronizing the driving of the CMOS sensor 32 and supplies it to the CMOS sensor 32.

  The control command transmission circuit 35 transmits a control command for controlling the operation of the CMOS sensor 32 to the CMOS sensor 32 by performing serial communication with the CMOS sensor 32.

  The small-capacity memory 36 (hereinafter simply referred to as the memory 36) has a capacity of about several bytes, holds part of the image data supplied from the CMOS sensor 32, and uses it as a synchronization signal from the synchronization signal generation circuit 38. In response, a part of the held image data is supplied to the image processing unit 39.

  The delay detection circuit 37 detects a delay of image data supplied from the CMOS sensors 32-1 to 32-N to the memories 36-1 to 36-N. Specifically, among the image data supplied from the CMOS sensors 32-1 to 32-N to the memories 36-1 to 36-N, the delay between the image data supplied with the most delay and the other image data. The amount is obtained, and a signal representing the delay amount is supplied to the synchronization signal generation circuit 38.

  In response to the signal from the delay detection circuit 37, the synchronization signal generation circuit 38 simultaneously outputs the image data held in the memories 36-1 to 36-N to the memories 36-1 to 36-N, respectively. A synchronization signal for instructing to do so is supplied. The synchronization signal generation circuit 38 also supplies a synchronization signal for the memory 36 to the image processing unit 39.

  The image processing unit 39 performs predetermined image processing on the image data output simultaneously (synchronously) from the memories 36-1 to 36-N.

  A CPU (Central Processing Unit) 40 controls each unit of the imaging device 11.

[Configuration of CMOS sensor]
Here, the configuration of the CMOS sensor 32 will be described.

  As shown in FIG. 1, the CMOS sensor 32 includes a pixel array unit 51, a synchronization circuit 52, and a serial I / F (Interface) 53.

  The pixel array unit 51 includes pixels as photoelectric conversion elements arranged in a matrix, and acquires image data as an electrical signal by photoelectrically converting light incident thereon.

  The synchronization circuit 52 is configured to include, for example, a PLL (Phase Locked Loop) circuit which is an analog circuit, and is necessary for driving each unit in the CMOS sensor 32 based on the clock signal from the clock signal generation circuit 34. An internal synchronization signal (clock signal) is generated and output to each part in the CMOS sensor 32.

  The serial I / F 53 receives a control command from the control command transmission circuit 35 and supplies an instruction corresponding to the control command to each unit in the CMOS sensor 32.

<2. Image output synchronization processing>
Next, image output synchronization processing of the imaging device 11 will be described with reference to the flowchart of FIG. The image output synchronization process is a process of synchronizing the image data output from the CMOS sensors 32-1 to 32-N and outputting the image data to the image processing unit 39.

  The CMOS sensors 32-1 to 32 -N are simultaneously reset by a reset signal from the reset signal generation circuit 33 and are driven in synchronization with the clock signal from the clock signal generation circuit 34.

  In such a state, when execution of predetermined image processing is instructed in accordance with a user operation on an operation unit (not shown), in step S11, the control command transmission circuit 35 controls the CMOS under the control of the CPU 40. An image output start command is broadcast to each sensor 32.

For example, the control command transmission circuit 35 transmits an image output start command to each CMOS sensor 32 at the same time by performing I2C (I ² C: Inter Integrated Circuit) communication as serial communication.

  I2C communication is a communication method for exchanging data between devices arranged mainly at a short distance such as on the same substrate. In I2C communication, one-to-many channel communication can be performed by using one device as a master and connecting a plurality of slave devices to the bus. In I2C communication, a master and a slave communicate by sharing only two signal lines of SCL (Serial Clock Line) and SDA (Serial Data Line) as a bus.

  The serial communication performed between the control command transmission circuit 35 and the CMOS sensor 32 (serial I / F 53) is not limited to the above-described I2C communication, but is serial communication of other standards such as SPI (Serial Peripheral Interface). May be.

  As described above, when an image output start command is broadcast from the control command sending circuit 35 to each of the CMOS sensors 32, it is generated by the synchronizing circuits 52-1 to 52-N of the CMOS sensors 32-1 to 32-N. Thus, the phases of the internal synchronization signals are substantially matched, and image data obtained by imaging is output to the memories 36-1 to 36-N almost simultaneously.

  However, as described above, the synchronization circuits 52-1 to 52 -N include analog circuits such as PLL circuits, and are output from the CMOS sensors 32-1 to 32 -N due to their individual differences. There may be a slight phase difference between the image data.

  Therefore, in step S12, the delay detection circuit 37 detects the delay of the image data output from the CMOS sensors 32-1 to 32-N to the memories 36-1 to 36-N.

  Specifically, for example, the delay detection circuit 37 extracts a synchronization signal (horizontal synchronization signal) representing the timing of one horizontal line of the image from the image data output from the CMOS sensors 32-1 to 32-N. Thus, the delay of the image data output from the CMOS sensors 32-1 to 32-N is detected, and the phase difference between the image data output with the most delay and the other image data is obtained.

  For example, assuming that the imaging device 11 is configured as a four-lens camera including four CMOS sensors 32-1 to 32-4, the image is output from the CMOS sensors 32-1 to 32-4 to the memories 36-1 to 36-4. Assume that the synchronization signal as shown in FIG. 3 is extracted from the image data 1 to 4.

  In the example of FIG. 3, the synchronization signal (falling) is extracted from the image data 1 at time t1, the synchronization signal (falling) is extracted from the image data 2 at time t2, and the synchronization signal from the image data 3 at time t3. (Falling) is extracted, and a synchronization signal (falling) is extracted from the image data 4 at time t4. That is, the image data 1 is supplied to the memory 36-1 earliest, the image data 2 is supplied to the memory 36-2 the second earliest, and the image data 3 is supplied to the memory 36-3 the third earliest. 4 is the latest supplied to the memory 36-4.

  The delay detection circuit 37 extracts the time t4 at which the synchronization signal (falling) of the image data 4 output with the most delay is extracted and the times t1 to t3 at which the synchronization signals (falling) of the image data 1 to 3 are extracted. The phase difference (time difference) is obtained. That is, the phase difference t4-t1 is the phase difference between the image data 4 and the image data 1, the phase difference t4-t2 is the phase difference between the image data 4 and the image data 2, and the phase difference t4-t3 is The phase difference between the image data 4 and the image data 3 is obtained. As described above, this phase difference is caused by an individual difference between the analog circuits included in the synchronization circuit 52, and is only equivalent to several pixels, which is sufficiently smaller than one line in the horizontal direction of the image.

  Then, the delay detection circuit 37 supplies a signal representing each phase difference, that is, a delay amount, to the synchronization signal generation circuit 38.

  In step S13, the synchronization signal generation circuit 38, based on the signal from the delay detection circuit 37, stores the image data held in the memories 36-1 to 36-N for each of the memories 36-1 to 36-N. By supplying a synchronization signal for outputting the image data, the respective image data are output simultaneously.

  For example, the synchronization signal generation circuit 38 delays the image data 1 described in FIG. 3 by the phase difference t4-t1, delays the image data 2 by the phase difference t4-t2, and delays the image data 3 by the phase difference t4-t3. A synchronization signal for delaying and outputting the image data 4 as it is is supplied to the memories 36-1 to 36-4. As a result, the image data 1 to 3 that are partly held in the memories 36-1 to 36-3 are output to the image processing unit 39 at the same time as the image data 4 that is output most delayed. Become.

  At this time, the data amount of the image data 1 to 3 held in the memories 36-1 to 36-3 is about several pixels supplied until the image data 4 is supplied to the memory 36-4. Become.

  The synchronization signal generation circuit 38 also supplies the synchronization signal supplied to the memories 36-1 to 36 -N to the image processing unit 39. In other words, in the imaging device 11, the multi-camera camera can be operated synchronously by setting the phase (phase signal) of the image data output with the most delay among the plurality of image data as the synchronization signal of the entire device. Done.

  According to the above processing, the delay of the image data output to the memories 36-1 to 36-N from the synchronously driven CMOS sensors 32-1 to 32-N is detected, and based on the maximum delay among them. The image data held in the memories 36-1 to 36-N are output. At this time, the delay of the image data is equivalent to several pixels, and the data amount of the image data held in the memory 36 is about several pixels at most. Therefore, since it is not necessary to prepare a large-capacity memory like the frame memory used in the conventional frame synchronizer method, a multi-lens camera that outputs images synchronously can be configured at a lower cost. .

  Specifically, for example, according to the conventional frame synchronizer method, when the resolution of the image data is Full HD, a memory capacity of about 20,000 (1920 × 1080) pixels is required. According to the above, since a memory capacity of about several pixels is sufficient, the memory capacity can be reduced by about one millionth order.

  Further, in the conventional frame synchronizer type camera system, since the camera itself performs asynchronous operation, the synchronism of video signals is not guaranteed. However, in the imaging device 11, the CMOS sensors 32-1 to 32-N are not Since the synchronous operation (drive) is performed based on the control command from the control command sending circuit 35, the simultaneity of the video signals can be kept to a practically unaffected level.

  Note that the delay detected in the above-described processing does not change after the image output start command is sent, so it is only necessary to be executed once in the image output synchronization processing. Thereafter, the detected delay is detected. Based on the delay, the image data is synchronized and output.

  By the way, in the imaging device 11 described above, the memory 36 may be configured as a FIFO (First In First Out).

[Configuration with memory as FIFO]
FIG. 4 is a diagram illustrating the configuration of the imaging device 11 when the memory 36 is a FIFO in the imaging device 11. Here, the imaging device 11 is assumed to be configured as a four-lens camera including four CMOS sensors 32-1 to 32-4.

  In FIG. 4, FIFO memories 131-1 through 131-4 are provided in place of the memories 36-1 through 36-4, and a NOR gate 132 is provided in place of the delay detection circuit 37 and the synchronization signal generation circuit 38, respectively. In FIG. 4, the lens 31, the CMOS image sensor 32, the reset signal generation circuit 33, the clock signal generation circuit 34, the control command transmission circuit 35, the image processing unit 39, and the CPU 40 are not shown.

  The NOR gate 132 latches the falling edge of the synchronization signal extracted from the image data 1 to 4, and outputs an enable signal to the FIFO memories 131-1 to 131-4 when all the synchronization signals fall.

  As a result, the image data held in the FIFO memory 131 is output at the same time as the image data output with the most delay, and the same operation as that of the imaging device 11 of FIG. There is an effect.

  In the above, the configuration in which the present technology is applied to an imaging device as a multi-view camera has been described. However, in the following, the configuration in which the present technology is applied to an image processing system having a plurality of cameras (imaging devices) will be described. To do.

<3. Configuration of image processing system to which this technology is applied>
FIG. 5 shows a configuration of an embodiment of an image processing system to which the present technology is applied.

  An image processing system 201 in FIG. 5 includes cameras 211-1 to 211 -N, an image output device 212, and an image processing device 213.

  In the image processing system 201 of FIG. 5, the cameras 211-1 to 211 -N supply captured images to the image output device 212, and the image output device 212 simultaneously receives the images from the cameras 211-1 to 211 -N. And output to the image processing apparatus 213.

  The cameras 211-1 to 211 -N are provided with CMOS sensors 221-1 to 221 -N, respectively. The CMOS sensor 221 has the same function and configuration as the CMOS sensor 32 of FIG.

  The image output device 212 includes a reset signal generation circuit 231, a clock signal generation circuit 232, a control command transmission circuit 233, a memory 234, a delay detection circuit 235, a synchronization signal generation circuit 236, and a CPU 237. The reset signal generation circuits 231 to CPU 237 are respectively the reset signal generation circuit 33, the clock signal generation circuit 34, the control command transmission circuit 35, the memory 36, the delay detection circuit 37, the synchronization signal generation circuit 38, and the CPU 40 of FIG. The function and configuration are the same as those in FIG.

  The image processing device 213 performs predetermined image processing on the plurality of images output in synchronization from the image output device 212.

  For example, when the image processing system 201 in FIG. 5 is applied to a multi-view camera system that relays sports such as soccer, the image processing device 213 outputs the image synchronously from the image output device 212 based on the operation of the operator. Switch a plurality of relay images.

  In addition, when the image processing system 201 in FIG. 5 is applied to an image generation system that generates a multi-viewpoint image, the image processing device 213 is output from the image output device 212 in synchronization with the operation of the operator. A plurality of images are combined to generate one multi-viewpoint image.

  Furthermore, when the image processing system 201 in FIG. 5 is applied to a stereo camera system, the image processing apparatus 213 is imaged by the two cameras 211-1 and 211-2 based on the operation of the operator, and image output is performed. The distance to the subject is calculated based on the two images output synchronously from the device 212.

  Note that the image output synchronization processing by the image output device 212 of the image processing system 201 of FIG. 5 is basically the same as the processing of the imaging device 11 of FIG. 1 described with reference to the flowchart of FIG. The description is omitted.

  That is, according to the image output synchronization processing by the image output device 212, the delay of the image data output to the memories 234-1 to 234-N from the synchronously driven CMOS sensors 221-1 to 221-N is detected, Based on the maximum delay, the image data held in the memories 234-1 to 234-N are output. At this time, the delay of the image data is equivalent to several pixels, and the data amount of the image data held in the memory 234 is about several pixels at most. Therefore, since it is not necessary to prepare a large-capacity memory like the frame memory used in the conventional frame synchronizer method, it is possible to construct a multi-lens camera system that outputs images synchronously at a lower cost. Become.

  Further, in the conventional frame synchronizer system camera system, the camera itself performs asynchronous operation, and thus the simultaneity of the video signals is not guaranteed. However, in the image processing system 201, the CMOS sensors 221-1 to 221-N Since the synchronous operation (drive) is performed based on the control command from the control command transmission circuit 233, the simultaneity of the video signals can be kept to a practically unaffected level.

  In the configuration described above, one reset signal generating circuit is provided for a plurality of CMOS sensors. However, each reset signal generating circuit may be provided for a plurality of CMOS sensors. .

  The embodiments of the present technology are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present technology.

Furthermore, this technique can take the following structures.
(1) a plurality of memories each holding image data output from a plurality of solid-state imaging devices that are driven synchronously based on one clock signal;
A detection unit for detecting a delay of each of the image data output from the plurality of solid-state imaging devices;
Instructing the plurality of memories to output the image data based on the delay of the image data detected by the detection unit so that the image data held in the plurality of memories are simultaneously output. An image processing apparatus comprising: a signal generation unit that generates a signal.
(2)
A plurality of solid-state imaging devices, further comprising a sending unit that broadcasts a command for outputting the image data;
The image processing device according to (1), wherein the detection unit detects a delay of each of the image data output from the plurality of solid-state imaging devices substantially simultaneously based on the command.
(3) one clock signal generator for generating the clock signal;
The image processing apparatus according to (1) or (2), further including at least one reset signal generation unit that generates a reset signal for resetting the plurality of solid-state imaging devices.
(4) The image processing device according to any one of (1) to (3), wherein the solid-state imaging device is configured as a CMOS (Complementary Metal Oxide Semiconductor) image sensor.
(5) In an image processing method of an image processing apparatus including a plurality of memories respectively holding image data output from a plurality of solid-state imaging devices driven synchronously based on one clock signal,
The image processing apparatus is
Detecting a delay of each of the image data output from the plurality of solid-state imaging devices;
Based on the detected delay of the image data, a signal instructing the plurality of memories to output the image data is generated so as to simultaneously output the respective image data held in the plurality of memories. An image processing method including steps.
(6) An image processing system including a plurality of cameras and an image output device that outputs image data output from the plurality of cameras to an image processing device that performs predetermined image processing in synchronization with each other.
The plurality of cameras are
Each of which has a solid-state imaging device that is driven synchronously based on one clock signal,
The image output device includes:
A plurality of memories each holding the image data output from the plurality of solid-state imaging devices;
A detection unit for detecting a delay of each of the image data output from the plurality of solid-state imaging devices;
Instructing the plurality of memories to output the image data based on the delay of the image data detected by the detection unit so that the image data held in the plurality of memories are simultaneously output. An image processing system comprising: a signal generation unit that generates a signal.

  11 imaging device, 32-1 to 32-N, 32 CMOS sensor, 33 reset signal generation circuit, 34 clock signal generation circuit, 35 control command transmission circuit, 36-1 to 36-N, 36 memory, 37 delay detection circuit, 38 synchronization signal generation circuit, 201 image processing system, 211-1 to 211 -N, 211 camera, 212 image output device, 221-1 to 221 -N, 221 CMOS sensor, 231 reset signal generation circuit, 232 clock signal generation circuit , 233 control command transmission circuit, 234-1 to 234-N, 234 memory, 235 delay detection circuit, 236 synchronization signal generation circuit

Claims (6)

A plurality of memories each holding image data output from a plurality of solid-state imaging devices driven synchronously based on one clock signal;
A detection unit for detecting a delay of each of the image data output from the plurality of solid-state imaging devices;
Instructing the plurality of memories to output the image data based on the delay of the image data detected by the detection unit so that the image data held in the plurality of memories are simultaneously output. An image processing apparatus comprising: a signal generation unit that generates a signal. A plurality of solid-state imaging devices, further comprising a sending unit that broadcasts a command for outputting the image data;
The image processing device according to claim 1, wherein the detection unit detects a delay of each of the image data output from the plurality of solid-state imaging devices substantially simultaneously based on the command. A clock signal generator for generating the clock signal;
The image processing apparatus according to claim 1, further comprising at least one reset signal generation unit that generates a reset signal for resetting the plurality of solid-state imaging devices. The image processing apparatus according to claim 1, wherein the solid-state imaging device is configured as a CMOS (Complementary Metal Oxide Semiconductor) image sensor. In an image processing method of an image processing apparatus including a plurality of memories each holding image data output from a plurality of solid-state imaging devices driven synchronously based on one clock signal,
The image processing apparatus is
Detecting a delay of each of the image data output from the plurality of solid-state imaging devices;
Based on the detected delay of the image data, a signal instructing the plurality of memories to output the image data is generated so as to simultaneously output the respective image data held in the plurality of memories. An image processing method including steps. An image processing system comprising a plurality of cameras and an image output device that outputs image data output from the plurality of cameras to an image processing device that performs predetermined image processing in synchronization with each other,
The plurality of cameras are
Each of which has a solid-state imaging device that is driven synchronously based on one clock signal,
The image output device includes:
A plurality of memories each holding the image data output from the plurality of solid-state imaging devices;
A detection unit for detecting a delay of each of the image data output from the plurality of solid-state imaging devices;
Instructing the plurality of memories to output the image data based on the delay of the image data detected by the detection unit so that the image data held in the plurality of memories are simultaneously output. An image processing system comprising: a signal generation unit that generates a signal.

Images