JP2013025376A - Image drawing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image drawing device for efficiently performing rasterization processing while suppressing costs.SOLUTION: The image drawing device comprises: a drawing primitive identification information generation part for reading a primitive parameter of a vertex of a primitive drawn in a pertinent block from a first memory by a block unit, generating identification information of the primitive drawn on a front surface for respective pixels within the block, and writing it in a primitive number memory of a second memory; and a pixel data generation part for reading the primitive parameter of an object parameter from the first memory in an input order of a drawing instruction of the primitive by the block unit, and generating and writing pixel data for the pixels having the identification information of the object primitive in the primitive number memory. The drawing primitive identification generation part holds the identification information of the primitive which is drawn in the block and has the earliest input order as leading identification information during generation of the identification information, and the pixel data generation part reads the primitive parameter in the input order from the primitive of the leading identification information.

Description

  The present invention relates to an image drawing apparatus.

  In an image drawing apparatus such as three-dimensional graphics, an image to be drawn is regarded as a set of a plurality of primitives (for example, polygons such as triangles), and drawing processing is performed for each primitive. Also, a method called tiling architecture is known for image drawing processing (for example, Patent Document 1).

  According to the tiling architecture, the image drawing apparatus performs rasterization processing on primitives having pixels in tiles for each tile obtained by dividing a frame into a predetermined size (for example, 8 × 8 pixels). Since the size of the tile is small, the image drawing apparatus generates pixel data of each pixel in the tile by performing rasterization processing in units of tiles in a high-speed internal memory such as SRAM. Then, the image drawing apparatus writes the pixel data generated in the internal memory to the low-speed external memory. Since the SRAM has a higher access speed than the external memory, the tiling architecture makes the memory access more efficient and the rasterizing process is faster.

  Specifically, the image drawing apparatus performs a depth test and a primitive drawing process for each tile as the rasterizing process. The rasterization process is performed for each tile based on scene data having vertex parameters and setting information of a primitive to be drawn in the order of input of drawing commands. The vertex parameter includes, for example, coordinate information, depth information, color information, and the like of each vertex of the primitive, and the setting information includes, for example, a primitive transparency setting.

  Since scene data has a large capacity, it is generally stored in an external memory. Also, the setting information of each primitive in the scene data is held as difference information with respect to the setting information of the previous primitive in the input order of the drawing command. When acquiring the setting information of the target primitive, the image drawing apparatus adds the setting information of the newly read target primitive to the setting information of the primitive whose input order has already been read. For this reason, the primitive setting information needs to be read in accordance with the input order of primitive drawing commands.

  Specifically, the tile unit depth test and the primitive rendering process in the rasterization process are performed as follows. As a depth test, the image drawing apparatus determines whether or not each pixel of the target tile is a primitive drawn on the front surface based on a vertex parameter including depth information partially read from the scene data. At this time, the image drawing apparatus generates identification information indicating the primitive drawn on the front surface for each pixel of the target tile, and stores it in the primitive number memory of the internal memory.

  Subsequently, as a primitive drawing process, the image drawing apparatus reads the primitive vertex parameters and setting information indicated by the identification number from the scene data based on the identification information read from the primitive number memory, and generates pixel data. Since the vertex parameters and setting information of the primitive are stored in the external memory, it is desirable that the reading process is minimized. However, as described above, since the setting information is held as difference information based on the input order, the image drawing apparatus needs to read the vertex parameters of the primitive and the setting information in accordance with the input order of the drawing command.

  Therefore, the image drawing apparatus performs primitive drawing processing as follows. First, the image drawing apparatus searches the primitive number memory based on the identification information indicating the primitive whose input order is the first (0th). When identification information indicating the 0th primitive is detected, the image drawing apparatus reads the vertex parameter and setting information of the 0th primitive from the scene data, and generates pixel data of the corresponding pixel.

JP-A-5-135147

  However, in the above-described primitive drawing process, when the 0th primitive is not drawn on the target tile, identification information indicating the 0th primitive is not stored in the primitive number memory. Therefore, the primitive number memory search process using the identification information indicating the 0th primitive is useless.

  As described above, in the primitive number memory search process in the primitive drawing process, an inefficient search process may occur, which causes a reduction in drawing performance. On the other hand, there is a method of improving the drawing performance by parallelizing the search processing of the primitive number memory. However, depending on the degree of parallelization, the circuit scale of the image drawing apparatus increases and the cost increases.

  Therefore, the present invention provides an image drawing apparatus that efficiently performs rasterization processing while reducing costs.

According to a first aspect, a primitive parameter including coordinate information of a vertex of a primitive drawn in the block and depth information indicating a depth is read from the first memory in units of blocks obtained by dividing the frame into a plurality of primitive parameters. A drawing primitive identification information generating unit that generates identification information of the primitive drawn on the front surface and writes the primitive identification information in a primitive number memory of a second memory for each pixel in the block;
Primitive parameters including coordinate information and color information of the vertexes of the target primitive are read from the first memory in the input order of the rendering command of the primitive for each block, and the target primitive is identified in the primitive number memory. A pixel data generating unit that generates pixel data based on the primitive parameter and writes the pixel data to a frame buffer for the pixel having information;
The drawing primitive identification information generating unit holds the identification information of the primitive that is drawn in the block during generation of the identification information of the primitive and is the earliest in the input order as head identification information,
The pixel data generation unit reads the primitive parameters from the first memory in the input order from the primitive of the held head identification information.

  According to the first aspect, the rasterizing process is efficiently performed while suppressing the cost.

It is a figure which shows an example of a structure of the image drawing apparatus in this Embodiment. It is a figure showing an example of the block diagram of GPU. It is a figure which shows an example of the vertex parameter of a primitive. It is a figure showing an example of the block into which the frame was divided. It is a figure showing the example of a block diagram of a rendering process part and a rasterization process part. It is a figure showing an example of the primitive for drawing in the example of a 1st embodiment. It is a flowchart figure showing the flow of processing of a rendering processing part. It is a figure showing an example of the scene data before and behind sorting based on the specific example of FIG. It is a flowchart figure explaining a primitive process. It is a flowchart figure explaining the depth test of the example of a 1st embodiment. It is a hardware block diagram of the depth test processing unit in the first embodiment. It is a figure showing the default value of a depth memory, a primitive number memory, and a register. It is a figure showing each memory after the depth test of primitive P2. It is a figure showing each memory after the depth test of primitive P4. It is a figure showing each memory after the depth test of primitive P5. It is a flowchart figure explaining the drawing process of the example of 1st Embodiment. FIG. 3 is a hardware configuration example diagram of a drawing processing unit in the first embodiment. It is a figure explaining the drawing process in case search primitive number PN = 2. FIG. 10 is a second diagram illustrating a drawing process when a search primitive number PN = 2. It is a figure explaining the drawing process at the time of search primitive number PN = 2,4. It is a figure explaining the drawing process at the time of search primitive number PN = 4,5. It is a flowchart figure showing the process of the depth test of the example of a 2nd embodiment. It is a hardware structural example figure of the depth test process part in the example of a 2nd embodiment. It is a flowchart figure explaining the drawing process of 2nd Example. It is a hardware structural example figure of the drawing process part in a 2nd embodiment. It is a figure explaining the drawing process of the division area which has the identification number 2 in a register. It is a figure explaining the drawing process of the division area which has the identification numbers 4 and 5 in a register.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and equivalents thereof.

  FIG. 1 is a diagram illustrating an example of a configuration of an image drawing apparatus according to the present embodiment. In FIG. 1, the image drawing apparatus includes, for example, a CPU (Central Processing Unit) 101, a GPU (Graphics Processing Unit) 100, and an external memory 102. The external memory 102 is composed of, for example, a DRAM (Dynamic Random Access Memory), and stores a frame buffer and the like. In the figure, an application (not shown) passes three-dimensional data of a three-dimensional object composed of a plurality of primitives and a drawing command to the GPU 100. The GPU 100 generates pixel data of a two-dimensional image when the stereoscopic object is viewed from a predetermined viewpoint based on the three-dimensional data, and writes the pixel data in the frame buffer.

  FIG. 2 is a diagram illustrating an example of a block diagram of the GPU 100. The GPU 100 includes a command interpretation unit 10, a geometry processing unit 11, and a rendering processing unit 12. In the figure, for example, the command interpreter 10 of the GPU 100 reads a drawing command list from the external memory 102 and interprets the drawing command. In general, a three-dimensional object is expressed as a collection of a large number of primitives. Based on the drawing command, the geometry processing unit 11 generates a vertex parameter and setting information of a primitive that is a two-dimensional coordinate on the display screen, and passes it to the rendering processing unit 12.

  FIG. 3 is a diagram illustrating an example of vertex parameters of the primitive Pm generated by the geometry processing unit 11. The vertex parameters of the primitive Pm are coordinates of each vertex (pk1, y1), (x2, y2), (x3, y3) of the vertices pk1 to pk3 on the display screen DIS and RGB color levels which are image parameters at each vertex coordinate. It has tone values (hereinafter, color values) rgb1 to rgb3, and distances in the depth direction (hereinafter, depth values) z1 to z3. In the example of the figure, color values and depth values are illustrated as image parameters, but the image parameters may further include texture coordinate values for texture display and the like. Further, the setting information includes, for example, settings such as primitive transparency settings and whether or not to draw primitives (not shown).

  Returning to FIG. 2, subsequently, the rendering processing unit 12 generates pixel data having a color value for each pixel in the region defined by the vertex parameter of the primitive, based on the vertex parameter and the setting information. In the present embodiment, the rendering processing unit 12 scans in the X and Y directions in units of tiles (hereinafter referred to as blocks) obtained by dividing a frame into “8 pixels × 8 pixels”, for example, and displays primitives included in the blocks. Pixel data of the pixel to be defined is generated.

  FIG. 4 is a diagram illustrating an example of a block obtained by dividing the frame FB. The frame FB in the figure is divided into 12 blocks (3 × 4) of 8 pixels × 8 pixels. The block is not limited to a square as shown in the figure, and may be a rectangle or another polygon. In the present embodiment, the drawing process is sequentially performed from the lower left block b0 to the right adjacent block b1. However, the present invention is not limited to this example, and a plurality of blocks may be subjected to drawing processing in any order. Next, more detailed configurations of the rendering processing unit 12 and the rasterization processing unit 24 will be described.

  The upper diagram of FIG. 5 is a diagram illustrating an example of a block diagram of the rendering processing unit 12. The rendering processing unit 12 includes a setup unit 21, a tiling processing unit 22, a sort processing unit 23, and a rasterization processing unit 24. The setup unit 21 processes the vertex parameters of the primitive received from the geometry processing unit 11 for subsequent processing as necessary. The subsequent tiling processing unit 22 determines in which block each primitive is included based on the vertex parameter. As a result, for each primitive, scene data having vertex parameters and setting information and block information in which the primitive is drawn is generated. Since the scene data has a large capacity, it is stored in the external memory 102, for example.

  Subsequently, the sort processing unit 23 sorts the scene data, and generates scene data having the vertex parameters and setting information of the primitive drawn in the block for each block. Then, the rasterization processing unit 24 performs rasterization processing on a block basis based on the scene data.

  The lower diagram of FIG. 5 is a diagram illustrating an example of a block diagram of the rasterization processing unit 24. The primitive parameter reading unit 41 reads a vertex parameter including coordinate information and depth information of a primitive drawn in the processing target block from the external memory 102. Then, the depth test processing unit 42 performs a depth test based on the vertex parameter. Although details will be described later, at this time, the depth test processing unit 42 generates an identification number indicating a rendering target primitive for each pixel of the processing target block and writes the identification number in the primitive number memory PM. Since the primitive number memory PM does not require a large memory capacity, it is held in a high-speed internal memory such as an SRAM.

  Subsequently, the primitive number memory search unit 43 searches the primitive number memory PM for an identification number indicating the primitive to be drawn, thereby detecting a pixel on which the target primitive is drawn. Then, the primitive drawing processing unit 45 generates pixel data of the detected pixel based on the vertex parameter and setting information of the target primitive read by the primitive parameter reading unit 44.

[First Embodiment]
Next, the first embodiment will be described in detail based on a flowchart and specific examples.

  FIG. 6 is a diagram illustrating an example of the primitives P0 to P5 to be drawn in the first embodiment. In this specific example, six primitives P0 to P5 are drawn on the frame in a partially overlapping manner. In this example, primitive drawing commands are input in the order of primitives P0 to P5. In the figure, blocks b0 to b11 indicate respective areas of 8 × 8 pixels surrounded by dotted lines. In the present embodiment, the image drawing apparatus sequentially performs processing from the lower left block t0 to the upper right block t11 of the frame.

  FIG. 7 is a flowchart showing the processing flow of the rendering processing unit 12 (FIGS. 2 and 5) of the image drawing apparatus according to this embodiment. As described above, first, the setup processing unit 21 of the rendering processing unit 12 sequentially receives the vertex parameters and setting information of the primitive from the geometry processing unit 11, and if necessary, the subsequent tiling processing unit 22 and rasterization processing unit 24. Then, it is processed into a state that can be easily processed (S11). In addition, the setup processing unit 21 adds identification numbers to the primitives in the order in which drawing commands are input. For example, in the specific example of FIG. 6, the identification numbers such as primitive P0 “0”, primitive P1 “1”, primitive P2 “2”, primitive P3 “3”, primitive P4 “4”, and primitive P5 “5” Is added.

  Next, the tiling processing unit 22 of the rendering processing unit 12 determines by calculation which of the blocks b0 to b11 in the frame the pixel on which each primitive is drawn is included (S12). Further, the tiling processing unit 22 generates scene data having vertex parameters and setting information and block information on which the primitive is drawn for each primitive, and stores the scene data in the external memory 102 (S13, S14). However, since the vertex parameter of the primitive has a large data capacity, the vertex parameter in the present embodiment is stored in a primitive data buffer in the external memory 102 different from the scene data. In this case, address information in the primitive data buffer of vertex parameters of each primitive is stored in the scene data.

  Subsequently, the sort processing unit 23 of the rendering processing unit 12 sorts the scene data read from the external memory 102 in units of blocks (S15 and S16). The sorted scene data includes, for each block, primitive vertex parameters and setting information drawn in the block. As described above, the scene data in the present embodiment stores the vertex parameter storage address of each primitive in the primitive data buffer. For this reason, the data capacity to be sorted is suppressed, and the speed of the sorting process is improved.

  FIG. 8 is a diagram illustrating an example of scene data SD1 and SD2 before and after sorting based on the specific example of FIG. The scene data SD1 at the top of the figure is an example of scene data before sorting. The scene data SD1 before sorting has vertex parameters and setting information in the order of input of the drawing command (P0 to P5) and block information on which the primitive is drawn for each primitive drawn on the frame. The setting information is held as difference information with respect to the sum of the setting information of the previous primitive in the input order of the drawing command.

  Specifically, the scene data SD1 before sorting is, for example, NO. For the primitive P4 of No. 4, the setting information of the difference between the vertex parameter storage address of the primitive P4 in the primitive data buffer PDB and the total setting information of the primitives P0 to P3, and the information b4 and b8 of the block in which the primitive P4 is drawn , B9.

  The scene data SD2 in FIG. 8 is an example of the sorted scene data. The sorted scene data SD2 has, for each block, the vertex parameters and setting information of the primitive drawn in the block in the order of input of the drawing command. Similarly, for the scene data SD2 after sorting, the setting information is held as difference information with respect to the sum of the setting information of the preceding primitives in the input order of the drawing command. Here, the scene data SDx of the block b8 after sorting is illustrated and described specifically.

  In the specific example of FIG. 6, primitives P2, P4, and P5 are drawn in the block b8, and the input order of the drawing commands is the primitives P2, P4, and P5. For this reason, the scene data SDx first has setting information of the primitives P0 to P2 and the storage address of the vertex parameter of the primitive P2 in the primitive data buffer PDB. The scene data SDx has the setting information of the primitives P3 to P4 and the storage address of the vertex parameter of the primitive P4 in the primitive data buffer PDB for the primitive P4 having the next highest input order. The same applies to the primitive P5.

  Therefore, when acquiring the setting information of the primitive P4, the image drawing apparatus adds the setting information of the primitive P4, which is difference information, to the information obtained by adding the setting information of the primitives P0 to P3. As described above, the image drawing apparatus needs to read the primitive vertex parameters and the setting information in accordance with the input order of the drawing commands.

  Returning to the flowchart of FIG. 7, after the scene data is sorted, the rasterization processing unit 24 of the rendering processing unit 12 performs primitive processing on each primitive drawn in the processing target block in the order of input of the drawing command (S18). And a drawing process (S19). First, the primitive processing (S18) will be described based on the flowchart of FIG.

  FIG. 9 is a flowchart for explaining the primitive processing. As the primitive processing, the rasterization processing unit 24 generates an identification number indicating the primitive drawn on the front surface for each pixel of the processing target block, and writes the identification number in the primitive number memory PM.

  First, the rasterization processing unit 24 reads a primitive list drawn in the processing target block from the scene data in the external memory 102 (S21). Subsequently, the rasterization processing unit 24 performs the processes S22 and S23 in the input order of the drawing command for all primitives drawn in the processing target block. As processing S <b> 22, the rasterization processing unit 24 reads out coordinate information and depth information from the vertex parameters of the primitive to be processed (target primitive) from the external memory 102. Then, the rasterization processing unit 24 performs a depth test on each pixel on which the target primitive in the processing target block is drawn (S23). Next, the depth test (S23) will be described based on the flowchart of FIG.

  FIG. 10 is a flowchart for explaining the depth test. In the present embodiment, the smaller the depth value, the more the front surface is located. Therefore, at first, the default depth memory ZB has a large depth value for each pixel. Then, the rasterization processing unit 24 reads the depth value Dm of a certain pixel (target pixel) among the pixels in which the target primitive is drawn from the depth memory ZB (S31). Subsequently, the rasterization processing unit 24 calculates and acquires the depth value D of the target pixel based on the coordinate information and the depth value of the vertex of the target primitive (S32), and compares it with the depth value Dm (S33).

  When the depth value D of the target pixel is smaller than the depth value Dm (YES in S33), the rasterization processing unit 24 writes the depth value D to the address corresponding to the target pixel in the depth memory ZB (S34). Subsequently, the rasterization processing unit 24 writes an identification number indicating the target primitive to an address corresponding to the target pixel in the primitive number memory PM (S35). Then, in the case of the first writing to the primitive number memory PM of the processing target block (YES in S35), the rasterization processing unit 24 in the present embodiment holds the identification number in the register R1 (S36). . Accordingly, the register R1 is not updated in the second and subsequent writes to the primitive number memory PM of the block to be processed (NO in S35).

  On the other hand, when the depth value D of the target pixel is larger than the depth value Dm (NO in S33), it means that the target primitive is not a primitive drawn in front of the target pixel. Therefore, the rasterization processing unit 24 does not write to the depth memory ZB and the primitive number memory PM, and performs a depth test on the next pixel of interest (S31 to S37).

  When the depth test is performed for all pixels in which the target primitive in the processing target block is drawn, the primitive number memory PM stores the identification number of the primitive drawn in the foreground for each pixel in the processing target block. . The register R1 holds an identification number that is first written in the primitive number memory PM, that is, an identification number that indicates a primitive that is drawn in the processing target block and that has the earliest input order.

  FIG. 11 is a diagram illustrating a hardware configuration example of the depth test processing unit 42 according to the present embodiment. The depth test processing unit 42 in the present embodiment includes a depth calculation unit 51, memory address conversion units 52 and 54, a depth test unit 53, a write determination unit 55, a primitive number memory PM, a depth memory ZB, a register R1, and timing adjustment. Registers t1 to t5. Timing adjustment registers t1 to t5 are provided to match the processing timing. The depth calculation unit 51 calculates and acquires the depth value D of the target pixel based on the vertex parameter, and also sends the coordinate information (x, y) of the target pixel to the memory address conversion unit 52 and the coordinate information (x, y). And the depth value D is passed to the timing adjustment register t1. The memory address conversion unit 52 converts the coordinate information (x, y) into the address of the depth memory ZB, reads the depth value Dm of the target pixel from the depth memory ZB, and passes it to the depth test unit 53.

  Then, the depth test unit 53 compares the depth value D with the depth value Dm read from the depth memory ZB. When the depth value D is smaller than the depth value Dm, the depth test unit 53 outputs the coordinate information (x, y) of the target pixel output from the timing adjustment register t3 to the memory address conversion unit 54. The depth test unit 53 outputs the depth value D to the timing adjustment register t4 and the identification number of the target primitive to the timing adjustment register t5. Then, the depth value D is written to the address of the depth memory ZB corresponding to the target pixel, and the identification number is written to the address of the primitive number memory PM corresponding to the target pixel output from the memory address conversion unit 54. Further, the write determination unit 55 writes the identification number in the register R1 when it is the first write to the primitive number memory PM.

  In the present embodiment, the depth test is performed in parallel on each of the M pixels (four in the present embodiment) included in the segmented region. Therefore, the primitive number memory PM is divided into M pieces corresponding to the parallel unit in which the corresponding pixel is processed. Here, the depth test process will be described based on a specific example of FIG. Here, among the blocks b0 to b11, the block b8 will be exemplified and described as a processing target block. First, the initial value of each memory at the time of the depth test of the processing target block will be described.

  FIG. 12 is a diagram illustrating values held as default values in the depth memory ZB, the primitive number memory PM, and the registers R1 and R2 in the depth test. Note that the register R2 (R20 to R2f) in the figure is a register used in the second embodiment, and will be described later in the second embodiment. Initially, the maximum depth value “1.0” is stored as a default value at an address corresponding to each pixel of the depth memory ZB. First, “6” which is the total number of primitives (Max value) drawn in the frame is stored as a default value in the address corresponding to each pixel of the primitive number memory PM and the register R1. The input order of the drawing commands of the primitives P2, P4, and P5 drawn in the block b8 is P2, P4, and P5. Therefore, the rasterization processing unit 24 first performs a depth test on the primitive P2.

  FIG. 13 is a diagram illustrating the depth memory ZB, the primitive number memory PM, and the register R1 after the depth test of the primitive P2 in the block b8. In this example, the processing will be described with a pixel g1 on which the primitive P2 is drawn as a target pixel. The rasterization processing unit 24 reads the depth value Dm “1.0 (default value)” of the target pixel g1 from the depth memory ZB (S31 in FIG. 10). Subsequently, the rasterization processing unit 24 calculates and acquires the depth value 0.1 of the target pixel g1 based on the vertex coordinate information and the depth value of the primitive P2 (S32).

  The depth value D “0.1” of the target pixel is smaller than the default depth value Dm “1.0” read from the depth memory ZB (YES in S33). Accordingly, the rasterization processing unit 24 writes the depth value 0.1 to the address corresponding to the target pixel of the depth memory ZB (S34), and the identification number indicating the primitive P2 at the address corresponding to the target pixel of the primitive number memory PM. “2” is written (S35). In this case, since this is the first writing in the primitive number memory PM (YES in S36), the rasterization processing unit 24 holds the identification number “2” in the register R1 (S37).

  The rasterization processing unit 24 similarly compares the depth values for other pixels on which the primitive P2 in the block b8 is drawn (S33), and updates the depth memory ZB and the primitive number memory PM according to the result (S34, S35). At this time, since it is not the first writing of the primitive number memory PM (NO in S36), the rasterization processing unit 24 does not update the register R1. As a result, as shown in FIG. 13, 0.1 is written in the address of the depth memory ZB corresponding to the pixel on which the primitive P2 is drawn, and the identification number “2” is written in the address of the primitive number memory PM. When the depth test of the primitive P2 is completed, the rasterization processing unit 24 similarly performs the depth test on the primitive P4 having the next highest input order.

  FIG. 14 is a diagram illustrating the depth memory ZB, the primitive number memory PM, and the register R1 after the depth test of the primitive P4 in the block b8. The depth value of the pixel on which the primitive P4 obtained based on the coordinate information and depth value of each vertex of the primitive P4 is drawn is 0.3 or 0.4, and the depth value of the primitive P2 written to the depth memory ZB Greater than 0.1 (NO in S33). This indicates that the primitive P4 is located behind the primitive P2. Accordingly, the depth value 0.3 or 0.4 is written to the address of the depth memory ZB corresponding to the pixel in which the primitive P4 is drawn and the primitive P2 is not drawn (S34), and the primitive corresponding to the pixel is drawn. The identification number “4” indicating the primitive P4 is written in the address of the number memory PM (S35). Further, the register R1 holds the identification number “2” (NO in S36). When the depth test of the primitive P2 is completed, the rasterization processing unit 24 similarly performs the depth test on the primitive P5 having the next highest input order.

  FIG. 15 is a diagram illustrating the depth memory ZB, the primitive number memory PM, and the register R1 after the depth test of the primitive P5 in the block b8. The depth value acquired based on the coordinate information and depth value of each vertex of the primitive P5 is 0.9, which is larger than the depth values of the primitives P2 and P4. This indicates that the primitive P5 is located behind the primitives P2 and P4. Accordingly, the primitives P2 and P4 are not drawn, the depth value 0.9 is written to the address of the depth memory ZB corresponding to the pixel on which the primitive P5 is drawn (S34), and the address of the primitive number memory PM corresponding to the pixel is written. The identification number “5” indicating the primitive P5 is written in (S35). Further, the register R1 holds the identification number “2” (NO in S36).

  As described above, the rasterization processing unit 24 performs the depth test (FIG. 10) in the order of input of the rendering command for all primitives rendered in the processing target block as all primitive processing (S18 in FIGS. 9 and 7). As a result, the primitive number memory PM stores an identification number indicating the primitive drawn on the front surface for each pixel of the processing target block. The register R1 holds an identification number indicating a primitive drawn in the processing target block and having the earliest input order. After all primitive processing, the rasterization processing unit 24 performs drawing processing of the processing target block (S19 in FIG. 7).

  FIG. 16 is a flowchart for explaining a primitive drawing process. The rasterization processing unit 24 in the present embodiment has completion flags fl0 to flf for each of N divided areas obtained by further dividing the processing target block. In addition, the rasterization processing unit 24 in the present embodiment performs processing of each of the M pixels included in the segmented region in parallel.

  First, the rasterization processing unit 24 sets the identification number held in the register R1 in the depth test of FIG. 10 to the search primitive number PN (S41). As a result, the primitive number memory PM is searched for not from the first (0th) primitive in the input order but from the primitive drawn in the processing target block and having the earliest input order. The rasterization processing unit 24 sets an initial value 0 to the completion flags fl0 to flf corresponding to the N segment areas n0 to nf, respectively (S42). Subsequently, the rasterization processing unit 24 sets the total number (Max value) of primitives drawn in the frame as an initial value to the next candidate search primitive number (next search primitive number nPN) (S43).

  Subsequently, the rasterization processing unit 24 sequentially performs processes S44 to S55 for each divided area. First, the rasterization processing unit 24 acquires the number (hereinafter, region number ar) of the segmented region (target segmented region) to which the target pixel belongs based on the coordinate information (x, y) of the target pixel (S44). Then, it is determined whether or not the completion flag fl of the noticed segment area is 0 (S45). When the completion flag fl is 1 (NO in S45), it means that the pixel data of all the pixels in the target segment area have been generated. In this case, the rasterization processing unit 24 ends the process in the attention segment area, and continues the process from process S44 for the next attention segment area.

  On the other hand, when the completion flag fl is 0 (YES in S45), the attention segment area indicates that the pixel data has pixels that have not been generated. Therefore, the rasterization processing unit 24 sets 1 to the completion flag fl (S46), and performs processes S47 to S55 in parallel for each of the M pixels (hereinafter referred to as each pixel of interest) included in the region of interest.

  First, the rasterization processing unit 24, for each target pixel, the identification number (PM [mn] [ar]) of the primitive number memory PM corresponding to the target pixel matches the search primitive number PN set in step S41. It is determined whether or not (S47). If they match (YES in S47), it means that the primitive indicated by the search primitive number PN is drawn on the target pixel. Therefore, the rasterization processing unit 24 reads the primitive vertex parameter and setting information indicated by the search primitive number PN from the external memory 102 (S48). If the vertex parameter and setting information of the search primitive number PN have already been read, no new reading process is performed. The rasterization processing unit 24 acquires coordinate information of the target pixel (S49), acquires pixel data of the target pixel based on the vertex parameter (S50), and stores it in the internal memory (S51).

  On the other hand, if they do not match (NO in S47), it means that the primitive drawn on the target pixel is not the primitive indicated by the search primitive number PN. Therefore, the rasterization processing unit 24 determines whether or not the search primitive number PN is smaller than the identification number (PM [mn] [ar]) of the target pixel included in the primitive number memory PM (S52). When the search primitive number PN is equal to or greater than the identification number (NO in S52), the primitive drawn in the target pixel is in the input order before the primitive indicated by the search primitive number PN, and the generation of the pixel data is finished. Means that. Therefore, the rasterization processing unit 24 does not perform the processes S53 to S55.

  On the other hand, when the search primitive number PN is smaller than the identification number (YES in S52), the primitive drawn in the target pixel is later in input order than the primitive indicated by the search primitive number PN, and the pixel data is not generated. Means that. Therefore, the rasterization processing unit 24 updates the completion flag fl of the noticed segment area with 0 indicating that pixel data has not been generated (S53). Subsequently, the rasterization processing unit 24 determines whether or not the next retrieval primitive number nPN is larger than the identification number (PM [mn] [ar]) (S54).

  When the next search primitive number nPN is equal to or smaller than the identification number (NO in S54), the primitive indicated by the next search primitive number nPN means that the input order is the same as or ahead of the primitive drawn on the target pixel. In this case, since the next search primitive number nPN already holds an identification number indicating the primitive with the next highest input order, the rasterization processing unit 24 does not update the next search primitive number nPN. On the other hand, when the next search primitive number nPN is larger than the identification number (YES in S54), the primitive indicated by the next search primitive number nPN means that the input order is later than the primitive drawn in the target pixel. Therefore, the rasterization processing unit 24 updates the next retrieval primitive number nPN with the identification number (S55).

  When the processing S44 to S55 is performed with the search primitive number PN being maintained for all the divided areas in the processing target block, all pixels having the same identification number as the search primitive number PN are stored in the primitive number memory PM. It is detected (search process), and pixel data of the pixel is generated. The next retrieval primitive number nPN holds an identification number indicating a primitive drawn in the processing target block and indicating the primitive in the input order next to the retrieval primitive number PN.

  Further, 1 is held in the completion flag fl of the segmented area where generation of pixel data of all pixels is completed, and 0 is held in the completion flag fl of the segmented area where generation of pixel data of all pixels is not completed. Since the generation of pixel data has already been completed for the segmented region with the completion flag fl set to 1, it is excluded from the search processing of the primitive number memory PM having the same identification number as the subsequent search primitive number PN. Thereby, useless search processing is omitted, and the search efficiency of the primitive number memory PM is improved.

  When the processes S44 to S55 are performed for all the divided areas, the rasterization processing unit 24 subsequently determines whether or not the next search primitive number nPN and the Max value match (S56). If they do not match (NO in S56), this means that the next retrieval primitive number nPN has been updated, that is, there is a primitive for which drawing processing has not been completed. Therefore, the rasterization processing unit 24 sets the next retrieval primitive number nPN to the retrieval primitive number PN (S57), initializes the next retrieval primitive number nPN with the Max value (S43), and sets all the divided areas whose completion flag fl is 0. Processes S44 to S55 are performed on the target.

  On the other hand, if the next retrieval primitive number nPN matches the Max value (YES in S56), it means that the drawing processing of all primitives drawn in the processing target block has been completed. Therefore, the rasterization processing unit 24 writes the pixel data of the processing target block stored in the internal memory to the frame buffer of the external memory 102 (S58), and ends the drawing process. When the drawing process of the processing target block in FIG. 16 (S19 in FIG. 7) ends, the rendering processing unit 12 performs the rasterization process (S18, S19 in FIG. 7) with the next block as the processing target block. When rasterization processing is performed for all blocks, the rasterization processing unit 24 ends the frame rendering processing.

  FIG. 17 is a diagram illustrating a hardware configuration example of the primitive drawing processing unit 44 (FIG. 5) according to the present embodiment. The primitive drawing processing unit 44 in this embodiment includes a coordinate generation unit 61, a memory address conversion unit 62, a primitive number memory PM, a comparison unit 63, a next search primitive number acquisition unit 64, a register R1, a completion flag fl, and timing adjustment. Registers t11 to t14.

  The coordinate generation unit 61 sequentially generates the coordinate information (x, y) of the pixels in the segmented region and outputs them to the memory address conversion unit 62 and the timing adjustment register t11. The memory address conversion unit 62 converts the coordinate information (x, y) into the address of the primitive number memory PM, reads the identification number of the primitive number memory PM corresponding to the pixel of interest, and compares the comparison unit 63 and the next search primitive number. The data is output to the acquisition unit 64. Then, the comparison unit 63 compares the identification number (search primitive number PN) held in the register R1 with the identification number, and instructs to acquire pixel data if they match. At this time, in addition to the instruction to acquire pixel data, the identification number indicating the target primitive from the register R1 via the timing adjustment register t14 and the coordinate information (x, y) of the target pixel from the timing adjustment register t13. Is output.

  The next retrieval primitive number acquisition unit 64 sets 1 to the completion flag fl when an identification number larger than the retrieval primitive number PN is not stored in the primitive number memory PM area corresponding to the divided area. Then, the coordinate generation unit 61 does not generate coordinates for a segmented area having 1 in the completion flag fl. The next search primitive number acquisition unit 64 acquires the next search primitive number nPN as the next search primitive number nPN from among the primitives to be drawn thereafter, and acquires the identification number indicating the next search primitive number nPN. When the number nPN matches the Max value, the search process is terminated. Next, the drawing process will be described based on the specific example of FIG.

  FIG. 18 is a diagram for explaining a drawing process when “search primitive number PN = 2”. In the lower left diagram NB of the same figure, 16 (N) divided areas n0 to nf each having 4 pixels are represented by bold lines. Numbers 0 to 3 assigned to the pixels in the divided areas n0 to nf represent pixel positions in the divided areas corresponding to four (M) parallel units. In the present embodiment, the rasterization processing unit 24 performs the processing of the divided areas in the order indicated by the arrow ya, for example.

  First, the rasterization processing unit 24 sets the identification number “2” held in the register R1 to the search primitive number PN (S41), and sets 0 to completion flags fl0 to flf corresponding to each segmented area (S41). S42). In addition, the rasterization processing unit 24 initializes the next retrieval primitive number nPN by setting the Max value “6” (S43), and obtains the region number 0 of the attention divided region n0 (S44). Then, the rasterization processing unit 24 compares each identification number in the primitive number memory pm0 corresponding to each pixel (target pixel) in the target segmented region n0 in FIG. 18 with the search primitive number PN “2”. Thus, the pixel having the identification number “2” is searched for in the primitive number memory pm0.

  In FIG. 18, the pixel having the identification number “2” is not detected from the primitive number memory pm0 corresponding to the attention divided area n0 (NO in S47). Further, since the identification number “5” is larger than the search primitive number PN “2” (YES in S52), the completion flag fl0 is set to 0 (S53). Since the identification number “5” is smaller than the next retrieval primitive number nPN “6” (YES in S54), “5” is set to the next retrieval primitive number nPN (S53).

  As described above, the rasterization processing unit 24 according to the present embodiment performs the search processing in order from the search primitive number PN “2”, not from the search primitive number PN “0”. As a result, in the case of the block in which the 0th primitive is not drawn, such as the block b8, unnecessary search processing (search processing of the search primitive number PN “0”) is omitted, and the search processing of the primitive number memory PM becomes efficient. Is done.

  The left diagram of FIG. 19 is a diagram for explaining the rendering process of the segmented region n1 when “search primitive number PN = 2”. Subsequently, the rasterization processing unit 24 searches the corresponding primitive number memory pm1 for the pixel having the identification number “2” in the same manner using the divided region n1 as the target divided region. In the figure, identification numbers “4” and “5” are stored in the primitive number memory pm1 (NO in S47). Since the identification numbers “4” and “5” are larger than the search primitive number PN “2” (YES in S52), the completion flag fl1 is set to 0 (S53). Since the identification number “4” is smaller than the next retrieval primitive number nPN “5” (YES in S54), “4” is set in the next retrieval primitive number nPN (S55).

  The right diagram of FIG. 19 is a diagram for explaining the rendering process of the segmented region n9 when “search primitive number PN = 2”. For example, when the segmented area n9 is the focused segmented area, the rasterization processing unit 24 searches for the pixel having the identification number “2” from the corresponding primitive number memory pm9. As shown in the drawing, the identification number “2” is stored in the primitive number memory pm9 at addresses corresponding to all the pixels in the segmented region n9 (YES in S47). For this reason, pixel data of all the pixels in the attention segmented region pm9 is generated (S48 to S51), and 1 is set to the completion flag fl9. At this time, the next retrieval primitive number nPN is not updated.

  The left diagram of FIG. 20 is a diagram for explaining the rendering process when the rendering process for all the divided areas is completed in “search primitive number PN = 2”. When all the divided areas n0 to nf are processed, the register R1 indicates a primitive drawn in the processing target block, which is the primitive in the input order next to the primitive indicated by the search primitive number PN “2”. The identification number “4” is stored. Then, for the divided areas n9 to nb in which the identification number “2” is stored in the primitive number memory corresponding to all the pixels, 1 is set in the completion flags fl9 to flb.

  When the processing of the search primitive number PN = 2 is completed, the rasterization processing unit 24 performs the same processing using the next search primitive number nPN “4” as the search primitive number PN. At this time, since the generation of the pixel data of all the pixels is completed in the divided areas n9 to nb having 1 in the completion flag, it is excluded from the search area for the pixel having the identification number “4” in the primitive number memory PM. Become. This eliminates unnecessary search processing and improves the search efficiency of the primitive number memory PM.

  The right diagram of FIG. 20 is a diagram for explaining the rendering process when “search primitive number PN = 4”. The rasterization processing unit 24 sequentially searches for the pixel having the identification number “4” from the corresponding primitive number memories pm0 to pmf for the segmented areas whose completion flags fl0 to flf are 0, and the pixel data of the detected pixels Is generated. As a result, for example, for the segmented region n1, a pixel having the identification number “4” is detected from the corresponding primitive number memory pm1, and pixel data of the pixel is generated (S48 to S51). Further, 0 is set in the completion flag fl1 (YES in S52, S53), and the next retrieval primitive number nPN remains “5” updated during the processing of the segmented area n0 (NO in S54).

  The left diagram of FIG. 21 is a diagram for explaining the rendering process when the rendering process for all the divided areas is completed in “search primitive number PN = 4”. When all the divided areas n0 to nf are processed, the register R1 stores the primitive identification number “5” in the next input order. For the divided areas fl2, fl3, fl9 to flb in which either or both of the identification numbers “2” and “4” are stored in the primitive number memory corresponding to all the pixels, 1 is set in the completion flag fl. Thus, it is excluded from the scope of subsequent search processing.

  The right part of FIG. 21 is a diagram for explaining the drawing process when the drawing process for all the divided areas is finished in “search primitive number PN = 5”. When all the divided areas n0 to nf are processed, all the pixels having the search primitive number PN “5” in the corresponding primitive number memory are searched, and pixel data is generated. As a result, the drawing processing of all primitives drawn in the processing target block is completed, and the completion flags fl0 to flf of all the divided areas are updated to 1.

  In this case, since the primitive number memories pm0 to pmf do not have an identification number larger than the retrieval primitive number PN “5” (NO in S52), the next retrieval primitive number nPN is an initial value of the Max value “6”. Not updated. Thereby, the rasterization processing unit 24 considers that the rendering processing of all primitives rendered in the processing target block has been completed, and writes the pixel data stored in the internal memory to the frame buffer of the external memory 102 (S56).

  As described above, the image drawing apparatus according to the present embodiment stores, in the block unit, the vertex parameter (primitive parameter) including the coordinate information of the vertex of the primitive drawn in the block and the depth information indicating the depth in the first memory. The identification number (identification information) of the primitive drawn on the front surface is generated for each pixel in the target block based on the vertex parameter, read from (external memory), and stored in the primitive number memory of the second memory (internal high-speed memory) Write. At this time, during the generation of the primitive identification number, the image drawing apparatus holds the primitive identification number that is drawn in the target block and that has the earliest input order as head identification information (head identification information). For example, when generating the primitive identification number, the image drawing apparatus reads the vertex parameters of the primitive in the order of input of the drawing command, and holds the identification number that is initially written in the primitive number memory as the head identification information.

  Then, the image drawing apparatus reads, from the first memory, the vertex parameters including the coordinate information and the color information of the vertex of the target primitive in the input order from the primitive of the head identification information, and also stores the target primitive in the primitive number memory. Pixel data is generated based on the vertex parameter and written to the frame buffer for the pixel having the identification number.

  As a result, the image drawing apparatus can search for a pixel having the identification number of the target primitive in the primitive number memory from the primitive drawn in the processing target block and having the earliest input order. As a result, when the 0th primitive in the input order is not drawn in the processing target block, unnecessary search processing of the primitive number memory (of the 0th primitive) can be omitted. As a result, the search process of the primitive number memory is performed more efficiently.

  In addition, the image drawing apparatus divides the block into a plurality of divided areas, and when searching for a pixel having the identification number of the target primitive in the primitive number memory, the primitive number corresponding to the divided area in which pixel data of all the pixels has been generated The memory area is excluded from the scope of search processing. Thereby, the image drawing apparatus can limit the target area at the time of searching the primitive number memory, and can improve the search efficiency. Further, the image drawing apparatus parallelizes the processing for a plurality of pixels in the partitioned area. As a result, the image drawing device can make the primitive number memory search process more efficient while reducing the degree of parallelization of the image drawing devices and reducing the circuit scale.

[Second Embodiment]
The image drawing apparatus in the first embodiment holds the identification number of the primitive that is drawn in the processing target block and is the earliest in the input order, whereas in the second embodiment, The image drawing apparatus holds, for each partitioned area of the processing target block, an identification number of a primitive that is drawn in the partitioned area and that has the earliest input order. As a result, the image drawing apparatus can more efficiently search the primitive number memory. Hereinafter, description will be given based on a flowchart.

  FIG. 22 is a flowchart showing the depth test process in the second embodiment. In the figure, the processing (S61 to S65) up to writing to the primitive number memory is the same as that in the first embodiment (S31 to S35). When the depth value D of the pixel of interest is smaller than the depth value Dm of the pixel of interest read from the depth memory ZB (YES in S63), the rasterization processing unit 24 in the second embodiment is a partitioned region including the pixel of interest. Is the first write to the primitive number memory PM corresponding to (YES in S66), the identification number is held in the register R2 [area number] corresponding to the partition area (S67).

  When the depth test is performed on all primitives drawn in the processing target block, the identification number of the primitive drawn on the front surface is stored in the primitive number memory PM for each pixel of the processing target block. Further, in the register R2 of each segmented area, the identification number written first in the primitive number memory PM area corresponding to each segmented area, that is, the primitive drawn in the segmented area and having the earliest input order Is stored.

  FIG. 23 is a diagram illustrating a configuration example of hardware in the depth test processing unit 42 according to the present embodiment. Except for the register R2 and the write determination unit 75, the second embodiment is the same as the first embodiment. In the present embodiment, when the depth value D of the target pixel is smaller than the depth value Dm read from the depth memory ZB, the writing determination unit 75 determines whether or not the writing is the first time in the segmented region including the target pixel. Determine whether. In the case of the first writing, an identification number indicating the target primitive is written in the register R2 corresponding to the divided area. Here, the depth test process in the present embodiment will be described based on a specific example of FIG.

  The right diagram of FIG. 13 shows registers R20 to R2f after the depth test of the primitive P2 related to the block b8 in the second embodiment. The depth memory ZB and the primitive number memory PM are the same as those in the first embodiment. As a result of the depth test of the primitive P2, the identification number “2” is held in the registers R24 to R2f of the divided area including the pixel on which the primitive P2 is drawn. 14 shows the registers R20 to R2f after the depth test of the primitive P4 to be performed subsequently. As a result of the depth test of the primitive P4, the identification number “4” is written into the registers R21 to R23 of the partitioned area having the pixel in which the primitive P4 is drawn and first written to the corresponding primitive number memory. .

  The right diagram of FIG. 15 shows registers R20 to R2f after the depth test of the primitive P5 to be performed subsequently. At the time of the depth test of the primitive P5, the primitive number memory corresponding to each divided area has already been written. Therefore, none of the registers R20 to R2f is updated. The rasterization processing unit 24 efficiently performs subsequent primitive drawing processing based on the registers R20 to R2f based on the depth test. Next, the primitive drawing process will be described with reference to a flowchart.

  FIG. 24 is a flowchart for explaining a primitive drawing process according to the second embodiment. In the figure, the rasterization processing unit 24 first sets and initializes the Max value to the search primitive number PN and the next search primitive number nPN (S71). Then, when the identification number of the corresponding register R20 to R2f is smaller than the search primitive number PN (S72, YES in S73), the rasterization processing unit 24 sets the identification number to the search primitive number PN for each divided region. At the same time, the area number ar of the segmented area is held as the attention area number Sar (S74).

  When the processes S72 to S74 are performed for all the divided areas, the identification number having the smallest value (fastest input order) among the identification numbers of the registers R20 to R2f is set as the search primitive number PN. The area number ar of the divided area corresponding to the registers R20 to R2f having the identification number is held as the attention area number Sar.

  Subsequently, the rasterization processing unit 24 compares the search primitive number PN with the Max value (S75). If they do not match (YES in S75), the rasterization processing unit 24 sets the partitioned area indicated by the focused area number Sar as the focused partitioned area. Then, as in the first embodiment, the rasterization processing unit 24 matches the search primitive number PN with the corresponding primitive number memory in parallel for each of the M pixels (hereinafter referred to as the target pixel) of the target segment area. The target pixel having the identification number is searched (YES in S76), and pixel data is generated (S76 to S80).

  If the search primitive number PN and the identification number (PM [mn] [Sar]) of the primitive number memory PM corresponding to the target pixel do not match (NO in S76), is the search primitive number PN smaller than the identification number? It is determined whether or not (S81). When the search primitive number PN is smaller than the identification number (YES in S81) and the next search primitive number nPN is larger than the identification number (YES in S82), the rasterization processing unit 24 assigns the identification number to the next search primitive number nPN. Set (S83). As a result, the next retrieval primitive number nPN holds an identification number indicating a primitive drawn in the attention segment area and next to the retrieval primitive number PN in the input order earlier.

  When the processing of the attention segment area (S76 to S83) is finished, the rasterization processing unit 24 writes the next retrieval primitive number nPN in the register R2 [Sar] corresponding to the attention classification area (S84). As a result, the register R2 [Sar] corresponding to the attention segment area is updated with an identification number indicating a primitive drawn in the attention segment area and having the next primitive in the input order. Then, returning to the process S71, similarly, the rasterizing process sets the identification number having the smallest value (fastest input order) among the identification numbers of the registers R20 to R2f to the search primitive number PN, and the identification number The segmented area corresponding to the registers R20 to R2f having the is set as the attention area.

  Then, if the search primitive number PN does not match the Max value (YES in S75), the rasterization processing unit 24 performs the same process on the attention segment area (S75 to S84). On the other hand, when the search primitive number PN matches the Max value (NO in S75), it means that the drawing processing of all the primitives drawn in the processing block is completed. Therefore, the rasterization processing unit 24 writes the pixel data of the processing target block stored in the internal memory to the frame buffer of the external memory 102 (S85), and ends the drawing process.

  FIG. 25 is a diagram illustrating a hardware configuration example of the drawing processing unit 44 (FIG. 5) according to the present embodiment. In the present embodiment, the drawing processing unit 44 does not have the completion flag fl, but has a register R2 for each segmented area. Further, in the present embodiment example, unlike the first embodiment example, the coordinate generation unit 81 detects the smallest identification number from the register R2 (R20 to R2f) for each divided region, and the identification number is obtained. The coordinate information (x, y) of the divided areas is sequentially generated and output to the memory address conversion unit 62. Further, the next retrieval primitive number acquisition unit 84 updates the register R2 corresponding to the attention segment area with an identification number indicating the primitive with the earliest input order among the primitives drawn thereafter in the attention segment area. Next, the drawing process will be described based on the specific example of FIG.

  FIG. 26 is a diagram illustrating the drawing process when “search primitive number PN = 2”. The rasterization processing unit 24 sets the identification number having the smallest value among the identification numbers held in the registers R20 to R2f, that is, the identification number “2” indicating the primitive with the earliest input order to the search primitive number PN. Then, the partitioned area n4 holding the identification number in the registers R20 to R2f is set as the focused partitioned area. Then, the rasterization processing unit 24 searches for the pixel having the identification number “2” from the primitive number memory pm4 corresponding to the attention division area n4 (YES in S76), and generates pixel data of the pixel (S77 to S80). ).

  In this case, the primitive number memory PM area corresponding to the divided areas n4 to nf corresponding to the registers R24 to R2f having the identification number “2” always includes a pixel having the identification number “2”. The rasterization processing unit 24 always performs a search process for a pixel in which the identification number “2” is stored in the primitive number memory PM area, targeting the primitive number memory PM area having the identification number “2”. Thereby, the search efficiency of the primitive number memory PM is improved.

  The rasterization processing unit 24 performs pixel data generation processing, and identifies primitives that are drawn in the corresponding divided areas n4 to nf in the registers R24 to R2f and have the next highest input order. The number “4” is written and updated (S84). As a result, the registers R20 to R2f always hold an identification number indicating a primitive drawn in the corresponding segmented area and having the earliest input order.

  The right diagram of FIG. 26 is a diagram for explaining the drawing process when the drawing process of the segmented area having the identification number “2” in the registers R20 to R2f is completed. As described above, the registers R20 to R2f hold the identification numbers “4” and “5” indicating the primitives drawn in the divided area and indicating the next primitive in the next input order. In addition, the Max value “6” is set in the divided areas n9 to nb in which only the primitive P2 is drawn, that is, the registers R29 to R2b in the divided areas where the generation of the pixel data of all the pixels is completed.

  Subsequently, the rasterization processing unit 24 similarly uses the identification number “4” indicating the primitive with the earliest input order among the identification numbers held in the registers R20 to R2f as the search primitive number PN, and stores it in the primitive number memory PM. Perform search processing. At this time, the rasterization processing unit 24 performs a search process on the primitive number memory PM area corresponding to the divided area of the register R2 holding the identification number “4”. Similarly, search processing is performed on the primitive number memory PM area corresponding to the divided area having the pixel on which the primitive P4 is drawn, and the search efficiency of the primitive number memory PM is improved.

  The left diagram of FIG. 27 is a diagram for explaining the rendering process when the rendering process for the segmented area having the identification number “4” in the registers R20 to R2f is completed. As a result of the drawing process, the registers R22, R23, R26, and R29 to R2b of the partitioned areas n2, n3, n6, and n9 to nb having only the identification number “2” or “4” in the corresponding primitive number memory PM have Max. The value “6” is held. Subsequently, the rasterization processing unit 24 searches the primitive number memory PM using the identification number “5” indicating the primitive in the input order that is the earliest among the identification numbers held in the registers R20 to R2f as the search primitive number PN. . Similarly, at this time, the rasterization processing unit 24 performs a search process for the primitive number memory PM area corresponding to the partitioned area of the register R2 holding the identification number “5”.

  The right diagram of FIG. 27 is a diagram for explaining the drawing process when the drawing process of the segmented area having the identification number “5” in the registers R20 to R2f is completed. Since drawing processing of all primitives drawn in the processing target block is completed, as a result of the drawing processing, the registers R20 to R2f all hold the Max value “6”. Since the search primitive number PN matches the Max value (NO in S75), the rasterization processing unit 24 writes the pixel data of each pixel of the processing target block stored in the internal memory to the frame buffer of the external memory 102 (S85). ).

  As described above, the image drawing apparatus according to the present embodiment stores, in the block unit, the vertex parameter (primitive parameter) including the coordinate information of the vertex of the primitive drawn in the block and the depth information indicating the depth in the first memory. The identification number (identification information) of the primitive drawn on the front surface is generated for each pixel in the target block based on the vertex parameter, read from (external memory), and stored in the primitive number memory of the second memory (internal high-speed memory) Write. At this time, during the generation of the identification number of the primitive, the image drawing apparatus obtains the primitive identification number that is drawn in the divided area for each divided area obtained by dividing the block into a plurality of blocks and that has the earliest input order. Stored as head identification information. For example, when generating the identification number of the primitive, the image drawing apparatus reads the vertex parameters of the primitive in the order of input of the drawing command, and holds the identification number that is initially written in the primitive number memory area corresponding to the segmented area as the head identification information.

  Then, the image drawing apparatus reads, from the first memory, vertex parameters including the vertex coordinate information and color information of the primitive of the earliest head identification information in the input order among the plurality of head identification information in units of blocks. Pixel data is generated based on the vertex parameter and written to the frame buffer for the pixel having the top identification information in the primitive number memory area corresponding to the segment area of the top identification information. Then, the image drawing apparatus further updates the identification number in the primitive number memory area, which is next in the input order, as new head identification information in the segmented area.

  As a result, the image drawing apparatus targets the primitive number memory area corresponding to the divided area where the primitive is drawn in order from the primitive with the earliest input order that is drawn in the processing target block. It is possible to search for pixels having the identification number. As a result, when the 0th primitive in the input order is not drawn in the processing target block, unnecessary search processing of the primitive number memory (of the 0th primitive) can be omitted.

  In addition, the image drawing apparatus according to the present embodiment always holds, for each segmented area, an identification number indicating a primitive that is rendered on a pixel in each segmented area and that is the next primitive in the input order. In addition to information on primitives that are drawn next to the target block in the next input order first, it is possible to specify a segmented region including a pixel on which the primitive is drawn. As a result, the image drawing apparatus further improves the search efficiency of the primitive number memory by setting the primitive number memory area corresponding to the specified segmented area, which always has an identification number indicating the primitive to be searched, as the search target area. be able to.

  Furthermore, the image drawing apparatus according to the present embodiment parallelizes the processing for a plurality of pixels in the partitioned area. As a result, the image drawing device can make the primitive number memory search process more efficient while reducing the degree of parallelization of the image drawing devices and reducing the circuit scale.

  The above embodiment is summarized as follows.

(Appendix 1)
For each block obtained by dividing the frame into a plurality of blocks, primitive parameters including the coordinate information of the vertices of the primitive drawn in the block and the depth information indicating the depth are read from the first memory, and based on the primitive parameters, the block A drawing primitive identification information generating unit that generates identification information of the primitive drawn on the front surface and writes the primitive identification information in a primitive number memory of the second memory,
Primitive parameters including coordinate information and color information of the vertexes of the target primitive are read from the first memory in the input order of the rendering command of the primitive for each block, and the target primitive is identified in the primitive number memory. A pixel data generating unit that generates pixel data based on the primitive parameter and writes the pixel data to a frame buffer for the pixel having information;
The drawing primitive identification information generating unit holds the identification information of the primitive that is drawn in the block during generation of the identification information of the primitive and is the earliest in the input order as head identification information,
The image drawing device, wherein the pixel data generation unit reads the primitive parameters from the first memory in the input order from the primitive of the held head identification information.

(Appendix 2)
In Appendix 1,
The drawing primitive identification information generation unit reads the primitive parameters of the primitives in the order of input, and holds identification information to be initially written in the primitive number memory as the head identification information.

(Appendix 3)
In Appendix 1,
The second memory is an image drawing apparatus having an access speed higher than that of the first memory.

(Appendix 4)
In Appendix 1,
Each of the blocks is divided into a plurality of partitioned regions;
The pixel data generation unit searches the primitive number memory to detect a pixel having identification information of the target primitive, and in the detection process, a primitive number corresponding to a segmented area in which pixel data of all pixels has been generated An image rendering device that excludes the memory area from the search range.

(Appendix 5)
In Appendix 4,
The pixel data generation unit is an image drawing device that performs processing in parallel for a plurality of pixels in the segmented region.

(Appendix 6)
For each block obtained by dividing the frame into a plurality of blocks, primitive parameters including the coordinate information of the vertices of the primitive drawn in the block and the depth information indicating the depth are read from the first memory, and based on the primitive parameters, the block A drawing primitive identification information generating unit that generates identification information of the primitive drawn on the front surface and writes the primitive identification information in a primitive number memory of the second memory,
Primitive parameters including coordinate information and color information of the vertexes of the target primitive are read from the first memory in the input order of the rendering command of the primitive for each block, and the target primitive is identified in the primitive number memory. A pixel data generating unit that generates pixel data based on the primitive parameter and writes the pixel data to a frame buffer for the pixel having information;
The drawing primitive identification information generation unit is a primitive drawn in the division area for each of the division areas obtained by dividing the block into a plurality of primitives during generation of the identification information of the primitive, and the primitive having the earliest input order Is held as the head identification information,
The pixel data generation unit reads out the primitive parameter of the primitive with the earliest input identification information in the input order from the first memory among the plurality of pieces of the head identification information, and corresponds to the segmented area of the head identification information An image drawing apparatus that generates pixel data for a pixel having the top identification information in the primitive number memory area to be updated, and further updates the identification information in the primitive number memory area next in the input order as the top identification information.

(Appendix 7)
In Appendix 6,
The drawing primitive identification information generation unit reads the primitive parameters of the primitives in the order of input, and holds the identification information to be initially written in the primitive number memory area corresponding to the segmented area as the head identification information.

(Appendix 8)
In Appendix 6,
The second memory is an image drawing apparatus having an access speed higher than that of the first memory.

(Appendix 9)
In Appendix 6,
The pixel data generation unit is an image drawing device that performs processing in parallel for a plurality of pixels in the segmented region.

101: CPU, 100: GPU, 102: external memory, 10: command interpretation unit, 11: geometry processing unit, 12: rendering processing unit, 21: setup processing unit, 22: tiling processing unit, 23: sort processing unit, 24: Rasterization processing unit

Claims (5)

For each block obtained by dividing the frame into a plurality of blocks, primitive parameters including the coordinate information of the vertices of the primitive drawn in the block and the depth information indicating the depth are read from the first memory, and based on the primitive parameters, the block A drawing primitive identification information generating unit that generates identification information of the primitive drawn on the front surface and writes the primitive identification information in a primitive number memory of the second memory,
Primitive parameters including coordinate information and color information of the vertexes of the target primitive are read from the first memory in the input order of the rendering command of the primitive for each block, and the target primitive is identified in the primitive number memory. A pixel data generating unit that generates pixel data based on the primitive parameter and writes the pixel data to a frame buffer for the pixel having information;
The drawing primitive identification information generating unit holds the identification information of the primitive that is drawn in the block during generation of the identification information of the primitive and is the earliest in the input order as head identification information,
The image drawing device, wherein the pixel data generation unit reads the primitive parameters from the first memory in the input order from the primitive of the held head identification information. In claim 1,
The drawing primitive identification information generation unit reads the primitive parameters of the primitives in the order of input, and holds identification information to be initially written in the primitive number memory as the head identification information. In claim 1,
Each of the blocks is divided into a plurality of partitioned regions;
The pixel data generation unit searches the primitive number memory to detect a pixel having identification information of the target primitive, and in the detection process, a primitive number corresponding to a segmented area in which pixel data of all pixels has been generated An image rendering device that excludes the memory area from the search range. For each block obtained by dividing the frame into a plurality of blocks, primitive parameters including the coordinate information of the vertices of the primitive drawn in the block and the depth information indicating the depth are read from the first memory, and based on the primitive parameters, the block A drawing primitive identification information generating unit that generates identification information of the primitive drawn on the front surface and writes the primitive identification information in a primitive number memory of the second memory,
Primitive parameters including coordinate information and color information of the vertexes of the target primitive are read from the first memory in the input order of the rendering command of the primitive for each block, and the target primitive is identified in the primitive number memory. A pixel data generating unit that generates pixel data based on the primitive parameter and writes the pixel data to a frame buffer for the pixel having information;
The drawing primitive identification information generation unit is a primitive drawn in the division area for each of the division areas obtained by dividing the block into a plurality of primitives during generation of the identification information of the primitive, and the primitive having the earliest input order Is held as the head identification information,
The pixel data generation unit reads out the primitive parameter of the primitive with the earliest input identification information in the input order from the first memory among the plurality of pieces of the head identification information, and corresponds to the segmented area of the head identification information An image drawing apparatus that generates pixel data for a pixel having the top identification information in the primitive number memory area to be updated, and further updates the identification information in the primitive number memory area next in the input order as the top identification information. In claim 4,
The drawing primitive identification information generation unit reads the primitive parameters of the primitives in the order of input, and holds the identification information to be initially written in the primitive number memory area corresponding to the segmented area as the head identification information.

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