JP2013004158A - Semiconductor storage device and refresh control method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the frequency of refresh operation of a plate that is frequently accessed.SOLUTION: A semiconductor device comprises: a disturb counter circuit that detects access frequencies to plates and outputs an activation signal when an access frequency exceeds a predetermined threshold value; and a refresh counter circuit that outputs a refresh interruption signal for a plate with an access frequency exceeding the predetermined threshold value when the activation signal is detected at an auto-refresh command.

Description

  The present invention relates to a semiconductor device having a configuration for interrupting refresh to a frequently accessed plate and a refresh control method thereof.

  In a semiconductor memory device such as a dynamic RAM, data information is stored by holding electric charge in a capacitor. In order to recover the deterioration of the data information, a refresh operation for re-storing is required.

  Patent Document 1 discloses a semiconductor device including a plurality of memory blocks. Each memory block has a memory cell array, an I / O gate, a drive circuit, a column decoder, a row decoder, etc., and an address signal input from the input terminal 1 is an operation block selection circuit 2, a column address buffer 3, and a row address. Provided to buffer 4. One of the memory blocks is selected by the block selection signal from the operation block selection circuit 2. The inputted input column address signal is given from the column address buffer 3 to the column decoder, and the column decoder designates a column address according to the column address signal. The input row address signal is applied from the row address buffer 4 to the row decoder, and the row decoder activates the word line in response to the row address signal. In such a semiconductor device, a test called a disturb refresh test is performed to find a memory cell defect.

  In recent years, with the miniaturization of processes, the influence of disturbing adjacent word lines cannot be ignored. In the semiconductor device as described above, there is a problem of data disturbance in which data of a non-selected cell is inverted while reading and writing operations are repeated. In other words, data disturb means that when a voltage for writing and reading is applied to a specific word line in a memory cell, the voltage is applied to adjacent cells (non-selected cells) connected to the selected row and column. This is a phenomenon in which the information of cells other than the selected cell is inverted due to the accumulation of slight influences while giving a slight influence and repeating the operation. For example, when data is written, data in unselected memory cells connected to the selected word line may deteriorate.

Japanese Patent Laid-Open No. 07-105698

  Therefore, in the semiconductor device, the refresh operation for recovering the deterioration of the logical data of the memory cell must be frequently executed, and the refresh busy rate increases. An increase in the refresh busy rate is a cause of hindering normal read / write operations and an increase in current consumption.

  Further, when performing refresh, it is very difficult to make a circuit in terms of a word line unit after birth, and the circuit becomes complicated.

  As a result of intensive research aimed at eliminating the drawbacks of the prior art and increasing the resistance due to disturbance, the present inventors have found that there is a disturbed word line on a plate (PLT) with high access frequency. From the standpoint of high establishment, it is possible to simplify the circuit by adopting a configuration that detects the access frequency of the plate, increases the refresh frequency of the plate with the high access frequency, and controls by the plate unit. It was discovered that the influence of disturb could be reduced while making it possible to achieve the plan, and the invention based on this finding was completed.

  An object of this invention is to provide the technique which can reduce the influence by a disturbance by changing refresh frequency per plate.

  In view of the above problems, according to one embodiment of the present invention, in a semiconductor device that performs a refresh operation of stored data written in a memory cell during a memory operation, the semiconductor device detects the access frequency to the plate, and the access frequency is A disturb counter circuit that outputs an activation signal when a predetermined threshold is exceeded, and a refresh counter circuit that outputs a refresh interrupt signal for a plate whose access frequency is equal to or higher than the predetermined threshold when the activation signal is detected during an auto-refresh command And, in response to the refresh interrupt signal, a refresh operation of the plate is performed more frequently than refresh operations of other plates.

  Furthermore, another aspect of the present invention provides a refresh control method for storage data written in a memory cell, and detects an access frequency to a plate and outputs an activation signal when the access frequency exceeds a predetermined threshold value. Refresh control that outputs a refresh interrupt signal for a plate whose access frequency is equal to or higher than a predetermined threshold when an active signal is detected during an auto-refresh command, and performs a refresh operation of the plate more frequently than a refresh operation of other plates in response to the refresh interrupt signal Regarding the method.

  According to the present invention, the influence of disturbance is reduced by changing the refresh frequency, and the tolerance of the semiconductor device due to disturbance can be improved.

  Further, according to the embodiment of the present invention, the refresh (REF) operation of a plate having a high access frequency can be approximately doubled to improve the disturb characteristic.

  Further advantages and embodiments of the present invention are described in detail below using the description and the drawings.

1 shows a schematic diagram of a disturb counter circuit and a refresh counter circuit according to an embodiment of the present invention. FIG. FIG. 6 is a timing diagram illustrating a refresh operation according to an embodiment of the present invention.

  Hereinafter, a semiconductor device and a refresh method thereof according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, the technical scope of the present invention is not construed as being limited by the embodiments described below.

  First, a general configuration of a DRAM targeted by the present invention will be described. The DRAM includes a memory cell array, sense amplifiers, X decoders, Y decoders arranged around the cell array, an address buffer for control signals, an input / output interface, a command buffer & decoder, a data circuit, and the like. The memory cell array is arranged in units of banks, and each bank has a bank control circuit.

  The above-described banks share the same data input / output with the outside, but can individually perform internal operations (for example, can be refreshed in units of banks) by each bank control circuit. The bank includes an X decoder, a Y decoder, a sense amplifier, a cell array, and the like. The bank is further composed of a plurality of sub-blocks (plates), and the decoder can be divided and hierarchized. Of course, the configuration of the bank is not limited to such a configuration. In the present invention, a plate means a memory cell array bank divided into a plurality of sub-blocks.

  As shown in FIG. 1, in the embodiment of the present invention, the DRAM includes a disturb counter circuit 10 that outputs a “Hi” plate disturb information signal (PLTDIST) when there is an access frequency equal to or higher than a predetermined threshold, and a plate. And a refresh counter circuit 20 that outputs a refresh interrupt signal (REFADD). In the embodiment of the present invention, a disturb counter circuit 10 and a refresh counter circuit 20 are prepared for each plate of the DRAM, and the refresh operation of each plate is individually controlled. The access frequency is counted by the number of application of the write voltage to the word line on the plate.

  A DRAM according to an embodiment of the present invention stores data information in the form of electric charges in a capacitor in a memory cell. If this charge is reduced by leakage current or disturbance, the stored information is lost. Therefore, in order to prevent data loss from the capacitor, a refresh operation (rewrite operation) for recharging the charge at regular intervals is required.

  The refresh operation includes an auto refresh mode and a self refresh mode. In the auto refresh mode, when a command is issued from the memory controller to the DRAM, a refresh operation is performed on a row address indicated by a refresh counter in the DRAM. In order to retain data, it is necessary to perform a DRAM refresh operation for all row addresses within a refresh cycle.

  In the embodiment of the present invention, the disturb counter circuit 10 counts the frequency of the detected plate selection signal (PLTm selection signal) in the disturb counter circuit 10 and when the frequency exceeds the predetermined threshold value or more. The plate disturb information signal (PLTDIST) is output to the refresh counter circuit 20. The counter value of the disturb counter circuit 10 is reset by a reset signal (RSTm).

  The refresh counter circuit 20 receives an auto-refresh signal (AREF) and a plate disturb information signal from the disturb counter circuit 10 from the outside, and outputs a refresh interrupt signal (REFADD) to the subsequent stage. The refresh counter circuit 20 is initialized by a reset signal.

  Next, a refresh control method for a semiconductor device according to an embodiment of the present invention will be described with reference to FIG.

  In the embodiment of the present invention, auto refresh is performed 4K to 16K times during a tREF period of, for example, 64 ms, depending on the product and capacity.

  In the embodiment of the present invention, at the time of auto refresh, each disturb counter circuit counts a plate (PLTm) selection signal to its own plate. When the count value is N times or more, the plate disturb information signal output from the disturb counter circuit 10 is “Hi”. Then, the refresh command for the corresponding plate is interrupted according to the refresh interrupt signal output from the refresh counter circuit 20 at the time of the auto refresh command for switching the plate. When the count value indicating the number of disturbances in the plate has not reached N times, the counter value of the disturb counter circuit 10 is reset when the refresh operation for the own plate is started. As a result, only when the plate has been accessed N times or more before the refresh operation of the plate itself, a refresh interrupt for the plate is entered. Since the refresh period is extended for the plate without interruption by the amount of interruption, it is necessary to secure the refresh ability in a state where there are not many normal disturbances.

  Next, a specific timing example of the semiconductor device according to the embodiment of the present invention shown in FIG. 2 will be described. In the following, a semiconductor device in which the memory cell array bank has 16 plates will be described as an example. The timing example is a timing chart assuming a case where disturbances are concentrated on specific plates of PLT5 and PLT12 in a memory configuration having 16 plates (PLT0 to 15).

  The disturb counter circuit 10 and the refresh counter circuit 20 are reset by a reset (RESET) signal at initialization. Thereafter, the number of times of disturb of each plate is counted, and since the number of times of PLT 12 has refreshed PLT 6, the number of times of disturb exceeds N times. Therefore, the plate disturb information signal (PLTDIST 12) for PLT 12 becomes “Hi”. In response to this “Hi”, the refresh of the PLT 12 is interrupted when the refresh of the PLT 7 of the next plate is started. By this interruption, the reset (RST12) becomes “Hi”, and the disturb counter circuit 10 for PLT12 is reset.

  On the PLT 5 side, after the disturb counter for PLT 5 is reset by the refresh operation of PLT 5, the number of accesses of PLT 5 exceeds N times during the refresh period of PLT 11, and the plate disturb information signal (PLTDIST 5) for PLT 5 becomes “Hi. "", The refresh of PLT 5 is interrupted at the start of refresh of PLT 12 which is the next refresh plate. By this interruption, reset (RST5) becomes "Hi", and the disturb counter circuit 10 for PLT5 is reset. In a similar manner, N times of access detection are performed for each plate.

  In the timing chart of FIG. 2, when attention is paid to PLTs 3, 4, and 6, there are four interrupts before the next refresh. The number of interruptions can be adjusted to a desired number by changing the value of N. For example, the refresh operation can be doubled by changing the value of N.

  As described above, it is possible to increase the refresh frequency for a plate having a high access frequency, and it is possible to increase the number of refreshes of a disturbed word line that is highly likely to exist in the plate. Therefore, the resistance of the semiconductor device to disturbance is enhanced.

10 disturb counter circuit 20 refresh counter circuit PLT plate (sub block)
REFRESH refresh signal PLTDIST plate disturb information signal AREF auto refresh signal RSTm reset signal RESET reset signal REFADD refresh interrupt signal

Claims (5)

In a semiconductor device that performs a refresh operation of stored data written in a memory cell during a memory operation,
A disturb counter circuit for detecting an access frequency to the plate and outputting an activation signal when the access frequency exceeds a predetermined threshold;
A refresh counter circuit that outputs a refresh interrupt signal for a plate whose access frequency is equal to or higher than a predetermined threshold when the activation signal is detected during an auto-refresh command,
In accordance with the refresh interrupt signal, the semiconductor device is characterized in that the refresh operation of the plate is performed more frequently than the refresh operation of other plates.   The semiconductor device according to claim 1, wherein the disturb counter circuit and the refresh counter circuit are provided for each plate.   3. The semiconductor device according to claim 1, wherein the access frequency to the plate is counted by the number of times of applying a write voltage to a word line in the plate.   4. The semiconductor device according to claim 1, wherein the predetermined threshold is set to a value that doubles a refresh operation for the plate. In a refresh control method for stored data written in a memory cell,
An activation signal is output when the access frequency to the plate is detected and the access frequency exceeds a predetermined threshold, and when the activation signal is detected at the time of an auto-refresh command, refreshing is performed for a plate whose access frequency is equal to or higher than the predetermined threshold. A refresh control method, comprising: outputting an interrupt signal, and performing a refresh operation of the plate more frequently than refresh operations of other plates in response to the refresh interrupt signal.

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