JP2012503233A - Processor power consumption control and voltage drop by bandwidth throttling of microarchitecture - Google Patents

Abstract

A method, apparatus and system are disclosed. In one embodiment, the method includes providing a first voltage to the processor. The method further comprises the step of enabling the processor to function in the extended processor hibernation state at the first voltage. The first voltage is a voltage that is lower than the lowest adaptive voltage related to the extended processor hibernation state. The method includes the step of allowing the processor to execute instructions upon wake from extended processor hibernation at a first voltage by reducing a maximum throughput rate of instructions executed by the processor.

Description

  The present invention relates to microarchitecture bandwidth throttling for specific processor power states.

  Current processors, such as, for example, Intel architecture processors or other brand processors, generally have multiple power states available to allow power savings when the processor is not busy. The processor typically has a fully operational power state called C0. C0 generally has a high frequency mode (HFM) and a low frequency mode (LFM). Another common processor power state is C1E. In the C1E state, the processor is available for snoop servicing but does not execute or retire any instructions. Snoop servicing requires a specific voltage that is sufficient to keep the processor cache operational.

Embodiments of a computer system that can use microarchitecture bandwidth throttling to enable operation in extended processor hibernation at lower supply voltage levels than are compatible with extended processor hibernation are described. Embodiments of power management logic utilized to implement deep C1E voltage are described. FIG. 6 is a flow diagram of an embodiment of a processor entering and exiting a deep C1E processor power management state.

  The invention will now be described by way of non-limiting example with reference to the drawings. In the drawings, like reference numbers indicate like elements.

  Embodiments of methods, apparatus, and systems for operating a processor in a C1E power state at a voltage lower than a C1E power state voltage level by implementing processor bandwidth throttling are disclosed.

  Current processors typically have multiple power states available to allow power savings when the processor is not busy. In many processors, one such state is the C0 state, where the processor is fully operational. During normal operation, the processor operates in the C0 state in either a high frequency mode (HFM) or a low frequency mode (LFM). The processor is supplied with a different voltage at HFM vs. LFM, which is generally a lower voltage than the HFM voltage.

  Another processor power state is a C1E state that requires the processor to be available for snoop servicing. In many embodiments, the C1E state may be referred to as an enhanced processor halt state. The C1E state requires a lower voltage to be supplied to the processor than the C0 HFM state.

  With standard LFM voltages, the processor can schedule and retire the maximum number of instructions every clock cycle. In general, the C1E state uses the same voltage as the LFM voltage because the processor immediately transitions to maximum execution and retire rate upon wakeup from the C1E state. A deep C1E voltage may be implemented to reduce power consumption in the C1E state, which is a lower voltage than the standard C1E (ie, LFM) voltage. Deep C1E voltage does not meet maximum instruction schedule and retire rate. Therefore, to keep the voltage compatibility with the schedule and retirement rate possible at the end of the C1E state at the deep C1E voltage, the processor immediately leaves the C1E state as soon as it exits the microarchitecture band such as the instruction schedule rate or instruction retire rate. Width throttling may be performed. Since throttling limits instruction bandwidth through the processor, it also reduces processor power consumption limits.

  Two things happen when the processor leaves the C1E state with a deep C1E voltage. First, the voltage level begins to rise to a standard LFM voltage that is compatible with maximum processor execution and retirement rates. Further, after leaving the C1E state, the processor may implement a micro-architecture bandwidth throttling mechanism for some time before the voltage reaches the LFM voltage. This can reduce the maximum power consumption possible and reduce the required voltage to at least the deep C1E voltage.

  This allows the deep C1E voltage to be supplied to the processor during the C1E state and preserves the voltage compatibility at the end of the C1E state while the voltage is initially raised to the LFM voltage. . The amount of voltage supply reduction is processor and implementation specific. For example, the greater the throttling, the greater the drop in available voltage.

  In the following description and claims, references to “embodiments” or “examples” of the disclosed technology refer to specific functions, configurations, or characteristics described in relation to the embodiments or examples. In at least one embodiment. Thus, the phrases “in an embodiment (or example)” appearing in various places throughout this specification are not necessarily all referring to the same embodiment.

  In the following description and in the claims, the words “comprising”, “including” and their derivatives may be used, but these are intended to be treated as synonyms for each other. Further, in the following description and claims, the terms “coupled”, “connected” and their derivatives may be used. It should be noted that these terms are not treated as synonyms for each other. Rather, in certain embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

  FIG. 1 describes an embodiment of a computer system that can use microarchitecture bandwidth throttling to enable operation at the end of extended processor hibernation at a lower supply voltage level than is compatible with extended processor hibernation. To do.

  In various embodiments, the computer system may be a desktop computer, server computer, laptop computer, portable electronic device, television set top computer, integrated computer in equipment or vehicle, or application of various embodiments described below. There may be other types of possible computer systems within the scope.

  In many embodiments, the computer system has a processor 100. The processor 100 may have a single core, such as the core 102, or may have multiple cores 102 and 104 (or more). There is also a cache memory 110 in the processor die. The cache memory 110 may have multiple levels of cache, such as a level 1 cache and a level 2 cache. Further, when there are multiple cores in a processor, each of the different levels of cache memory 110 may be shared, or in different embodiments, there may be a cache memory for each core.

  In some embodiments, processor 100 may be an Intel architecture microprocessor. In some embodiments, the processor 100 may have Intel SpeedStep® technology or other power management related technology that provides two or more voltage / frequency operating points. In some embodiments, the processor 100 may be various types of processors such as, for example, an embedded processor or a digital signal processor.

  The microarchitecture throttling mechanism can take several forms. In some embodiments, the microarchitecture throttling mechanism may limit the retirement rate of instructions executed by the processor. In other embodiments, the microarchitecture throttling mechanism may limit the assignment of instructions sent to a scheduler that schedules instructions to be executed. For example, a scheduler that schedules instructions may force one or more dead clock cycles in which instructions are not scheduled between clock cycles used to schedule instructions.

  In some embodiments, microarchitecture bandwidth throttling limits instruction scheduling and / or retirement in a reduced instruction set computer (RISC) architecture. In other embodiments, microarchitecture bandwidth throttling limits instruction scheduling and / or retirement in a multiple instruction set computer (CISC) architecture. In the CISC embodiment, the instructions being executed by the processor are divided into one or more microarchitecture operations (UOPs). UOPs generally cannot be divided and constitute an instruction pipeline of a CISC processor.

  Thus, in many RISC and CISC embodiments, the processor has a scheduling unit that schedules instructions to be executed by the execution unit of the processor and a retire unit that retires instructions that have already been executed in the execution unit. The power consumption of the processor is determined in part by the processor's schedule rate and retirement rate. Most processors have the ability to schedule and retire more than one instruction every clock cycle. For example, many processors can schedule and retire up to four instructions during each clock cycle.

  Processor bandwidth throttling can occur when the core is limited to schedule and retire less than the maximum number of instructions per clock cycle. For example, a retire unit can typically retire four instructions every clock cycle, and the processor is inherently constrained if the logic in the processor limits the retire rate to one instruction per clock cycle. This results in performance degradation as well as potential power loss reduction.

  Each core may have a scheduling unit (SU), such as SU 134 and SU 136, for cores 102 and 104, respectively. Further, each core may have a retire unit (RU) such as RU 106 and RU 108 for cores 102 and 104, respectively.

  The logic in the SU schedules instructions to be executed by the core. In a CISC architecture, the SU may schedule instructions in a disjointed order to speed up instructions within the pipeline. Further, in the CISC architecture, the RU may have a re-order buffer (ROB). The ROB in the CISC architecture RU returns the UOPs to their original program order after the UOPs are executed (possibly in disjoint order).

  As mentioned above, most processors have the ability to schedule and retire more than one instruction per core clock, for example, four instructions between each core clock in multiple processors per core. May be scheduled and retired. Thus, microarchitecture bandwidth throttling can occur when the logic in the SU, RU, or both limits the instruction schedule rate and / or retirement rate to less than 4 instructions per core clock. .

  In some embodiments, throttling is when the logic in the SU limits the schedule rate to one instruction per core clock instead of the maximum rate for four instructions per core clock. Occur. In other embodiments, throttling occurs when the logic in the SU limits instruction scheduling to every other core clock instead of every core clock. Thus, if the maximum scheduling rate is 4 instructions per clock, and only every other clock is available for scheduling, the effective maximum schedule rate is 2 instructions per core clock. Reduced.

  In other embodiments, throttling is when the logic in the RU limits the rate of retirement to one instruction per core clock instead of the maximum rate for four instructions per core clock. Occur. Many other standard microarchitecture bandwidth throttling mechanisms may be implemented, or a combination of mechanisms may be implemented. As a result of some throttling mechanism, instruction throughput over time is limited to less than what the core can produce. This results in an instruction flow bandwidth that is less than optimal through the core, so the core never reaches a state during throttling where the maximum specific supply voltage is required.

  In this way, the supply voltage to the core may be reduced during microarchitecture bandwidth throttling.

  In addition, the processor 100 further includes an integrated memory controller 112 in many embodiments. In other embodiments not shown, the memory controller 112 is a discrete device or integrated into a bridge device or other system chip remote from the processor 100. Memory controller 112 is coupled to system memory 114 through a processor-memory interconnect. The memory controller 112 allows the processor 100 and other devices in the computer system to access the system memory 114. In many embodiments, the system memory 114 may have a random access memory (RAM), such as dynamic RAM (DRAM), flash memory, or other form of memory.

  The processor 100 is also coupled to a discrete input / output (I / O) complex 116 in many embodiments. In other embodiments not shown, the I / O complex 116 may be incorporated into the processor 100. The I / O complex 116 has one or more integrated I / O host controllers (not shown) that allow I / O devices such as keyboards, mass storage devices, etc. to connect to the computer system. You can do it.

  The system further includes a voltage regulator (VR) 118. VR 118 is coupled to processor 100. The VR 118 may supply power operating voltage to the processor 100 and operate according to a version of the IMVP (Intel® Mobile Voltage Positioning) standard, such as the IMVP-6 standard. VR 118 may include logic that reduces the voltage to processor 100 to one or more low voltage states in response to one or more signals. The logic of the VR 118 may also increase the voltage to the processor 100 again after exiting the low voltage state. Furthermore, VR 118 may be incorporated into processor 100 in other embodiments not shown.

  The processor 100 further includes power state entry / exit logic 120 that controls entry and exit into one or more voltage states. Each power state has a specific voltage that is used as a power operating voltage supplied from the VR 118 to the processor 100. In certain embodiments, the processor 100 may transmit the voltage value to the VR 118 using a voltage ID (VID) value. In other embodiments, the processor 100 may transmit the voltage value to the VR 118 using information other than VID. The information sent to the VR 118 is information specific to different platforms using different types of VRs that receive different formats of voltage change instructions / information.

  In many embodiments that utilize VID, the power state VID is paired with a specific processor operating frequency. Thus, in many embodiments, a power state table that stores voltage / frequency pairs is maintained in the computer system. This table may be located in the microcode in the processor 100, in the storage in the I / O complex 116, in the basic input / output system (BIOS) 122, or in other firmware in the system. In many embodiments, the power state table includes incremental voltage values in a linear fashion. For example, the first table entry may match the minimum voltage amount, in which case the next entry may increment the voltage linearly by a uniform amount for each entry. In other embodiments, the first table entry may coincide with the maximum voltage amount of the processor, and the next entry may be linearly decremented by a uniform amount for each entry.

  In many embodiments, the operating system 124 is loaded into the system memory 114 as the computer system operates. The operating system 124 may have code that supports an advanced configuration and power interface (ACPI) 126. Using this code, the operating system 124 may have access to the power state table and instruct the ACIP interface to enter and exit different power states.

  The I / O complex 116 further includes a power management microcontroller 128 in many embodiments. The power management microcontroller 128 has state control logic that controls transitions between the normal operating state associated with the processor 100 and the power management state. Each power management state has at least one specific voltage level and frequency combination. The voltage level is a voltage level supplied to the processor 100, and the frequency is a frequency at which the processor 100 operates. The power management microcontroller 128 may provide information to the voltage change logic 130 in the VR 118 to set the voltage supplied to the processor 100. The power management microcontroller 128 can also provide information to a clock generator circuit 132 that provides a clock signal to the processor 100. In many embodiments, the clock generator circuit 132 is a phase locked loop (PLL). In many embodiments, the power state entry / exit logic 120 can also control frequency changes within the processor 100 for different power states. In general, there are a plurality of power management states.

  Hereinafter, the embodiment transitions the processor 100 from a fully operational C0 power state to a C1E power state and during the transition between the deep C1E voltage state and between the deep C1E voltage state and the LFM voltage state. It will be described with respect to re-establishing using a ring.

  When the processor 100 is operating in the C0 power state, ACIP or other commands from the operating system 124 or from elsewhere in the computer system are sent to the power management microcontroller 128 to place the processor 100 in the C1E state. To reach. In some embodiments, if the processor 100 is operating at an HFM frequency, the processor 100 is first lowered to a lower support frequency and a corresponding voltage, the LFM frequency / voltage pair. The power state entry / exit logic 120 may change the frequency to cause the processor 100 to transition to the LFM frequency. In an alternative embodiment, the clock generator circuit 132 may change the clock supplied to the processor 100 externally, which further changes the frequency of the processor 100.

  In many embodiments, when the frequency is changed to the LFM frequency, the power management microcontroller 128 sends voltage information, such as VID, to the VR 118 to lower the voltage to the LFM voltage level. The LFM voltage level is the same voltage that is utilized when the processor 100 is in the standard C1E state.

  In some embodiments, the power state entry / exit logic 120 may cause the processor 100 to enter the C1E state when the frequency and voltage are at the LFM level. As described above, the C1E state requires the processor to be available for snoop servicing, but the processor 100 is not executing any instructions in this state.

  Upon entering the C1E state, the power management microcontroller 128 may send a command to the voltage change logic 130 in the VR 118 to cause the voltage to fall below the voltage paired with the C1E / LFM frequency. In some embodiments, this voltage level can be lowered by subtracting the delta VID value from the standard LFM / C1E VID value. Thus, the resulting lower VID value can be sent to VR 118 to reduce the voltage. This voltage level is below the standard LFM / C1E voltage level and may be referred to as the deep C1E voltage level. The amount by which the voltage supplied to the processor 100 can be lowered varies in different embodiments (using different processors).

  In many embodiments, the microarchitecture bandwidth throttling mechanism may be involved at the same time that the deep C1E voltage information is transmitted to the VR 118. In many embodiments, the signal that commands VR 118 to lower the supply voltage to the core is the same signal that is sent to processor 100 to command the core to perform a throttling mechanism. Thus, the microarchitecture bandwidth throttling mechanism can be involved in the C1E state even if the processor 100 is not executing instructions. This allows the processor to quickly exit the C1E state and return to executing instructions in the C0LFM state without waiting for the voltage to rise from the deep C1E voltage to the standard LFM / C1E voltage level. .

  In other words, the throttling mechanism is used to reduce processor instruction throughput during the portion of the LFM state where the supply voltage to the processor is below the LFM / C1E voltage level. Specifically, when the processor enters the LFM state from the C1E state, the amount of time that the VR 118 needs to increase the voltage from the deep C1E voltage level to the LFM / C1E voltage level is finite. Thus, during this time period, the processor core limits the processor from executing a stressed workload where the throttling mechanism requires an LFM voltage level, so that the voltage is specific for the LFM state. Even if it is lower than the voltage of, the instruction is allowed to be executed when in the C0LFM state.

  Thus, in many embodiments, when the processor is operating in the C1E power state at the deep C1E voltage level, an interrupt may be sent to the power management microcontroller 128 that wakes the processor to the full operating C0 power state. . In many embodiments, when an interrupt is received, the core initiates a wake-up procedure and begins servicing standard interrupts at the LFM frequency. At the beginning of the C1E to C0 transition, the power management microcontroller 128 sends information to the VR 118 (and voltage change logic 130 in the VR 118) to begin increasing the voltage from the deep C1E voltage level to the standard LFM / C1E voltage level. May be sent to.

  In some embodiments, microarchitecture throttling continues until the voltage level reaches the LFM voltage level. In such an embodiment, throttling stops when the LFM voltage level is reached. In other embodiments, the processor leaves C1E and proceeds directly to the C0HFM state. In such an embodiment, throttling continues at least until the voltage level reaches the LFM voltage level during the voltage ramp. In such an embodiment, when the voltage level increases to the standard LFM voltage level, throttling stops for the remaining voltage ramp to the C0HFM voltage.

  FIG. 2 describes an embodiment of power management logic used to implement deep C1E voltage. In many embodiments, the value is entered into logic. The values may include a software frequency value 200, an LFM frequency value 202, a software voltage value 204, and an LFM voltage value 206, in some embodiments, originating from one or more types of memory locations that store these values. Value. In some embodiments, these values may be stored in registers located in the processor or elsewhere in the computer system. In other embodiments, the value is stored in non-volatile memory associated with the BIOS, in system memory, or in other storage locations within the computer system. In many embodiments, the value may have a representative value corresponding to a location in one or more tables stored in the computer system at one or more storage locations.

  For example, the frequency value may correspond to a column in the frequency value table. The table may store all of the frequencies at which the processor can operate. Table 1 represents a partial frequency table embodiment.

このテーブルは、全て０の周波数値に対応する０ギガヘルツ（ＧＨｚ）での周波数から始まる。その後、テーブルは、高周波数として３．０ＧＨｚから始まって、８ビットの２進周波数値のインクリメントごとに、対応する周波数が１００メガヘルツ（ＭＨｚ）ずつ下がることを示す。テーブルは、プロセッサ周波数が１．９ＧＨｚまで下がることしか示していないが、テーブル全体は、２進周波数値における更なるインクリメントと、プロセッサ周波数における対応する更なるデクリメントとにより、下へ続いていく。先と同じく、このテーブルは、テーブルを記憶するのに十分な記憶空間を有するコンピュータシステム内のいずれかの場所に置かれてよい。このように、ソフトウェア周波数値２００（多くの実施形態で、システム内のソフトウェアが、プロセッサ周波数が設定されることを必要としている現在の値と呼ばれる。）は、表１のような周波数値テーブルにおける列に対応する８ビット周波数値を含んでよい。

This table starts with a frequency at 0 gigahertz (GHz) corresponding to a frequency value of all 0s. The table then indicates that the corresponding frequency decreases by 100 megahertz (MHz) for each increment of the 8-bit binary frequency value, starting at 3.0 GHz as the high frequency. The table only shows that the processor frequency drops to 1.9 GHz, but the entire table continues down with further increments in binary frequency values and corresponding further decrements in processor frequency. As before, this table may be placed anywhere in the computer system that has sufficient storage space to store the table. Thus, the software frequency value 200 (in many embodiments, the software in the system is referred to as the current value that requires the processor frequency to be set) in the frequency value table as in Table 1. An 8-bit frequency value corresponding to the column may be included.

  In another example, the voltage value may correspond to a column in a voltage table that stores all of the voltage levels that can be supplied to the processor. Table 2 represents an embodiment of a partial voltage value table implemented with specific VID values.

この表は、ＶＩＤ値が全てゼロである場合に、電圧がシャットオフされた状態で始まる。その後、テーブルは、高電圧として１．６ボルト（Ｖ）から始まって、８ビットの２進ＶＩＤ値のインクリメントごとに、対応する電圧が０．０１２５Ｖずつ低下すること示す。テーブルは、電圧供給値が１．４６２５Ｖまで下がることしか示していないが、テーブル全体は、２進値における更なるインクリメントと、供給電圧における対応する更なるデクリメントとにより、下へ続いていく。先と同じく、このテーブルは、テーブルを記憶するのに十分な記憶空間を有するコンピュータシステム内のいずれかの場所に置かれてよい。このように、ソフトウェアＶＩＤ値２０４（多くの実施形態で、システム内のソフトウェアが、プロセッサ電圧が設定されることを必要としている現在の値と呼ばれる。）は、表２のようなＶＩＤテーブルにおける列に対応する８ビットＶＩＤ値を含んでよい。

The table starts with the voltage shut off when the VID values are all zero. Thereafter, the table shows that starting from 1.6 volts (V) as a high voltage, for every increment of the 8-bit binary VID value, the corresponding voltage decreases by 0.0125V. The table only shows that the voltage supply value drops to 1.4625V, but the whole table continues down with further increments in the binary value and corresponding further decrements in the supply voltage. As before, this table may be placed anywhere in the computer system that has sufficient storage space to store the table. Thus, the software VID value 204 (in many embodiments, the software in the system is referred to as the current value that requires the processor voltage to be set) is a column in a VID table such as Table 2. May include an 8-bit VID value corresponding to.

  The LFM frequency value 202 and the LFM VID value 206 correspond to the processor frequency and the supply voltage to the processor that are used when the processor is in the LFM. Thus, the respective voltage and frequency values for the LFM may be preset values to be used when the power management logic decides to bring the processor to the LFM. In many embodiments, the deep C1E delta value 208 is also provided to the power management logic. The deep C1E delta value 208 has a difference between the standard LFM VID and a lower voltage corresponding to the deep C1E VID. For example, the LFM VID may be 00001010b, which corresponds to 1.55V in Table 2. The deep C1E voltage value may be 00001110b, which corresponds to 1.475V in Table 2. Thus, the deep C1E delta value 208 corresponds to the difference between the two values and is 00001100b (ie, 00001010b + 000001100b = 00010110b).

  The LFM VID value 206 and deep C1E delta value 208 are input to summing logic 210. Addition logic 210 adds these two values. The result is the value in Table 2 corresponding to the deep C1E VID value.

  In many embodiments, the power management logic has multiple gates that determine which of the two values are supplied to various components in the computer system. The gate 212 can switch whether the LFM VID value 206 or the calculated deep C1E VID value 210 is sent to the gate 214. The gate 214 can then switch between the software VID value 204 or the VID value output from the gate 212 to be placed on the VR 118. Finally, the gate 216 can switch between the software frequency value 200 or the LFM frequency value 202 to be sent to the PLL 132 for radio modulation.

  The determination of which of the inputs to gates 214 and 216 is output is made by power state entry / exit logic 120. The power state entry / exit logic 120 can switch between software-determined VID and frequency values and LFM VID and frequency values. In many embodiments, the deep C1E control value 218 can determine whether a deep C1E VID value is sent to the gate 212 instead of the LFM VID value 206. In some embodiments, the deep C1E control value 218 may be located in a control register or other storage location in the processor or elsewhere in the computer system. In various embodiments, the deep C1E control value 218 may be located within the power management microcontroller (128 in FIG. 1), within the power state entry / exit logic 120, at a location in the system memory 114, or elsewhere.

  In many embodiments, the deep C1E control value 218 also determines the microarchitecture throttling logic in the core whether the throttling logic in the core is involved in throttling instructions executed by the core. Give the input value. In some embodiments, the deep C1E control value 218 is a single bit. For example, if the deep C1E control value 218 is “1”, this indicates that deep C1E power management is active. This “1” is sent to the gate 212. Gate 212 then received control “1”, allowing the calculated deep C1E VID value from summing logic 210 to be sent to gate 214. A “1” deep C1E control value 218 is also sent to the microarchitecture throttling logic. The microarchitecture throttling logic is involved in the throttling mechanism because it receives a "1". On the other hand, if the deep C1E control value 218 is “0”, this indicates that deep C1E power management is inactive. This “0” is sent to the gate 212. Gate 212 then received the control “0” and allows the LFM VID value to be sent to gate 214. A deep C1E control value 218 of “0” is also sent to the microarchitecture throttling logic. The microarchitecture throttling logic does not participate in the throttling mechanism because it receives a “0”.

  In many embodiments, the microarchitecture bandwidth throttling logic 224 includes a timer that starts when deep C1E power management is deactivated. The throttling logic may wait until the timer reaches the end before releasing the throttling mechanism. This timer may coincide with the standard length of time that the voltage rises from the deep C1E voltage level to the LFM voltage level. In other embodiments, the logic in the core or in the VR may determine when the voltage supplied to the processor has reached the LFM voltage during a voltage ramp from the deep C1E voltage level. You can let the logic know. This information provided to the throttling logic confirms that the voltage supplied to the core is at least at the LFM voltage level. Once the throttling logic confirms that this information has achieved the LFM voltage level, it may then release the throttling mechanism.

  Further, in many embodiments, the deep C1E control value 218 is ORed with the throttling debug control register 226. The debug register 226 may also implement microarchitecture bandwidth throttling. This register 226 allows the core to throttle the instruction throughput rate without changing the VID sent to the VR 118.

  FIG. 3 is a flow diagram of an embodiment of a processor entering and exiting a deep C1E power management state. Processing is performed by processing logic. Processing logic may comprise hardware, software, or a combination thereof. Further, in various embodiments, processing logic may be located in the processor, in an I / O complex remote from the processor, in system memory, or elsewhere in the computer system. Further, the processing logic that executes the blocks in the flow diagram may be located in more than one of those locations. Processing begins by processing logic determining whether there is a command, instruction, or other piece of information indicating that the processor should enter a deep C1E state (processing block 300). The deep C1E state allows the processor to operate in the C1E state (extended processor hibernate) with a supply voltage below the normal specified voltage for the C1E state, as described above with respect to FIGS. The processor power management state as described above.

  In the process embodiment shown in FIG. 3, the processor initiates a process that is fully operational in the C0 state. Returning to processing block 300, if there is no indication to enter the deep C1E state, the processor continues to function in the C0 state and processing block 300 checks again to see if an indication to enter the deep C1E state has arrived. . In some embodiments, the interrupt informs the processing logic to enter the deep C1E state.

  If there is an indication to enter the deep C1E state, processing logic changes the processor frequency and voltage to the LFM frequency and voltage (processing block 302). This occurs when the processor is functioning at the HFM frequency and voltage in the C0 state.

  Once the LFM frequency and voltage are achieved, processing logic causes the processor to enter the C1E processor state (processing block 304). Once in the C1E processor state, processing logic begins to reduce instruction throughput by the processor by using one or more of the throttling mechanisms described above (eg, instruction schedule rate, instruction retire rate, etc.) (processing logic). 306). Although the suppressed instruction throughput rate is lower per clock than the unsuppressed throughput rate, the specific instruction throughput rates in the suppressed and unsuppressed modes are implementation specific.

  After the instruction throughput rate is throttled, processing logic reduces the voltage supplied to the processor below the amount of LFM voltage (processing logic 308). Such voltage changes may be based on a set delta amount that is added to the LFM voltage value (or subtracted from the LFM voltage, depending on the voltage table implementation) to obtain a new, lower voltage value. The new voltage value is sent to the VR supplying the processor, and the processing logic within the VR reduces the supply voltage to a new voltage amount.

  At this point, the processor is operating in the deep C1E state because the processor frequency is set to the LFM (ie, C1E) frequency and the voltage supplied to the processor is at the deep C1E voltage level.

  At some point after the processor has completely entered the deep C1E state, an interrupt may be sent to cause the processor to exit deep C1E power management. In many embodiments, the interrupt requires the processor to return to at least the C0LFM state.

  Processing logic waits for an interrupt and determines whether the interrupt is seeking to exit deep C1E (processing block 310). If the interrupt does not require exiting from deep C1E, then processing logic returns to block 310 and again checks for an end event from deep C1E. If the interrupt wants to exit deep C1E, the processing logic changes the voltage supplied to the processor to the LFM voltage value when an interrupt to exit deep C1E arrives. This voltage value is sent to VR, which begins to increase the voltage to the LFM voltage (processing block 312). When an interrupt arrives at the processor to leave the deep C1E state, the processor may begin to service standard interrupts.

  Processing logic then checks to see if the voltage supplied to the processor has increased to an LFM voltage amount (processing block 314). If the voltage has not reached the LFM voltage amount, processing logic continues to check to see if the LFM voltage amount has been reached at block 314. The processing logic stops suppressing the instruction throughput rate in the processor when the LFM voltage is reached, and the process ends.

  In other embodiments not shown, the further block 316 may further increase the voltage and frequency to their HFM level.

  While the embodiments described herein focus on the C1E state to implement an instruction throughput rate throttling mechanism that allows a reduction in supply voltage level in the C1E state, many further embodiments, The throttling mechanism may be used to reduce the voltage of processor states other than the C1E state (ie, extended processor hibernation).

  Thus, embodiments of a method, apparatus and system for operating a processor in a C1E power state at a voltage lower than the C1E power state voltage level by implementing bandwidth throttling of the processor are disclosed. These embodiments are described with reference to specific example embodiments thereof. It goes without saying to those skilled in the art that various modifications and changes can be made to these embodiments without departing from the spirit and scope of the embodiments described herein. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive.

Claims (25)

Providing the processor with a first voltage that is less than a second voltage that is the lowest compatible voltage for extended processor hibernation;
Allowing the processor to execute instructions upon wake from the extended processor hibernation state at the first voltage by reducing a maximum throughput rate of instructions executed by the processor. Transitioning the processor to a first frequency in a low frequency mode and to the second voltage associated with the low frequency mode;
The method of claim 1, further comprising: causing the processor to enter the extended processor hibernation state by further transitioning the processor to the first voltage and simultaneously performing instruction throughput rate reduction. Receiving a processor interrupt request while the processor is in the extended processor hibernation state;
Providing a service to the interrupt at the first voltage; and
The method of claim 2, wherein the request asks the processor to leave the extended processor hibernation state and service the request. Increasing the voltage supplied to the processor from the first voltage to the second voltage while continuing to reduce the instruction throughput rate;
4. The method of claim 3, further comprising: causing the processor to exit the extended processor hibernation state by stopping the reduction of the instruction throughput rate when the voltage supplied to the processor reaches the second voltage. the method of. Increasing the voltage supplied to the processor from the first voltage to the second voltage while continuing to reduce the instruction throughput rate;
Stopping the reduction of the instruction throughput rate when the voltage supplied to the processor reaches the second voltage;
When the reduction of the instruction throughput rate is stopped, increasing the voltage supplied to the processor from the second voltage to a third voltage higher than the second voltage and associated with a high frequency mode;
Transitioning the processor out of the extended processor hibernation state by transitioning the processor to a second frequency associated with the high frequency mode when a voltage supplied to the processor reaches the third voltage. The method of claim 3 comprising: The method of claim 4, further comprising: servicing the interrupt during a voltage ramp when the instruction throughput rate is being reduced.   The processor can retire less than or equal to the first number of instructions per cycle, and the processor is limited to retire less than the first number of instructions per cycle while reducing the instruction throughput rate The method of claim 1, wherein:   The method of claim 1, wherein the processor is available for snoop servicing during the extended processor hibernation state.   The method of claim 1, wherein the extended processor hibernation state is a C1E power state. Providing a first voltage to the processor that is lower than a second voltage that is the lowest compatible voltage for extended processor hibernation;
An apparatus comprising a processor power management circuit that allows the processor to execute instructions on wake from the extended processor hibernate state at the first voltage by reducing a maximum throughput rate of instructions executed on the processor. The processor power management circuit further includes:
Transitioning the processor to a first frequency in a low frequency mode and to the second voltage associated with the low frequency mode;
11. The apparatus of claim 10, further operable to transition the processor to the first voltage and at the same time perform an instruction throughput rate reduction. The processor power management circuit further includes:
Receiving a processor interrupt request while the processor is in the extended processor sleep state;
Operative to cause the processor to service the interrupt at the first voltage;
12. The apparatus of claim 11, wherein the request asks the processor to leave the extended processor hibernation state and service the request. The processor power management circuit further includes:
Increasing the voltage supplied to the processor from the first voltage to the second voltage while continuing to reduce the instruction throughput rate;
The apparatus of claim 12, wherein the apparatus is operative to stop reducing the instruction throughput rate when a voltage supplied to the processor reaches the second voltage. The processor power management circuit further includes:
Increasing the voltage supplied to the processor from the first voltage to the second voltage while continuing to reduce the instruction throughput rate;
Stop reducing the instruction throughput rate when the voltage supplied to the processor reaches the second voltage;
When the reduction of the instruction throughput rate is stopped, the voltage supplied to the processor is increased from the second voltage to a third voltage higher than the second voltage and related to the high frequency mode;
The apparatus of claim 12, wherein the apparatus is operative to transition the processor to a second frequency associated with the high frequency mode when a voltage supplied to the processor reaches the third voltage.   The apparatus of claim 13, wherein the processor is further operable to service the interrupt during a voltage ramp when the instruction throughput rate of the processor is being reduced.   The processor can retire less than or equal to the first number of instructions per cycle, and the processor is limited to retire less than the first number of instructions per cycle while reducing the instruction throughput rate The device of claim 10.   The apparatus of claim 10, wherein the processor is available for snoop servicing during the extended processor hibernation state.   The apparatus of claim 10, wherein the extended processor hibernation state is a C1E power state. A multi-core processor;
A voltage regulator;
A processor power management circuit, and
The processor power management circuit includes:
Causing the voltage regulator to supply the processor with a first voltage that is lower than a second voltage that is the lowest compatible voltage for the extended processor hibernation state;
Allowing the processor to execute instructions on wake from the extended processor hibernation state at the first voltage by reducing a maximum throughput rate of instructions executed on the processor;
system. The processor power management circuit further includes:
Transitioning the processor to a first frequency in a low frequency mode and to the second voltage associated with the low frequency mode;
The system of claim 19, further operating to transition the processor to the first voltage and simultaneously perform instruction throughput rate reduction. The processor power management circuit further includes:
Receiving a processor interrupt request while the processor is in the extended processor sleep state;
Operative to cause the processor to service the interrupt at the first voltage;
21. The system of claim 20, wherein the request asks the processor to leave the extended processor hibernation state and service the request. The processor power management circuit further includes:
Increasing the voltage supplied to the processor from the first voltage to the second voltage while continuing to reduce the instruction throughput rate;
The system of claim 21, wherein the system is operative to stop reducing the instruction throughput rate when a voltage supplied to the processor reaches the second voltage. The processor power management circuit further includes:
Increasing the voltage supplied to the processor from the first voltage to the second voltage while continuing to reduce the instruction throughput rate;
Stop reducing the instruction throughput rate when the voltage supplied to the processor reaches the second voltage;
When the reduction of the instruction throughput rate is stopped, the voltage supplied to the processor is increased from the second voltage to a third voltage higher than the second voltage and related to the high frequency mode;
The system of claim 21, wherein the system is operative to transition the processor to a second frequency associated with the high frequency mode when a voltage supplied to the processor reaches the third voltage.   The processor can retire less than or equal to the first number of instructions per cycle, and the processor is limited to retire less than the first number of instructions per cycle while reducing the instruction throughput rate 23. The system of claim 22, wherein:   The system of claim 19, wherein the extended processor hibernation state is a C1E power state.

Images