JP2012239240A - Method for generating parity-check matrices of low-density parity-check codes - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for generating parity-check matrices of low-density parity-check (LDPC) codes.SOLUTION: This invention relates to a communication system having at least a control unit using LDPC codes, and provides a method for generating parity-check matrices based on control by the control unit. Parameters for designing the LDPC code are determined, and a first parity-check matrix of a quasi-cyclic LDPC code is formed according to the determined parameters. A second parity-check matrix is created through the elimination of a predetermined portion of a parity part in the first parity-check matrix, and a third parity-check matrix is created by rearranging the second parity-check matrix.

Description

  The present invention relates to a communication system using a low-density parity check (hereinafter referred to as “LDPC”) code, and more particularly, to a parity check matrix generation method for a specific form of LDPC code.

  In a wireless communication system, link performance is significantly degraded due to various channel noises, fading phenomena, and inter-symbol interference (hereinafter referred to as “ISI”). Therefore, in order to realize high-speed digital communication systems that require high data throughput and reliability, such as next-generation mobile communication, digital broadcast, and mobile Internet, technologies that overcome noise, fading, and ISI are developed. It is important to. In recent years, research on error correction codes has been actively conducted as a method for improving communication reliability by efficiently restoring distorted information.

  The LDPC code, first introduced by Gallager in the 1960s, has long been forgotten due to the complexity of implementation that far surpassed the technology at that time. However, since the turbo codes discovered by 1993 Berrou, Glavieux, and Thiimajshima show performance close to Shannon's channel limit, channel code based on iterative decoding and graphs, while many analyzes on turbo code performance and characteristics have been made A lot of research has been carried out on computerization. Due to such research, LDPC codes were re-researched in the late 1990s, applying iterative decoding based on sum-product algorithm on Tanner graph (a special case of factor graph) corresponding to LDPC codes Performing decryption with, proved to have performance close to Shannon's channel limit.

  LDPC codes are usually shown using graph representation techniques, and many properties can be analyzed through methods based on graph theory, algebra, and probability theory. In general, a graph model of a channel code is useful for describing the code, mapping information about the encoded bits to vertices in the graph, and mapping the relationship between each bit to an edge in the graph By doing so, each vertex can be regarded as a communication network in which a predetermined message is exchanged via each edge, and thus a natural decoding algorithm can be derived. For example, decoding algorithms derived from trellis that can be considered a type of graph include the well-known Viterbi algorithm, and the Bahl, Cocke, Jelinek, and Raviv (BCJR) algorithms.

  The LDPC code is generally defined as a parity check matrix and can be expressed using a bipartite graph called a Tanner graph. This bipartite graph means that the vertices constituting the graph are divided into two different types, and the LDPC code is represented by a bipartite graph including vertices called variable nodes and check nodes. This variable node is mapped one-to-one to this encoded bit.

With reference to FIG.1 and FIG.2, the graph representation method of a LDPC code is demonstrated.
Figure 1 shows an example of a parity-check matrix H ₁ of the LDPC code including 4 rows and 8 columns.
Referring to FIG. 1, since the number of columns is 8, the parity check matrix H ₁ means an LDPC code that generates a codeword having a length of 8, and this column is mapped to encoded 8 bits. Is done.

Figure 2 is a diagram illustrating a Tanner graph corresponding to H ₁ of FIG.
Referring to FIG. 2, a Tanner graph of an LDPC code includes eight variable nodes x ₁ (202), x ₂ (204), x ₃ (206), x ₄ (208), x ₅ (210), x ₆ (212), x ₇ (214), and x ₈ (216) and four check nodes 218, 220, 222, and 224. Here, the i th column and the j th row of the parity check matrix H ₁ of the LDPC code are mapped to the variable node x _i and the j th check node. In addition, a value of 1 at a point where the i-th column and j-th row of the parity check matrix H ₁ of the LDPC code intersect each other, that is, a value other than 0 is a variable node x _This means that an edge exists between the _i and jth check nodes.

In the Tanner graph of an LDPC code, the order of variable nodes and check nodes means the number of edges connected to each node, and this order is a column or row corresponding to a related node in the parity check matrix of the LDPC code. This is the same as the number of non-zero entries. For example, in FIG. 2, variable nodes x ₁ (202), x ₂ (204), x ₃ (206), x ₄ (208), x ₅ (210), x ₆ (212), x ₇ (214), And x ₈ (216) have orders of 4, 3, 3, 3, 2, 2, 2, and 2, respectively, and check nodes 218, 220, 222, and 224 have orders of 6, 5, 5, respectively. , And 5.

Also, the number of non-zero entries in each column of the parity check matrix H ₁ of FIG. 1 corresponding to the variable node of FIG. 2 is the above-described orders 4, 3, 3, 3, 2, 2, 2, and 2. The number of entries that match and are not 0 in each row of the parity check matrix H ₁ of FIG. 1 corresponding to the check node of FIG. 2 matches the above-described orders 6, 5, 5, and 5.

To demonstrate the degree distribution (degree distribution) for a node of the LDPC code, defines the ratio of the total number of the number and variable nodes of the variable node degree is i as _{f i,} and the number of check nodes degree-j The ratio with the total number of check nodes is defined as g _j .
For example, for the LDPC code corresponding to FIGS. 1 and _{2, f 2 = 4/8,} f 3 = 3/8, f 4 = 1/8, f i with respect to i ≠ 2, 3, 4 = 0, g ₅ = 3/4, g ₆ = 1/4, j ≠ 5, 6 for g _j = 0.

When the length of the LDPC code is defined as N, that is, the number of columns is defined as N and the number of rows is defined as N / 2, the density of entries that are not 0 in the all parity check matrix having the above-described degree distribution is as follows. It is calculated like the following formula (1).

  In Equation (1), as N increases, the density of ‘1’ in the parity check matrix decreases. In general, for an LDPC code, an LDPC code with a large N has a very low density because the code length N is inversely proportional to the density of entries that are not zero. The term “low density” in the name of the LDPC code is derived from the relationship described above.

Next, characteristics of the parity check matrix of the structural LDPC code applied in the present invention will be described with reference to FIG.
FIG. 3 schematically shows an LDPC code adopted as a standard technology in the second generation satellite digital video broadcast (DVB-S2), which is one of the European digital broadcast standards.
In FIG. 3, N ₁ indicates the length of the LDPC codeword, K ₁ provides the length of the information word, and (N ₁ -K ₁ ) provides the parity length. The integers M ₁ and q are determined so as to satisfy q = (N ₁ −K ₁ / M ₁ ). Preferably K ₁ / M ₁ should be an integer.

Referring to FIG. 3, the parity part of the parity check matrix, that is, the configuration from the K _1st column to the (N ₁ −1) th column has a dual diagonal configuration. Therefore, for the order distribution of the columns corresponding to the parity part, all the columns have the order '2' except for the last column having the order '1'.

In the parity check matrix, the information word part, that is, the configuration from the 0th column to the (K ₁ −1) th column is made using the following rules.
By grouping [Rule 1] K ₁ piece corresponding to the information word in the parity-check matrix of the column into a plurality of groups composed of M ₁ single row, generating a total K _{1 /} M ₁ column groups To do. The method of forming columns belonging to each column group follows the rule 2 below.

と仮定すると、‘１’を有する行の位置

は、ｉ番目の列グループ内のｊ（ここで、ｊ＝１，２，．．．，Ｍ_１−１）番目の列で下記の数式（２）のように定義される。

[Rule 2] First, the position of “1” in each 0th column in the i (where i = 1,..., K ₁ / M ₁ ) th column group is determined. The order of 0th column in each i th column group when represented by D _i, the positions of rows with '1'

Assuming that the position of the row with '1'

Is defined by the following equation (2) in the j-th column (where j = 1, 2,..., M ₁ −1) in the i-th column group.

According to the rules described above, it can be seen that all the orders of the columns belonging to the i-th (where i = 1,..., K ₁ / M ₁ ) column group are equal to D _i .
In order to easily understand the configuration of the DVB-S2 LDPC code storing information related to the parity check matrix in accordance with the rules described above, the following specific example will be described.

As a specific example, for N ₁ = 30, K ₁ = 15, M ₁ = 5, and q = 3, it relates to the position of the row having '1' for the 0th column in the three column groups The three sequences of information can be expressed as follows: Here, these sequences are referred to as “weight-1 position sequences” for convenience of explanation.

For the “weighted value-1 position sequence” of the 0th column in each column group, for convenience of explanation, only the corresponding position sequence can be expressed as follows for each column group. For example,
0 1 2
0 11 13
0 10 14
In other words, the i-th “weight-1 position sequence” in the i-th line sequentially indicates information about the position of the row for the i-th column group.

An LDPC code having the same concept as the DVB-S2 LDPC code of FIG. 4 can be generated by constructing a parity check matrix using information corresponding to the specific example described above and rule 1 and rule 2. it can.
It is known that DVB-S2 LDPC codes designed according to rules 1 and 2 can be efficiently encoded using structural shapes. Each step in the process of performing LDPC encoding using DVB-S2 based on the parity check matrix will be described with reference to the following example.

として示され、長さ（Ｎ_１−Ｋ_１）を有するパリティビットは、

として表現される。 In the following description, an encoding process using a DVB-S2 LDPC code having N ₁ = 16200, K ₁ = 10800, M ₁ = 360, and q = 15 will be described as a specific example. For convenience of explanation, an information word bit having a length K ₁ is

And the parity bits having length (N ₁ −K ₁ ) are

Is expressed as

[Step 1] The LDPC encoder initializes the parity bits as follows.

[Step 2] The LDPC encoder reads information about the row where “1” is located in the column group from the 0th “weight value-1 position sequence” of the stored sequence indicating the parity check matrix.
0 2084 1613 1548 1286 1460 3196 4297 2481 3369 3451 4620 2622

の値を示す。

上述した数式（３）において、

は、

として表現することもでき、

は、２進加算を意味する。 LDPC encoder updates particular parity bits p _x in accordance with the following equation (3) using the information and the first information bits i ₀ read above. Where x is

Indicates the value of.

In Equation (3) above,

Is

Can also be expressed as

Means binary addition.

上述した数式（４）において、ｘは、

の値を示す。上述した数式（４）は、上述した数式（２）と同一の概念を有することに留意しなければならない。 [Step 3] Next, the LDPC encoder performs the following _equation for the next 359 information word bits i _m (where m = 1, 2,..., 359) after i _0. The value of (4) is obtained.

In the above equation (4), x is

Indicates the value of. It should be noted that the above formula (4) has the same concept as the above formula (2).

をアップデートする。例えば、ｍ＝１、すなわち、ｉ_１に対して、ＬＤＰＣ符号化器は、下記の数式（５）で定義されるように、パリティビット

をアップデートする。

上述した数式（５）において、ｑ＝１５であることに留意しなければならない。ＬＤＰＣ符号化器は、ｍ＝１，２，．．．，３５９に対して上記のような工程を同様に実行する。 Next, the LDPC encoder performs an operation similar to Equation (3) using the value obtained in Equation (4) described above. That, LDPC encoder for _{i m}

Update. For example, for m = 1, i.e., i ₁ , the LDPC encoder may use parity bits as defined in equation (5) below.

Update.

It should be noted that q = 15 in Equation (5) above. The LDPC encoder has m = 1, 2,. . . , 359 are similarly performed.

の情報を読み出し、特定のｐ_ｘをアップデートする。ここで、ｘは、

である。
ＬＤＰＣ符号化器は、ｉ_３６０の後の次の３５９個の情報語ビットｉ_３６１，ｉ_３６２，．．．，ｉ_７１９に数式（４）を同様に適用することにより、

をアップデートする。 [Step 4] Similar to step 2, the LDPC encoder performs the first “weight value-1 position sequence” on the 361-th information word bit i ₃₆₀ .

It reads the information, updates the particular p _x. Where x is

It is.
LDPC _encoder, the following 359 information bits _{i 361, i 362} after _{i 360,.} . . , I ₇₁₉ by applying Equation (4) in the same way,

Update.

  [Step 5] The LDPC encoder repeats Steps 2, 3, and 4 for all groups having 360 information word bits respectively.

[Step 6] The LDPC encoder finally determines parity bits using Equation (6).

The parity bit p _i in the above equation (6) is a parity bit for which LDPC encoding has been completed.
As described above, in DVB-S2, the LDPC encoder performs LDPC encoding through steps 1 to 6.

  It is well known that the performance of LDPC codes is closely related to the cycle characteristics of Tanner graphs. In particular, it is well known from experiments that performance degradation can occur in a Tanner graph when the number of short-length cycles is large. Therefore, in order to design an LDPC code having high performance, the cycle characteristics on the Tanner graph should be considered.

  However, a method for designing a DVB-S2 LDPC code having good cycle characteristics has not been proposed. In fact, for the DVB-S2 LDPC code, the optimization of the cycle characteristics of the Tanner graph is not considered, so the error floor phenomenon is observed with a high signal-to-noise ratio (SNR). For these reasons, there is a problem that a method capable of efficiently improving cycle characteristics is required when designing an LDPC code having a DVB-S2 structure.

  Accordingly, the present invention has been proposed to solve the above-described problems of the prior art, and its purpose is to use a cyclic permutation matrix to design a DVB-S2 LDPC code in a communication system using an LDPC code. And a parity check matrix generation method of a quasi-cyclic LDPC code designed based on the above.

  Another object of the present invention is to provide a parity check matrix generation method for the same LDPC code as the DVB-S2 LDPC code having good Tanner graph characteristics in a communication system using the LDPC code.

  In order to achieve the above object, according to one aspect of the present invention, a parity check matrix generation method under the control of a control unit in a communication system having at least the control unit using a low density parity check (LDPC) code Is provided. The method includes determining parameters for designing the LDPC code, forming a first parity check matrix of a quasi-cyclic LDPC code according to the determined parameters, and the first parity check matrix. Generating a second parity check matrix through removal of a predetermined part of the parity part; and generating a third parity check matrix by realigning the second parity check matrix.

  In designing the DVB-S2 LDPC code, the present invention can optimize the performance of a communication system using the LDPC code by optimizing the characteristics of the Tanner graph.

It is a figure which shows an example of the parity check matrix of LDPC code whose length is 8. It is a figure which shows the Tanner graph of an example of the parity check matrix of LDPC code whose length is 8. It is a figure which shows the schematic structure of a DVB-S2 LDPC code. It is a figure which shows an example of the parity check matrix of a DVB-S2 LDPC code. FIG. 5 is a diagram illustrating a parity check matrix generated by rearranging columns and rows according to a predetermined rule in the parity check matrix of the DVB-S2 LDPC code of FIG. 4 according to an embodiment of the present invention. It is a figure which shows the parity check matrix of a quasi-cyclic LDPC code required for the design of DVB-S2 LDPC code by embodiment of this invention. It is a figure which shows the result obtained by converting the parity check matrix of a quasi-cyclic LDPC code required for the design of DVB-S2 LDPC code by embodiment of this invention. 4 is a flowchart illustrating a process of designing a DVB-S2 LDPC code according to an embodiment of the present invention. It is a figure which shows the computer simulation result of DVB-S2 LDPC code by embodiment of this invention. FIG. 2 is a block diagram illustrating a configuration of a transceiver in a communication system using a redesigned DVB-S2 LDPC code according to an embodiment of the present invention. It is a block diagram which shows the structure of the transmitter which uses the LDPC code by embodiment of this invention. It is a block diagram which shows the structure of the receiver which uses the LDPC code by embodiment of this invention. 6 is a flowchart illustrating a receiving operation in a receiving apparatus using an LDPC code according to an embodiment of the present invention.

DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, a preferred embodiment of the invention will be described in detail with reference to the accompanying drawings.
In the following description, from the viewpoint of clarity and conciseness, if it is determined that a specific description related to a known function or configuration related to the present invention obscures the gist of the present invention, a detailed description thereof will be given. Is omitted.

  The present invention provides a method for designing a DVB-S2 LDPC code with excellent Tanner graph characteristics. In addition, the present invention provides a method and apparatus for generating an LDPC codeword using a parity check matrix of the designed LDPC code.

The structural characteristics of the DVB-S2 LDPC code will be described using the parity check matrix of the DVB-S2 LDPC code shown in FIG.
In the case of the parity check matrix shown in FIG. 4, N ₁ = 30, K ₁ = 15, M ₁ = 5, and q = 3, and the row “weight” for the 0th column in the three column groups The “-1 position sequence” is as follows.
0 1 2
0 11 13
0 10 14
Here, the i-th “weight-1 position sequence” in the i-th line sequentially indicates information regarding the position of the row having 1 in the i-th column group.

First, the parity check matrix of FIG. 4 is reconstructed according to the following rules. FIG. 4 is a diagram illustrating a parity check matrix of the DVB-S2 LDPC code.
[Rule 3] The 0th row to the (N ₁ −K ₁ −1) th row are rearranged so that the (q · i + j) th row is positioned at the (M ₁ · j + i) th row. Here, 0 ≦ i <M ₁ and 0 ≦ j <q.
[Rule 4] The 0th column to the (K ₁ −1) th column are left as they are, and the K _1st column to the (N ₁ −1) th column are the (K ₁ + q · i + j) th column. Is rearranged so that is located in the (K ₁ + M ₁ · j + i) th column.

A parity check matrix having the form shown in FIG. 5 is obtained by reconstructing the parity check matrix of FIG. 4 according to rules 3 and 4.
FIG. 5 is a diagram illustrating a parity check matrix generated by rearranging each column and row according to a predetermined rule in the parity check matrix of the DVB-S2 LDPC code of FIG. 4 according to an embodiment of the present invention.

In FIG. 5, assuming that '1' is in the (N ₁ −1) th column of the 0th row, the parity check matrix of FIG. 5 has a size of M ₁ × M ₁ , that is, 5 × 5. It can be seen that this is a kind of quasi-cyclic LDPC code composed of a cyclic permutation matrix.
Here, “cyclic permutation matrix” means one type of permutation matrix obtained by cyclically moving each row of the identity matrix one by one to the right. 'Quasi-cyclic LDPC code' means a type of LDPC code generated by dividing a parity check matrix into several blocks having the same size and mapping a cyclic permutation matrix or 0 matrix to each block. To do.

  In summary, it can be seen that the parity check matrix approximated to the quasi-cyclic LDPC code can be obtained by reconstructing the parity check matrix of the DVB-S2 LDPC code through rules 3 and 4. It is also anticipated that a DVB-S2 LDPC code can be generated from a quasi-cyclic LDPC code through the inverse process of rules 3 and 4.

  Although little is known about the results of research on DVB-S2 LDPC codes, very various design methods are known for quasi-cyclic LDPC codes. In particular, the quasi-cyclic LDPC code design method includes a well-known method for optimizing cycle characteristics on a Tanner graph.

Embodiments of the present invention provide a method for designing a DVB-S2 LDPC code using a well-known method for improving cycle characteristics on a Tanner graph of a quasi-cyclic LDPC code.
However, since the method for improving the cycle characteristics of the quasi-cyclic LDPC code is not the main content, the specific content is omitted for convenience of explanation.

Hereinafter, a method for designing a DVB-S2 LDPC code using a quasi-cyclic LDPC code will be described. DVB-S2 LDPC code has a codeword length _{N 1,} an information word length _{K 1,} the parity length _(N 1 _-K 1), and _q = the _{(N 1 -K 1) / M} 1.

A parity check matrix of the quasi-cyclic LDPC code is shown in FIG.
FIG. 6 is a diagram illustrating a parity check matrix of a quasi-cyclic LDPC code necessary for designing a DVB-S2 LDPC code according to an embodiment of the present invention.
The parity check matrix shown in FIG. 6 has (N ₁ −K ₁ ) rows and N ₁ columns, and is divided into M ₁ × M ₁ partial blocks. For convenience of explanation, when t = K ₁ / M ₁ , the information word part and the parity part in the parity check matrix of FIG. 6 are each composed of t column blocks and q column blocks, and the total q Has row blocks. Here, N ₁ / M ₁ = t + q.

Each partial block constituting the parity check matrix of FIG. 6 corresponds to a cyclic permutation matrix or a zero matrix. Here, the cyclic permutation matrix has a size of M ₁ × M ₁ and is generated based on a cyclic permutation matrix P defined as follows.

In FIG. 6, a _ij has an integer from 0 to M ₁ −1 or a value of “∞”, P ⁰ is defined as the identity matrix I, and P ^∞ means an M ₁ × M ₁ zero matrix. . Also, the number “0” in the parity part means an M ₁ × M ₁ zero matrix.

と、を有することにある。
言い換えれば、パリティに対応する列ブロックは、図６に示す構成に固定される。巡回置換行列

は、次のように定義される。

The greatest feature of the parity check matrix of FIG. 6 is that the column block corresponding to the parity is the identity matrix I and the cyclic permutation matrix as shown in the figure.

It is in having.
In other words, the column block corresponding to the parity is fixed to the configuration shown in FIG. Cyclic permutation matrix

Is defined as follows:

The quasi-cyclic LDPC code shown in FIG. 6 is a portion that does not change in the process of optimizing the cycle of the quasi-cyclic LDPC code because the configuration of the column block corresponding to the parity portion is fixed.
In other words, since the column block corresponding to this parity part is fixed by the parity check matrix of FIG. 6, the connection state between the variable nodes corresponding to this parity is determined on the Tanner graph, whereby the Tanner graph In order to optimize the cycle, it is only necessary to optimize the connection state between the variable nodes corresponding to the information word part.

  As described above, a great variety of methods are known for optimizing the cycle characteristics on the Tanner graph of a quasi-cyclic LDPC code. In the present invention, the design method of a quasi-cyclic LDPC code having a Tanner graph with optimized cycle characteristics is not the main content, and therefore the specific content is omitted.

It is assumed that the degree distribution is determined so that the quasi-cyclic LDPC code design method can have excellent performance in a state where the configuration of the parity part is fixed in the quasi-cyclic parity check matrix of FIG.
According to the corresponding degree distribution, the positions of the cyclic permutation matrix and the zero matrix are determined in the column block corresponding to the information word part, and the cycle characteristics of the Tanner graph are optimized.

で１番目の行での最後の列の‘１’を除去することにより行うことができる。
図７は、本発明の実施形態によるＤＶＢ−Ｓ２ ＬＤＰＣ符号の設計のために必要な準巡回ＬＤＰＣ符号のパリティ検査行列を変換することにより得られた結果を示す図である。
図７において、巡回置換行列

が次のような行列Ｑに変更されることに留意すべきである。

For example, the form shown in FIG. 7 is a cyclic permutation matrix corresponding to the last (N ₁ / M ₁ ) th or (t + q) th column block in the _first row block in the parity check matrix of FIG.

This can be done by removing the last column '1' in the first row.
FIG. 7 is a diagram illustrating a result obtained by converting a parity check matrix of a quasi-cyclic LDPC code necessary for designing a DVB-S2 LDPC code according to an embodiment of the present invention.
In FIG. 7, a cyclic permutation matrix

Note that is changed to a matrix Q as follows:

The following rule 5 and rule 6 are defined by applying the reverse process of rule 3 and rule 4.
[Rule 5] The 0th column to the (K ₁ −1) th column are left as they are, and the K _1st column to the (N ₁ −1) th column are the (K ₁ + M ₁ · j + i) th columns. Rearrange so that the column is located in the (K ₁ + q · i + j) th column. Here, 0 ≦ i <M ₁ and 0 ≦ j <q.
[Rule 6] The 0th row to the (N ₁ −K ₁ −1) th row are rearranged so that the (M ₁ · j + i) th row is positioned at the (q · i + j) th row. .

The parity check matrix of the LDPC code generated from the quasi-cyclic LDPC code of FIG. 6 through the above-described steps by applying the rules 5 and 6 is, for example, a parity having the form of the DVB-S2 LDPC code shown in FIG. It becomes a check matrix.
The code word length, the information word length, and the parity length are N ₁ , K ₁ , and (N ₁ −K ₁ ), respectively, and DVB− in which q = (N ₁ −K ₁ ) / M ₁ The above-described method for designing the S2 parity check matrix can be summarized in the following steps.

[DVB-S2 LDPC code design process]
FIG. 8 is a flowchart illustrating a process of designing a DVB-S2 LDPC code according to an embodiment of the present invention.
Referring to FIG. 8, in step 801, parameters necessary for designing a desired DVB-S2 LDPC code are determined. In the present invention, it is assumed that not only a good degree distribution but also parameters such as code word length and information word length are predetermined in order to design a DVB-S2 LDPC code.

Next, in step 803, as shown in FIG. 6, the parity check matrix of the quasi-cyclic LDPC code composed of a cyclic permutation matrix of size M ₁ × M ₁ and a zero matrix is configured according to the parameters determined in step 801. Is done. In FIG. 6, the column block corresponding to the parity portion is always fixed in a specific form.

Next, in step 805, the cyclic permutation matrix of the column block corresponding to the information word portion of FIG. 6 is determined by applying an algorithm that improves the cycle characteristics of the Tanner graph of the quasi-cyclic LDPC code. Here, a known algorithm may be used to improve the cycle characteristics.
Next, in step 807, the parity check matrix shown in FIG. 7 is obtained by, for example, removing “1” in the last column in the first row in the parity check matrix of FIG. 6 determined in step 805. can get.

Next, in step 809, the columns and rows in the parity check matrix of FIG. 7 are realigned by applying rules 5 and 6 to the parity check matrix of FIG. The finally obtained parity check matrix can be, for example, the DVB-S2 LDPC code shown in FIG.
The codeword can be generated by applying the DVB-S2 LDPC encoding process described above to the LDPC code designed through the above steps.

In order to analyze the performance of the DVB-S2 LDPC code, a DVB-S2 LDPC code having the following parameters was designed. For example,
N ₁ = 648000, K ₁ = 38880, M ₁ = 360, q = 72

In order to design a DVB-S2 LDPC code having a coding rate of 3/5 having this parameter, the parity check matrix shown in Table 1 and Table 2 below applies, for example, a DVB-S2 LDPC code design process. Can be obtained from a quasi-cyclic LDPC code having a total of N ₁ / M ₁ = 180 column blocks and q = (N ₁ −K ₁ ) / M ₁ = 72 row blocks. The i-th “weight-1 position sequence” in the i-th column sequentially indicates information regarding the position of the row having 1 in the i-th column group.

In addition, a DVB-S2 LDPC code having the following parameters was designed. For example,
N ₁ = 16200, K ₁ = 9720, M ₁ = 360, q = 18
In order to design a DVB-S2 LDPC code having a coding rate of 3/5 having this parameter, the parity check matrix shown in Tables 3 to 6 is applied to, for example, the DVB-S2 LDPC code design process. It can be obtained from a quasi-cyclic LDPC code with a total of N ₁ / M ₁ = 45 column blocks and q = (N ₁ −K ₁ ) / M ₁ = 18 row blocks. Note that the i-th “weight-1 position sequence” of the i-th column sequentially indicates information about the position of the row having 1 in the i-th column group.

A performance comparison between the newly designed DVB-S2 LDPC code and the existing DVB-S2 LDPC code is shown in FIG.
FIG. 9 is a diagram illustrating a computer simulation result of the DVB-S2 LDPC code according to the embodiment of the present invention.

It can be seen that when the Additive White Gaussian Noise (AWGN) channel uses a binary phase shift (BPSK) modulation scheme, a performance improvement of about 0.15 dB is made at BER = 10-4.
As shown in Tables 1 to 6, the performance of the DVB-S2 LDPC code having a coding rate of 3/5 can be improved by changing only the information related to the parity check matrix.

The DVB-S2 LDPC code design process described with reference to FIG. 8 can be used not only for a coding rate of 3/5 but also for various coding rates. A DVB-S2 LDPC code having the following parameters was designed as an embodiment for designing DVB-S2 LDPC codes having other coding rates.
N ₁ = 64800, K ₁ = 43200, M ₁ = 360, q = 60

In order to design a DVB-S2 LDPC code having a coding rate of 2/3 having this parameter, the parity check matrix shown in Tables 7 to 10 applies, for example, the DVB-S2 LDPC code design process of FIG. By doing so, it can be obtained from a quasi-cyclic LDPC code having a total of N ₁ / M ₁ = 180 column blocks and q = 60 row blocks.

  FIG. 10 is a block diagram illustrating a configuration of a transceiver in a communication system using a redesigned DVB-S2 LDPC code according to an embodiment of the present invention.

を無線チャネル１０２０を介して受信されたデータから計算する。 Referring to FIG. 10, the message u is input to the LDPC encoder 1011 in the transmitter 1010 before being transmitted to the receiver 1030. The LDPC encoder 1011 encodes the input message u and transmits the encoded signal c to the modulator 1013. The modulator 1013 modulates the encoded signal and transmits the modulated signal s to the receiver 1030 through the radio channel 1020. A demodulator 1031 in the receiver 1030 demodulates the signal r transmitted from the transmitter 1010 and outputs the demodulated signal x to the LDPC decoder 1033. After that, the LDPC decoder 1033 determines the estimated value of the message.

Is calculated from the data received via the wireless channel 1020.

FIG. 11 shows a specific configuration of the transmission apparatus in the communication system using the redesigned DVB-S2 LDPC code.
FIG. 11 is a block diagram illustrating a configuration of a transmission apparatus using a redesigned LDPC code according to an embodiment of the present invention.
The transmission apparatus includes a control unit 1130, an LDPC code parity check matrix extraction unit 1110, and an LDPC encoder 1150.

  The LDPC code parity check matrix extraction unit 1110 extracts an LDPC code parity check matrix according to system requirements. The LDPC code parity check matrix can be extracted from the sequence information shown in Tables 1 to 10, can be extracted from the memory storing the parity check matrix, can be given from the transmission device, or can be transmitted. It can also be generated on the device.

The control unit 1130 performs control so as to determine a necessary parity check matrix according to the coding rate, the length of the codeword, or the length of the information word so as to meet the requirements of the system.
The LDPC encoder 1150 performs encoding based on the LDPC code parity check matrix information read by the control unit 1130 and the LDPC code parity check matrix extraction unit 1110.

FIG. 12 is a block diagram showing a configuration of a receiving apparatus according to the embodiment of the present invention.
FIG. 12 is a diagram illustrating a receiving apparatus that receives a signal transmitted from a communication system using the redesigned DVB-S2 LDPC code and restores data desired by a user from the received signal.

The reception apparatus includes a control unit 1250, a parity check matrix determination unit 1230, an LDPC code parity check matrix extraction unit 1270, a demodulator 1210, and an LDPC decoder 1290.
Demodulator 1210 demodulates the received LDPC code, and transmits the demodulated signal to parity check matrix determination section 1230 and LDPC decoder 1290.

The parity check matrix determination unit 1230 determines the parity check matrix of the LDPC code used in the system based on the demodulated signal under the control of the control unit 1250.
The controller 1250 transmits the determination result from the parity check matrix determination unit 1230 to the LDPC code parity check matrix extraction unit 1270 and the LDPC decoder 1290.

  The LDPC code parity check matrix extraction unit 1270 extracts a parity check matrix of an LDPC code requested by the system under the control of the control unit 1250 and transmits the parity check matrix to the LDPC decoder 1290. As described above, the parity check matrix of the LDPC code can be extracted from the sequence information shown in Tables 1 to 10, can be extracted from the memory storing the parity check matrix, and is given from the receiving apparatus. It can also be generated by the receiving device.

  The LDPC decoder 1290 performs decoding based on the received signal transmitted from the demodulator 1210 and information on the parity check matrix of the LDPC code transmitted from the LDPC code parity check matrix extraction unit 1270 under the control of the control unit 1250. Execute the conversion.

FIG. 13 shows an operation flowchart of the receiving apparatus in FIG.
In step 1301, the demodulator 1210 receives a signal transmitted from a communication system using the redesigned DVB-S2 LDPC code, and demodulates the received signal. Thereafter, in step 1303, the parity check matrix determination unit 1230 determines the parity check matrix of the LDPC code used in the system based on the demodulated signal.

  The result determined by the parity check matrix determination unit 1230 is transmitted to the LDPC code parity check matrix extraction unit 1270 in step 1305. In step 1307, the LDPC code parity check matrix extraction unit 1270 extracts a parity check matrix of an LDPC code required by the system, and transmits the extracted parity check matrix to the LDPC decoder 1290.

  As described above, the parity check matrix of the LDPC code can be extracted from the sequence information shown in Tables 1 to 10, or can be extracted from the memory storing the parity check matrix, and is given from within the transmission apparatus. Or can be generated at the transmitter.

  Thereafter, the LDPC decoder 1290 performs decoding based on the information related to the parity check matrix of the LDPC code transmitted from the LDPC code parity check matrix extraction unit 1270 in step 1309.

  Although the present invention has been described in detail with reference to specific embodiments, it will be apparent to those skilled in the art that various modifications can be made without departing from the scope and spirit of the invention. The scope of the present invention should not be limited to the above-described embodiments, but should be defined within the scope of the appended claims and their equivalents.

1010 Transmitter 1011 LDPC Encoder 1013 Modulator 1020 Radio Channel 1030 Receiver 1031 Demodulator 1033 LDPC Decoder 1110 LDPC Code Parity Check Matrix Extraction Unit 1130 Control Unit 1150 LDPC Encoder 1210 Demodulator 1230 Parity Check Matrix Determination Unit 1250 Control unit 1270 LDPC code parity check matrix extraction unit 1290 LDPC decoder

Claims (7)

A parity check matrix generation method under the control of a control unit in a communication system having at least a control unit using a low density parity check (Low-Density Parity-Check: hereinafter referred to as LDPC) code,
Determining parameters for designing the LDPC code;
Forming a first parity check matrix of a quasi-cyclic LDPC code according to the determined parameters;
Generating a second parity check matrix through removal of a predetermined part of the parity part in the first parity check matrix;
Generating a third parity check matrix by rearranging the second parity check matrix, and generating a parity check matrix of a low density parity check code.   The step of generating a second parity check matrix generates the second parity check matrix by removing the last column of “1” in the first row in the first parity check matrix. The parity check matrix generation method of the low density parity check code according to claim 1. Generating a third parity check matrix includes realigning the second parity check matrix according to the following rules 1 and 2:
The rule 1 is that the 0th column to the (K ₁ −1) th column of the second parity check matrix are left as they are, and the K _1st column to the (N ₁ −1) th column are , (K ₁ + M ₁ · j + i) -th column is rearranged so that it is located in the (K ₁ + q · i + j) -th column. Here, K ₁ indicates the length of the information word of the second parity check matrix, N ₁ indicates the length of the code word, and 0 ≦ i <M ₁ , 0 ≦ j <q, and q = (N ₁ −K ₁ ) / M ₁ , where M ₁ , q, and K ₁ / M ₁ are integers,
The rule 2 is that the 0th to (N ₁ −K ₁ −1) th rows of the second parity check matrix are the (M ₁ · j + i) th row and the (q · i + j) th row. Realign to be located at Here, K ₁ indicates the length of the information word of the second parity check matrix, N ₁ indicates the length of the code word, and 0 ≦ i <M ₁ , 0 ≦ j <q, and q The low density parity check code according to claim ₁ , wherein = (N ₁ -K ₁ ) / M ₁ , wherein M ₁ , q, and K ₁ / M ₁ are integers. Parity check matrix generation method. The method of claim 1, wherein the third parity check matrix is generated as defined in Table 1 below.

The method of claim 4, wherein the third parity check matrix is generated as defined in Table 2 below.

The method of claim 4, wherein the third parity check matrix is generated as defined in Table 3 below.

The third parity check matrix is composed of a plurality of column groups obtained by grouping columns corresponding to information words into columns each having a predetermined number of columns.
5. The low-density parity check code according to claim 4, wherein each row in Table 1 includes sequence information indicating a position of a row where “1” is located in a corresponding column group of the parity check matrix. Parity check matrix generation method.

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