JP2012233966A - Drive circuit of display device and test control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that the number of probes used in testing increases.SOLUTION: Drive circuits of a display device respectively drive first and second data lines of the display device. The drive circuits respectively include: first and second data registers for respectively storing first and second display data to be displayed in the display device and outputting first and second signals; first and second DA converters for respectively outputting first and second analog signals in response to the first and the second signals, a pair of output terminals for driving the first and second data lines in response to the first and second analog signals; a switching circuit for selectively outputting a first test output based on the first display data and a second test output based on the second display data to one of the pair of the output terminals in response to a test control signal from an external test circuit when testing; and a control circuit for controlling the switching circuit.

Description

  The present invention relates to a display device driving circuit and a test control method thereof.

  In a display device, particularly a data line driving circuit LSI for a liquid crystal display, the total number of input terminals and power input terminals is about several tens to one hundred, and the number of output terminals for driving the data lines of the liquid crystal display is several hundred. Since then, there are those that exceed a thousand.

  On the other hand, LSI testers that simultaneously test over 1,000 output signals (output terminals) are expensive, and there is a problem that the inspection cost increases when they are introduced. In addition, it is necessary to amortize the LSI tester corresponding to several hundreds of output signals (output terminals) that have been used in the past, and this also raises the problem that the inspection cost increases.

  On the other hand, in order to shorten the test time and test cost of the data line drive circuit LSI, the drive circuit LSI having a small number of output terminals may perform a multi-test for simultaneously testing a plurality of LSIs at a time.

  As described above, in the test for LSI products, an attempt is made to reduce the number of LSI tester inspection units (probes) used for the output terminals of the LSI to be inspected. For example, there is a conventional technique as disclosed in Patent Document 1. Patent Document 1 is a technology related to a tape carrier package on which an LSI chip is mounted, and will be described with reference to FIG.

  As shown in FIG. 41, the tape carrier package of Patent Document 1 includes a tape carrier 1 and an LSI chip 2 mounted on the tape carrier 1. The LSI chip 2 has a number of outputs D1 to D4 and includes bumps 20 corresponding to the outputs. The tape carrier 1 is formed with outer leads 16 connected to the bumps 20 and test electrodes 3A and 3B. The outer lead 16 corresponding to the output D1 is connected to the test electrode 3B. The outer leads 16 corresponding to the outputs D2 and D4 are respectively connected to the test electrode 3A.

  The LSI chip 2 includes switches SW1 to SW4 corresponding to the outputs D1 to D4 and switches SW5 connected between the bumps 20 of the outputs D1 and D3. The LSI chip 2 controls on / off of the switches SW1 to SW5, so that one of the outputs D4 and D2 and the outputs D3 and D1 among the outputs D1 to D4 is respectively The selected test electrodes 3A and 3B are selected to be connected. As a result, the number of test electrodes can be reduced for a plurality of outputs of the LSI chip, and the area on the tape carrier necessary for the arrangement can be reduced.

  Further, as related technologies, there are also those disclosed in Patent Documents 2 and 3. Patent Documents 2 and 3 disclose techniques related to a drive circuit for a liquid crystal display device. However, in Patent Documents 2 and 3, there is no description about the quality determination test of the semiconductor integrated circuit chip on which the drive circuit is mounted, or no suggestion about the test method, and each component included in the drive circuit at the time of the test The control method of the switch between them is also unclear.

Japanese Patent Laid-Open No. 10-209201 Japanese Patent Laid-Open No. 11-95729 JP 2006-323341 A

  Here, in the pass / fail judgment test of the semiconductor element (LSI), the state in which the semiconductor element (LSI) is formed on the semiconductor wafer arranged in a matrix and the tape carrier package after separating each semiconductor element (LSI) Two tests are usually performed in the state of being mounted on. However, in the technique of Patent Document 1 described above, the effect can be obtained only after being mounted on a tape carrier package. Therefore, when the LSI is mounted on a semiconductor wafer, the number of output terminal inspection units (probes) used is reduced. There is a problem that can not be.

  In addition, with recent advances in manufacturing miniaturization technology, the pitch between the output terminals of LSI chips and the distance between terminals has been reduced. For this reason, it is increasingly difficult to bring a large number of inspection units (probes) into contact with the narrow pitched LSI output terminals when mounted on a semiconductor wafer. There is a need for a test method that reduces the number of probes.

  One embodiment of the present invention is a display device driver circuit that drives a first data line and a second data line of a display device, respectively, and the first display data and the second display data are displayed on the display device. And a first data register and a second data register for outputting a first signal and a second signal, respectively, and in accordance with the first signal and the second signal, In response to the first DA signal and the second DA converter that output the analog signal and the second analog signal, respectively, and the first data line and the second analog signal according to the first analog signal and the second analog signal. And a first test output based on the first display data for one of the output terminal pairs in response to a test control signal from an external test circuit during testing. And the second display device A switching circuit for selectively outputting a second test output based on data, a display device drive circuit and a control circuit for controlling the switch circuit.

  Another aspect of the present invention is a test control method for a display device driving circuit that drives a first data line and a second data line of a display device, respectively, wherein the display device driving circuit displays on the display device. A first data register and a second data register for storing the first display data and the second display data, respectively, and outputting the first signal and the second signal, respectively, and the first signal And a first DA converter and a second DA converter that respectively output a first analog signal and a second analog signal in response to the second signal, the first analog signal, and the second analog signal, In response to the output terminal pair for driving the first data line and the second data line, and for one of the output terminal pairs in response to a test control signal from an external test circuit during the test, First display data And a switch circuit that selectively outputs a first test output based on the second test output based on the second display data, and a test control method for a display device drive circuit that controls the switch circuit. .

  The present invention captures the test output of the display device driving circuit into the external test circuit if the probe from the external test circuit is connected to only one of the output terminal pairs even when testing the display device driving circuit on the semiconductor wafer. Can do. Then, whether or not the display device drive circuit is good can be determined based on whether or not the test output satisfies a specified value. For this reason, it is possible to reduce the number of probes necessary for testing the display device driving circuit, whether it is mounted on a semiconductor wafer or mounted on a tape carrier package.

  The present invention can reduce the number of inspection units (probes) used during testing.

1 is an inspection system according to a first embodiment; FIG. 3 is a diagram illustrating a relationship between an LSI chip on which the drive circuit according to the first embodiment is mounted and a probe. 2 is a block configuration of a drive circuit according to the first exemplary embodiment; 3 is a flowchart of the entire wafer test according to the first embodiment. 3 is a flowchart of a function test according to the first embodiment. FIG. 6 is a schematic diagram for explaining the operation of the drive circuit in the function test according to the first embodiment; FIG. 6 is a schematic diagram for explaining the operation of the drive circuit in the function test according to the first embodiment; FIG. 6 is a schematic diagram for explaining the operation of the drive circuit in the function test according to the first embodiment; FIG. 6 is a schematic diagram for explaining the operation of the drive circuit in the function test according to the first embodiment; 3 is a flowchart of a leak test according to the first embodiment. FIG. 6 is a schematic diagram for explaining the operation of the drive circuit in the leak test according to the first embodiment; FIG. 6 is a schematic diagram for explaining the operation of the drive circuit in the leak test according to the first embodiment; FIG. 6 is a schematic diagram for explaining the operation of the drive circuit in the leak test according to the first embodiment; FIG. 6 is a schematic diagram for explaining the operation of the drive circuit in the leak test according to the first embodiment; It is a schematic diagram explaining the problem of the conventional drive circuit. FIG. 6 is a schematic diagram for explaining the effect of the drive circuit according to the first embodiment; 3 is a block configuration of a drive circuit according to a second exemplary embodiment. FIG. 10 is a schematic diagram for explaining the operation of a drive circuit in a function test according to a second embodiment; FIG. 10 is a schematic diagram for explaining the operation of a drive circuit in a function test according to a second embodiment; FIG. 10 is a schematic diagram for explaining the operation of a drive circuit in a function test according to a second embodiment; FIG. 10 is a schematic diagram for explaining the operation of a drive circuit in a function test according to a second embodiment; 10 is a flowchart of a leak test according to the second embodiment. FIG. 10 is a schematic diagram for explaining the operation of the drive circuit in the leak test according to the second embodiment; FIG. 10 is a schematic diagram for explaining the operation of the drive circuit in the leak test according to the second embodiment; FIG. 10 is a schematic diagram for explaining the operation of the drive circuit in the leak test according to the second embodiment; FIG. 10 is a schematic diagram for explaining the operation of the drive circuit in the leak test according to the second embodiment; FIG. 10 is a schematic diagram for explaining the operation of the drive circuit in the leak test according to the second embodiment; FIG. 10 is a schematic diagram for explaining the operation of the drive circuit in the leak test according to the second embodiment; 4 is a block configuration of a drive circuit according to a third embodiment. FIG. 10 is a schematic diagram for explaining the operation of a drive circuit in a function test according to a third embodiment; FIG. 10 is a schematic diagram for explaining the operation of a drive circuit in a function test according to a third embodiment; FIG. 10 is a schematic diagram for explaining the operation of a drive circuit in a function test according to a third embodiment; FIG. 10 is a schematic diagram for explaining the operation of a drive circuit in a function test according to a third embodiment; 10 is a flowchart of a leak test according to the third exemplary embodiment. FIG. 10 is a schematic diagram for explaining the operation of a drive circuit in a leak test according to a third embodiment; FIG. 10 is a schematic diagram for explaining the operation of a drive circuit in a leak test according to a third embodiment; FIG. 10 is a schematic diagram for explaining the operation of a drive circuit in a leak test according to a third embodiment; FIG. 10 is a schematic diagram for explaining the operation of a drive circuit in a leak test according to a third embodiment; FIG. 10 is a schematic diagram for explaining the operation of a drive circuit in a leak test according to a third embodiment; FIG. 10 is a schematic diagram for explaining the operation of a drive circuit in a leak test according to a third embodiment; This is a conventional LSI chip configuration.

  Embodiment 1 of the Invention

  Hereinafter, a specific first embodiment to which the present invention is applied will be described in detail with reference to the drawings. In the first embodiment, the present invention is applied to a driving circuit for a display device and a test method for a semiconductor integrated circuit (hereinafter referred to as LSI) chip on which the driving circuit is mounted.

  First, a wafer test test system on which the LSI chip according to the first embodiment is mounted will be described. FIG. 1 shows the configuration of the test system. As shown in FIG. 1, the test system according to the first embodiment includes a tester 101, a probe card 102, and a wafer 103.

  On the wafer 103, LSI chips before being cut are arranged in a matrix. Each LSI chip is provided with a drive circuit 100 for a display device to be described later according to the first embodiment. The drive circuit 100 drives data lines of a display device such as a liquid crystal display. The driving circuit 100 has, for example, 960 output terminals for data line driving signals for driving the data lines in the first embodiment.

  The probe card 102 includes a plurality of inspection units 104 (hereinafter referred to as probes 104). In the first embodiment, the number of probes 104 included in the probe card 102 is, for example, 1536 pins. As shown in FIG. 2, these probes 104 are brought into contact with the output terminal of the drive circuit 100 mounted on the LSI chip and the test signal input terminal.

  Here, in the first embodiment, these probes 104 are applied to one of the adjacent output terminals of the drive circuit 100 (for example, an odd-numbered output terminal 16A (see FIG. 3) described later). That is, 480 chips are used per LSI chip. As described above, since the probe card 102 has 1536 pins, even if there are 30 input terminals, a maximum of 3 LSI chips can be tested at a time ((480 + 30) × 3 = 1530 <1536). .

  Of course, it is necessary to supply power to the LSI chip to be inspected from the tester 101 during the test, but the power supply is common to all of the LSI chips to be inspected. In a general LSI tester, the number of power supplies is not counted as the number of signal pins. It is common to supply in a grid. In addition, a common input signal is applied to each LSI chip to be inspected from the probe connected to the input terminal of the LSI chip. Since a test similar to the output leak test described later is also performed on the input terminal, Different probes need to be applied. CMOS input terminals that are not pulled up or pulled down inside the LSI chip cannot be opened during testing, but the number of input terminals is smaller than the output terminals and the terminal pitch on the LSI chip is also increased. Therefore, there is no problem that the probes interfere with each other even if the probes are applied to all the input pins.

  The tester 101 inputs a test signal to the LSI chip via the probe card 102 and detects an output signal (for example, voltage or current) output from the output terminal of the LSI chip. If the detected output signal is within the standard compared with a predetermined standard value, the LSI chip to be inspected is determined as a non-defective product, and if it is out of the standard, it is determined as a defective product.

  Next, the drive circuit 100 of the display device according to the first embodiment mounted on the LSI chip to be inspected will be described. FIG. 3 shows the configuration of the drive circuit 100 of the display device according to the first embodiment. Note that the drive circuit 100 shown in FIG. 3 shows two adjacent channels, and actually there are drive circuits corresponding to a plurality of channels having the same configuration. In this example, a drive circuit corresponding to one of two adjacent channels is referred to as an odd-numbered stage, and a drive circuit corresponding to the other is referred to as an even-numbered stage.

  As shown in FIG. 3, the drive circuit 100 includes a pair of data registers 11A and 11B, a pair of data latches 12A and 12B, a pair of level shift circuits 13A and 13B, and a pair of digital-analog conversion circuits (hereinafter referred to as “digital-analog conversion circuits”). 14A, 14B), a pair of output amplifiers 15A, 15B, a pair of output terminals 16A, 16B, switch circuits 17-19, a control circuit 20, and a common line K.

  The switch circuit 17 includes switch elements SW11A, SW11B, SW12A, and SW12B.

  Switch element SW11A is connected between data register 11A and data latch 12A. Switch element SW11B is connected between data register 11B and data latch 12B. Switch element SW12A is connected between data register 11A and data latch 12B. Switch element SW12B is connected between data register 11B and data latch 12A.

  The switch elements SW11A and SW11B, and SW12A and SW12B may be simultaneously controlled to be turned on or off in accordance with a control signal from the control circuit 20. Alternatively, the switch elements SW11A, SW11B, SW12A, and SW12B may be individually controlled to be turned on or off in accordance with a control signal from the control circuit 20.

  The switch circuit 18 includes switch elements SW21A, SW21B, SW22A, and SW22B.

  The switch element SW21A is connected between the DAC 14A and the output amplifier 15A. The switch element SW21B is connected between the DAC 14B and the output amplifier 15B. The switch element SW22A is connected between the DAC 14A and the output amplifier 15B. The switch element SW22B is connected between the DAC 14B and the output amplifier 15A.

  The switch elements SW21A and SW21B and SW22A and SW22B may be simultaneously controlled to be turned on or off in accordance with a control signal from the control circuit 20. Alternatively, the switch elements SW21A, SW21B, SW22A, and SW22B may be individually controlled to be turned on or off in accordance with a control signal from the control circuit 20.

  The switch circuit 19 includes switch elements SW30, SW32A, and SW32B.

  Switch element SW30 is connected between output terminals 16A and 16B. The switch element SW32A is connected between the output terminal 16A and the common line K. The switch element SW32B is connected between the output terminal 16B and the common line K.

  The switch elements SW30, SW32A, and SW32B may be simultaneously controlled to be turned on or off in accordance with a control signal from the control circuit 20. Alternatively, the switch elements SW30, SW32A, and SW32B may be individually controlled to be turned on or off in accordance with a control signal from the control circuit 20.

  The data registers 11A and 11B take in image data for one pixel assigned to each channel at a predetermined cycle and output it to the next stage. The predetermined period is determined by a sampling signal from each shift register corresponding to each channel (not shown).

  The data latches 12A and 12B latch output image data from one or the other of the data registers 11A and 11B, respectively, and output them to the next stage. The image data latched by the data latches 12A and 12B is determined according to the connection state of the switch circuit 17.

  For example, when the switch elements SW11A and SW11B of the switch circuit 17 are on and the switch elements SW12A and SW12B are off, the data latch 12A latches the output data of the data register 11B and the data latch 12B. Conversely, when the switch elements SW11A and SW11B are off and the switch elements SW12A and SW12B are on, the data latch 12A latches the output data of the data register 11B and the data latch 12B.

  The level shift circuits 13A and 13B convert the logical voltages of the image data output from the corresponding data latches 12A and 12B to higher voltages (for example, 3V to 20V) that can be handled by the circuit elements of the DACs 14A and 14B, and output them. .

  The DACs 14A and 14B decode the digital output image data from the corresponding level shift circuits 13A and 13B, respectively, and output a voltage level corresponding to the display gradation corresponding to the image data.

  Note that the DAC 14A inputs a gradation voltage from a negative voltage generation circuit that generates a negative voltage range (for example, 0 V to 10 V). For this reason, the output voltage level also becomes a voltage value according to the negative voltage range. Similarly, the DAC 14B inputs a gradation voltage from a positive voltage generation circuit that generates a positive voltage range (for example, 10V to 20V). For this reason, the output voltage level also has a voltage value corresponding to the positive voltage range. Note that the positive voltage range or the negative voltage range input by the DACs 14A and 14B may be opposite to those described above.

  The output amplifiers 15A and 15B amplify the output gradation image data from one or the other of the DACs 14A and 14B, respectively, and output them to the next stage. The output amplifiers 15A and 15B are activated and deactivated separately according to the enable signal EN from the control circuit 20, and when activated, amplify and output the input gradation image data, and deactivate In this case, the output is in a high impedance state.

  When performing a leak test, which will be described later, when the output amplifiers 15A and 15B are activated according to the enable signal EN, for example, 0V (ground voltage VSS), 20V (power supply voltage) according to the output from the previous stage. The switch circuit 18 is controlled by a control signal from the control circuit 20 so as to output (VDD).

  In the drive circuit of the first embodiment shown in FIG. 3, the output amplifiers 15A and 15B can amplify in all voltage ranges including the positive voltage range and the negative voltage range described above. Hereinafter, this is referred to as a full amplifier. As shown in later embodiments, there are output amplifiers (for example, 25A and 25B in FIG. 17 described later) that can amplify only one voltage range of the positive voltage range or the negative voltage range, and this is referred to as a half amplifier.

  The image gradation data to be amplified by the output amplifiers 15A and 15B is determined according to the connection state of the switch circuit 18.

  For example, when the switch elements SW21A and SW21B of the switch circuit 18 are on and the switch elements SW22A and SW22B are off, the output amplifier 15A amplifies the output gradation data of the DAC 14A, and the output amplifier 15B amplifies the output gradation data of the DAC 14B. Conversely, when the switch elements SW21A and SW21B are off and the switch elements SW22A and SW22B are on, the output amplifier 15A amplifies the output gradation data of the DAC 14B, and the output amplifier 15B amplifies the output gradation data of the DAC 14A.

  In the normal operation in which the drive circuit 100 drives the data lines of the liquid crystal display device, when the switch elements SW11A and SW11B of the switch circuit 17 are on and the switch elements SW12A and SW12B are off, the switch circuit 18 The switch elements SW21A and SW21B are turned on, and the switch elements SW22A and SW22B are turned off. Conversely, when the switch elements SW11A and SW11B of the switch circuit 17 are off and the switch elements SW12A and SW12B are on, the switch elements SW21A and SW21B of the switch circuit 18 are off and the switch elements SW22A and SW22B are on. Become. This makes it possible to invert the polarity of the pixels of the liquid crystal display device.

  The output terminals 16A and 16B output the output image gradation data output from the output amplifiers 15A and 15B, respectively, to the data lines (not shown) of the corresponding liquid crystal display device as data line drive signals, and drive the data lines. Although not shown in FIG. 3, an ESD protection element is connected to each of the output terminals 16A and 16B. For example, diodes (see FIG. 11 and the like) are connected between the power supply terminal VDD and the output terminal, and between the output terminal and the ground terminal VSS, respectively.

  Note that, during the display operation in which the drive circuit 100 drives the data lines of the liquid crystal display device, the switch elements SW30, SW32A, and SW32B of the switch circuit 19 are turned off. Further, in order to realize power saving, all output amplifiers are deactivated by the enable signal EN and the switch elements SW32A, SW32B, and SW30 are turned on during the charge recovery operation for recovering the charges on the data lines of the display panel. Thus, charge sharing (charge recovery) of all data lines is performed via the common line K.

  The control circuit 20 controls, for example, on / off control of switch element groups included in each of the switch circuits 17 to 19 and enable of the output amplifiers 15A and 15B in accordance with a test signal from the tester 101 outside the LSI chip. To do. Further, it has a function of applying a predetermined voltage (for example, power supply voltage VDD) to the common line K. For example, conduction of each switch (not shown) between the power supply terminal VDD, the ground terminal VSS and the common line K is controlled.

  FIG. 4 shows a flowchart of a pass / fail judgment test performed by the tester 101 on the target LSI chip drive circuit 100. Here, as described above, in the first embodiment, a probe is applied to one of the adjacent output terminals of the LSI chip drive circuit 100. In this example, as shown in FIG. It is assumed that the probe 104 is applied to.

  As shown in FIG. 4, first, the tester 101 performs a later-described function test on the drive circuit 100 (S101). If the output signal output from the output terminal of the drive circuit 100 is a specified value as a result of the function test, the function test is passed (YES in S102).

  Next, the tester 101 performs a leak test to be described later on the drive circuit 100 (S103). If the output signal output from the output terminal of the drive circuit 100 is a specified value as a result of the leak test, the leak test is passed (YES in S104). If the leak test is passed in step S104, the target LSI chip drive circuit 100 is determined to be non-defective (S105). On the other hand, if the pass could not be made in step S102 or S104 (S102NO or S104NO), the target LSI chip drive circuit 100 is determined as a defective product (S106).

  In order to shorten the entire test time, an LSI chip that is determined to be defective in one test skips the subsequent test and performs a defect determination S106 to end the test. For this reason, more typical failure mode tests (for example, a single stuck-at fault mode test of the logic part caused by open / short of an element or wiring and a reproducibility test of the analog part) are performed first, and it takes more test time. A rigorous test (eg, a leak standard test) is performed later. In the example of FIG. 4, since the function test is performed first, a sample having a leak that does not perform the function is determined to be defective in the determination step S102 without performing the leak test S103. Of course, depending on the circuit of the LSI chip, this order may be reversed as long as the test time reduction condition is satisfied. Further, the entire test may be performed by sequentially repeating a part of the functional test mode and a part of the leak test mode. What is necessary is just to design the test program of the tester 101 so that the test time is the shortest and the pass / fail judgment can be performed accurately and effectively.

  Next, the function test in step S101 in FIG. 4 will be described with reference to FIGS. FIG. 5 shows a flowchart of a function test performed by the tester 101 on the driving circuit 100 of the LSI chip targeted. As shown in FIG. 5, first, the tester 101 performs a mode 1 test (see FIG. 6) described later on the drive circuit 100 (S201). If the output signal output from the output terminal of the drive circuit 100 is a specified value as a result of the mode 1 test, the mode 1 test is passed (YES in S202).

  Next, the tester 101 performs a mode 2 test (see FIG. 7) described later on the drive circuit 100 (S203). If the output signal output from the output terminal of the drive circuit 100 is a specified value as a result of the mode 2 test, the mode 2 test is passed (YES in S204).

  Next, the tester 101 performs a mode 3 test (see FIG. 8) described later on the drive circuit 100 (S205). If the output signal output from the output terminal of the drive circuit 100 is a specified value as a result of the mode 3 test, the mode 3 test is passed (YES in S206).

  Next, the tester 101 performs a mode 4 test (see FIG. 9) described later on the drive circuit 100 (S207). If the output signal output from the output terminal of the drive circuit 100 is a specified value as a result of the mode 4 test, the mode 4 test is passed (YES in S208).

  If the mode 4 test is passed in step S208, it is determined that the target LSI chip drive circuit 100 has passed the functional test in step S101 of FIG. 4 (S209). On the other hand, if the pass cannot be made in any of steps S202, S204, S206, and S208 (S202NO, S204NO, S206NO, and S208NO), the target LSI chip drive circuit 100 performs the function test in step S101 of FIG. It is determined that a failure has occurred (S210).

  FIG. 6 shows the operating state of each component circuit of the drive circuit 100 during the mode 1 test. Circuits indicated by hatching in FIG. 6 are circuit groups to be tested in this mode 1 test. As shown in FIG. 6, in the mode 1 test, in response to a control signal from the control circuit 20, the switch element SW11A of the switch circuit 17 is turned on, SW12A and SW12B are turned off, and the switch element SW21A of the switch circuit 18 is turned on. SW22A and SW22B are turned off, and switch elements SW30 and SW32A of switch circuit 19 are turned off. Further, the output amplifier 15A is enabled in response to the enable signal EN from the control circuit 20.

  For this reason, the data line drive signal is output from the output terminal 16A via the data register 11A, the switch element SW11A, the data latch 12A, the level shift circuit 13A, the DAC 14A, the switch element SW21A, and the output amplifier 15A. The probe 104 detects the voltage of the data line drive signal output to the output terminal 16A, and the tester 101 determines whether or not the voltage value detected by the probe 104 is a specified value.

  In this determination, whether each component of the data register 11A, the switch element SW11A (ON), the data latch 12A, the level shift circuit 13A, the DAC 14A, the switch element SW21A (ON), the output amplifier 15A is operating correctly, and It can be determined that the wiring between the components is not broken or short-circuited. Along with this, an odd-stage shift register and a clock supply path (not shown) for supplying a clock to the shift register, an image data supply path (not shown) to the data register 11A, and the negative side to the DAC 14A It can also be determined whether or not there is a defect in the voltage range supply path (not shown) and the enable signal EN supply path to the output amplifier 15A.

  As is well known, whether or not a switch element is good is determined by transmitting a signal when the switch element is in an on state (the on-resistance of the switch element is sufficiently small) and not transmitting a signal when the switch element is in an off state (one of the switch elements). The switch element has a sufficiently high off-resistance when both the first terminal is at the high level and the other terminal is at the low level and one of the switch elements is at the low level and the other terminal is at the high level. Determined.

  Therefore, at the same time, the switch element SW11B of the switch circuit 17 is turned on, the switch element SW21B of the switch circuit 18 is turned on, the switch element SW32B of the switch circuit 19 is turned off, and the output amplifier 15B is turned on according to the enable signal EN from the control circuit 20 By enabling and setting some appropriate data (different from the data register 11A) in the data register 11B, the switch elements SW12A, SW12B, SW22A, SW22B, SW30, and SW32A to be turned off are correctly turned off. It can be estimated that the circuit is not short-circuited, and that the odd-numbered circuit and the even-numbered circuit are correctly separated in signal (no parasitic signal link). The reason why this is estimated rather than judgment is that the operation of the even-numbered stage circuit next to the circuit currently being tested is not inspected. When the odd-numbered and even-numbered inputs are short-circuited from the beginning, it can be determined that the odd-numbered circuit and the even-numbered circuit are correctly signal-separated (no parasitic signal link). This is not always the case. As will be described later, this estimation can be determined from the estimation by passing the mode 2 test (confirming the normal operation of the even-numbered stage circuit).

  In addition, as described above, in order to determine a defect at an early stage of a test program, it is preferable to perform all tests in a typical failure mode here.

  As a result of the determination, if the mode 1 test is passed, the process proceeds to the mode 2 test as described in FIG.

  It should be noted that in the mode 1 test, the control circuit 20 controls the switch circuit exactly the same as in normal operation. The display data in the data register 11A is latched in the data latch 12A, DA-converted by the DAC 14A having a negative polarity range, and output to the output terminal 16A through the output amplifier 15A. The display data in the data register 11B is latched in the data latch 12B and positive. It is the operation of the drive circuit of the normal display device that performs DA conversion with the DAC 14B in the sex range and outputs it to the output terminal 16B through the output amplifier 15B.

  Next, FIG. 7 shows an operation state of each component circuit of the drive circuit 100 in the mode 2 test. Circuits shown by hatching in FIG. 7 are circuit groups to be tested in this mode 2 test. As shown in FIG. 7, in the mode 2 test, in response to a control signal from the control circuit 20, the switch element SW11B of the switch circuit 17 is turned on, SW12A and SW12B are turned off, the switch element SW21B of the switch circuit 18 is turned on, and SW22A SW22B is turned off, switch element SW30 of switch circuit 19 is turned on, and SW32A and SW32B are turned off. Further, the output amplifier 15B is enabled in response to the enable signal EN from the control circuit 20. At the same time, the output amplifier 15A is disabled (inactivated, high impedance output) according to the enable signal EN from the control circuit 20. As a result, the signal passing through the switch element SW30 from the output amplifier 15B can be output from the output terminal 16A to the probe 104 without interfering with the output value of the output amplifier 15A.

  For this reason, the data line drive signal is output from the output terminal 16A via the data register 11B, the switch element SW11B, the data latch 12B, the level shift circuit 13B, the DAC 14B, the switch element SW21B, the output amplifier 15B, and the switch element SW30. Is done. The probe 104 detects the voltage of the data line drive signal output to the output terminal 16A, and the tester 101 determines whether or not the voltage value detected by the probe 104 is a specified value.

  With this determination, each component of the data register 11B, the switch element SW11B (ON), the data latch 12B, the level shift circuit 13B, the DAC 14B, the switch element SW21B (ON), the output amplifier 15B, and the switch element SW30 (ON) operates correctly. It can be determined whether or not the wiring between the components is disconnected or short-circuited. Along with this, an even number of shift registers, a clock supply path (not shown) for supplying clocks to the shift register, an image data supply path (not shown) to the data register 11B, and a positive side to the DAC 14B It can also be determined whether or not there is a defect in the voltage range supply path (not shown) and the enable signal EN supply path to the output amplifier 15B.

  At the same time, the switch element SW11A of the switch circuit 17 is turned on, the switch element SW21A of the switch circuit 18 is turned on, and data of an appropriate value (a value different from the data register 11B) is set in the data register 11A. The switch elements SW12A, SW12B, SW22A, and SW22B to be turned off are correctly turned off, the output amplifier 15A is correctly deactivated, and the even-numbered and odd-numbered circuits are correctly separated in terms of signal. It can be determined that there is no parasitic signal link. This is because it has been confirmed that the odd-numbered stage circuit operates correctly in the mode 1 test, so that the even-numbered stage circuit can operate normally in the mode 2 regardless of the value of the odd-numbered stage circuit. The switch elements SW12A, SW12B, SW22A, SW22B, SW30, and SW32A to be turned off estimated in the mode 1 test are correctly turned off, and the odd-numbered circuit and the even-numbered circuit are signally correct. This is because it can be determined that they are separated (there is no parasitic signal link).

  In addition, as described above, in order to determine a defect at an early stage of a test program, it is preferable to perform all tests in a typical failure mode here. As a result of the determination, if the mode 2 test is passed, the process proceeds to the mode 3 test as described with reference to FIG.

  It should be noted here that in the mode 2 test, the control circuit 20 controls the switch circuit different from that in the normal operation. The display data of the data register 11A is latched in the data latch 12A, DA-converted by the negative polarity DAC 14A and inputted to the output amplifier 15A, but the output amplifier 15A is set to high impedance so as not to be outputted to the output terminal 16A. This is the first difference. The display data of the data register 11B is latched in the data latch 12B, DA-converted by the DAC 14B having the positive polarity range, and output to the output terminal 16B through the output amplifier 15B. At the same time, the output terminal is always turned off when the output terminal is driven. The second difference is that the switch element SW30 is turned on. These two points are different from the operation of the control circuit of the drive circuit of a normal display device. Further, it should be noted here that in this mode 2 test, the test method is different from that during normal operation. In general, the feature of the first embodiment is that an expected output value to be compared at the output terminal 16B is compared with a test output value at the output terminal 16A.

  Next, FIG. 8 shows an operation state of each component circuit of the drive circuit 100 during the mode 3 test. Circuits shown by hatching in FIG. 8 are circuit groups to be tested in this mode 3 test. As shown in FIG. 8, in the mode 3 test, the switch element SW12A of the switch circuit 17 is turned on, SW11A and SW11B are turned off, and the switch element SW22B of the switch circuit 18 is turned on in response to a control signal from the control circuit 20. The switch elements SW30 and SW32A of the switch circuit 19 are turned off. Further, the output amplifier 15A is enabled in response to the enable signal EN from the control circuit 20.

  For this reason, the data line drive signal is output from the output terminal 16A through the data register 11A, the switch element SW12A, the data latch 12B, the level shift circuit 13B, the DAC 14B, the switch element SW22B, and the output amplifier 15A. The probe 104 detects the voltage of the data line drive signal output to the output terminal 16A, and the tester 101 determines whether or not the voltage value detected by the probe 104 is a specified value.

  In this determination, whether each component of the data register 11A, the switch element SW12A (ON), the data latch 12B, the level shift circuit 13B, the DAC 14B, the switch element SW22B (ON), and the output amplifier 15A is operating correctly, and It can be determined that the wiring between the components is not broken or short-circuited. That is, it is possible to perform a function test of the ON state of the switch elements SW12A and SW22B that could not be tested by the above-described mode 1 test and mode 2 test.

  At the same time, it can be determined that the switch elements SW11B, SW21A, SW21B, and SW30 to be turned off are correctly turned off (not short-circuited).

  Here, for the purpose of confirming that SW12A of switch circuit 17 is turned on, SW11B is turned off, switch element SW22B of switch circuit 18 is turned on, and SW21A is turned off, only the minimum necessary test pattern for confirming it is passed. It is preferable to reduce the test time.

  If the mode 3 test is passed as a result of this determination, the process proceeds to the mode 4 test as described with reference to FIG.

  It should be noted here that in this mode 3 test, the control circuit controls the same switching circuit as in normal operation. The display data in the data register 11A is latched in the data latch 12B, DA-converted by the DAC 14B in the positive polarity range, and output to the output terminal 16A through the output amplifier 15A. The display data in the data register 11B is latched in the data latch 12A and positive. It is the operation of the drive circuit of a normal display device that performs DA conversion with the DAC 14A in the sex range and outputs it to the output terminal 16B through the output amplifier 15B.

  Next, FIG. 9 shows an operation state of each component circuit of the drive circuit 100 in the mode 4 test. Circuits indicated by hatching in FIG. 9 are circuit groups to be tested in the mode 4 test. As shown in FIG. 9, in the mode 4 test, the switch element SW12B of the switch circuit 17, the switch element SW22A of the switch circuit 18, and the switch element SW30 of the switch circuit 19 are turned on in accordance with the control signal from the control circuit 20. Become. Further, the output amplifier 15B is enabled in response to the enable signal EN from the control circuit 20. At the same time, the output amplifier 15A is disabled (deactivated, output high impedance) according to the enable signal EN from the control circuit 20. As a result, the signal passing through the switch element SW30 from the output amplifier 15B can be output from the output terminal 16A to the probe 104 without interfering with the output value of the output amplifier 15A.

  For this reason, the data line drive signal is output from the output terminal 16A via the data register 11B, the switch element SW12B, the data latch 12A, the level shift circuit 13A, the DAC 14A, the switch element SW22A, the output amplifier 15B, and the switch element SW30. Is done. The probe 104 detects the voltage of the data line drive signal output to the output terminal 16A, and the tester 101 determines whether or not the voltage value detected by the probe 104 is a specified value.

  With this determination, each component of the data register 11B, the switch element SW12B (ON), the data latch 12A, the level shift circuit 13A, the DAC 14A, the switch element SW22A (ON), the output amplifier 15B, and the switch element SW30 (ON) operates correctly. It can be determined whether or not the wiring between the components is disconnected or short-circuited. That is, it is possible to perform a function test in the ON state of the switch elements SW12B and SW22A that could not be tested in the above-described mode 1 test to mode 3 test.

  Here, for the purpose of confirming that the switch element SW12B of the switch circuit 17 is turned on and the switch element SW22A of the switch circuit 18 is turned on, the test time is shortened by passing only the minimum necessary test pattern for confirming that. It is preferable.

  As a result of the determination, if the mode 4 test is passed, it is determined that the function test is passed as described with reference to FIG.

  It should be noted here that in the mode 4 test, the control circuit controls the switch circuit different from that in the normal operation. The display data of the data register 11A is latched in the data latch 12B, DA-converted by the DAC 14B having the negative polarity range, and input to the output amplifier 15A, but the output amplifier 15A is set to high impedance so as not to be output to the output terminal 16A. This is the first difference. Further, the display data of the data register 11B is latched in the data latch 12A, DA-converted by the DAC 14A of the negative polarity range, and output to the output terminal 16B through the output amplifier 15B. At the same time, it is always turned off when the output terminal is driven by the output amplifier. The second difference is that the switch element SW30 is turned on. These two points are different from the operation of the control circuit of the drive circuit of a normal display device. Further, it should be noted here that the test method is different from that in the normal operation in the mode 4 test. The feature of the first embodiment is that the expected output value to be compared at the normal output terminal 16B is compared with the test output value at the output terminal 16A.

  Next, the leak test in step S103 in FIG. 4 will be described with reference to FIGS. FIG. 10 shows a flowchart of a leak test performed by the tester 101 on the driving circuit 100 of the LSI chip targeted. As shown in FIG. 10, first, the tester 101 performs a mode 5 test (see FIG. 11) described later on the drive circuit 100 (S301). If the output signal (current value) output from the output terminal of the drive circuit 100 is a specified value as a result of the mode 5 test, the mode 5 test is passed (YES in S302).

  Next, the tester 101 performs a mode 6 test (see FIG. 12) described later on the drive circuit 100 (S303). If the output signal (current value) output from the output terminal of the drive circuit 100 is a specified value as a result of the mode 6 test, the mode 6 test is passed (YES in S304).

  Next, the tester 101 performs a mode 7 test (see FIG. 13) described later on the drive circuit 100 (S305). If the output signal (current value) output from the output terminal of the drive circuit 100 is a specified value as a result of the mode 7 test, the mode 7 test is passed (YES in S306).

  Next, the tester 101 performs a mode 8 test (see FIG. 14) described later on the driving circuit 100 (S307). If the output signal (current value) output from the output terminal of the drive circuit 100 is a specified value as a result of the mode 8 test, the mode 8 test is passed (YES in S308).

  If the mode 8 test is passed in step S308, the target LSI chip drive circuit 100 is determined to have passed the leak test in step S103 of FIG. 4 (S309). On the other hand, if the pass cannot be made in any of steps S302, S304, S306, and S308 (S302NO, S304NO, S306NO, and S308NO), the target LSI chip drive circuit 100 performs the leak test in step S103 of FIG. It is determined that a failure has occurred (S310).

  11 and 12 show the operation states of the output amplifiers 15A and 15B, the output terminals 16A and 16B, and the switch circuit 19 of the drive circuit 100 during the mode 5 test and the mode 6 test. 11 and 12 is a circuit group that is a current leak test target in this mode 5 test. 11 to 14 show the ESD protection elements ESD1 and ESD2 which are omitted in FIG.

  The diode D1A of the ESD protection element ESD1 has a cathode connected to the power supply terminal VDD and an anode connected to the output terminal 16A. The diode D2A has a cathode connected to the output terminal 16A and an anode connected to the ground terminal VSS. The diode D1B of the ESD protection element ESD2 has a cathode connected to the power supply terminal VDD and an anode connected to the output terminal 16B. The diode D2B has a cathode connected to the output terminal 16B and an anode connected to the ground terminal VSS.

  In the mode 5 test and the mode 6 test, as shown in FIGS. 11 and 12, the output amplifiers 15A and 15B are deactivated (high impedance output) in accordance with the enable control signal and the control signal from the control circuit 20, The switch elements SW32A and SW32B of the switch circuit 19 are turned off, and the SW30 is turned on. In this state, a mode 5 test (FIG. 11) and a mode 6 test (FIG. 12) are performed. As a result, current leakage to the switch elements SW32A and SW32B indicated by hatching in FIGS. 11 and 12, the reverse breakdown voltage leakage of the protection diodes D2A, D2B, D1A, and D1B, and the leakage at the time of high impedance of the output amplifiers 15A and 15B The total value of the current is measured.

  First, in the mode 5 test of FIG. 11, a predetermined voltage, for example, 20 V, which is the same as the power supply voltage VDD, is applied to the output terminal 16A via the probe 104 by the tester 101. Further, the control circuit 20 applies a predetermined voltage, for example, 0 V, which is the same as the ground voltage VSS, to the common line K. Furthermore, the output amplifiers 15A and 15B enter a high impedance state (Hi-Z) in response to the enable signal EN from the control circuit 20. At this time, the value of the display data in the data registers 11A and 11B is set to the maximum amplitude (LSB (Least Significant Bit) for the normally white panel, MSB (Most Significant Bit) for the normally black panel). Thus, VSS (0V) is output from the negative DAC 14A, and VDD (20V) is output from the positive DAC 14B. Then, the switch elements SW22B and SW21B of the switch circuit 18 are turned off and the switch elements SW21A and SW22A are turned on by the control signal of the control circuit 20. Thereby, 0V can be set to both inputs of the output amplifiers 15A and 15B. Then, in response to the enable signal EN from the control circuit 20, the output amplifiers 15A and 15B are deactivated and the output is output as a high impedance (Hi-Z) in a 0V output ready state. The Hi-Z output in the 0V output ready state is that the normal output amplifier 15 is largely composed of an input stage and an output stage, but the output stage outputs Hi-Z while the input stage outputs 0V. State. At this time, if the circuit that controls the output amplifier 15 to the output Hi-Z is faulty, the output of the output amplifier may not be fully Hi-Z, and a leak fault may occur with VSS. One purpose of this test is to detect this fault.

  In this mode 5 test, as described above, since the voltage of the output terminal 16A is 20V, the voltage of the common line K is 0V, and the output amplifiers 15A and 15B are in the high impedance state, the switch elements SW32A and SW32B, the protection diode D2A, When current leakage is present on any of the VSS sides of the high impedance outputs of D2B and the output amplifiers 15A and 15B, current flows from the output terminal 16A toward the common line K or VSS. That is, since a current flows from the probe 104 to the output terminal 16A, the tester 101 measures this current value as an output signal and compares it with a reference value. The reference value at this time is set to, for example, twice the leak standard value when the output terminal is in the high impedance state. If the measured current value is larger than the reference value, the failure is determined and the test is terminated.

  Note that the current leakage on the VSS side of the high-impedance outputs of the output amplifiers 15A and 15B is caused by a MOS transistor (usually an NMOS transistor) connected between the output node inside the output amplifiers 15A and 15B and the ground terminal VSS. Current leakage is assumed.

  If the tester 101 determines that the mode 5 test is passed as a result of the measurement, the process proceeds to the mode 6 test as described with reference to FIG.

  Next, in the mode 6 test of FIG. 12, a predetermined voltage, for example, 0 V which is the same as the ground voltage VSS is applied to the output terminal 16A via the probe 104 by the tester 101. Further, the control circuit 20 applies a predetermined voltage, for example, 20 V, which is the same as the power supply voltage VDD, to the common line K. Furthermore, the output amplifiers 15A and 15B enter a high impedance state (Hi-Z) in response to the enable signal EN from the control circuit 20. At this time, the value of the display data in the data registers 11A and 11B is set to the maximum amplitude (LSB for the normally white panel, MSB for the normally black panel), and VSS (0V) from the negative DAC 14A. ) And VDD (20 V) is output from the positive DAC 14B. Then, the switch elements SW22B and SW21B of the switch circuit 18 are turned on and the switch elements SW21A and SW22A are turned off by the control signal of the control circuit 20. Thereby, 20V can be set to the inputs of both the output amplifiers 15A and 15B. Then, in response to the enable signal EN from the control circuit 20, the output amplifiers 15A and 15B are deactivated, and the output outputs a high impedance (Hi-Z) in a 20V output ready state. The Hi-Z output in the 20V output ready state is that the normal output amplifier 15 is largely composed of an input stage and an output stage, but the output stage outputs Hi-Z while the input stage outputs 20V. State. At this time, if the circuit that controls the output amplifier 15 to the output Hi-Z is faulty, the output of the output amplifier may not be fully Hi-Z, and a leak fault may occur between VDD. One purpose of this test is to detect this fault.

  In this mode 6 test, as described above, since the voltage of the output terminal 16A is 0V, the voltage of the common line K is 20V, and the output amplifiers 15A and 15B are in the high impedance state, the switch elements SW32A and SW32B, the protection diode D1A, When a current leak exists on either the VDD side of the high impedance outputs of D1B and the output amplifiers 15A and 15B, a current flows from the common line K or VDD toward the output terminal 16A. That is, since a current flows from the output terminal 16A to the probe 104, the tester 101 measures this current value as an output signal and compares it with a reference value. The reference value at this time is set to, for example, twice the leak standard value when the output terminal is in the high impedance state. If the measured current value is larger than the reference value, the failure is determined and the test is terminated.

  The current leakage on the VDD side of the high impedance outputs of the output amplifiers 15A and 15B is caused by the MOS transistor (usually a PMOS transistor) connected between the output node inside the output amplifiers 15A and 15B and the power supply terminal VDD. Current leakage is assumed.

  If the tester 101 determines that the mode 6 test is passed as a result of the measurement, the process proceeds to the mode 7 test as described with reference to FIG.

  Next, in the mode 7 test and the mode 8 test, as shown in FIGS. 13 and 14, the output amplifier 15A is deactivated (high impedance) in accordance with the enable control signal and the control signal from the control circuit 20, and the switch circuit The 19 switch elements SW30, SW32A, and SW32B are turned off. In this state, a mode 7 test (FIG. 13) and a mode 8 test (FIG. 14) are performed. Thereby, the current leakage with respect to the ESD protection element ESD1 and the switch elements SW30 and SW32A indicated by hatching in FIGS. 13 and 14 is measured.

  First, in the mode 7 test of FIG. 13, a predetermined voltage, for example, 20 V, which is the same as the power supply voltage VDD, is applied to the output terminal 16A via the probe 104 by the tester 101. Further, the control circuit 20 applies a predetermined voltage, for example, 0 V, which is the same as the ground voltage VSS, to the common line K. Furthermore, the value of the display data in the data registers 11A and 11B is set to the maximum amplitude (LSB for the normally white panel, MSB for the normally black panel), and VSS (0V) from the negative DAC 14A. And VDD (20 V) is output from the positive-side DAC 14B. Then, the switch elements SW22B and SW21B of the switch circuit 18 are turned off and the switch elements SW21A and SW22A are turned on by the control signal of the control circuit 20. Thereby, 0V can be set to both inputs of the output amplifiers 15A and 15B. Then, in response to the enable signal EN from the control circuit 20, the output amplifier 15A is deactivated, the output is a high impedance (Hi-Z) in a 0V output preparation state, and the output amplifier 15B is activated to output 0V.

  In this mode 7 test, as described above, the voltage of the output terminal 16A is 20V, the voltage of the common line K is 0V, and 0V is output from the output amplifier 15B. Therefore, if there is a current leak on the VSS side of the high impedance output of the diode D2A of the ESD protection element ESD1, the switch elements SW30 and SW32A, and the output amplifier 15A, the common line K or the ground terminal VSS Current flows toward That is, since a current flows from the probe 104 to the output terminal 16A, the tester 101 measures this current value as an output signal and compares it with a reference value. The reference value at this time is set to, for example, one time the leak standard value when the output terminal is in a high impedance state. If the measured current value is larger than the reference value, the failure is determined and the test is terminated.

  If the tester 101 determines that the mode 7 test is passed as a result of the measurement, the process proceeds to the mode 8 test as described with reference to FIG.

  Next, in the mode 8 test of FIG. 14, a predetermined voltage, for example, 0 V, which is the same as the ground voltage VSS, is applied to the output terminal 16 </ b> A via the probe 104 by the tester 101. Further, the control circuit 20 applies a predetermined voltage, for example, 0 V, which is the same as the ground voltage VSS, to the common line K. Further, as in the mode 7 test, VSS (0 V) is output from the negative DAC 14A, and VDD (20 V) is output from the positive DAC 14B. Then, the switch elements SW21A and SW22A of the switch circuit 18 are turned off and the switch elements SW22B and SW21B are turned on by the control signal of the control circuit 20. Thereby, 20V can be set to the inputs of both the output amplifiers 15A and 15B. Then, in response to the enable signal EN from the control circuit 20, the output amplifier 15A is deactivated, the output is a high impedance (Hi-Z) in a 20V output ready state, and the output amplifier 15B is activated to output 20V. Note that the reason why the output amplifier 15A can output 0V to 20V is because the above-mentioned full amplifier is used (this also applies to the output amplifier 15B).

  In the mode 8 test, as described above, the voltage of the output terminal 16A is 0V, the common line K is 20V, and the output amplifier 15B outputs 20V. Therefore, if there is a current leak on the VDD side of the high impedance output of the diode D1A of the ESD protection element ESD1, the switch elements SW30 and SW32A, and the output amplifier 15A, the output terminal 16A from the common line K or the power supply terminal VDD. Current flows toward That is, since a current flows into the probe 104 from the output terminal 16A, the tester 101 measures this current value as an output signal and compares it with the reference value. The reference value at this time is set to, for example, one time the leak standard value when the output terminal is in a high impedance state. If the measured current value is larger than the reference value, the failure is determined and the test is terminated.

  When the tester 101 determines that the mode 8 test is passed as a result of the measurement, it is determined that the leak test is passed as described with reference to FIG.

  As described above, the drive circuit 100 of the display device according to the first embodiment performs all of the output terminals (960 in this example) on the LSI chip by performing the above-described function test and leak test in the wafer test. The probe 104 does not need to be applied to the drive circuit 100, and the probe 104 may be applied to only one of the adjacent output terminals of the drive circuit 100 (for example, the odd-numbered output terminal 16A).

  For this reason, in the first embodiment, 960 probes are not required for one LSI chip while maintaining the same test quality as in the prior art, and only 480 probes, which is half that number, are used. That's it. For this reason, it is not necessary to prepare an expensive tester having a large number of probes, and an increase in the inspection cost can be suppressed. For this reason, it is possible to reduce the number of probes necessary for testing the display device driving circuit, whether it is mounted on a semiconductor wafer or mounted on a tape carrier package.

  Here, for example, when the configuration of the drive circuit 100 as in the first embodiment is not provided, for example, when there are 960 output terminals in an LSI chip, the number of probes is 960 for that one LSI chip. Need. For this reason, when the number of probes 104 included in the probe card 102 is 1536, only one LSI chip can perform a wafer test at a time. For this reason, there is a problem that the period for performing the wafer test on all LSI chips on the wafer becomes long and the inspection cost increases.

  However, in the first embodiment, when the number of probes 104 included in the probe card 102 is 1536, the wafer test can be performed on up to three LSI chips at a time. This is because the number of output probes required for inspection per LSI chip is 480. Even if there are 30 input terminals, the total number of probes required for three LSI chips is 1530. This is because it is sufficient. Therefore, the total number of probes required for the three LSI chips can be suppressed to the number of probes (1536) included in the probe card 102 or less. Therefore, the number of LSI chips that can be inspected at a time can be increased by a factor of three compared to the case described above, and the period for performing all wafer tests on LSI chips on a wafer can be reduced to one third by simple calculation. Thus, the inspection cost can be reduced.

  Further, for example, when the configuration of the drive circuit 100 as in the first embodiment is not provided, the probe 104 must be applied to all output terminals of the LSI chip with a narrow pitch as shown in FIG. Don't be. In this case, the interval L1 between the adjacent probes 104 becomes narrow, and the possibility of contact during inspection increases. Naturally, when the probe 104 comes into contact, an accurate wafer test cannot be performed, and the deterioration of the inspection quality becomes a problem.

  However, in the first embodiment, as shown in FIG. 16, the distance L2 between adjacent probes 104 is L2 that is double that of the example of FIG. For this reason, possibility that probes will contact at the time of inspection can be reduced. Further, even when the output terminal interval is further narrowed from now on, the interval margin is increased, so that it is possible to cope with the narrow pitch.

  Embodiment 2 of the Invention

  Hereinafter, a specific second embodiment to which the present invention is applied will be described in detail with reference to the drawings. In the second embodiment, the present invention is also applied to a driving circuit for a display device and an inspection method for an LSI chip on which the driving circuit is mounted. The second embodiment is different from the first embodiment in the configuration of the drive circuit of the display device mounted on the LSI chip to be inspected. Therefore, the test system is the same as that shown in FIG. 1, and a description thereof is omitted here.

  FIG. 17 shows the configuration of the drive circuit 200 of the display device according to the second exemplary embodiment.

  As shown in FIG. 17, the drive circuit 200 includes a pair of data registers 11A and 11B, a pair of data latches 12A and 12B, a pair of level shift circuits 13A and 13B, a pair of DACs 14A and 14B, and a pair of outputs. Amplifiers 25A and 25B, a pair of output terminals 16A and 16B, switch circuits 17 and 21, a control circuit 20, and a common line K are provided.

  In addition, the structure which attached | subjected the code | symbol same as FIG. 3 among the code | symbols shown in FIG. 17 has shown the same or similar structure as FIG. For this reason, in this Embodiment 2, a different part from Embodiment 1 is demonstrated, and description of the same part is abbreviate | omitted.

  The switch circuit 21 includes switch elements SW30, SW31A, SW31B, SW32A, SW32B, SW41A, and SW41B.

  Switch element SW30 is connected between output terminals 16A and 16B. The switch element SW31A is connected between the output amplifier 25A and the output terminal 16A. The switch element SW31B is connected between the output amplifier 25B and the output terminal 16B. The switch element SW32A is connected between the output terminal 16A and the common line K. The switch element SW32B is connected between the output terminal 16B and the common line K.

  The switch element SW41A is connected between the output amplifier 25A and the output terminal 16B. The switch element SW41B is connected between the output amplifier 25B and the output terminal 16A.

  The switch elements SW31A and SW31B, the switch elements SW32A and SW32B, and the switch elements SW41A and SW41B may be simultaneously controlled to be turned on or off in accordance with a control signal from the control circuit 20. Alternatively, the switch elements SW31A, SW31B, SW32A, SW32B, SW41A, and SW41B may be individually controlled to be turned on or off in accordance with a control signal from the control circuit 20.

  In response to the enable signal EN from the control circuit 20, the output amplifiers 25A and 25B amplify the output gradation image data of the corresponding DACs 14A and 14B, respectively, and output them to the next stage. Unlike the first embodiment, the output amplifiers 25A and 25B are the half amplifiers described above, and the output amplifier 25A that receives the output of the DAC 14A that outputs the negative voltage range outputs the positive voltage range and the DAC 14B that outputs the positive voltage range. The output amplifier 25B that receives the output of the signal amplifies only the negative voltage range and one of the voltage ranges. As a result, the maximum withstand voltage of the output amplifier 25 can be reduced to half of the voltage VDD, so that the size of the transistor to be used on the chip layout can be reduced and the cost of the chip can be reduced.

  Similarly to the first embodiment, the output amplifiers 25A and 25B are activated and deactivated separately according to the enable signal EN from the control circuit 20, respectively. When amplified and output and deactivated, the output is in a high impedance state.

  In the display operation in which the drive circuit 200 drives the data lines of the liquid crystal display device, when the switch elements SW11A and SW11B of the switch circuit 17 are on and the switch elements SW12A and SW12B are off, the switch circuit 21 The switch elements SW31A and SW31B are turned on, and the switch elements SW41A and SW41B are turned off. Thereby, the output terminal 16A outputs a negative polarity, and the output terminal 16B outputs a positive polarity. Conversely, when the switch elements SW11A and SW11B of the switch circuit 17 are off and the switch elements SW12A and SW12B are on, the switch elements SW31A and SW31B of the switch circuit 21 are interlocked and the switch elements SW41A and SW41B are on. Become. As a result, contrary to the previous case, the output terminal 16A outputs positive polarity and the output terminal 16B outputs negative polarity. This makes it possible to invert the polarity of the pixels of the liquid crystal display device.

  The control circuit 20 controls, for example, on / off control of the switch element groups included in each of the switch circuits 17 and 21 and enable of the output amplifiers 25A and 25B according to a test signal from the tester 101 outside the LSI chip. . Further, it has a function of applying a predetermined voltage (for example, power supply voltage VDD) to the common line K. For example, the conduction of a switch between the power supply terminal VDD and the common line K is controlled.

  Next, a quality determination test for the drive circuit 200 will be described. The flowchart of the pass / fail judgment test and the flowchart of the function test performed on the driving circuit 200 of the LSI chip targeted by the tester 101 are the same as those in FIGS. In the second embodiment, a probe is applied to one of the adjacent output terminals of the LSI chip drive circuit 200. In this example, the probe 104 is applied to the output terminal 16A as shown in FIG. It is assumed that

  FIG. 18 shows the operating state of each component circuit of the drive circuit 200 during the mode 1 test. Circuits indicated by hatching in FIG. 18 are a circuit group to be tested in this mode 1 test. As shown in FIG. 18, in the mode 1 test, the switch element SW11A of the switch circuit 17 and the switch element SW31A of the switch circuit 21 are turned on in response to the control signal from the control circuit 20. Further, the output amplifier 25A is enabled in response to the enable signal EN from the control circuit 20.

  For this reason, the data line drive signal is output from the output terminal 16A via the data register 11A, the switch element SW11A, the data latch 12A, the level shift circuit 13A, the DAC 14A, the output amplifier 25A, and the switch element SW31A. The probe 104 detects the voltage of the data line drive signal output to the output terminal 16A, and the tester 101 determines whether or not the voltage value detected by the probe 104 is a specified value.

  In this determination, whether each component of the data register 11A, the switch element SW11A (ON), the data latch 12A, the level shift circuit 13A, the DAC 14A, the output amplifier 25A, and the switch element SW31A (ON) is operating correctly and It can be determined that the wiring between the components is not broken or short-circuited. Along with this, an odd-stage shift register and a clock supply path (not shown) for supplying a clock to the shift register, an image data supply path (not shown) to the data register 11A, and the negative side to the DAC 14A It can also be determined whether or not there is a defect in the voltage range supply path (not shown) and the enable signal EN supply path to the output amplifier 25A. Similarly to the first embodiment, the switch elements SW12A, SW12B, SW41A, SW41B, SW30, and SW32A that are to be turned off are correctly turned off (short-circuited) by setting the data register 11B differently from the data register 11A. It can be estimated that the odd-numbered stage circuit and the even-numbered stage circuit are correctly signal-separated (there is no parasitic signal link).

  As a result of the determination, if the mode 1 test is passed, the process proceeds to the mode 2 test as described in FIG. It should be noted here that, as in the first embodiment, in this mode 1 test, the control circuit 20 controls the same switching circuit as in the normal display operation.

  Next, FIG. 19 shows an operation state of each component circuit of the drive circuit 200 in the mode 2 test. A circuit shown by hatching in FIG. 19 is a circuit group to be tested in this mode 2 test. As shown in FIG. 19, in the mode 2 test, the switch element SW11B of the switch circuit 17 and the switch elements SW31B and SW30 of the switch circuit 21 are turned on in response to the control signal from the control circuit 20. Further, the output amplifier 25B is enabled in response to the enable signal EN from the control circuit 20. At the same time, the output amplifier 25A is disabled (inactivated, output high impedance) according to the enable signal EN from the control circuit 20. As a result, the signal that has passed through the switch element SW30 from the output amplifier 25B can be output from the output terminal 16A to the probe 104 without interference with the output value of the output amplifier 25A.

  For this reason, the data line drive signal is output from the output terminal 16A through the data register 11B, the switch element SW11B, the data latch 12B, the level shift circuit 13B, the DAC 14B, the output amplifier 25B, the switch elements SW31B and SW30. . The probe 104 detects the voltage of the data line drive signal output to the output terminal 16A, and the tester 101 determines whether or not the voltage value detected by the probe 104 is a specified value.

  With this determination, each component of the data register 11B, the switch element SW11B (ON), the data latch 12B, the level shift circuit 13B, the DAC 14B, the output amplifier 25B, the switch element SW31B (ON), and the SW30 (ON) operates correctly. It can be determined whether or not the wiring between the components is disconnected or short-circuited. Along with this, an even number of shift registers, a clock supply path (not shown) for supplying clocks to the shift register, an image data supply path (not shown) to the data register 11B, and a positive side to the DAC 14B It can also be determined whether or not there is a defect in the voltage range supply path (not shown) and the enable signal EN supply path to the output amplifier 25B.

  Similarly to the first embodiment, the switch elements SW12A, SW12B, SW41A, and SW41B to be turned off are correctly turned off by setting several data of appropriate values (different values from the data register 11B) in the data register 11A. It can be determined that the output amplifier 25A is correctly inactive, and that the even-numbered and odd-numbered circuits are correctly separated (no parasitic signal link). As a result of the determination, if the mode 2 test is passed, the process proceeds to the mode 3 test as described with reference to FIG.

  It should be noted here that, as in the first embodiment, in the mode 2 test, the control circuit 20 controls the switch circuit different from that in the normal display operation. The first difference is that the output amplifier 25A is set to high impedance so as not to be output to the output terminal 16A. The display data of the data register 11B is latched in the data latch 12B, DA-converted by the positive polarity range DAC 14B and output to the output terminal 16B through the output amplifier 25B. At the same time, the output terminal is always turned off when the output terminal is driven. The second difference is that the switch element SW30 is turned on. These two points are different from the operation of the control circuit of the drive circuit of a normal display device. Further, it should be noted here that in this mode 2 test, the test method is different from that during normal operation. In general, the feature of the second embodiment is that an expected output value to be compared at the output terminal 16B is compared with a test output value at the output terminal 16A.

  Next, FIG. 20 shows an operation state of each component circuit of the drive circuit 200 during the mode 3 test. A circuit shown by hatching in FIG. 20 is a circuit group to be tested in this mode 3 test. As shown in FIG. 20, in the mode 3 test, the switch element SW12A of the switch circuit 17 and the switch element SW41B of the switch circuit 21 are turned on in response to a control signal from the control circuit 20. Further, the output amplifier 25B is enabled in response to the enable signal EN from the control circuit 20.

  For this reason, the data line drive signal is output from the output terminal 16A through the constituent elements of the data register 11A, the switch element SW12A, the data latch 12B, the level shift circuit 13B, the DAC 14B, the output amplifier 25B, and the switch element SW41B. The probe 104 detects the voltage of the data line drive signal output to the output terminal 16A, and the tester 101 determines whether or not the voltage value detected by the probe 104 is a specified value.

  In this determination, whether or not each component of the data register 11A, the switch element SW12A (ON), the data latch 12B, the level shift circuit 13B, the DAC 14B, the output amplifier 25B, and the switch element SW41B (ON) is operating correctly and It can be determined that the wiring between the components is not broken or short-circuited. That is, it is possible to perform a function test of the switch elements SW12A and SW41B that are not tested in the mode 1 test and the mode 2 test described above.

  Here, for the purpose of confirming that SW12A of switch circuit 17 is turned on, SW11B is turned off, switch element SW41B of switch circuit 21 is turned on, and SW31A is turned off, only the minimum necessary test pattern for confirming it is passed. It is preferable to reduce the test time. If the mode 3 test is passed as a result of this determination, the process proceeds to the mode 4 test as described with reference to FIG.

  It should be noted here that, as in the first embodiment, in this mode 1 test, the control circuit 20 controls the same switching circuit as in the normal display operation.

  Next, FIG. 21 shows an operation state of each component circuit of the drive circuit 200 in the mode 4 test. Circuits shown by hatching in FIG. 21 are a circuit group to be tested in this mode 4 test. As shown in FIG. 21, in the mode 4 test, the switch element SW12B of the switch circuit 17 and the switch elements SW41B and SW30 of the switch circuit 21 are turned on in response to the control signal from the control circuit 20. Further, the output amplifier 25A is enabled in response to the enable signal EN from the control circuit 20. At the same time, the output amplifier 25B is disabled (inactivated, output high impedance) according to the enable signal EN from the control circuit 20. As a result, the signal passing through the switch element SW41B from the output amplifier 25B can be output to the probe 104 from the output terminal 16A without being interfered with the output value of the output amplifier 25A.

  For this reason, the data line drive signal is output from the output terminal 16A through the data register 11B, the switch element SW12B, the data latch 12A, the level shift circuit 13A, the DAC 14A, the output amplifier 25A, the switch elements SW41A and SW30. . The probe 104 detects the voltage of the data line drive signal output to the output terminal 16A, and the tester 101 determines whether or not the voltage value detected by the probe 104 is a specified value.

  With this determination, each component of the data register 11B, the switch element SW12B (ON), the data latch 12A, the level shift circuit 13A, the DAC 14A, the output amplifier 25A, the switch element SW41A (ON), and the SW30 (ON) operates correctly. It can be determined whether or not the wiring between the components is disconnected or short-circuited. That is, it is possible to perform a function test of the ON state of the switch elements SW12B and SW41A that could not be tested in the above-described mode 1 test to mode 3 test.

  Here, since the purpose is to confirm that the switch 12B of the switch circuit 17 is turned on and the switch element SW41A of the switch circuit 21 is turned on, only the minimum necessary test pattern for confirming this is flowed to shorten the test time. Is preferred.

  As a result of the determination, if the mode 4 test is passed, it is determined that the function test is passed as described with reference to FIG.

  It should be noted that in the mode 4 test, the control circuit 20 controls the switch circuit different from that in the normal display operation. The first difference is that the output amplifier 25B is set to high impedance so as not to be output to the output terminal 16A. Further, the display data of the data register 11B is latched in the data latch 12A, DA-converted by the DAC 14A having the negative polarity range and output to the output terminal 16B through the output amplifier 25A. At the same time, the output terminal is always turned off when the output terminal is driven. The second difference is that the switch element SW30 is turned on. These two points are different from the operation of the control circuit of the drive circuit of a normal display device. Further, it should be noted here that the test method is different from that in the normal operation in the mode 4 test. The feature of the second embodiment is that the expected output value to be compared at the normal output terminal 16B is compared with the test output value at the output terminal 16A.

  Next, the leak test in the second embodiment in step S103 in FIG. 4 will be described with reference to FIGS.

  FIG. 22 shows a flowchart of a leak test performed by the tester 101 on the driving circuit 200 for the LSI chip targeted. As shown in FIG. 22, first, the tester 101 performs a mode 5 test (see FIG. 23) described later on the drive circuit 200 (S501). If the output signal (current value) output from the output terminal of the drive circuit 200 is a specified value as a result of the mode 5 test, the mode 5 test is passed (YES in S502).

  Next, the tester 101 performs a mode 6 test (see FIG. 24) described later on the driving circuit 200 (S503). If the output signal (current value) output from the output terminal of the drive circuit 200 is a specified value as a result of the mode 6 test, the mode 6 test is passed (S504 YES).

  Next, the tester 101 performs a mode 7 test (see FIG. 25) described later on the driving circuit 200 (S505). If the output signal (current value) output from the output terminal of the drive circuit 200 is a specified value as a result of the mode 7 test, the mode 7 test is passed (YES in S506).

  Next, the tester 101 performs a mode 8 test (see FIG. 26) described later on the drive circuit 200 (S506). If the output signal (current value) output from the output terminal of the drive circuit 200 is a specified value as a result of the mode 8 test, the mode 8 test is passed (YES in S508).

  Next, the tester 101 performs a mode 9 test (see FIG. 27) described later on the drive circuit 200 (S509). If the output signal (current value) output from the output terminal of the drive circuit 200 is a specified value as a result of the mode 9 test, the mode 9 test is passed (S510 YES).

  Next, the tester 101 performs a mode 10 test (see FIG. 28) described later on the driving circuit 200 (S511). If the output signal (current value) output from the output terminal of the drive circuit 200 is a specified value as a result of the mode 10 test, the mode 10 test is passed (YES in S512).

  If the mode 10 test is passed in step S512, it is determined that the target LSI chip drive circuit 200 has passed the leak test in step S103 of FIG. 4 (S513). On the other hand, if the pass cannot be made in any of steps S502, S504, S506, S508, S510, and S512 (S502NO, S504NO, S506NO, S508NO, S510NO, and S512NO), the target LSI chip drive circuit 200 is shown in FIG. 4, it is determined that the leak test in step S103 has failed (S514).

  23 to 28 show the ESD protection elements ESD1 and ESD2 that are omitted in FIG. The diode D1A of the ESD protection element ESD1 has a cathode connected to the power supply terminal VDD and an anode connected to the output terminal 16A. The diode D2A has a cathode connected to the output terminal 16A and an anode connected to the ground terminal VSS. The diode D1B of the ESD protection element ESD2 has a cathode connected to the power supply terminal VDD and an anode connected to the output terminal 16B. The diode D2B has a cathode connected to the output terminal 16B and an anode connected to the ground terminal VSS.

  23 and 24 show the operation states of the output amplifiers 25A and 25B, the output terminals 16A and 16B, and the switch circuit 21 of the drive circuit 200 during the mode 5 test and the mode 6 test. 23 and FIG. 24 is a circuit group that is a current leak test target in this mode 5 test and mode 6 test.

  In the mode 5 test and the mode 6 test, as shown in FIGS. 23 and 24, the output amplifiers 25A and 25B are deactivated (high impedance output) in accordance with the enable signal EN and the control signal from the control circuit 20, The switch elements SW41A, SW41B, and SW32B of the switch circuit 21 are turned on, and the switch elements SW31A, SW31B, SW30, and SW32A are turned off. In this state, a mode 5 test (FIG. 23) and a mode 6 test (FIG. 24) are performed. As a result, current leakage to the ESD protection element ESD1 and switching elements SW32A and SW32B indicated by hatching in FIGS. 23 and 24, reverse breakdown voltage leakage of the protection diode D1A or D2A, and leakage current at the time of high impedance of the output amplifier 25B The total value of is measured.

  First, in the mode 5 test of FIG. 23, a predetermined voltage, for example, 20 V, which is the same as the power supply voltage VDD, is applied to the output terminal 16A via the probe 104 by the tester 101. Further, the control circuit 20 applies a predetermined voltage, for example, 0 V, which is the same as the ground voltage VSS, to the common line K. Furthermore, in response to the enable signal EN from the control circuit 20, the output amplifiers 25A and 25B enter a high impedance state (Hi-Z).

  In this mode 5 test, as described above, the voltage of the output terminal 16A is 20V, the voltage of the common line K is 0V, and the output amplifiers 25A and 25B are in the high impedance state. Therefore, if the diode D2A of the ESD protection element ESD1 When there is a current leak on the VSS side of the high impedance output of SW31A, SW31B, SW30, SW32A, or output amplifier 25B, a current flows from the output terminal 16A toward the common line K or the ground terminal VSS. That is, since a current flows from the probe 104 to the output terminal 16A, the tester 101 measures this current value as an output signal and compares it with a reference value. The reference value at this time is set to, for example, twice the leak standard value when the output terminal is in the high impedance state. If the measured current value is larger than the reference value, the failure is determined and the test is terminated. As in the first embodiment, the current leakage on the VSS side of the high impedance outputs of the output amplifiers 25A and 25B is caused by a MOS transistor connected between the output node inside the output amplifiers 25A and 25B and the ground terminal VSS. Current leakage (usually an NMOS transistor) is assumed.

  If the tester 101 determines that the mode 5 test is passed as a result of the measurement, the process proceeds to the mode 6 test as described with reference to FIG.

  Next, in the mode 6 test of FIG. 24, a predetermined voltage, for example, 0 V, which is the same as the ground voltage VSS, is applied to the output terminal 16A via the probe 104 by the tester 101. Further, the control circuit 20 applies a predetermined voltage, for example, 20 V, which is the same as the power supply voltage VDD, to the common line K. Furthermore, in response to the enable signal EN from the control circuit 20, the output amplifiers 25A and 25B enter a high impedance state (Hi-Z).

  In this mode 6 test, since the voltage of the output terminal 16A is 0V, the voltage of the common line K is 20V, and the output amplifiers 25A and 25B are in the high impedance state as described above, the diode D1A of the ESD protection element ESD1 and the switching element When a current leak exists on any of the VDD sides of the high impedance outputs of SW31A, SW31B, SW30, SW32A, and output amplifier 25B, a current flows from the common line K or the power supply terminal VDD toward the output terminal 16A. That is, since a current flows from the output terminal 16A to the probe 104, the tester 101 measures this current value as an output signal and compares it with a reference value. The reference value at this time is set to, for example, twice the leak standard value when the output terminal is in the high impedance state. If the measured current value is larger than the reference value, the failure is determined and the test is terminated. As in the first embodiment, the current leakage on the VDD side of the high-impedance output of the output amplifiers 25A and 25B is caused by a MOS transistor connected between the output node inside the output amplifiers 25A and 25B and the power supply terminal VDD. Current leakage (usually a PMOS transistor) is assumed.

  If the tester 101 determines that the mode 5 test is passed as a result of the measurement, the process proceeds to the mode 7 test as described with reference to FIG.

  Next, in the mode 7 test and the mode 8 test, as shown in FIGS. 25 and 26, the output amplifiers 25A and 25B are deactivated (high impedance output) according to the enable signal EN and the control signal from the control circuit 20. ), The switch elements SW31A, SW31B, and SW32B of the switch circuit 21 are turned on, and the switch elements SW41A, SW41B, SW32A, and SW30 are turned off. In this state, a mode 7 test (FIG. 25) and a mode 8 test (FIG. 26) are performed. Thereby, the current leakage to the ESD protection element ESD1, the switch elements SW41A, SW41B, SW32A, and SW30 shown by hatching in FIGS. 25 and 26, the reverse breakdown voltage leakage of the protection diode D1A or D2A, and the high impedance of the output amplifier 25A The total value of the leakage current is measured.

  First, in the mode 7 test of FIG. 25, a predetermined voltage, for example, 20 V, which is the same as the power supply voltage VDD, is applied to the output terminal 16A via the probe 104 by the tester 101. Further, the control circuit 20 applies a predetermined voltage, for example, 0 V, which is the same as the ground voltage VSS, to the common line K. Furthermore, in response to the enable signal EN from the control circuit 20, the output amplifiers 25A and 25B enter a high impedance state (Hi-Z).

  In the mode 7 test, as described above, the voltage of the output terminal 16A is 20V, the voltage of the common line K is 0V, and the output amplifiers 25A and 25B are in the high impedance state. Therefore, if the diode D2A of the ESD protection element ESD1 When there is a current leak on the VSS side of the high impedance output of SW41A, SW41B, SW32A, SW30, or output amplifier 25A, a current flows from the output terminal 16A toward the common line K or the ground terminal VSS. That is, since a current flows from the probe 104 to the output terminal 16A, the tester 101 measures this current value as an output signal and compares it with a reference value. The reference value at this time is set to, for example, twice the leak standard value when the output terminal is in the high impedance state. If the measured current value is larger than the reference value, the failure is determined and the test is terminated.

  When the tester 101 determines that the mode 7 test is passed as a result of the measurement, the process proceeds to the mode 8 test as described with reference to FIG.

  Next, in the mode 8 test of FIG. 26, a predetermined voltage, for example, 0 V, which is the same as the ground voltage VSS, is applied to the output terminal 16A via the probe 104 by the tester 101. Further, the control circuit 20 applies a predetermined voltage, for example, 0 V, which is the same as the ground voltage VSS, to the common line K. Furthermore, the output amplifiers 25A and 25B become high impedance (Hi-Z) in response to the enable signal EN from the control circuit 20.

  In this mode 8 test, since the voltage of the output terminal 16A is 0V, the common line K is 20V, and the output amplifiers 25A and 25B are in a high impedance state as described above, the diode D1A of the ESD protection element ESD1, the switch element SW41A, When there is a current leak on the VDD side of the high impedance output of SW41B, SW32A, SW30, or output amplifier 25A, a current flows from the common line K or the power supply terminal VDD toward the output terminal 16A. That is, since a current flows into the probe 104 from the output terminal 16A, the tester 101 measures this current value as an output signal and compares it with the reference value. The reference value at this time is set to, for example, twice the leak standard value when the output terminal is in the high impedance state. If the measured current value is larger than the reference value, the failure is determined and the test is terminated.

  If the tester 101 determines that the mode 8 test is passed as a result of the measurement, the process proceeds to the mode 9 test as described with reference to FIG.

  Next, in the mode 9 test and the mode 10 test, as shown in FIGS. 27 and 28, the output amplifiers 25A and 25B are deactivated (high impedance output) according to the enable signal EN and the control signal from the control circuit 20. ), The switch elements SW31A, SW31B, SW41A, SW41B, and SW30 of the switch circuit 21 are turned on, and the switch elements SW32A and SW32B are turned off. In this state, a mode 9 test (FIG. 27) and a mode 10 test (FIG. 28) are performed. Accordingly, the total value of the reverse breakdown voltage leakage of the ESD protection elements ESD1 and ESD2, the current leakage to the switching elements SW32A and SW32B, and the leakage current at the time of high impedance of the output amplifiers 25A and 25B, which are shown by hatching in FIGS. Measured.

  First, in the mode 9 test of FIG. 27, a predetermined voltage, for example, 20 V, which is the same as the power supply voltage VDD, is applied to the output terminal 16A by the tester 101 via the probe 104. Further, the control circuit 20 applies a predetermined voltage, for example, 0 V, which is the same as the ground voltage VSS, to the common line K. Furthermore, the output amplifiers 25A and 25B become high impedance (Hi-Z) in response to the enable signal EN from the control circuit 20.

  In this mode 9 test, as described above, the voltage of the output terminal 16A is 20V, the voltage of the common line K is 0V, and the output amplifiers 25A and 25B are in the high impedance state, so if the diodes D2A and ESD2 of the ESD protection element ESD1 When there is a current leak on the VSS side of the high impedance output of the diode D2B, the switch elements SW32A and SW32B, and the output amplifiers 25A and 25B, a current flows from the output terminal 16A toward the common line K or the ground terminal VSS. That is, since a current flows from the probe 104 to the output terminal 16A, the tester 101 measures this current value as an output signal and compares it with a reference value. The reference value at this time is set to, for example, one time the leak standard value when the output terminal is in a high impedance state. If the measured current value is larger than the reference value, the failure is determined and the test is terminated.

  If the tester 101 determines that the mode 9 test is passed as a result of the measurement, the process proceeds to the mode 10 test as described with reference to FIG.

  Next, in the mode 10 test of FIG. 28, a predetermined voltage, for example, 0 V, which is the same as the ground voltage VSS, is applied to the output terminal 16A via the probe 104 by the tester 101. Further, the control circuit 20 applies a predetermined voltage, for example, 20 V, which is the same as the power supply voltage VDD, to the common line K. Furthermore, the output amplifiers 25A and 25B become high impedance (Hi-Z) in response to the enable signal EN from the control circuit 20.

  In this mode 10 test, as described above, the voltage at the output terminal 16A is 0V, the common line K is 20V, and the output amplifiers 25A and 25B are in the high impedance state, so that the diode D1A of the ESD protection element ESD1 and the diode D1B of ESD2 When there is a current leak on the VDD side of the high impedance outputs of the switch elements SW32A and SW32B and the output amplifiers 25A and 25B, a current flows from the common line K or the power supply terminal VDD toward the output terminal 16A. That is, since a current flows into the probe 104 from the output terminal 16A, the tester 101 measures this current value as an output signal and compares it with the reference value. The reference value at this time is set to, for example, one time the leak standard value when the output terminal is in a high impedance state. If the measured current value is larger than the reference value, the failure is determined and the test is terminated.

  If the tester 101 determines that the mode 10 test is passed as a result of the measurement, it is determined that the leak test is passed as described with reference to FIG.

  As described above, in the drive circuit 200 using a half amplifier as in the second embodiment, the function test and the leak test described above are performed in the wafer test in the same manner as in the first embodiment. It is not necessary to apply the probe 104 to all of the terminals (960 in this example). For this reason, the probe 104 may be applied only to one of the adjacent output terminals (for example, the odd-numbered output terminal 16A) of the drive circuit 200 of the second embodiment.

  Therefore, in the second embodiment as in the first embodiment, 960 probes are not required for one LSI chip while maintaining the same test quality as in the prior art, and the number of 480 probes, which is half that number. Just use. For this reason, it is not necessary to prepare an expensive tester having a large number of probes, and an increase in the inspection cost can be suppressed. Further, it is the same as in the first embodiment in that it is effective for narrowing the output terminal interval.

  Embodiment 3 of the Invention

  Hereinafter, a specific third embodiment to which the present invention is applied will be described in detail with reference to the drawings. In the third embodiment, the present invention is also applied to a driving circuit for a display device and an inspection method for an LSI chip on which the driving circuit is mounted. The third embodiment is different from the first and second embodiments in the configuration of the drive circuit of the display device mounted on the LSI chip to be inspected. Therefore, the test system is the same as that shown in FIG. 1, and a description thereof is omitted here.

  FIG. 29 shows the configuration of the drive circuit 300 of the display apparatus according to the third embodiment.

  As shown in FIG. 29, the drive circuit 300 includes a pair of data registers 11A and 11B, a pair of data latches 12A and 12B, a pair of level shift circuits 13A and 13B, a pair of DACs 14A and 14B, and a pair of outputs. Amplifiers 25A and 25B, a pair of output terminals 16A and 16B, switch circuits 17 and 31, and a control circuit 20 are included.

  29, the same reference numerals as those in FIG. 17 denote the same or similar structures as those in FIG. For this reason, in this Embodiment 3, a different part from Embodiment 2 is demonstrated, and description of the same part is abbreviate | omitted.

  The switch circuit 31 includes switch elements SW31A, SW31B, SW41A, and SW41B.

  The switch element SW31A is connected between the output amplifier 25A and the output terminal 16A. The switch element SW31B is connected between the output amplifier 25B and the output terminal 16B. The switch element SW41A is connected between the output amplifier 25A and the output terminal 16B. The switch element SW41B is connected between the output amplifier 25B and the output terminal 16A.

  The switch elements SW31A, SW31B, SW41A, and SW41B are individually controlled to be turned on or off in accordance with a control signal from the control circuit 20.

  The difference between the switch circuit 31 of the second embodiment and the switch circuit 31 of the third embodiment is that the common line K and the switch elements SW32A and SW32B connected thereto are deleted.

  In the normal display operation in which the drive circuit 300 drives the data lines of the liquid crystal display device, the switch elements SW11A and SW11B of the switch circuit 17 are on and the switch elements SW12A and SW12B are off as in the second embodiment. In this case, the switch elements SW31A and SW31B of the switch circuit 31 are turned on and the switch elements SW41A and SW41B are turned off in conjunction with each other. Conversely, when the switch elements SW11A and SW11B of the switch circuit 17 are off and the switch elements SW12A and SW12B are on, the switch elements SW31A and SW31B of the switch circuit 31 are off and the switch elements SW41A and SW41B are on. Become. As a result, contrary to the previous case, the output terminal 16A outputs positive polarity and the output terminal 16B outputs negative polarity. This makes it possible to invert the polarity of the pixels of the liquid crystal display device.

  The control circuit 20 controls, for example, on / off control of switch element groups included in each of the switch circuits 17 and 31 and enable of the output amplifiers 25A and 25B in accordance with a test signal from the tester 101 outside the LSI chip. .

  Next, a quality determination test for the drive circuit 300 will be described. The flowchart of the pass / fail judgment test and the flowchart of the function test performed on the driving circuit 300 of the LSI chip targeted by the tester 101 are the same as those in FIGS. In the second embodiment, a probe is applied to one of the adjacent output terminals of the LSI chip drive circuit 100. In this example, the probe 104 is applied to the output terminal 16A as shown in FIG. It is assumed that

  FIG. 30 shows the operating state of each component circuit of the drive circuit 300 during the mode 1 test. A circuit indicated by hatching in FIG. 30 is a circuit group to be tested in this mode 1 test. As shown in FIG. 30, in the mode 1 test, the switch element SW11A of the switch circuit 17 and the switch element SW31A of the switch circuit 31 are turned on in response to the control signal from the control circuit 20. Further, the output amplifier 25A is enabled in response to the enable signal EN from the control circuit 20.

  For this reason, the data line drive signal is output from the output terminal 16A via the data register 11A, the switch element SW11A, the data latch 12A, the level shift circuit 13A, the DAC 14A, the output amplifier 25A, and the switch element SW31A. The probe 104 detects the voltage of the data line drive signal output to the output terminal 16A, and the tester 101 determines whether or not the voltage value detected by the probe 104 is a specified value.

  In this determination, whether each component of the data register 11A, the switch element SW11A (ON), the data latch 12A, the level shift circuit 13A, the DAC 14A, the output amplifier 25A, and the switch element SW31A (ON) is operating correctly and It can be determined that the wiring between the components is not broken or short-circuited. Along with this, an odd-stage shift register and a clock supply path (not shown) for supplying a clock to the shift register, an image data supply path (not shown) to the data register 11A, and the negative side to the DAC 14A It can also be determined whether or not there is a defect in the voltage range supply path (not shown) and the enable signal EN supply path to the output amplifier 25A. Similarly to the second embodiment, the switch elements SW12A, SW12B, SW41A, and SW41B to be turned off are correctly turned off (not short-circuited) by setting several data registers 11B different from the data register 11A. In addition, it can be estimated that the odd-numbered circuit and the even-numbered circuit are correctly separated in terms of signal (no parasitic signal link). As a result of the determination, if the mode 1 test is passed, the process proceeds to the mode 2 test as described in FIG. It should be noted here that, as in the second embodiment, in the mode 1 test, the control circuit 20 controls the same switching circuit as in the normal display operation.

  Next, FIG. 31 shows an operation state of each component circuit of the drive circuit 300 in the mode 2 test. Circuits indicated by hatching in FIG. 31 are circuit groups to be tested in this mode 2 test. As shown in FIG. 31, in the mode 2 test, the switch element SW11B of the switch circuit 17 and the switch element SW41B of the switch circuit 31 are turned on in response to the control signal from the control circuit 20. Further, the output amplifier 25B is enabled in response to the enable signal EN from the control circuit 20. At the same time, the output amplifier 25A is disabled (inactivated, output high impedance) in accordance with the enable signal EN from the control circuit 20, or the switch element SW31A is turned off. As a result, the signal passing through the switch element SW41B from the output amplifier 25B can be output to the probe 104 from the output terminal 16A without being interfered with the output value of the output amplifier 25A.

  For this reason, the data line drive signal is output from the output terminal 16A through the data register 11B, the switch element SW11B, the data latch 12B, the level shift circuit 13B, the DAC 14B, the output amplifier 25B, the switch elements SW31B and SW30. . The probe 104 detects the voltage of the data line drive signal output to the output terminal 16A, and the tester 101 determines whether or not the voltage value detected by the probe 104 is a specified value.

  In this determination, whether each component of the data register 11B, the switch element SW11B (ON), the data latch 12B, the level shift circuit 13B, the DAC 14B, the output amplifier 25B, and the switch element SW41B (ON) is operating correctly and It can be determined that the wiring between the components is not broken or short-circuited. Along with this, an even number of shift registers, a clock supply path (not shown) for supplying clocks to the shift register, an image data supply path (not shown) to the data register 11B, and a positive side to the DAC 14B It can also be determined whether or not there is a defect in the voltage range supply path (not shown) and the enable signal EN supply path to the output amplifier 25B.

  Similarly to the second embodiment, the switch elements SW12A and SW12B to be turned off are correctly turned off by setting several data of appropriate values (different values from the data register 11B) in the data register 11A. Then, it can be determined that the output amplifier 25A is correctly inactivated, and that the even-numbered and odd-numbered circuits are correctly separated in signal (no parasitic signal link). Note that when the switch element SW31A is turned off, it can be determined that the switch element SW31A is correctly turned off. As a result of the determination, if the mode 2 test is passed, the process proceeds to the mode 3 test as described with reference to FIG.

  It should be noted here that, as in the second embodiment, in the mode 2 test, the control circuit 20 controls the switch circuit different from that in the normal display operation. The first difference is that the output amplifier 25A is set to high impedance so as not to be output to the output terminal 16A. In addition, when the display data of the data register 11B is latched in the data latch 12B and DA-converted by the DAC 14B having the positive polarity range and output from the output amplifier 25B, the switch element SW41B that is always turned off is turned on. This is the second difference. These two points are different from the operation of the control circuit of the drive circuit of a normal display device. Further, it should be noted here that in this mode 2 test, the test method is different from that during normal operation. In general, the feature of the third embodiment is that an expected output value to be compared at the output terminal 16B is compared with a test output value at the output terminal 16A.

  Next, FIG. 32 shows the operating state of each component circuit of the drive circuit 300 during the mode 3 test. Circuits indicated by hatching in FIG. 32 are circuit groups to be tested in this mode 3 test. As shown in FIG. 32, in the mode 3 test, the switch element SW12A of the switch circuit 17 and the switch elements SW31A, SW31B, and SW41A of the switch circuit 31 are turned on in response to the control signal from the control circuit 20. Further, the output amplifier 25B is enabled in response to the enable signal EN from the control circuit 20. At the same time, the output amplifier 25A is disabled (inactivated, output high impedance) according to the enable signal EN from the control circuit 20. As a result, a signal that has passed through the switch element SW41A from the output amplifier 25A can be output from the output terminal 16A to the probe 104 without interfering with the output value of the output amplifier 25B.

  For this reason, the data line drive signal is output from the output terminal 16A via the data register 11A, the switch element SW12A, the data latch 12B, the level shift circuit 13B, the DAC 14B, the output amplifier 25B, the switch elements SW31A, SW31B, and SW41A. Is done. The probe 104 detects the voltage of the data line drive signal output to the output terminal 16A, and the tester 101 determines whether or not the voltage value detected by the probe 104 is a specified value.

  With this determination, each component of the data register 11A, the switch element SW12A (ON), the data latch 12B, the level shift circuit 13B, the DAC 14B, the output amplifier 25B, the switch element SW31A (ON), SW31B (ON), and SW41A (ON). It can be determined whether or not the circuit is operating correctly and whether the wiring between the constituent elements is not broken or short-circuited. That is, it is possible to perform a function test of the switch elements SW12A, SW31B, and SW41A that have not been tested in the above-described mode 1 test and mode 2 test.

  Here, for the purpose of confirming that SW12A of switch circuit 17 is turned on, SW11B is turned off, switch elements SW31B and SW41B of switch circuit 31 are turned on, and SW41A is turned off, only the minimum necessary test pattern for confirming this is required. It is preferable to reduce the test time by passing If the mode 3 test is passed as a result of this determination, the process proceeds to the mode 4 test as described with reference to FIG.

  It should be noted here that in the mode 3 test, the control circuit 20 controls the switch circuit different from that in the normal display operation. The first difference is that the output amplifier 25A is set to high impedance so as not to be output to the output terminal 16A. Further, when the output data is output from the output amplifier 25B after the display data of the data register 11A is latched in the data latch 12B and DA-converted by the positive polarity range DAC 14B, the switch is always turned off when the output terminal is driven by the output amplifier. The second difference is that the elements SW31A and SW31B are turned on and the switch element SW41B that is always turned on is turned off. These two points are different from the operation of the control circuit of the drive circuit of a normal display device.

  Next, FIG. 33 shows the operating state of each component circuit of the drive circuit 300 during the mode 4 test. A circuit shown by hatching in FIG. 33 is a circuit group to be tested in this mode 4 test. As shown in FIG. 33, in the mode 4 test, the switch element SW12B of the switch circuit 17 and the switch element SW31A of the switch circuit 31 are turned on in response to the control signal from the control circuit 20. Further, the output amplifier 25A is enabled in response to the enable signal EN from the control circuit 20.

  For this reason, the data line drive signal is output from the output terminal 16A through the data register 11B, the switch element SW12B, the data latch 12A, the level shift circuit 13A, the DAC 14A, the output amplifier 25A, and the switch element SW31A. The probe 104 detects the voltage of the data line drive signal output to the output terminal 16A, and the tester 101 determines whether or not the voltage value detected by the probe 104 is a specified value.

  In this determination, whether each component of the data register 11B, the switch element SW12B (ON), the data latch 12A, the level shift circuit 13A, the DAC 14A, the output amplifier 25A, and the switch element SW31A (ON) is operating correctly and It can be determined that the wiring between the components is not broken or short-circuited. That is, it is possible to perform a function test in the ON state of the switch element SW12B that could not be tested in the mode 1 test to the mode 3 test. Here, for the purpose of confirming that the SW 12B of the switch circuit 17 is turned on, it is preferable to reduce the test time by passing only the minimum necessary test pattern for confirming that. As a result of the determination, if the mode 4 test is passed, it is determined that the function test is passed as described with reference to FIG.

  It should be noted that in the mode 4 test, the control circuit 20 controls the switch circuit different from that in the normal display operation. When the display data of the data register 11B is latched in the data latch 12A, DA-converted by the DAC 14A having the negative polarity range and output from the output amplifier 25A, the switch element SW31A that is always turned off is turned on and is always turned on. This is different from the normal display operation in that the switch element SW41A is turned off. Furthermore, the feature of the third embodiment is that the expected output value to be compared at the normal output terminal 16B is compared with the test output value at the output terminal 16A.

  Next, the leak test in step S103 in FIG. 4 will be described with reference to FIGS. FIG. 34 shows a flowchart of a leak test performed by the tester 101 on the driving circuit 300 of the LSI chip targeted. As shown in FIG. 34, first, the tester 101 performs a mode 5 test (see FIG. 35) described later on the drive circuit 100 (S401). If the output signal (current value) output from the output terminal of the drive circuit 300 is a specified value as a result of the mode 5 test, the mode 5 test is passed (S402 YES).

  Next, the tester 101 performs a mode 6 test (see FIG. 36) to be described later on the drive circuit 300 (S403). If the output signal (current value) output from the output terminal of the drive circuit 300 is a specified value as a result of the mode 6 test, the mode 6 test is passed (S404 YES).

  Next, the tester 101 performs a mode 7 test (see FIG. 37) described later on the drive circuit 300 (S405). If the output signal (current value) output from the output terminal of the drive circuit 300 is a specified value as a result of the mode 7 test, the mode 7 test is passed (S406 YES).

  Next, the tester 101 performs a mode 8 test (see FIG. 38) to be described later on the drive circuit 300 (S407). If the output signal (current value) output from the output terminal of the drive circuit 300 is a specified value as a result of the mode 8 test, the mode 8 test is passed (YES in S408).

  Next, the tester 101 performs a mode 9 test (see FIG. 39) to be described later on the drive circuit 300 (S409). If the output signal (current value) output from the output terminal of the drive circuit 300 is a specified value as a result of the mode 9 test, the mode 7 test is passed (S410 YES).

  Next, the tester 101 performs a mode 10 test (see FIG. 40), which will be described later, on the drive circuit 300 (S411). If the output signal (current value) output from the output terminal of the drive circuit 300 is a specified value as a result of the mode 10 test, the mode 10 test is passed (S412 YES).

  If the mode 10 test is passed in step S412, it is determined that the target LSI chip drive circuit 300 has passed the leak test in step S103 of FIG. 4 (S413). On the other hand, if the pass is not successful in steps S402, S404, S406, S408, and S410 (S402NO, S404NO, S406NO, S408NO, and S410NO), the target LSI chip drive circuit 300 performs the leak test in step S103 of FIG. Is determined to have failed (S414).

  35 and 36 show the operating states of the output amplifiers 25A and 25B, the output terminals 16A and 16B, and the switch circuit 31 of the drive circuit 300 during the mode 5 test and the mode 6 test. 35 and FIG. 36 is a circuit group to be a current leak test target in the mode 5 test and the mode 6 test. 35 to 40, the ESD protection elements ESD1 and ESD2 omitted in FIG. 29 are described.

  The diode D1A of the ESD protection element ESD1 has a cathode connected to the power supply terminal VDD and an anode connected to the output terminal 16A. The diode D2A has a cathode connected to the output terminal 16A and an anode connected to the ground terminal VSS. The diode D1B of the ESD protection element ESD2 has a cathode connected to the power supply terminal VDD and an anode connected to the output terminal 16B. The diode D2B has a cathode connected to the output terminal 16B and an anode connected to the ground terminal VSS.

  In the mode 5 test and the mode 6 test, as shown in FIGS. 35 and 36, the output amplifier 25B is deactivated (high impedance output) according to the enable control signal and the control signal from the control circuit 20, and the switch circuit 31 switch elements SW41A and SW41B are turned on, and switch elements SW31A and SW31B are turned off. Then, by conducting the mode 5 test (FIG. 35) and the mode 6 test (FIG. 36) in this state, current leakage to the switch elements SW31A and SW31B shown by hatching in FIGS. 35 and 36, and the protection diode D2A The total value of the reverse breakdown voltage leakage and the leakage current at the time of high impedance of the output amplifier 25B is measured.

  First, in the mode 5 test of FIG. 35, the tester 101 applies a predetermined voltage, for example, 20 V, which is the same as the power supply voltage VDD, to the output terminal 16A via the probe 104. Furthermore, the value of the display data in the data registers 11A and 11B is set to the maximum amplitude (LSB (Least Significant Bit) for a normally white panel, MSB (Most Significant Bit) for a normally black panel), VSS (0V) is output from the negative DAC 14A, and VDD (20V) is output from the positive DAC 14B. Then, the switch elements SW41A and SW41B of the switch circuit 31 are turned on and the switch elements SW31A and SW31B are turned off by the control signal of the control circuit 20. Then, in response to the enable signal EN from the control circuit 20, the output amplifier 25B is deactivated, the output is high impedance (Hi-Z), and the output amplifier 25A is activated to output 0V.

  In this mode 5 test, as described above, the voltage of the output terminal 16A is 20V, the output amplifier 25A outputs 0V, and the output amplifier 25B is in a high impedance state. Therefore, if the diode D2A of the ESD protection element ESD1, the switch element SW31A, When there is a current leak on the VSS side of the high impedance output of the SW 31B and the output amplifier 25B, a current flows from the output terminal 16A toward the output amplifier 25A or the ground terminal VSS. That is, since a current flows from the probe 104 to the output terminal 16A, the tester 101 measures this current value as an output signal and compares it with a reference value. The reference value at this time is set to, for example, twice the leak standard value when the output terminal is in the high impedance state. If the measured current value is larger than the reference value, the failure is determined and the test is terminated. As in the second embodiment, the current leakage on the VSS side of the high impedance outputs of the output amplifiers 25A and 25B is caused by a MOS transistor connected between the output node inside the output amplifiers 25A and 25B and the ground terminal VSS. Current leakage (usually an NMOS transistor) is assumed.

  When the tester 101 determines that the mode 5 test is passed as a result of the measurement, the process proceeds to the mode 6 test as described with reference to FIG.

  Next, in the mode 6 test of FIG. 36, a predetermined voltage, for example, 0 V, which is the same as the ground voltage VSS, is applied to the output terminal 16A via the probe 104 by the tester 101. Furthermore, the display data value of the data registers 11A and 11B is set to the minimum amplitude (MSB for the normally white panel, LSB for the normally black panel), and 10 V is output from the negative DAC 14A. For example, 10 V is output from the positive-side DAC 14B. Then, the switch elements SW41A and SW41B of the switch circuit 31 are turned on and the switch elements SW31A and SW31B are turned off by the control signal of the control circuit 20. Then, in response to the enable signal EN from the control circuit 20, the output amplifier 25B is deactivated, the output is high impedance (Hi-Z), and the output amplifier 25A is activated to output 10V.

  In this mode 6 test, as described above, the voltage at the output terminal 16A is 0V, the output amplifier 25A outputs 10V, and the output amplifier 25B is in a high impedance state. Therefore, if the diode D1A of the ESD protection element ESD1, the switch element SW31A, If there is a current leak on either the SW 31B or the high impedance output VDD side of the output amplifier 25B, a current flows from the output amplifier 25A or the power supply terminal VDD toward the output terminal 16A. That is, since a current flows from the output terminal 16A to the probe 104, the tester 101 measures this current value as an output signal and compares it with a reference value. The reference value at this time is set to, for example, twice the leak standard value when the output terminal is in the high impedance state. If the measured current value is larger than the reference value, the failure is determined and the test is terminated. As in the second embodiment, the current leakage on the VDD side of the high-impedance output of the output amplifiers 25A and 25B is caused by a MOS transistor connected between the output node inside the output amplifiers 25A and 25B and the power supply terminal VDD. Current leakage (usually a PMOS transistor) is assumed.

  When the tester 101 determines that the mode 6 test is passed as a result of the measurement, the process proceeds to the mode 7 test as described with reference to FIG.

  Next, in the mode 7 test and the mode 8 test, as shown in FIGS. 37 and 38, the output amplifier 25A is deactivated (high impedance output) in accordance with the enable control signal and the control signal from the control circuit 20. The switch elements SW31A and SW31B of the switch circuit 31 are turned on, and the switch elements SW41A and SW41B are turned off. In this state, by conducting the mode 7 test (FIG. 37) and the mode 8 test (FIG. 38), current leakage to the switch elements SW41A and SW41B indicated by shading in FIGS. 37 and 38, and the protection diode D1A The total value of the reverse breakdown voltage leakage and the leakage current at the time of high impedance of the output amplifier 25A is measured.

  In the mode 7 test of FIG. 37, a predetermined voltage, for example, 0 V, which is the same as the ground voltage VSS, is applied to the output terminal 16A via the probe 104 by the tester 101. Further, the value of the display data in the data registers 11A and 11B is set to the maximum amplitude (LSB for the normally white panel, MSB for the normally black panel), and VSS (0 V) is set from the negative DAC 14A. Then, VDD (20 V) is output from the positive-side DAC 14B. Then, the switch elements SW41A and SW41B of the switch circuit 31 are turned off and the switch elements SW31A and SW31B are turned on by the control signal of the control circuit 20. Then, in response to the enable signal EN from the control circuit 20, the output amplifier 25A is deactivated to output high impedance (Hi-Z), and the output amplifier 25B is activated to output 20V.

  In this mode 7 test, as described above, the voltage of the output terminal 16A is 0V, the output amplifier 25B outputs 20V, and the output amplifier 25A is in a high impedance state. Therefore, if the diode D1A of the ESD protection element ESD1 and the switch element When there is a current leak on the VDD side of the high impedance output of SW41A, SW41B, or output amplifier 25A, current flows from output amplifier 25B or power supply terminal VDD toward output terminal 16A. That is, since a current flows into the probe 104 from the output terminal 16A, the tester 101 measures this current value as an output signal and compares it with the reference value. The reference value at this time is set to, for example, twice the leak standard value when the output terminal is in the high impedance state. If the measured current value is larger than the reference value, the failure is determined and the test is terminated.

  If the tester 101 determines that the mode 7 test is passed as a result of the measurement, the process proceeds to the mode 8 test as described with reference to FIG.

  Next, in the mode 8 test of FIG. 38, a predetermined voltage, for example, 0 V, which is the same as the ground voltage VSS, is applied to the output terminal 16A via the probe 104 by the tester 101. Furthermore, the display data value of the data registers 11A and 11B is set to the minimum amplitude (MSB for the normally white panel, LSB for the normally black panel), and 10 V is output from the negative DAC 14A. For example, 10 V is output from the positive-side DAC 14B. Then, the switch elements SW41A and SW41B of the switch circuit 31 are turned off and the switch elements SW31A and SW31B are turned on by the control signal of the control circuit 20. Then, in response to the enable signal EN from the control circuit 20, the output amplifier 25A is inactivated, the output is high impedance (Hi-Z), and the output amplifier 25B is activated to output 10V.

  In this mode 8 test, as described above, the voltage of the output terminal 16A is 20V, the output amplifier 25B outputs 10V, and the output amplifier 25A is in a high impedance state, so that the diode D2A of the ESD protection element ESD1, the switch element SW41A, When there is a current leak on either the SW41B or the VSS side of the high impedance output of the output amplifier 25A, a current flows from the output terminal 16A toward the output amplifier 25A or the ground terminal VSS. That is, since a current flows from the probe 104 to the output terminal 16A, the tester 101 measures this current value as an output signal and compares it with a reference value. The reference value at this time is set to, for example, twice the leak standard value when the output terminal is in the high impedance state. If the measured current value is larger than the reference value, the failure is determined and the test is terminated.

  If the tester 101 determines that the mode 8 test is passed as a result of the measurement, the process proceeds to the mode 9 test as described with reference to FIG.

  Next, in the mode 9 test and the mode 10 test, as shown in FIGS. 39 and 40, the output amplifiers 25A and 25B are deactivated according to the enable control signal and the control signal from the control circuit 20 (high impedance output). ), And the switch elements SW31A, SW31B, SW41A, and SW41B of the switch circuit 31 are turned on. In this state, a mode 9 test (FIG. 39) and a mode 10 test (FIG. 40) are performed. As a result, the total value of the reverse breakdown voltage leakage of the protection diodes D1A, D2A, D1B, D2B and the leakage current at the time of high impedance of the output amplifiers 25A, 25B, which are indicated by hatching in FIGS. 39 and 40, is measured.

  First, in the mode 9 test shown in FIG. 39, a predetermined voltage, for example, 20 V, which is the same as the power supply voltage VDD, is applied to the output terminal 16A via the probe 104 by the tester 101. Further, in response to the enable signal EN from the control circuit 20, the output amplifiers 25A and 25B become high impedance (Hi-Z).

  In this mode 9 test, the voltage at the output terminal 16A is 20V and the output amplifiers 25A and 25B are in the high impedance state as described above. Therefore, if the diode D2A of the ESD protection element ESD1, the diode D2B of the ESD protection element ESD2, and the output amplifier are used. When there is a current leak on either VSS side of the high impedance outputs of 25A and 25B, a current flows from the output terminal 16A toward the ground terminal VSS. That is, since a current flows from the probe 104 to the output terminal 16A, the tester 101 measures this current value as an output signal and compares it with a reference value. The reference value at this time is set to, for example, one time the leak standard value when the output terminal is in a high impedance state. If the measured current value is larger than the reference value, the failure is determined and the test is terminated.

  If the tester 101 determines that the mode 9 test is passed as a result of the measurement, the process proceeds to the mode 10 test as described with reference to FIG.

  Next, in the mode 10 test of FIG. 40, a predetermined voltage, for example, 0 V, which is the same as the ground voltage VSS, is applied to the output terminal 16A via the probe 104 by the tester 101. Further, in response to the enable signal EN from the control circuit 20, the output amplifiers 25A and 25B become high impedance (Hi-Z).

  In this mode 10 test, since the voltage of the output terminal 16A is 0V and the output amplifiers 25A and 25B are in the high impedance state as described above, the diode D1A of the ESD protection element ESD1, the diode D1B of the ESD protection element ESD2, and the output amplifier When there is a current leak on either the VDD side of the high impedance outputs of 25A and 25B, a current flows from the power supply voltage VDD toward the output terminal 16A. That is, since a current flows into the probe 104 from the output terminal 16A, the tester 101 measures this current value as an output signal and compares it with the reference value. The reference value at this time is set to, for example, one time the leak standard value when the output terminal is in a high impedance state. If the measured current value is larger than the reference value, the failure is determined and the test is terminated.

    When the tester 101 determines that the mode 10 test is passed as a result of the measurement, it is determined that the leak test is passed as described with reference to FIG.

  As described above, in the drive circuit 300 having the configuration without the switch element SW30 for connecting adjacent output terminals as in the third embodiment, the function test and the leak described above are performed in the wafer test as in the first and second embodiments. By performing the test, it is not necessary to apply the probe 104 to all the output terminals (960 in this example) in the LSI chip. For this reason, the probe 104 may be applied to only one of the adjacent output terminals (for example, the odd-numbered output terminal 16A) of the drive circuit 300 according to the third embodiment.

  Therefore, in the third embodiment as in the first and second embodiments, 960 probes are not required for one LSI chip while maintaining the same test quality as in the prior art, and half of the number is 480. Just use the number of probes. For this reason, it is not necessary to prepare an expensive tester having a large number of probes, and an increase in the inspection cost can be suppressed. Further, it is the same as in the first and second embodiments in that it is effective for narrowing the pitch between output terminals.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, in the drive circuit 100 of the first embodiment, when the common line K is not necessary, the switch elements SW32A and SW32B can be omitted.

101 Tester 102 Probe card 103 Wafer 104 Probe (inspection unit)
100, 200, 300 Driving circuit 11A, 11B Data register 12A, 12B Data latch 13A, 13B Level shift circuit 14A, 14B Digital-analog conversion circuit (DAC)
15A, 15B, 25A, 25B Output amplifiers 16A, 16B Output terminals 17-19 Switch circuit 20 Control circuit K Common lines SW11A, SW11B, SW12A, SW12B, SW22A, SW22B, SW30, SW31A, SW31B, SW32A, SW32B, SW41A, SW41B Switch element

Claims (15)

A display device driving circuit for driving the first data line and the second data line of the display device, respectively,
A first data register and a second data register which respectively store first display data and second display data to be displayed on the display device, and which respectively output a first signal and a second signal;
A first DA converter and a second DA converter that respectively output a first analog signal and a second analog signal in response to the first signal and the second signal;
An output terminal pair for driving the first data line and the second data line in response to the first analog signal and the second analog signal;
During a test, a first test output based on the first display data and a second test data based on the second display data are applied to one of the output terminal pairs in response to a test control signal from an external test circuit. A switch circuit that selectively outputs a test output;
And a control circuit that controls the switch circuit. The display device driving circuit according to claim 1, further comprising a first switch circuit that switches between the first signal and the second signal and outputs the first signal and the second signal to the first DA converter and the second DA converter. 2. The display device driving circuit according to claim 1, further comprising a second switch circuit that drives the first data line and the second data line by switching between the first analog signal and the second analog signal. . A first output amplifier and a second output amplifier that are activated or deactivated according to an enable signal from the control circuit;
When activated, it amplifies corresponding to the voltage levels of both the first and second analog signals from the first and second DA converters,
The display device driving circuit according to claim 3, wherein when it is inactivated, a high impedance output is obtained. The switch circuit corresponds to the second switch circuit,
The second switch circuit includes a third switch circuit and a fourth switch circuit,
The third switch circuit is disposed between the first and second DA converters and the first and second output amplifiers,
The display device driving circuit according to claim 4, wherein the fourth switch circuit is disposed between the first and second output amplifiers and the output terminal pair. The switch circuit corresponds to the first switch circuit,
The first switch circuit includes:
A first switch element that outputs the output of the first data register to the first DA converter when conducting;
A second switch element that outputs the output of the second data register to the second DA converter when conducting;
A third switch element that outputs the output of the first data register to the second DA converter when conducting;
The display device drive circuit according to claim 2, further comprising: a fourth switch element that outputs an output of the second data register to the first DA converter when the switch is turned on. The third switch circuit includes:
A fifth switch element that outputs a first analog signal of the first DA converter to the first output amplifier when conducting;
A sixth switch element that outputs a second analog signal of the second DA converter to the second output amplifier when conducting;
A seventh switch element that outputs a first analog signal of the first DA converter to the second output amplifier when conducting;
An eighth switch element that outputs a second analog signal of the second DA converter to the first output amplifier when conducting,
The fourth switch circuit includes:
The display device driving circuit according to claim 5, further comprising: a ninth switch element that connects one of the output terminal pairs to the other when conducting. The fourth switch circuit further includes a tenth switch element that connects one of the output terminal pair and a common line when conducting,
An eleventh switch element that connects the other of the output terminal pair and the common line when conducting;
A twelfth switch element that connects the first output amplifier and one of the output terminal pairs when conducting;
The display device driving circuit according to claim 7, further comprising: a thirteenth switch element that connects the second output amplifier and the other of the output terminal pair when conducting. A first output amplifier and a second output amplifier that are activated or deactivated according to an enable signal from the control circuit;
The first output amplifier amplifies corresponding to the voltage level of the first analog signal from the first DA converter when activated, and becomes a high impedance output when deactivated,
4. The second output amplifier amplifies corresponding to the voltage level of the second analog signal from the second DA converter when activated, and becomes a high impedance output when deactivated. A display device driving circuit according to claim 1. The switch circuit corresponds to the second switch circuit,
The display device driving circuit according to claim 9, wherein the second switch circuit is disposed between the first and second output amplifiers and the output terminal pair. The second switch circuit includes:
A fifth switch element that outputs the output of the first output amplifier to one of the output terminal pairs when conducting;
A sixth switch element that outputs the output of the second output amplifier to the other of the output terminal pair when conducting;
A seventh switch element for outputting the output of the first output amplifier to the other of the output terminal pair when conducting;
11. The display device drive circuit according to claim 10, further comprising: an eighth switch element that outputs an output of the second output amplifier to one of the output terminal pairs when conducting. 11. The second switch circuit further includes:
The display device driving circuit according to claim 11, further comprising a ninth switch element that connects one of the output terminal pairs to the other when conducting. The second switch circuit further includes a tenth switch element that connects one of the output terminal pair and a common line when conducting,
The display device drive circuit according to claim 12, further comprising: an eleventh switch element that connects the other of the output terminal pair and the common line when conducting. A test control method for a display device driving circuit for driving a first data line and a second data line of a display device, respectively,
The display device driving circuit includes:
A first data register and a second data register for respectively storing and outputting first display data and second display data to be displayed on the display device;
A first DA converter for outputting a first analog signal and a second analog signal in response to a first signal and a second signal from the first data register and the second data register, respectively; DA converter,
An output terminal pair for driving the first data line and the second data line in response to the first analog signal and the second analog signal;
During a test, a first test output based on the first display data and a second test data based on the second display data are applied to one of the output terminal pairs in response to a test control signal from an external test circuit. A switch circuit for selectively outputting a test output,
A test control method for a display device driving circuit for controlling the switch circuit. A first data register and a second data register for respectively storing and outputting first display data and second display data to be displayed on the display device;
A first DA converter for outputting a first analog signal and a second analog signal in response to a first signal and a second signal from the first data register and the second data register, respectively; DA converter,
A first output amplifier and a second output amplifier that amplify and output the first analog signal and the second analog signal when activated, and a high impedance output when deactivated;
An output terminal pair for driving the first data line and the second data line in response to the output from the first and second output amplifiers;
A switch control circuit for outputting an output based on the first display data or the second display data to one of the output terminal pairs, and a test control method for a display device drive circuit comprising:
During a leak test, one of the output terminal pairs leaks by controlling the conduction and non-conduction of the switch elements connecting the output terminal pairs included in the switch circuit according to a test control signal from an external test circuit. A leak test control method for a display device driving circuit for outputting a test current.

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