JP2012209449A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device capable of reducing influence of heat to a semiconductor chip.SOLUTION: The method includes steps of: stacking a plurality of semiconductor chips 11a-11d on every region for semiconductor chip 10 on a surface of a semiconductor substrate 10A to which a plurality of regions for semiconductor chips 10 are formed side by side; encapsulating the plurality of semiconductor chips 11a-11c with a first molding compound 4 by filling a gap between the semiconductor substrate 10A and the semiconductor chip and gaps between the plurality of semiconductor chips 11a-11c with the first molding compound 4; and dividing into respective chip laminates 3A by cutting the semiconductor substrate 10A into each region for the semiconductor chip 10.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In recent years, the degree of integration of semiconductor chips has improved year by year, and accordingly, the chip size has been increased, the wiring has been miniaturized, and the number of layers has been increased. On the other hand, for high-density mounting, it is necessary to reduce the package size and reduce the thickness.

  In response to such a demand, a technique of mounting a plurality of semiconductor chips on a single wiring board called MCP (Multi Chip Package) has been developed. Among them, a CoC (Chip on Chip) type semiconductor package (semiconductor device) in which a chip laminated body in which semiconductor chips having through electrodes called TSV (Through Silicon Via) are laminated is mounted on one surface of a wiring board is attracting attention. .

  As a method of manufacturing a CoC type semiconductor package, a plurality of semiconductor chips constituting a chip stack are sequentially stacked on a wiring board, and an underfill material (first sealing body) is provided in each gap between the stacked semiconductor chips. After filling, the chip stack is sealed by thermosetting the underfill material. Furthermore, one surface of the wiring board is sealed with a mold resin (second sealing body) so as to cover the entire chip stack including the underfill material (see Patent Document 1). .

  On the other hand, a technique for obtaining a plurality of semiconductor chips by mounting a plurality of semiconductor chips on a base wafer and cutting the base substrate has been proposed (see Patent Document 2).

JP 2010-251347 A JP 2006-19429 A

  By the way, in the process of manufacturing the chip laminated body described above, the semiconductor chip cannot be stably sucked and held on the suction stage, and when the semiconductor chip is flip-mounted on the semiconductor chip using a bonding tool, ultrasonic waves are used. It may be difficult to apply. In this case, since thermocompression bonding at a high temperature (for example, about 300 ° C.) is required, there is a concern that the reliability of the semiconductor chip is lowered due to the influence of heat.

  A method of manufacturing a semiconductor device according to the present invention includes a step of laminating a plurality of semiconductor chips for each portion to be a semiconductor chip on a surface of a semiconductor substrate in which a plurality of portions to be semiconductor chips are formed side by side, A step of sealing the plurality of semiconductor chips with the first sealing body while filling the gaps between the plurality of semiconductor chips with the first sealing body, and an individual chip for each portion of the semiconductor substrate that becomes the semiconductor chip And a step of dividing the laminate.

  As described above, in the present invention, the semiconductor substrate can be stably sucked and held on the suction stage. Therefore, when a plurality of semiconductor chips are stacked on the semiconductor substrate using a bonding tool, Thermocompression bonding at a high temperature becomes unnecessary, and thermocompression bonding with ultrasonic waves applied at a lower temperature is possible.

  Therefore, according to the present invention, since the influence of heat on the semiconductor chip can be reduced, a highly reliable semiconductor device can be manufactured. Further, according to the present invention, the semiconductor substrate can be handled as it is until it is divided into individual chip stacks, so that the assembly process can be made more efficient.

It is sectional drawing which shows the structure of the semiconductor package shown as 1st Embodiment. FIG. 4 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 1. FIG. 4 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 1. FIG. 4 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 1. FIG. 4 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 1. FIG. 4 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 1. FIG. 4 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 1. FIG. 4 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 1. FIG. 4 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 1. FIG. 4 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 1. FIG. 4 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 1. FIG. 4 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 1. FIG. 4 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 1. FIG. 4 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 1. FIG. 4 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 1. It is sectional drawing which shows the structure of the semiconductor package shown as 2nd Embodiment. FIG. 17 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 16. FIG. 17 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 16. FIG. 17 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 16. FIG. 17 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 16. FIG. 17 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 16. FIG. 17 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 16. FIG. 17 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 16. FIG. 17 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 16. FIG. 17 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 16. FIG. 17 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 16. FIG. 17 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 16. FIG. 17 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 16. It is sectional drawing which shows the structure of the semiconductor package shown as 3rd Embodiment. FIG. 30 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 29; FIG. 30 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 29; FIG. 30 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 29; FIG. 30 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 29; FIG. 30 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 29; FIG. 30 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 29; FIG. 30 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 29; FIG. 30 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 29; FIG. 30 is a cross-sectional view for sequentially explaining a manufacturing process of the semiconductor package shown in FIG. 29;

Hereinafter, a method of manufacturing a semiconductor device to which the present invention is applied will be described in detail with reference to the drawings.
In addition, in the drawings used in the following description, in order to make the features easy to understand, there are cases where the portions that become the features are enlarged for the sake of convenience, and the dimensional ratios of the respective components are not always the same as the actual ones. Absent. In addition, the materials, dimensions, and the like exemplified in the following description are merely examples, and the present invention is not necessarily limited thereto, and can be appropriately modified and implemented without departing from the scope of the invention. .

[First Embodiment]
(Semiconductor device)
First, a CoC type semiconductor package 1A shown in FIG. 1 will be described as a first embodiment.
As shown in FIG. 1, the semiconductor package 1A includes a wiring board 2, a chip laminated body 3A mounted on one surface (upper surface) of the wiring board 2, and a first seal for sealing the chip laminated body 3A. The stopper 4, the second sealing body 5 a and the third sealing body 5 b that seal one surface of the wiring substrate 2 in a state of covering the first sealing member 4, and the other surface of the wiring substrate 2 By providing a plurality of solder balls (external connection terminals) 6 arranged on the (lower surface), a package structure called BGA (Ball Grid Array) is provided.

  The wiring board 2 is made of a printed wiring board having a rectangular shape in plan view, and this printed wiring board forms a conductor pattern made of a conductive material such as Cu on the surface of an insulating base made of glass epoxy resin, for example. The surface is covered with an insulating film such as a solder resist. In this example, the wiring board 2 having a thickness of about 0.2 mm is used.

  A mounting region 2 a on which the chip stack 3 </ b> A is mounted is provided at the center of the upper surface of the wiring board 2. A plurality of pad electrodes (third connection terminals) 7 are provided side by side in the mounting region 2 a of the wiring board 2. On the other hand, a plurality of connection lands 8 are provided side by side on the other surface (lower surface) of the wiring board 2. The solder balls 6 are disposed on the connection lands 8. In addition, the wiring substrate 2 has a lead wiring portion 9 (typically shown in FIG. 1) such as a via (through electrode) and a wiring pattern for electrically connecting the pad electrode 7 and the connection land 8. Is provided). The surface of the wiring board 2 is covered with an insulating film (not shown) except for the portion where the pad electrode 7 and the connection land 8 are formed.

  In the chip stacked body 3A, an IF chip (first semiconductor chip) 10 and a plurality (four in this example) of memory chips (second semiconductor chips) 11a to 11d are stacked in order from the wiring board 2 side. Have a structure.

  The IF chip 10 is formed with an IF (InterFace) circuit or the like for taking an interface between the memory chips 11a to 11d and the wiring board 2, and has a rectangular shape in plan view. It has a shape smaller than 2. The IF chip 10 has a plurality of first bump electrodes (first connection terminals) 12a on one side, a plurality of second bump electrodes (second connection terminals) 12b on the other side, It has a plurality of through electrodes (TSV) 13 that connect between one bump electrode 12a and the second bump electrode 12b. Further, the first bump electrode 12a of the IF chip 10 has a larger interval (200 μm or more) than the second bump electrode 12b and the through electrode 13 in accordance with the interval with the pad electrode 7 of the wiring board 2. Yes. For this reason, in the IF chip 10, a wiring pattern (not shown) for rewiring is provided between the first bump electrode 12 a and the through electrode 13, and the distance from the pad electrode 7 of the wiring board 2. Adjustments are being made. In this example, the IF chip 10 having a thickness of about 50 μm is used.

  The memory chips 11a to 11d are formed with a DRAM (Dynamic Random Access Memory) circuit or the like, have a rectangular shape in plan view, and have a shape smaller than that of the IF chip 10. Each of the memory chips 11a to 11d has a plurality of first bump electrodes (first connection terminals) 12a on one side and a plurality of second bump electrodes (second connection terminals) 12b on the other side. And a plurality of through-electrodes (TSV) 13 that connect between the first bump electrode 12a and the second bump electrode 12b. In this example, memory chips 11a to 11d having a thickness of about 50 μm are used.

  Then, the IF chip 10 and the plurality of memory chips 11a to 11d are bonded to the first bump electrode 12a and the second bump electrode 12b, respectively, with one surface and the other surface facing each other. Thus, the chip stack 3A is configured.

  Further, the chip stacked body 3A has the first bump electrode between the IF chip 10 and the one surface (mounting region 2a) facing each other with the IF chip 10 facing downward. It is mounted on one surface of the wiring board 2 by bonding the 12a and the pad electrode 7 together. Further, the chip laminated body 3A is bonded and fixed to the mounting region 2a of the wiring board 2 via an insulating adhesive member 14 filled between one surface of the wiring board 2 and one surface of the IF chip 10. The chip stacked body 3A is provided with a wire bump (joining member) on the pad electrode 7 of the wiring board 2, and the first bump electrode 12a and the pad electrode 7 are joined via the wire bump. It is also possible to mount on one surface of the wiring board 2.

  The first sealing body 4 seals the chip stack 3A with an underfill material filled in the gaps between the IF chip 10 and the plurality of memory chips 11a to 11d constituting the chip stack 3A.

  The second sealing body 5a completely seals the other surface side of the chip stacked body 3A with a mold resin covering the whole of the plurality of memory chips 11a to 11d sealed with the first sealing body 4. is doing.

  The third sealing body 5b completely seals one surface side of the wiring board 2 with a mold resin that covers the entire chip stack 3A sealed with the first and second sealing bodies 4 and 5a. is doing.

(Method for manufacturing semiconductor device)
Next, a manufacturing process of the semiconductor package 1A shown in FIG. 1 will be described as a manufacturing method of the semiconductor device to which the present invention is applied.
When manufacturing the semiconductor package 1A, first, a chip stacked body 3A in which a plurality of memory chips 11a to 11d are stacked on the IF chip 10 described above is manufactured.

  Specifically, first, as shown in FIG. 2, a semiconductor substrate 10 </ b> A provided with a plurality of portions to be the IF chip 10 is prepared. The semiconductor substrate 10A is made of a silicon base material 10a having a thickness larger than that of the IF chip 10, and a plurality of portions to be the IF chip 10 are formed side by side in a matrix, and finally a dicing line (dividing line) ) By cutting along L, the portion to be the IF chip 10 can be cut out as individual IF chips 10. In addition, in the portion to be the IF chip 10 of the semiconductor substrate 10A, the through electrode 13 in which a conductor such as Cu is embedded from one surface of the silicon base material 10a to the middle part in the depth direction, and the silicon base material 10a A first bump electrode 12a connected to the through electrode 13 is provided on one surface.

  Next, as shown in FIG. 3, a support substrate 31 is attached to one surface of the semiconductor substrate 10 </ b> A, that is, the surface on the side where the first bump electrode 12 a is formed via an adhesive layer 30. For the adhesive layer 30, for example, an ultraviolet (UV) curable acrylic adhesive can be used, and the adhesive layer 30 is formed on the one surface of the silicon substrate 10a with a predetermined thickness (for example, about 20 μm). It has a sufficient thickness (for example, about 50 μm) to cover the first bump electrode 12a. As the support substrate 31, a transparent substrate such as glass having sufficient rigidity to support the semiconductor substrate 10 </ b> A can be used.

  Next, as shown in FIG. 4, the other surface of the semiconductor substrate 10A is ground (back grind) until the through electrode 13 is exposed. In this example, grinding is performed until the semiconductor substrate 10A has a thickness of about 50 μm. Thereafter, the second bump electrode 12b connected to the through electrode 13 via the wiring pattern is formed on the other surface of the thinned semiconductor substrate 10A.

  Next, as shown in FIG. 5, the plurality of memory chips 11 a to 11 d are stacked and mounted (flip mounting) for each portion to be the IF chip 10 on the surface of the semiconductor substrate 10 </ b> A.

  Specifically, the semiconductor substrate 10A is placed on an adsorption stage (not shown) with the support substrate 31 facing downward. Thus, the semiconductor substrate 10A is stably held on the suction stage while being sucked by the plurality of suction holes provided in the suction stage.

  From this state, the first-layer memory chip 11a is stacked and mounted (flip chip mounting) on the portion of the semiconductor substrate 10A that becomes the IF chip 10 by using a bonding tool (not shown).

  In this flip chip mounting, the first chip memory chip 11a is sucked and held by a suction hole provided in the bonding tool, and the bonding tool has a surface (one surface) on which the first bump electrode 12a is formed. Is held facing downward.

  In this bonding tool, the first bump electrode 12a and the second bump between the one surface of the memory chip 11a of the first layer and the other surface of the portion that becomes the IF chip 10 thereunder are opposed to each other. The memory chip 11a of the first layer is placed on the portion to be the IF chip 10 in a state where the position with the electrode 12b is aligned.

  In this state, the bonding tool applies a load and an ultrasonic wave while heating at a predetermined temperature (for example, about room temperature to about 150 ° C.), thereby ultrasonicating the first bump electrode 12a and the second bump electrode 12b. Bonding (flip chip bonding) is performed by thermocompression bonding.

  As a result, the first bump electrode 12a and the second bump electrode 12b are electrically connected (flip chip connection), and the first-layer memory chip 11a is flip-chip into the portion that becomes the IF chip 10. Implemented.

  From this state, the second layer memory chip 11b and the second layer memory chip 11a are formed on the first layer memory chip 11a by using the same method as that for flip-chip mounting the first layer memory chip 11a. A third-layer memory chip 11c is mounted on the third memory chip 11b, and a fourth-layer memory chip 11d is flip-chip mounted on the third-layer memory chip 11c in this order. And operation using such a bonding tool is repeated for every part used as the said IF chip 10 of 10 A of semiconductor substrates.

  Next, as shown in FIG. 6, a dispenser (not shown) is used in the gaps between the plurality of memory chips 11a to 11d stacked on the semiconductor substrate 10A. Fill with a liquid underfill material.

  At this time, the underfill material is filled while penetrating into the gaps by capillary action. In addition, the underfill material that protrudes from each gap to the periphery has a shape that gradually expands in the width direction from the upper layer side toward the lower layer side.

  From this state, the underfill material is heated (cured) at, for example, about 150 ° C. to cure the underfill material. As a result, the gaps between the plurality of memory chips 11 a to 11 d stacked on the portion of the semiconductor substrate 10 </ b> A that becomes the IF chip 10 are sealed by the first sealing body 4. And operation using such a dispenser is repeated for every part used as the said IF chip 10 of 10 A of semiconductor substrates.

  Next, as shown in FIG. 7, the other surface side of the semiconductor substrate 10A is covered with the second sealing body 5a so as to cover the plurality of memory chips 11a to 11d sealed with the first sealing body 4. Seal with mold resin. Specifically, a transfer mold apparatus (not shown) is used. This transfer mold apparatus forms a lower mold (fixed mold) that holds the other surface side of the semiconductor substrate 10A, and a cavity space that is filled with mold resin so as to face the other surface side of the semiconductor substrate 10A. A pair of molding dies including an upper die (movable die) that is moved relative to and away from the die is provided.

  Then, after setting the semiconductor substrate 10A in the molding die of this transfer mold apparatus, the mold resin heated and melted is injected into the cavity space in the molding die. For this mold resin, for example, a thermosetting resin such as an epoxy resin is used.

  In this state, the mold resin is heated (cured) at a predetermined temperature (for example, about 180 ° C.) to cure the mold resin. Furthermore, the mold resin is completely cured by baking at a predetermined temperature. Thus, the other surface side of the semiconductor substrate 10A is completely sealed with the mold resin that becomes the second sealing body 5a.

  In the present invention, as described above, after the plurality of memory chips 11a to 11d sealed with the first sealing body 4 are mounted on the semiconductor substrate 10A, the second sealing is performed on the semiconductor substrate 10A. The generation of voids (bubbles) can be reduced by collectively sealing with the mold resin that becomes the body 5a.

  Next, as shown in FIG. 8, after pasting the dicing tape 40 on the other surface side of the semiconductor substrate 10A sealed with the second sealing body 5a, ultraviolet rays are irradiated from the support substrate 31 side, The adhesive force of the adhesive layer 30 is reduced by the ultraviolet rays that pass through the support substrate 31. Then, the support substrate 31 is removed together with the adhesive layer 30 to expose one surface of the semiconductor substrate 10.

  Next, as shown in FIG. 9, the dicing blade 50 is used to cut the semiconductor substrate 10 </ b> A along with the second sealing body 5 a along the dicing line L from the side opposite to the dicing tape 40. Are divided into individual chip stacks 3A. Then, the chip laminated body 3A is peeled off from the dicing tape 40.

  Thereby, as shown in FIG. 10, the chip laminated body 3A sealed by the first and second sealing bodies 4 and 5a can be manufactured collectively. And this chip | tip laminated body 3A is accommodated in the storage tray (not shown), and is sent to the following process.

  Next, as shown in FIG. 11, a mother wiring board 2 </ b> A in which a plurality of portions to be the wiring board 2 are formed side by side is prepared. The mother wiring board 2A is made of, for example, a glass epoxy board, and a plurality of portions to be the wiring board 2 are formed in a matrix and finally cut along a dicing line (partition line) L. The portions to be the wiring boards 2 can be cut out as individual wiring boards 2.

  Then, a liquid adhesive member called NCP (Non Conductive Paste) is applied to one surface of the mother wiring board 2A for each mounting region 2a of the wiring board 2 using a dispenser (not shown). To do.

  Next, as shown in FIG. 12, using a bonding tool (not shown), the chip stack 3A sealed with the first and second sealing bodies 4 and 5a is formed on the mother wiring board 2A. Flip mounting is performed on the mounting area 2 a of the portion to be the wiring board 2.

  In this flip chip mounting, the chip stack 3A is held with the IF chip 10 facing downward while the chip stack 3A is sucked and held by the suction hole of the bonding tool.

  In this bonding tool, with one surface of the IF chip 10 and the mounting region 2a of the portion to be the wiring substrate 2 facing each other, the positions of the first bump electrode 12a and the pad electrode 7 between them are aligned, The chip stack 3 </ b> A sealed by the first and second sealing bodies 4 and 5 a is placed on the mounting region 2 a of the portion to be the wiring board 2. In this state, the first bump electrode 12a and the pad electrode 7 are bonded by thermocompression bonding (flip chip bonding) by applying a load while the bonding tool is heated. At the time of this joining, not only a load but also an ultrasonic wave may be applied.

  As a result, the first bump electrode 12a and the pad electrode 7 are electrically connected (flip chip connection), and the chip stack is sealed by the first and second sealing bodies 4 and 5a. 3A is flip-chip mounted on the mounting area 2a of the portion that becomes the wiring board 2 of the mother wiring board 2A.

  The adhesive member 14 is cured in a state of protruding from between one surface of the mother wiring board 2A and one surface of the IF chip 10. As a result, the chip laminated body 3A sealed by the first and second sealing bodies 4 and 5a is formed in the mounting region 2a of the portion to be the wiring board 2 of the mother wiring board 2A via the adhesive member 14. Bonded and fixed. And operation using such a bonding tool is repeated for every part used as the said wiring board 2 of the mother wiring board 2A.

  Next, as shown in FIG. 13, one surface side of the mother wiring board 2A is covered with the third sealing so as to cover the chip laminated body 3A sealed with the first and second sealing bodies 4 and 5a. Sealing is performed with a mold resin to be the body 5b. Specifically, a transfer mold apparatus (not shown) is used. The transfer mold apparatus forms a cavity mold filled with a mold resin facing a lower mold (fixed mold) holding the other surface side of the mother wiring board 2A and one surface side of the mother wiring board 2A, A pair of molding dies including an upper die (movable die) that is moved relatively to and away from the lower die is provided.

  Then, after setting the mother wiring board 2A on which the chip laminated body 3A sealed by the first and second sealing bodies 4 and 5a is mounted in the molding die of this transfer mold apparatus, the molding die The mold resin heated and melted is injected into the cavity space. For this mold resin, for example, a thermosetting resin such as an epoxy resin is used.

  In this state, the mold resin is heated (cured) at a predetermined temperature (for example, about 180 ° C.) to cure the mold resin. Furthermore, the mold resin is completely cured by baking at a predetermined temperature. As a result, the one surface side of the mother wiring board 2A is completely sealed with the mold resin that becomes the third sealing body 5b.

  In the present invention, as described above, after the chip laminated body 3A sealed with the first and second sealing bodies 4 and 5a is mounted on the mother wiring board 2A, the mother wiring board 2A is placed on the mother wiring board 2A. The generation of voids (bubbles) can be reduced by collectively sealing with a mold resin that becomes the third sealing body 5b.

  Next, as shown in FIG. 14, the solder balls 6 are arranged on the connection lands 8 provided on the portions to be the wiring boards 2 of the mother wiring board 2 </ b> A. Specifically, using a mounting tool (not shown), a plurality of solder balls 6 are attracted and held by the mounting tool, and a flux is transferred and formed on the plurality of solder balls 6. Solder balls 6 are placed on the connection lands 8 for each portion to be each wiring board 2. Then, after the solder balls 6 are placed on all the wiring boards 2 of the mother wiring board 2A, the mother wiring board 2A is reflowed. As a result, the solder balls 6 are arranged on the connection lands 8 of the portion of the mother wiring board 2 </ b> A that will be the wiring boards 2.

  Next, as shown in FIG. 15, after the dicing tape 60 is adhered to the third sealing body 5b side of the mother wiring board 2A, the mother wiring board 2A is attached using a dicing blade (not shown). It cut | disconnects along the dicing line L from the opposite side to the dicing tape 60 with the 3rd sealing body 5b, and divides | segments for every semiconductor package 1A. Then, by peeling off these semiconductor packages 1A from the dicing tape 60, the semiconductor packages 1A shown in FIG. 1 can be manufactured collectively.

  As described above, in the present invention, since the semiconductor substrate 10A can be stably sucked and held on the above-described suction stage, when a plurality of memory chips 11a to 11d are flip-mounted on the semiconductor substrate 10A using a bonding tool. In addition, the conventional thermocompression bonding at a high temperature (for example, about 300 ° C.) becomes unnecessary, and for example, joining by ultrasonic thermocompression bonding at room temperature to about 150 ° C. is possible.

  Therefore, according to the present invention, since the influence of heat on the memory chips 11a to 11d can be reduced, it is possible to manufacture a highly reliable semiconductor package 1A. Further, according to the present invention, since the semiconductor substrate 10A can be handled as it is until it is cut and divided into individual chip stacks 3A, the assembly process can be made more efficient. .

[Second Embodiment]
(Semiconductor device)
Next, a CoC type semiconductor package 1B shown in FIG. 16 will be described as a second embodiment. In the following description, parts equivalent to those of the semiconductor package 1A are denoted by the same reference numerals in the drawings.

  As shown in FIG. 16, the semiconductor package 1B includes a wiring board 2, a chip laminated body 3B mounted on one surface (upper surface) of the wiring board 2, and a first seal for sealing the chip laminated body 3B. A stop body 4, a second sealing body 5 that seals one surface of the wiring substrate 2 in a state of covering the first sealing body 4, and a plurality of members disposed on the other surface (lower surface) of the wiring substrate 2. The solder ball (external connection terminal) 6 has a package structure called BGA (Ball Grid Array).

  The wiring board 2 is made of a printed wiring board having a rectangular shape in plan view, and this printed wiring board forms a conductor pattern made of a conductive material such as Cu on the surface of an insulating base made of glass epoxy resin, for example. The surface is covered with an insulating film such as a solder resist. In this example, the wiring board 2 having a thickness of about 0.2 mm is used.

  A mounting region 2a on which the chip stack 3B is mounted is provided at the center of the upper surface of the wiring board 2. A plurality of pad electrodes (third connection terminals) 7 are provided side by side in the mounting region 2 a of the wiring board 2. On the other hand, a plurality of connection lands 8 are provided side by side on the other surface (lower surface) of the wiring board 2. The solder balls 6 are disposed on the connection lands 8. In addition, the wiring substrate 2 has a lead wiring portion 9 (typically shown in FIG. 1) such as a via (through electrode) and a wiring pattern for electrically connecting the pad electrode 7 and the connection land 8. Is provided). The surface of the wiring board 2 is covered with an insulating film (not shown) except for the portion where the pad electrode 7 and the connection land 8 are formed.

  In the chip stacked body 3B, an IF chip (first semiconductor chip) 10 and a plurality (four in this example) of memory chips (second semiconductor chips) 11a to 11d are stacked in order from the wiring board 2 side. Have a structure.

  The IF chip 10 is formed with an IF (InterFace) circuit or the like for taking an interface between the memory chips 11a to 11d and the wiring board 2, and has a rectangular shape in plan view. It has a shape smaller than 2. The IF chip 10 has a plurality of first bump electrodes (first connection terminals) 12a on one side, a plurality of second bump electrodes (second connection terminals) 12b on the other side, It has a plurality of through electrodes (TSV) 13 that connect between one bump electrode 12a and the second bump electrode 12b. Further, the first bump electrode 12 a and the through electrode 13 of the IF chip 10 have a wider interval (200 μm or more) than the second bump electrode 12 b in accordance with the interval with the pad electrode 7 of the wiring board 2. Yes. For this reason, in the IF chip 10, a wiring pattern (not shown) for rewiring is provided between the second bump electrode 12 b and the through electrode 13, and the distance from the pad electrode 7 of the wiring board 2. Adjustments are being made. In this example, the IF chip 10 having a thickness of about 50 μm is used.

  The memory chips 11a to 11d are formed with a DRAM (Dynamic Random Access Memory) circuit or the like, have a rectangular shape in plan view, and have a shape smaller than that of the IF chip 10. Each of the memory chips 11a to 11d has a plurality of first bump electrodes (first connection terminals) 12a on one side and a plurality of second bump electrodes (second connection terminals) 12b on the other side. And a plurality of through-electrodes (TSV) 13 that connect between the first bump electrode 12a and the second bump electrode 12b. In this example, memory chips 11a to 11d having a thickness of about 50 μm are used.

  Then, the IF chip 10 and the plurality of memory chips 11a to 11d are bonded to the first bump electrode 12a and the second bump electrode 12b, respectively, with one surface and the other surface facing each other. Thus, the chip stack 3B is configured.

  Further, the chip stack 3B has a first bump electrode between the IF chip 10 and the one surface (mounting region 2a) facing each other with the IF chip 10 facing downward. It is mounted on one surface of the wiring board 2 by bonding the 12a and the pad electrode 7 together. Further, the chip laminated body 3B is bonded and fixed to the mounting region 2a of the wiring board 2 via an insulating adhesive member 14 filled between one surface of the wiring board 2 and one surface of the IF chip 10. The chip laminate 3B is provided with a wire bump (joining member) on the pad electrode 7 of the wiring board 2, and by joining the first bump electrode 12a and the pad electrode 7 via the wire bump, It is also possible to mount on one surface of the wiring board 2.

  The first sealing body 4 seals the chip stack 3B with an underfill material filled in the gaps between the IF chip 10 and the memory chips 11a to 11d constituting the chip stack 3B.

  The second sealing body 5 completely seals one surface side of the wiring substrate 2 with a mold resin that covers the entire chip stack 3 </ b> B sealed with the first sealing body 4.

(Method for manufacturing semiconductor device)
Next, a manufacturing process of the semiconductor package 1B shown in FIG. 16 will be described as a manufacturing method of the semiconductor device to which the present invention is applied.
When manufacturing the semiconductor package 1B, first, a chip stacked body 3B in which a plurality of memory chips 11a to 11d are stacked on the IF chip 10 described above is manufactured.

  Specifically, first, as shown in FIG. 17, a semiconductor substrate 10 </ b> B provided with a plurality of portions to be the IF chip 10 is prepared. The semiconductor substrate 10B is made of a silicon base material 10a having a thickness larger than that of the IF chip 10, and a plurality of portions to be the IF chip 10 are formed side by side in a matrix and finally a dicing line (partition line) ) By cutting along L, the portion to be the IF chip 10 can be cut out as individual IF chips 10. Further, in the portion of the semiconductor substrate 10B that becomes the IF chip 10, a through electrode 13 in which a conductor such as Cu is embedded from the other surface of the silicon base material 10a to a middle part in the depth direction, and the silicon base material 10a A second bump electrode 12b is provided on the other surface and connected to the through electrode 13 via a wiring pattern (not shown).

  Next, as shown in FIG. 18, the plurality of memory chips 11 a to 11 d are stacked and mounted on the surface of the semiconductor substrate 10 </ b> B for each portion to be the IF chip 10 (flip mounting).

  Specifically, the semiconductor substrate 10B is placed on an adsorption stage (not shown) with the support substrate 31 side facing downward. Thereby, the semiconductor substrate 10B is stably held on the suction stage while being sucked by the plurality of suction holes provided in the suction stage.

  From this state, the first-layer memory chip 11a is stacked and mounted (flip chip mounting) on the portion to be the IF chip 10 on the semiconductor substrate 10B using a bonding tool (not shown).

  In this flip chip mounting, the first chip memory chip 11a is sucked and held by a suction hole provided in the bonding tool, and the bonding tool has a surface (one surface) on which the first bump electrode 12a is formed. Is held facing downward.

  In this bonding tool, the first bump electrode 12a and the second bump between the one surface of the memory chip 11a of the first layer and the other surface of the portion that becomes the IF chip 10 thereunder are opposed to each other. The memory chip 11a of the first layer is placed on the portion to be the IF chip 10 in a state where the position with the electrode 12b is aligned.

  In this state, the bonding tool applies a load and an ultrasonic wave while heating at a predetermined temperature (for example, about room temperature to about 150 ° C.), thereby ultrasonicating the first bump electrode 12a and the second bump electrode 12b. Bonding (flip chip bonding) is performed by thermocompression bonding.

  As a result, the first bump electrode 12a and the second bump electrode 12b are electrically connected (flip chip connection), and the first-layer memory chip 11a is flip-chip into the portion that becomes the IF chip 10. Implemented.

  From this state, the second layer memory chip 11b and the second layer memory chip 11a are formed on the first layer memory chip 11a by using the same method as that for flip-chip mounting the first layer memory chip 11a. A third-layer memory chip 11c is mounted on the third memory chip 11b, and a fourth-layer memory chip 11d is flip-chip mounted on the third-layer memory chip 11c in this order. And operation using such a bonding tool is repeated for every part used as the said IF chip 10 of the semiconductor substrate 10B.

  Next, as shown in FIG. 19, a dispenser (not shown) is used in each gap between the plurality of memory chips 11a to 11d stacked on the semiconductor substrate 10B. Fill with a liquid underfill material.

  At this time, the underfill material is filled while penetrating into the gaps by capillary action. In addition, the underfill material that protrudes from each gap to the periphery has a shape that gradually expands in the width direction from the upper layer side toward the lower layer side.

  From this state, the underfill material is heated (cured) at, for example, about 150 ° C. to cure the underfill material. As a result, the gaps between the plurality of memory chips 11 a to 11 d stacked on the portion to be the IF chip 10 of the semiconductor substrate 10 </ b> B are sealed by the first sealing body 4. And operation using such a dispenser is repeated for every part used as the said IF chip 10 of semiconductor substrate 10B.

  Next, as shown in FIG. 20, the silicon substrate 10a is formed along the dicing line L of the portion of the semiconductor substrate 10B that becomes the IF chip 10 by half-cut dicing using a dicing blade (not shown). A groove portion 10b is formed by cutting from the other surface to a midway portion in the depth direction.

  Next, as illustrated in FIG. 21, a support substrate 31 is attached to the other surface side of the semiconductor substrate 10 </ b> B via an adhesive layer 30. For example, an ultraviolet (UV) curable acrylic adhesive can be used for the adhesive layer 30, and the adhesive layer 30 has a predetermined thickness (for example, about 20 μm) on the other surface of the memory chip 11 d located at the uppermost layer. It has a sufficient thickness (for example, about 50 μm) to cover the second bump electrode 12b formed in step (b). As the support substrate 31, a transparent substrate such as glass having sufficient rigidity to support the semiconductor substrate 10B can be used.

  Next, as shown in FIG. 22, one surface of the semiconductor substrate 10B is ground (back grind) until the through electrode 13 is exposed. In this example, grinding is performed until the semiconductor substrate 10B has a thickness of about 50 μm. Thereafter, a first bump electrode 12a connected to the through electrode 13 via a wiring pattern is formed on the other surface of the thinned semiconductor substrate 10B.

  Then, after irradiating ultraviolet rays from the support substrate 31 side and reducing the adhesive force of the adhesive layer 30 by the ultraviolet rays transmitted through the support substrate 31, the support substrate 31 is removed together with the adhesive layer 30. Thereby, as shown in FIG. 23, the chip laminated body 3B sealed by the first sealing body 4 can be manufactured in a lump. And this chip | tip laminated body 3B is accommodated in the tray for accommodating (not shown), and is sent to the following process.

  Next, as shown in FIG. 24, a mother wiring board 2A in which a plurality of portions to be the wiring board 2 are formed side by side is prepared. The mother wiring board 2A is made of, for example, a glass epoxy board, and a plurality of portions to be the wiring board 2 are formed in a matrix and finally cut along a dicing line (partition line) L. The portions to be the wiring boards 2 can be cut out as individual wiring boards 2.

  Then, a liquid adhesive member called NCP (Non Conductive Paste) is applied to one surface of the mother wiring board 2A for each mounting region 2a of the wiring board 2 using a dispenser (not shown). To do.

  Next, as shown in FIG. 25, using a bonding tool (not shown), the chip stack 3B sealed by the first sealing body 4 is connected to the wiring board 2 of the mother wiring board 2A. Flip mounting is performed in the mounting region 2a of the part to be formed.

  In this flip chip mounting, the chip stack 3B is held with the IF chip 10 facing downward while the chip stack 3B is sucked and held by the suction hole of the bonding tool.

  In this bonding tool, with one surface of the IF chip 10 and the mounting region 2a of the portion to be the wiring substrate 2 facing each other, the positions of the first bump electrode 12a and the pad electrode 7 between them are aligned, The chip stacked body 3 </ b> B sealed by the first sealing body 4 is placed on the mounting region 2 a of the portion that becomes the wiring substrate 2. In this state, the first bump electrode 12a and the pad electrode 7 are bonded by thermocompression bonding (flip chip bonding) by applying a load while the bonding tool is heated. At the time of this joining, not only a load but also an ultrasonic wave may be applied.

  As a result, the first bump electrode 12a and the pad electrode 7 are electrically connected (flip chip connection), and the chip stack 3B sealed by the first sealing body 4 becomes the mother wiring board. Flip-chip mounting is performed on the mounting area 2a of the portion to be the wiring board 2 of 2A.

  The adhesive member 14 is cured in a state of protruding from between one surface of the mother wiring board 2A and one surface of the IF chip 10. Thereby, the chip laminated body 3B sealed by the first sealing body 4 is bonded and fixed to the mounting region 2a of the portion of the mother wiring board 2A that becomes the wiring board 2 through the adhesive member 14. And operation using such a bonding tool is repeated for every part used as the said wiring board 2 of the mother wiring board 2A.

  Next, as shown in FIG. 26, a mold in which one surface side of the mother wiring board 2 </ b> A becomes the second sealing body 5 so as to cover the chip stack 3 </ b> B sealed by the first sealing body 4. Seal with resin. Specifically, a transfer mold apparatus (not shown) is used. The transfer mold apparatus forms a cavity mold filled with a mold resin facing a lower mold (fixed mold) holding the other surface side of the mother wiring board 2A and one surface side of the mother wiring board 2A, A pair of molding dies including an upper die (movable die) that is moved relatively to and away from the lower die is provided.

  Then, after setting the mother wiring board 2A on which the chip laminated body 3B sealed by the first sealing body 4 is mounted in the molding die of the transfer mold apparatus, the inside of the cavity space in the molding die A mold resin melted by heating is poured into the container. For this mold resin, for example, a thermosetting resin such as an epoxy resin is used.

  In this state, the mold resin is heated (cured) at a predetermined temperature (for example, about 180 ° C.) to cure the mold resin. Furthermore, the mold resin is completely cured by baking at a predetermined temperature. As a result, the one surface side of the mother wiring board 2A is completely sealed with the mold resin that becomes the second sealing body 5.

  In the present invention, as described above, after the chip laminated body 3B sealed with the first sealing body 4 is mounted on the mother wiring board 2A, the second sealing body is formed on the mother wiring board 2A. The generation of voids (bubbles) can be reduced by collectively sealing with the mold resin 5.

  Next, as shown in FIG. 27, the solder balls 6 are arranged on the connection lands 8 provided on the portion of the mother wiring board 2A that becomes each wiring board 2. Specifically, using a mounting tool (not shown), a plurality of solder balls 6 are attracted and held by the mounting tool, and a flux is transferred and formed on the plurality of solder balls 6. Solder balls 6 are placed on the connection lands 8 for each portion to be each wiring board 2. Then, after the solder balls 6 are placed on all the wiring boards 2 of the mother wiring board 2A, the mother wiring board 2A is reflowed. As a result, the solder balls 6 are arranged on the connection lands 8 of the portion of the mother wiring board 2 </ b> A that will be the wiring boards 2.

  Next, as shown in FIG. 28, after the dicing tape 60 is attached to the second sealing body 5 side of the mother wiring board 2A, the mother wiring board 2A is attached using a dicing blade (not shown). It cut | disconnects along the dicing line L from the opposite side to the dicing tape 60 with the 2nd sealing body 5, and it divides | segments for every semiconductor package 1B. Then, by peeling off these semiconductor packages 1B from the dicing tape 60, the semiconductor packages 1B shown in FIG. 16 can be manufactured collectively.

  As described above, in the present invention, since the semiconductor substrate 10B can be stably sucked and held on the above-described suction stage, when a plurality of memory chips 11a to 11d are flip-mounted on the semiconductor substrate 10B using a bonding tool. In addition, the conventional thermocompression bonding at a high temperature (for example, about 300 ° C.) becomes unnecessary, and for example, joining by ultrasonic thermocompression bonding at room temperature to about 150 ° C. is possible.

  Therefore, according to the present invention, since the influence of heat on these memory chips 11a to 11d can be reduced, a highly reliable semiconductor package 1B can be manufactured. Further, according to the present invention, since the semiconductor substrate 10B can be handled as it is until it is cut and divided into individual chip stacks 3B, it is possible to improve the efficiency of the assembly process.

  In addition, according to the present invention, the semiconductor substrate 10B is divided between the groove portions 10b for each portion that becomes the IF chip 10 during grinding, so that the portion that becomes the IF chip 10 is suppressed while suppressing the occurrence of chip chipping or the like. It is possible to divide into individual chip stacks 3B. Furthermore, it is possible to reduce the process of sealing with a mold resin, compared with the case where the semiconductor package 1A shown in the first embodiment is manufactured.

(Semiconductor device)
Next, a CoC type semiconductor package 1C shown in FIG. 29 will be described as a third embodiment. In the following description, parts equivalent to those of the semiconductor packages 1A and 1B are denoted by the same reference numerals in the drawings.

  As shown in FIG. 29, the semiconductor package 1C includes a wiring board 2, a chip laminated body 3C mounted on one surface (upper surface) of the wiring board 2, and a first seal for sealing the chip laminated body 3C. A stop body 4, a second sealing body 5 that seals one surface of the wiring substrate 2 in a state of covering the first sealing body 4, and a plurality of members disposed on the other surface (lower surface) of the wiring substrate 2. The solder ball (external connection terminal) 6 has a package structure called BGA (Ball Grid Array).

  The wiring board 2 is made of a printed wiring board having a rectangular shape in plan view, and this printed wiring board forms a conductor pattern made of a conductive material such as Cu on the surface of an insulating base made of glass epoxy resin, for example. The surface is covered with an insulating film such as a solder resist. In this example, the wiring board 2 having a thickness of about 0.2 mm is used.

  A mounting region 2 a on which the chip stack 3 </ b> C is mounted is provided at the center of the upper surface of the wiring board 2. A plurality of pad electrodes (third connection terminals) 7 are provided side by side in the mounting region 2 a of the wiring board 2. On the other hand, a plurality of connection lands 8 are provided side by side on the other surface (lower surface) of the wiring board 2. The solder balls 6 are disposed on the connection lands 8. In addition, the wiring substrate 2 has a lead wiring portion 9 (typically shown in FIG. 1) such as a via (through electrode) and a wiring pattern for electrically connecting the pad electrode 7 and the connection land 8. Is provided). The surface of the wiring board 2 is covered with an insulating film (not shown) except for the portion where the pad electrode 7 and the connection land 8 are formed.

  The chip stack 3C includes an IF chip (third semiconductor chip) 11e, and a plurality (three in this example) of second memory chips (second semiconductor chips) 11c to 11a in order from the wiring board 2 side. The first memory chip (first semiconductor chip) 110 is sequentially stacked.

  The first and second memory chips 110, 11 a to 11 c are formed with DRAM (Dynamic Random Access Memory) circuits and the like. The first and second memory chips 110, 11 a to 11 c have a rectangular shape in plan view and a smaller shape than the wiring board 2. is doing. Among these, the first memory chip 110 has a plurality of second bump electrodes (second connection terminals) 12b on one surface side. On the other hand, each of the second memory chips 11a to 11c has a shape smaller than that of the first memory chip 110. Each of the second memory chips 11a to 11c has a plurality of first bump electrodes (first connection terminals) 12a on one surface side and the other surface side. And a plurality of second bump electrodes (second connection terminals) 12b, and a plurality of through-electrodes (TSV) 13 that connect the first bump electrodes 12a and the second bump electrodes 12b. ing. In this example, the first memory chip 110 having a thickness of 300 μm or more and the second memory chips 11a to 11c having a thickness of about 50 μm are used.

  The IF chip 11e is formed with an IF (InterFace) circuit for taking an interface between each of the memory chips 110, 11a to 11c and the wiring board 2, and has a rectangular shape in plan view. It has a smaller shape than the second memory chips 11a to 11c. The IF chip 11e includes a plurality of first bump electrodes (first connection terminals) 12a on one surface side, a plurality of second bump electrodes (second connection terminals) 12b on the other surface side, It has a plurality of through electrodes (TSV) 13 that connect between one bump electrode 12a and the second bump electrode 12b. Further, the second bump electrode 12b of the IF chip 11e has a wider interval (200 μm or more) than the first bump electrode 12a and the through electrode 13 in accordance with the interval with the pad electrode 7 of the wiring board 2. Yes. For this reason, in the IF chip 11e, a wiring pattern (not shown) for rewiring is provided between the second bump electrode 12b and the through electrode 13, and the distance from the pad electrode 7 of the wiring board 2 is set. Adjustments are being made. In this example, an IF chip 11e having a thickness of about 50 μm is used.

  The first memory chip 110, the second memory chips 11a to 11c, and the IF chip 11e are arranged such that the first bump electrode 12a and the second bump 12a between the first surface and the other surface are opposed to each other. The chip stacked body 3C is configured by bonding and stacking the bump electrodes 12b.

  Further, the chip stack 3C has the IF chip 11e facing downward, and the second bump located between the other surface of the IF chip 11e and one surface (mounting region 2a) of the wiring substrate 2 is opposed to each other. The electrode 12 b and the pad electrode 7 are bonded to each other so as to be mounted on one surface of the wiring board 2. Further, the chip laminated body 3C is bonded and fixed to the mounting region 2a of the wiring board 2 through an insulating adhesive member 14 filled between one surface of the wiring board 2 and the other surface of the IF chip 11e. . The chip stack 3C is provided with a wire bump (joining member) on the pad electrode 7 of the wiring board 2, and the second bump electrode 12b and the pad electrode 7 are joined via the wire bump. It is also possible to mount on one surface of the wiring board 2.

  The first sealing body 4 is formed of the chip stack 3C by an underfill material filled in the gaps between the first memory chip, the second memory chips 11a to 11c, and the IF chip 11e constituting the chip stack 3C. Is sealed.

  The second sealing body 5 completely seals one surface side of the wiring substrate 2 with a mold resin that covers the entire chip stacked body 3 </ b> C sealed with the first sealing body 4.

(Method for manufacturing semiconductor device)
Next, a manufacturing process of the semiconductor package 1C shown in FIG. 29 will be described as a manufacturing method of the semiconductor device to which the present invention is applied.
When manufacturing the semiconductor package 1C, first, a chip stacked body 3C in which a plurality of second memory chips 11a to 11c and IF chips 11e are stacked on the first memory chip 110 described above is manufactured.

  Specifically, first, as shown in FIG. 30, a semiconductor substrate 110A provided with a plurality of portions to be the first memory chip 110 is prepared. The semiconductor substrate 110A is made of a silicon base 110a having a thickness (300 μm or more) larger than those of the second memory chips 11a to 11c, and a plurality of portions to be the first memory chips 110 are arranged in a matrix. At the same time, by finally cutting along the dicing lines (partition lines) L, it becomes possible to cut out the portions to be the first memory chips 110 as the individual first memory chips 110. . In addition, a second bump electrode 12b is provided on the other surface of the silicon substrate 110a at a portion to be the first memory chip 110 of the semiconductor substrate 110A.

  Next, as shown in FIG. 31, the plurality of second memory chips 11a to 11c and IF chip 11e are stacked and mounted on the surface of the semiconductor substrate 110A for each portion to be the first memory chip 110 ( Flip mounting).

  Specifically, the semiconductor substrate 110A is placed on an adsorption stage (not shown) with one side facing downward. Thereby, the semiconductor substrate 110A is stably held on the suction stage while being sucked by the plurality of suction holes provided in the suction stage.

  From this state, the second memory chip 11a of the first layer is stacked and mounted on the part to be the first memory chip 110 on the semiconductor substrate 110A using a bonding tool (not shown) (flip chip mounting). )

  In this flip chip mounting, the second memory chip 11a is formed by the first bump electrode 12a while the second memory chip 11a of the first layer is sucked and held by the suction hole provided in the bonding tool. Hold the surface (one surface) facing downward.

  The bonding tool has a first bump electrode located between one surface of the second memory chip 11a in the first layer and the other surface of the portion that becomes the first memory chip 110 below the second memory chip 11a. The second memory chip 11a of the first layer is placed on the portion to be the first memory 110 in a state where the positions of the 12a and the second bump electrode 12b are aligned.

  In this state, the bonding tool applies a load and an ultrasonic wave while heating at a predetermined temperature (for example, about room temperature to about 150 ° C.), thereby ultrasonicating the first bump electrode 12a and the second bump electrode 12b. Bonding (flip chip bonding) is performed by thermocompression bonding.

  Thereby, the first bump electrode 12a and the second bump electrode 12b are electrically connected (flip chip connection), and the second memory chip 11a in the first layer is connected to the first memory chip 10. It is flip-chip mounted on the part.

  From this state, a second layer second memory chip 11a is formed on the first layer second memory chip 11a by using the same method as that for flip-chip mounting the first layer second memory chip 11a. The second memory chip 11b of the third layer, the second memory chip 11c of the third layer on the second memory chip 11b of the second layer, and the IF chip 11e on the second memory chip 11c of the third layer, Flip chip mounting in order. And operation using such a bonding tool is repeated for every part used as the 1st memory chip 110 of semiconductor substrate 110A.

  Next, as shown in FIG. 32, a dispenser (not shown) is used in each gap between the plurality of second memory chips 11a to 11c and IF chip 11e stacked on the semiconductor substrate 110A. 1 is filled with a liquid underfill material to be a sealing body 4.

  At this time, the underfill material is filled while penetrating into the gaps by capillary action. In addition, the underfill material that protrudes from each gap to the periphery has a shape that gradually expands in the width direction from the upper layer side toward the lower layer side.

  From this state, the underfill material is heated (cured) at, for example, about 150 ° C. to cure the underfill material. As a result, the gaps between the plurality of second memory chips 11a to 11c and the IF chip stacked on the portion to be the first memory chip 110 of the semiconductor substrate 110A are sealed by the first sealing body 4. The The operation using such a dispenser is repeated for each portion of the semiconductor substrate 110A that becomes the first memory chip 110.

  Next, as shown in FIG. 33, after the dicing tape 40 is attached to the other side of the semiconductor substrate 110A, the semiconductor substrate 110A is opposite to the dicing tape 40 using a dicing blade (not shown). Cut along the dicing line L from the side to divide the portion to be the first memory chip 110 into individual chip stacks 3C.

  Then, by peeling off the chip laminated body 3C from the dicing tape 40, the chip laminated body 3C sealed by the first sealing body 4 can be manufactured in a lump. And this chip | tip laminated body 3C is accommodated in the tray for accommodating (not shown), and is sent to the following process.

  Next, as shown in FIG. 34, a mother wiring board 2A in which a plurality of portions to be the wiring board 2 are formed side by side is prepared. The mother wiring board 2A is made of, for example, a glass epoxy board, and a plurality of portions to be the wiring board 2 are formed in a matrix and finally cut along a dicing line (partition line) L. The portions to be the wiring boards 2 can be cut out as individual wiring boards 2.

  Then, a liquid adhesive member called NCP (Non Conductive Paste) is applied to one surface of the mother wiring board 2A for each mounting region 2a of the wiring board 2 using a dispenser (not shown). To do.

  Next, as shown in FIG. 35, using a bonding tool (not shown), the chip stack 3C sealed by the first sealing body 4 is connected to the wiring board 2 of the mother wiring board 2A. Flip mounting is performed in the mounting region 2a of the part to be formed.

  In this flip chip mounting, the chip stack 3C is held with the IF chip 11e facing downward while the chip stack 3C is sucked and held by the suction hole of the bonding tool.

  In this bonding tool, the other surface of the IF chip 11e and the mounting region 2a of the portion to be the wiring substrate 2 are opposed to each other, and the position of the second bump electrode 12b and the pad electrode 7 between them is aligned. Then, the chip stacked body 3 </ b> C sealed by the first sealing body 4 is placed on the mounting region 2 a of the portion to be the wiring substrate 2. In this state, the bonding tool applies a load while heating, whereby the second bump electrode 12b and the pad electrode 7 are joined by thermocompression bonding (flip chip bonding). At the time of this joining, not only a load but also an ultrasonic wave may be applied.

  As a result, the second bump electrode 12b and the pad electrode 7 are electrically connected (flip chip connection), and the chip stack 3C sealed by the first sealing body 4 becomes the mother wiring board. Flip-chip mounting is performed on the mounting area 2a of the portion to be the wiring board 2 of 2A.

  The adhesive member 14 is cured in a state of protruding from between one surface of the mother wiring board 2A and one surface of the IF chip 11e. As a result, the chip laminated body 3C sealed by the first sealing body 4 is bonded and fixed to the mounting region 2a of the portion of the mother wiring board 2A that becomes the wiring board 2 via the adhesive member 14. And operation using such a bonding tool is repeated for every part used as the said wiring board 2 of the mother wiring board 2A.

  Next, as shown in FIG. 36, a mold in which one surface side of the mother wiring board 2 </ b> A becomes the second sealing body 5 so as to cover the chip stacked body 3 </ b> C sealed by the first sealing body 4. Seal with resin. Specifically, a transfer mold apparatus (not shown) is used. The transfer mold apparatus forms a cavity mold filled with a mold resin facing a lower mold (fixed mold) holding the other surface side of the mother wiring board 2A and one surface side of the mother wiring board 2A, A pair of molding dies including an upper die (movable die) that is moved relatively to and away from the lower die is provided.

  Then, after setting the mother wiring board 2A on which the chip laminated body 3C sealed by the first sealing body 4 is mounted in the molding die of the transfer mold apparatus, the inside of the cavity space in the molding die A mold resin melted by heating is poured into the container. For this mold resin, for example, a thermosetting resin such as an epoxy resin is used.

  In this state, the mold resin is heated (cured) at a predetermined temperature (for example, about 180 ° C.) to cure the mold resin. Furthermore, the mold resin is completely cured by baking at a predetermined temperature. As a result, the one surface side of the mother wiring board 2A is completely sealed with the mold resin that becomes the second sealing body 5.

  In the present invention, as described above, after the chip stack 3C sealed with the first sealing body 4 is mounted on the mother wiring board 2A, the second sealing body is formed on the mother wiring board 2A. The generation of voids (bubbles) can be reduced by collectively sealing with the mold resin 5.

  Next, as shown in FIG. 37, the solder balls 6 are arranged on the connection lands 8 provided on the portion of the mother wiring board 2A that becomes each wiring board 2. Specifically, using a mounting tool (not shown), a plurality of solder balls 6 are attracted and held by the mounting tool, and a flux is transferred and formed on the plurality of solder balls 6. Solder balls 6 are placed on the connection lands 8 for each portion to be each wiring board 2. Then, after the solder balls 6 are placed on all the wiring boards 2 of the mother wiring board 2A, the mother wiring board 2A is reflowed. As a result, the solder balls 6 are arranged on the connection lands 8 of the portion of the mother wiring board 2 </ b> A that will be the wiring boards 2.

  Next, as shown in FIG. 38, after the dicing tape 60 is attached to the second sealing body 5 side of the mother wiring board 2A, the mother wiring board 2A is attached using a dicing blade (not shown). It cut | disconnects along the dicing line L from the opposite side to the dicing tape 60 with the 2nd sealing body 5, and it divides | segments for every semiconductor package 1C. Then, by peeling off these semiconductor packages 1C from the dicing tape 60, the semiconductor packages 1C shown in FIG. 16 can be manufactured collectively.

  As described above, in the present invention, since the semiconductor substrate 110A can be stably sucked and held on the above-described suction stage, a plurality of second memory chips 11a to 11c and IF are used on the semiconductor substrate 110A using a bonding tool. When flip-mounting the chip 11e, conventional thermocompression bonding at a high temperature (for example, about 300 ° C.) becomes unnecessary, and for example, joining by ultrasonic thermocompression bonding at room temperature to about 150 ° C. is possible.

  Therefore, according to the present invention, since the influence of heat on the second memory chips 11a to 11c and the IF chip 11e can be reduced, a highly reliable semiconductor package 1C can be manufactured. In addition, according to the present invention, since the semiconductor substrate 110A can be handled as it is until it is cut and divided into individual chip stacks 3C, the assembly process can be made more efficient. .

  Further, according to the present invention, the semiconductor substrate 110A can be handled without using the support substrate 31 described above. Furthermore, the process of sealing with a mold resin can be reduced as compared with the case where the semiconductor package 1A shown in the first embodiment is manufactured.

  Further, according to the present invention, since the IF chip 11e can be reduced in size, the connection area between the wiring board 2 and the chip laminated body 3C having different coefficients of thermal expansion is reduced, and the wiring board 2 and the chip laminated body 3C can be reduced. It is possible to reduce the thermal stress applied to the connection portion.

  Furthermore, in the chip stacked body 3C, the first memory chip 110 having a thickness larger than that of the second memory chips 11a to 11c is arranged in the uppermost layer, so that the second memory chips 11a to 11c are heated by heating after mounting. Even when the through electrode 13 that penetrates the 11c and the IF chip 11e in the thickness direction thermally expands, the first memory in which the through electrode 13 is not formed with stress applied to the second memory chips 11a to 11c and the IF chip 11e. Chip 110 will receive. Therefore, it is possible to reduce the stress applied to each chip 110, 11a to 11c, 11e of this chip laminated body 3C, and to suppress the occurrence of cracks or the like in these chips 110, 11a to 11c, 11e.

In addition, this invention is not necessarily limited to the thing of the said embodiment, A various change can be added in the range which does not deviate from the meaning of this invention.
For example, the present invention is not necessarily limited to the configuration of the above-described five-layered chip stack 3 </ b> A to 3 </ b> C, and may be four or less or six or more. Further, the arrangement and number of the first bump electrodes 12a, the through electrodes 13 and the second bump electrodes 12b are not limited to the configuration of the chip stacked bodies 3A to 3C, and can be changed as appropriate. .

  The present invention is not limited to the BGA type semiconductor packages 1A to 1C, and can be applied to, for example, a semiconductor package such as an LGA (Land Grid Array) type and a CSP (Chip Size Package) type.

  DESCRIPTION OF SYMBOLS 1A, 1B, 1C ... Semiconductor package (semiconductor device) 2A ... Mother wiring board 2 ... Wiring board 2a ... Mounting area | region 3A, 3B, 3C ... Chip laminated body 4 ... 1st sealing body 5a, 5 ... 2nd sealing Stop body 5b ... Third sealing body 6 ... Solder ball (external connection terminal) 7 ... Pad electrode (third connection terminal) 8 ... Connection land 9 ... Lead-out wiring section 10A, 10B, 110A ... Semiconductor substrate 10 ... IF chip (first semiconductor chip) 10a ... silicon substrate 10b ... groove 110 ... first memory chip (first semiconductor chip) 110A ... semiconductor substrate 110a ... silicon substrate 11a-11d ... memory chip (second Semiconductor chip) 11e ... IF chip (third semiconductor chip) 12a ... First bump electrode (first connection terminal) 12b ... Second bump electrode (second contact) Terminal) 13 ... through electrodes 14 ... bonding member

Claims (13)

A step of laminating a plurality of semiconductor chips for each portion to be a semiconductor chip on a surface of a semiconductor substrate formed with a plurality of portions to be semiconductor chips;
Sealing the plurality of semiconductor chips with the first sealing body while filling the gaps between the semiconductor substrate and the plurality of semiconductor chips with the first sealing body;
And a step of dividing the previous semiconductor substrate into individual chip stacks for each portion to be the semiconductor chip. A through electrode embedded from one surface of the base material to a midway portion in the depth direction and a first connection terminal located on the one surface of the base material and connected to the through electrode serve as the semiconductor chip. Preparing a semiconductor substrate provided for each part;
A step of attaching a support substrate to one surface of the semiconductor substrate via an adhesive layer;
Grinding the other surface of the semiconductor substrate until the through electrode is exposed;
The method of manufacturing a semiconductor device according to claim 1, further comprising: forming a second connection terminal connected to the through electrode on the other surface of the semiconductor substrate.   For each portion of the semiconductor substrate that becomes the semiconductor chip, a through electrode penetrating the base material, a first connection terminal connected to the through electrode on one surface of the base material, and the other surface of the base material on the other surface A semiconductor chip having a second connection terminal connected to the through electrode is arranged such that the first connection terminal and the second connection terminal between the semiconductor chip and the other connection surface are opposed to each other. The method for manufacturing a semiconductor device according to claim 2, wherein the layers are bonded and stacked.   4. The method of sealing the other surface side of the semiconductor substrate with a second sealing body so as to cover the entire chip stack sealed with the first sealing body. The manufacturing method of the semiconductor device as described in any one of. Mounting a chip laminated body sealed with the first and second sealing bodies on one surface of the mother wiring board formed with a plurality of parts to be the wiring boards for each part to be the wiring boards; ,
Sealing one surface side of the mother wiring board with a third sealing body so as to cover the whole chip stack sealed with the first and second sealing bodies;
5. The method of manufacturing a semiconductor device according to claim 4, further comprising a step of dividing the mother wiring board into individual semiconductor devices by cutting each portion to be the wiring board. The through-hole electrode embedded from the other surface of the base material to the middle in the depth direction, and the second connection terminal located on the other surface of the base material and connected to the through-electrode, the semiconductor chip A step of preparing a semiconductor substrate provided for each portion to be,
For each portion of the semiconductor substrate that becomes the semiconductor chip, a through electrode penetrating the base material, a first connection terminal connected to the through electrode on one surface of the base material, and the other surface of the base material on the other surface A semiconductor chip having a second connection terminal connected to the through electrode is arranged such that the first connection terminal and the second connection terminal between the semiconductor chip and the other connection surface are opposed to each other. Joining and laminating;
A step of forming a groove part cut out from the other surface of the base material along a parting line in a depth direction along a parting line of a part to be the semiconductor chip of the semiconductor substrate;
A step of attaching a support substrate to the other surface side of the semiconductor substrate via an adhesive layer;
Grinding one surface of the semiconductor substrate until the through electrode is exposed;
Forming a first connection terminal connected to the through electrode on one surface of the semiconductor substrate,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the front semiconductor substrate is divided into portions to be the semiconductor chips between the groove portions during the grinding. 3. Mounting a chip stack sealed with the first sealing body on each surface to be the wiring board on one surface of a mother wiring board in which a plurality of parts to be wiring boards are formed side by side;
Sealing one surface side of the mother wiring substrate with a second sealing body so as to cover the entire chip stack sealed with the first sealing body;
7. The method of manufacturing a semiconductor device according to claim 6, further comprising a step of dividing the mother wiring board into individual semiconductor devices by cutting each portion to be the wiring board.   The step of mounting the chip stack on the mother wiring board includes preparing a mother wiring board provided with a third connection terminal at a portion to be the wiring board, and for each portion of the mother wiring board to be the wiring board. In the state where the semiconductor chip located in the lowermost layer of the chip stack is directed downward, the third connecting terminal between the one surface of the semiconductor chip and the portion serving as the wiring board are opposed to each other. The method of manufacturing a semiconductor device according to claim 5, wherein the method is performed by bonding the first connection terminal. A step of preparing a semiconductor substrate in which the second connection terminal located on the other surface of the base material is provided for each portion to be the semiconductor chip;
For each portion of the semiconductor substrate that becomes the semiconductor chip, a through electrode penetrating the base material, a first connection terminal connected to the through electrode on one surface of the base material, and the other surface of the base material on the other surface A semiconductor chip having a second connection terminal connected to the through electrode is arranged such that the first connection terminal and the second connection terminal between the semiconductor chip and the other connection surface are opposed to each other. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of bonding and stacking. Mounting a chip stack sealed with the first sealing body on each surface to be the wiring board on one surface of a mother wiring board in which a plurality of parts to be wiring boards are formed side by side;
Sealing one surface side of the mother wiring substrate with a second sealing body so as to cover the entire chip stack sealed with the first sealing body;
The method for manufacturing a semiconductor device according to claim 9, further comprising a step of dividing the mother wiring board into individual semiconductor devices by cutting each portion to be the wiring board.   The step of mounting the chip stack on the mother wiring board includes preparing a mother wiring board provided with a third connection terminal at a portion to be the wiring board, and for each portion of the mother wiring board to be the wiring board. In the state where the semiconductor chip located in the uppermost layer of the chip stack is directed downward, the second connection terminal located between the other surface of the semiconductor chip and the portion serving as the wiring board is opposed to each other. The method for manufacturing a semiconductor device according to claim 10, wherein the method is performed by bonding the third connection terminal and the third connection terminal.   When the chip stack is mounted for each portion to be the wiring substrate, an adhesive member is provided between the chip stack and the portion to be the wiring substrate, and the chip stack is attached via the adhesive member. The method for manufacturing a semiconductor device according to claim 8, wherein the semiconductor device is bonded and fixed to a portion to be a wiring board.   12. The method of manufacturing a semiconductor device according to claim 8, further comprising a step of arranging an external connection terminal for each portion to be the wiring board on the other surface side of the mother wiring board.

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