JP2012199604A - Counter circuit and semiconductor integrated circuit incorporating the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a counter circuit that precisely counts pulses included in an input signal during a measurement period.SOLUTION: The counter circuit includes: a first counter for counting pulses of an input signal during a set measurement period to output a measured count value; a second counter for counting pulses of a reference clock signal from the count of the first pulse of the input signal in the measurement period by the first counter to the end of the measurement period to output a time count value; and a data conversion circuit for computing a composite count value including integral and decimal parts of a pulse number in the input signal from the count of the first pulse of the input signal in the measurement period by the first counter to the end of the measurement period on the basis of the measured count value output from the first counter in the measurement period and the time count value output from the second counter.

Description

  The present invention relates to a counter circuit used for counting the number of pulses of an input signal in a set measurement period, and further relates to a semiconductor integrated circuit incorporating such a counter circuit.

  For example, in a temperature measurement circuit that uses a thermistor as a sensor element, an oscillation signal is generated by an oscillation circuit (resistance frequency conversion circuit) that oscillates according to the time constant of the thermistor and capacitor, and a pulse of the oscillation signal is generated during a set measurement period. The number is counted by a counter circuit to obtain a count value, and temperature data is acquired based on the count value.

  Here, in order to acquire high-accuracy temperature data, it is conceivable to increase the count value by extending the measurement period, but in that case, the sampling time becomes longer or the power consumption increases. The harmful effect of doing. On the other hand, it is conceivable to increase the oscillation frequency of the oscillation circuit by reducing the time constants of the thermistor and the capacitor. However, in this case, there is a disadvantage that the power consumption increases.

As a related technique, Patent Document 1 discloses a temperature measurement device that detects a change in the resistance value of a resistance temperature detector by a change in the oscillation frequency of an oscillator. This temperature measuring device is selectively connected to a reference resistor whose resistance value hardly changes due to temperature change, a resistance temperature detector whose resistance value changes due to temperature change, and this temperature measuring resistor or reference resistor. An oscillator that oscillates at a frequency proportional to or inversely proportional to the resistance value, a time measuring means for measuring a certain number of pulses in a pulse train corresponding to the oscillation frequency of the oscillator, and a reference resistance or temperature measurement Using the time (M1, M2) measured by the time measuring means when the resistor is connected, T = T ₀ + (1 / α) · (M1−M2) / M1 (where T is the resistance temperature detector) And a means for calculating a temperature detected by the resistance temperature detector or a value correlated therewith.

JP 62-52249 A (first page, FIG. 1)

  In FIG. 1 of Patent Document 1, it is included in the output pulse train of the reference oscillator 11 while a predetermined number of pulses are output from the unstable multi 12 that oscillates at a frequency depending on the resistance value of the resistance temperature detector. The number of pulses that are present is counted. However, there is no particular disclosure regarding accurately counting the number of pulses output from the unstable multi 12.

  A counter circuit according to one aspect of the present invention includes a first counter that counts pulses of an input signal and outputs a measurement count value in a set measurement period, and a reference clock signal having a higher frequency than the input signal A second counter that counts the pulses of the reference clock signal and outputs a time count value until the measurement period ends after the first counter counts the first pulse of the input signal in the measurement period; Based on the measurement count value output from the first counter and the time count value output from the second counter in the measurement period, measurement is performed after the first counter counts the first pulse of the input signal in the measurement period. A composite card that includes an integer part and a fractional part of the number of pulses of the input signal until the period ends. And a data conversion circuit for obtaining a cement value.

  According to the counter circuit of one aspect of the present invention, the measurement count value output from the first counter that counts the pulses of the input signal and the second counter that counts the pulses of the reference clock signal are output. Based on the time count value, a composite count value including an integer part and a part less than an integer part of the number of pulses of the input signal is obtained, so that the number of pulses included in the input signal in the measurement period can be obtained with high accuracy.

Here, the final value of the measurement count value in the measurement period is N (N is an integer of 2 or more), the time count value when the measurement count value is (N-2) is TC _N-2 , and the measurement count When the time count value when the value becomes (N-1) is TC _N-1, and the final value of the time count value in the measurement period is LM, the data conversion circuit (LM-TC _N-1 ) / (TC _N-1 -TC _N-2 ), the less than integer part of the composite count value may be obtained.

  The semiconductor integrated circuit according to the first aspect of the present invention is an oscillation circuit that generates an oscillation signal by oscillating at a frequency related to a time constant between a resistance value of a connected resistor or thermistor and a capacitance value of a capacitor. And a counter circuit according to any of the aspects of the present invention for inputting an oscillation signal generated by the oscillation circuit, wherein the data conversion circuit counts the first pulse of the oscillation signal in the measurement period. A composite count value including an integer part and a part less than an integer part of the number of pulses of the oscillation signal after the measurement period ends is obtained, and a temperature corresponding to the composite count value is obtained.

  Here, the counter circuit controls the oscillation circuit to oscillate using the reference resistor in the first measurement period, and thereafter oscillates using the thermistor in the second measurement period. And a storage circuit that stores a time count value when the measurement count value becomes equal to a predetermined value in the first measurement period as a set count value that defines the end of the measurement period. The data conversion circuit may obtain the composite count value based on the measurement count value output from the first counter and the time count value output from the second counter in the second measurement period.

  Furthermore, a semiconductor integrated circuit according to a second aspect of the present invention includes a resistor formed in an N well of a semiconductor substrate and a capacitor formed in the semiconductor substrate, and includes a resistance value of the resistor and a capacitance value of the capacitor. An oscillation circuit that oscillates at a frequency related to a time constant to generate an oscillation signal; and a counter circuit according to any one aspect of the present invention that inputs an oscillation signal generated by the oscillation circuit. 1 counter obtains a composite count value including an integer part and a part less than an integer of the number of pulses of the oscillation signal from the time when the first pulse of the oscillation signal is counted in the measurement period to the end of the measurement period; Find the temperature corresponding to.

  The semiconductor integrated circuit according to the first or second aspect of the present invention further includes a lookup table that stores temperature data representing a plurality of reference temperatures and count value data representing a plurality of reference count values correspondingly. The data conversion circuit may refer to the lookup table based on the composite count value or an integer part thereof, and obtain a temperature corresponding to the composite count value based on the temperature data read from the lookup table. .

  In that case, the data conversion circuit includes the first count value data representing the first reference count value closest to the composite count value or the integer part thereof, and the first temperature data corresponding thereto, the composite count value or The second count value data representing the second reference count value that is second closest to the integer part and the second temperature data corresponding to the second reference count value are read from the lookup table, and the composite count value and the first and first count data are read. The temperature corresponding to the composite count value is obtained by interpolating the first and second reference temperatures represented by the first and second temperature data based on the relationship with the reference count value of 2, respectively. May be.

  According to the semiconductor integrated circuit of the first or second aspect of the present invention, the temperature is obtained based on the composite count value including the integer part and the integer part of the number of pulses of the oscillation signal. Even when the frequency becomes low, temperature measurement with high accuracy can be performed. Or it becomes possible to shorten the measurement time for obtaining effective accuracy in temperature measurement. As the measurement time is shortened, the energy consumed for one temperature measurement is also reduced.

The figure of the 1st structural example of the temperature measurement circuit using the counter circuit which concerns on this embodiment. The figure for demonstrating the specific operation example of the temperature measurement circuit shown in FIG. The figure of the 2nd example of composition of the temperature measurement circuit using the counter circuit concerning this embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same referential mark is attached | subjected to the same component and description is abbreviate | omitted.
FIG. 1 is a block diagram showing a first configuration example of a temperature measurement circuit using a counter circuit according to an embodiment of the present invention. This temperature measurement circuit includes a reference clock signal generation circuit 10, a reference resistor REF, a thermistor QTM, a capacitor CSH, a frequency divider circuit 20, an oscillation circuit 30, a counter circuit 40, and a temperature data LUT (lookup). Table) 60. The temperature data LUT 60 is realized by a nonvolatile memory such as a ROM.

  In the first configuration example, the frequency dividing circuit 20 to the temperature data LUT 60 are included in the semiconductor integrated circuit (IC) 100 among these components. Alternatively, the temperature data LUT is realized by an EEPROM (electrically writable and erasable read-only memory) 70 attached to the semiconductor integrated circuit 100 in place of the temperature data LUT 60 built in the semiconductor integrated circuit 100. It may be. In such a case, the temperature data LUT can be created in response to the temperature characteristics of various resistors.

  The reference clock signal generation circuit 10 generates a reference clock signal CK1 having a frequency within a range of 10 MHz to 30 MHz using, for example, a crystal resonator. The frequency dividing circuit 20 divides the reference clock signal CK1 generated by the reference clock signal generating circuit 10 by a predetermined frequency dividing ratio, thereby outputting a reference clock signal CK2 having a frequency of 2 MHz, for example. The reference clock signal CK2 has a sufficiently higher frequency than the oscillation signal OS generated by the oscillation circuit 30.

  The oscillation circuit 30 includes NAND circuits 31 and 32, P channel MOS transistors 33 and 34, a Schmitt trigger circuit 35, and an N channel MOS transistor 36, and an external reference resistor REF or thermistor QTM and a capacitor. Oscillates when the CSH is connected to generate an oscillation signal. The reference resistance REF is, for example, a metal film resistance, and the electric resistance value hardly changes with a temperature change. On the other hand, the thermistor QTM is a resistor having a large change in electric resistance value with respect to a change in temperature. The capacitor CSH may be built in the semiconductor integrated circuit 100.

An oscillation control signal OC1 is applied to one input terminal (non-inverting input terminal) of the NAND circuit 31. The output terminal of the NAND circuit 31 is connected to the gate of the transistor 33. The source of the transistor 33 is connected to the power supply potential V _DD, and the drain of the transistor 33 is connected to one end of the reference resistor REF. The other end of the reference resistor REF is connected to one end of the capacitor CSH and the input terminal of the Schmitt trigger circuit 35.

The oscillation control signal OC2 is applied to one input terminal (non-inverting input terminal) of the NAND circuit 32. The output terminal of the NAND circuit 32 is connected to the gate of the transistor 34. The source of the transistor 34 is connected to the power supply potential V _DD, and the drain of the transistor 34 is connected to one end of the thermistor QTM. The other end of the thermistor QTM is connected to one end of the capacitor CSH and an input terminal of the Schmitt trigger circuit 35.

The other end of the capacitor CSH is connected to the power supply potential V _SS (V _SS <V _DD ). The output terminal of the Schmitt trigger circuit 35 is connected to the other input terminal (inverted input terminal) of the NAND circuits 31 and 32 and the gate of the transistor 36. The drain of the transistor 36 is connected to an input terminal of the Schmitt trigger circuit 35, the source of the transistor 36 is connected to the power supply potential V _SS.

  When the oscillation control signal OC1 is activated to a high level and the oscillation control signal OC2 is deactivated to a low level, the high-level oscillation control signal OC1 is applied to the non-inverting input terminal of the NAND circuit 31. The output signal of the NAND circuit 31 is inverted by the transistor 33 and applied to the input terminal of the capacitor CSH and the Schmitt trigger circuit 35 via the reference resistor REF. The output signal of the Schmitt trigger circuit 35 is applied to the inverting input terminal of the NAND circuit 31. Thereby, a CR type oscillation circuit is formed. The oscillation frequency of the oscillation circuit is determined in relation to the time constant between the resistance value of the reference resistor REF and the capacitance value of the capacitor CSH. Since the low-level oscillation control signal OC2 is applied to one input terminal (non-inverting input terminal) of the NAND circuit 32, the output of the NAND circuit 32 is fixed to the high level, and the transistor 34 maintains the off state.

  On the other hand, when the oscillation control signal OC2 is activated to a high level and the oscillation control signal OC1 is deactivated to a low level, the high-level oscillation control signal OC2 is applied to the non-inverting input terminal of the NAND circuit 32. The output signal of the NAND circuit 32 is inverted by the transistor 34 and applied to the input terminal of the capacitor CSH and the Schmitt trigger circuit 35 through the thermistor QTM. The output signal of the Schmitt trigger circuit 35 is applied to the inverting input terminal of the NAND circuit 32. Thereby, a CR type oscillation circuit is formed. The oscillation frequency of the oscillation circuit is determined in relation to the time constant between the resistance value of the thermistor QTM and the capacitance value of the capacitor CSH. Since the low level oscillation control signal OC1 is applied to the non-inverting input terminal of the NAND circuit 31, the output of the NAND circuit 31 is fixed to the high level, and the transistor 33 maintains the off state.

  The counter circuit 40 includes a time base counter 41, a count value register 42, sampling buffers 43 and 44, a delay circuit 45, a gate signal generation circuit 46, an AND circuit 47, a delay circuit 48, and a control circuit 50. , A major counter 51, a count value register 52, a count value buffer 53, and a data conversion circuit 54.

  The time base counter 41 is supplied with the reference clock signal CK2 divided by the frequency dividing circuit 20. The time base counter 41 starts a count operation under the control of the control circuit 50, counts the pulses of the reference clock signal CK2, and outputs a time count value TC. The count value register 42 is a storage circuit constituted by, for example, a plurality of D flip-flops, and stores a set count value LM that defines the end of the measurement period. Each of the sampling buffers 43 and 44 is constituted by, for example, a plurality of D flip-flops, and sequentially stores the time count value TC in synchronization with the oscillation signal OS delayed by a predetermined time by the delay circuit 45.

  When the control circuit 50 activates the count control signal CC1 to high level when the measurement period starts, the gate signal generation circuit 46 activates the gate signal GS to high level. Thereafter, when the time count value TC becomes equal to the set count value LM, the time base counter 41 activates the count control signal CC3 to a high level and ends the count operation. The gate signal generation circuit 46 deactivates the gate signal GS to a low level when the count control signal CC3 is activated to a high level.

  The AND circuit 47 obtains the logical product of the gate signal GS generated by the gate signal generation circuit 46 and the oscillation signal OS, so that the oscillation signal OS is obtained during the measurement period in which the gate signal GS is activated to a high level. Is output. The measure counter 51 counts the pulses of the oscillation signal OS output from the AND circuit 47 during the measurement period, and outputs a measurement count value MC.

  The count value register 52 is composed of, for example, a plurality of D flip-flops, and stores the target count value of the pulse of the oscillation signal OS. The count value buffer 53 is composed of, for example, a plurality of D flip-flops, and sequentially stores the measurement count value MC in synchronization with the oscillation signal OS delayed by a predetermined time by the delay circuit 48.

  Based on the measurement count value MC output from the major counter 51 and the time count value TC output from the time base counter 41 during the measurement period, the data conversion circuit 54 detects the first oscillation signal OS in the measurement period. A composite count value including an integer part and a part less than an integer of the number of pulses of the oscillation signal OS from when the pulse is counted until the measurement period ends is obtained.

  Here, the first operation example of the temperature measurement circuit shown in FIG. 1 will be described in detail. In the first operation example, the temperature around the thermistor QTM is measured based on the count value of the pulse of the oscillation signal that the oscillation circuit 30 oscillates and outputs using the thermistor QTM. Note that the reference resistor REF is not used.

  First, when the control circuit 50 activates the oscillation control signal OC1 to a high level, the oscillation circuit 30 starts an oscillation operation. Further, the control circuit 50 initializes each part of the counter circuit 40, so that the operations of the major counter 51 and the time base counter 41, the count values, and the like are reset. In initialization, the control circuit 50 deactivates the count control signal CC1 to low level, the major counter 51 deactivates the count control signal CC2 to low level, and the time base counter 41 sets the count control signal CC3 to low. Deactivate to level. In addition, the control circuit 50 stores the set count value LM in the count value register 42.

  When the measurement period starts, the control circuit 50 activates the count control signal CC1 to a high level. As a result, the gate signal GS is activated to a high level in the gate signal generation circuit 46, and the oscillation signal OS generated by the oscillation circuit 30 is input to the major counter 51 via the AND circuit 47. Operation starts.

  When the major counter 51 counts the pulse of the oscillation signal OS, the value of the measurement count value MC changes, for example, 0, 1, 2,. Here, the major counter 51 activates the count control signal CC2 to a high level when counting the first pulse of the oscillation signal OS in the measurement period. As a result, the control circuit 50 causes the time base counter 41 to start a counting operation.

  When the time base counter 41 counts the pulses of the reference clock signal CK2 divided by the frequency dividing circuit 20, the value of the time count value TC changes, for example, 0, 1, 2,. Each of the sampling buffers 43 and 44 sequentially stores the time count value TC in synchronization with the oscillation signal OS output from the delay circuit 45.

  When the time count value TC becomes equal to the set count value LM, the time base counter 41 activates the count control signal CC3 to a high level and ends the count operation. As a result, the gate signal generation circuit deactivates the gate signal GS to the low level, so that the output of the AND circuit 47 is fixed to the low level, and the count operation in the measure counter 51 is also terminated.

  For example, the measurement counter value that the major counter 51 counts and outputs the first pulse of the oscillation signal OS in the measurement period is set to zero, and the final value of the measurement count value in the measurement period is set to N (N is an integer of 2 or more). . The final value N of the measurement count value in the measurement period is stored in the count value buffer 53.

Further, the final value of the time count value in the measurement period, that is, the set count value LM is stored in the count value register 42. Further, the time count value TC _N-1 when the measurement count value becomes (N-1) is stored in the sampling buffer 43, and the time count when the measurement count value becomes (N-2). The value TC _N−2 is stored in the sampling buffer 44.

The data conversion circuit 54 stores the final value N of the measurement count value in the measurement period stored in the count value buffer 53, the set count value LM stored in the count value register 42, and the sampling buffers 43 and 44, respectively. Based on the counted time values TC _N-1 and TC _N-2 , the pulse of the oscillation signal OS from when the major counter 51 counts the first pulse of the oscillation signal OS in the measurement period until the measurement period ends. A composite count value including an integer part and a fractional part of the number is obtained. The integer part of the composite count value is “N”, and the less than integer part of the composite count value can be obtained based on (LM−TC _N−1 ) / (TC _N−1 −TC _N−2 ).

  Furthermore, the data conversion circuit 54 obtains a temperature corresponding to the composite count value by referring to the temperature data LUT 60 based on the obtained composite count value. The temperature data LUT 60 stores temperature data representing a plurality of reference temperatures and count value data representing a plurality of reference count values in association with each other.

  FIG. 2 is a diagram for explaining a specific operation example of the temperature measurement circuit shown in FIG. In the oscillation circuit 30, a voltage generated by charging / discharging the capacitor CSH is applied to the input terminal of the Schmitt trigger circuit 35. The Schmitt trigger circuit 35 outputs an oscillation signal OS based on the input voltage waveform. When the input voltage reaches the high level threshold, the oscillation signal OS becomes high level, and when the input voltage reaches the low level threshold, the oscillation signal OS becomes low level.

  When the measurement period starts according to the set timing at time tm, the control circuit 50 causes the counter circuit 40 to start the measurement operation. When the control circuit 50 activates the count control signal CC1 to high level, the gate signal GS is activated to high level, and the major counter 51 starts counting operation. The sampling buffers 43 and 44 store the reset time count value “0”.

  At time t0, the major counter 51 counts the first pulse (rising edge) of the oscillation signal OS, outputs the measurement count value “0”, and activates the count control signal CC2 to high level. As a result, the time base counter 41 also starts counting. The time base counter 41 counts the pulses of the reference clock signal CK2 and outputs a time count value “0”. In synchronization with the pulse of the oscillation signal OS output from the delay circuit 45, the sampling buffer 43 latches the time count value “0” obtained at time t 0, and the sampling buffer 44 resets the time count value “ "0" is latched.

  At time t1, the major counter 51 counts the second pulse of the oscillation signal OS and outputs a measurement count value “1”. On the other hand, the time base counter 41 counts the pulses of the reference clock signal CK2 and outputs a time count value “A”. In synchronization with the pulse of the oscillation signal OS output from the delay circuit 45, the sampling buffer 43 latches the time count value “A” obtained at time t1, and the sampling buffer 44 obtains the time obtained at time t0. The count value “0” is latched.

  At time t2, the major counter 51 counts the third pulse of the oscillation signal OS and outputs a measurement count value “2”. On the other hand, the time base counter 41 counts the pulses of the reference clock signal CK2 and outputs a time count value “B”. In synchronization with the pulse of the oscillation signal OS output from the delay circuit 45, the sampling buffer 43 latches the time count value “B” obtained at time t2, and the sampling buffer 44 obtains the time obtained at time t1. The count value “A” is latched.

  At time t3, the major counter 51 counts the fourth pulse of the oscillation signal OS and outputs a measurement count value “3”. In synchronization with the pulse of the oscillation signal OS output from the delay circuit 48, the count value buffer 53 latches the measured count value “3” obtained at time t3. On the other hand, the time base counter 41 counts the pulses of the reference clock signal CK2 and outputs a time count value “C”. In synchronization with the pulse of the oscillation signal OS output from the delay circuit 45, the sampling buffer 43 latches the time count value “C” obtained at time t3, and the sampling buffer 44 obtains the time obtained at time t2. The count value “B” is latched.

  At time t4, the time base counter 41 counts the pulses of the reference clock signal CK2, and outputs a time count value “LM”. Since the time count value “LM” is equal to the set count value “LM” stored in the count value register 42, the time base counter 41 activates the count control signal CC3 to a high level and stops the count operation. . As a result, the gate signal generation circuit 46 deactivates the gate signal GS to a low level, and the measure counter 51 also stops the count operation. At this time, the time count value “C” obtained at time t3 is stored in the sampling buffer 43, and the time count value “B” obtained at time t2 is stored in the sampling buffer 44. .

  The count fraction calculation circuit 541 of the data conversion circuit 54 stores the set count value “LM” stored in the count value register 42, the time count value “C” stored in the sampling buffer 43, and the sampling buffer 44. The time count value (CB) for one cycle of the oscillation signal OS from time t2 to time t3 and the fractional time from time t3 to time t4 based on the time count value “B” that has been set The count value (LM-C) is calculated, and the less than integer part of the composite count value is calculated based on (LM-C) / (CB).

  For example, when a composite count value is obtained in units of 1/32 count, a value “M” obtained by converting 32 × (LM−C) / (CB) into an integer is calculated, and a portion less than an integer of the composite count value Is represented as M / 32 and the composite count value is represented as (3 + M / 32). When the value “M” is converted to an integer, rounding down, rounding up, or rounding is performed at the first decimal place. Or you may represent the part below the integer of a composite count value with a decimal. In that case, rounding down, rounding up or rounding off is performed at the desired place.

  The temperature data read circuit 542 may refer to the temperature data LUT 60 based on the composite count value (3 + M / 32), or may refer to the temperature data LUT 60 based on the integer part “3” of the composite count value. . In the latter case, the processing required for reading the temperature data is simplified. In any case, the temperature data read circuit 542 includes first count value data representing the first reference count value closest to the composite count value (or an integer part thereof), and first temperature data corresponding to the first count value data. The second count value data representing the second reference count value closest to the composite count value (or its integer part) and the second temperature data corresponding thereto are read from the temperature data LUT 60.

  The interpolation circuit 543 interpolates (interpolates) the first and second reference temperatures represented by the first and second temperature data based on the relationship between the composite count value and the first and second reference count values. Alternatively, the temperature corresponding to the composite count value is obtained.

  In the following, a case will be described where temperature data representing a reference temperature in increments of 8 ° C. and count value data representing a corresponding reference count value are stored in the temperature data LUT 60. For example, the reference count value “1000.0” is stored corresponding to the temperature data representing the reference temperature “25 ° C.”, and the reference count value “100 °” is corresponding to the temperature data representing the reference temperature “33 ° C.”. 950.5 "is stored.

  When the composite count value is (983 + 15/32), the temperature data reading circuit 542 includes first count value data representing the reference count value “1000.0” closest to the integer part “983” of the composite count value, And the first temperature data corresponding thereto, the second count value data representing the reference count value “950.5” second closest to the integer part “983” of the composite count value, and the second count data corresponding thereto Are read out from the temperature data LUT 60 and output to the interpolation circuit 543.

  The interpolator 543 calculates the reference temperature represented by the first and second temperature data based on the relationship between the composite count value (983 + 15/32) and the reference count values “1000.0” and “950.5”, respectively. The temperature “27.67 ° C.” corresponding to the composite count value (983 + 15/32) is obtained by interpolating “25 ° C.” and “33 ° C.”.

  Here, it is also possible to improve the measurement accuracy by obtaining a less than integer part of the measurement count value only in a low temperature environment, and not to obtain the less than integer part of the measurement count value in a high temperature environment. Alternatively, in a high-temperature environment, a count limit may be provided in the time base counter 41, and the count operation may be stopped when effective accuracy is obtained, so that unnecessary counting is not performed. In that case, for example, when the measurement count value output from the major counter 51 exceeds a predetermined value during the measurement period, the control circuit 50 determines that the thermistor QTM is in a high temperature environment, and the count value The setting count value stored in the register 42 is changed to a second setting count value smaller than normal, and the data conversion circuit 54 is set so as to refer to the second temperature data LUT corresponding to the second setting count value. Control.

  According to the first operation example, since the temperature is obtained based on the composite count value including the integer part and the integer part of the number of pulses of the oscillation signal, even when the frequency of the oscillation signal OS becomes low in a low temperature environment. It becomes possible to perform temperature measurement with high accuracy. Or it becomes possible to shorten the measurement time for obtaining effective accuracy in temperature measurement. As the measurement time is shortened, the energy consumed for one temperature measurement is also reduced.

  Next, a second operation example of the temperature measurement circuit shown in FIG. 1 will be described in detail. In the second operation example, the count value of the pulse of the oscillation signal OS that is oscillated and output by the oscillation circuit 30 using the reference resistor REF in the first measurement period, and the oscillation circuit 30 in the second measurement period. The temperature around the thermistor QTM is measured based on the count value of the pulse of the oscillation signal OS that is oscillated and output using the Mr. QTM. Here, the target count value of the pulse of the oscillation signal OS in the first measurement period is determined in advance and stored in the count value register 52.

  In the first measurement period, the control circuit 50 activates the oscillation control signal OC1 to high level and deactivates the oscillation control signal OC2 to low level, so that the oscillation circuit 30 uses the reference resistor REF. Start oscillation. The control circuit 50 sets a sufficiently large value as the set count value LM. When the control circuit 50 activates the count control signal CC1 to the high level, the measure counter 51 counts the pulses of the oscillation signal OS and outputs the measurement count value MC. Here, the major counter 51 activates the count control signal CC2 to a high level when counting the first pulse of the oscillation signal OS in the measurement period. As a result, the control circuit 50 causes the time base counter 41 to start a counting operation.

  When the oscillation operation continues and the measured count value MC becomes equal to the target count value, the major counter 51 deactivates the count control signal CC2 to the low level and stops the count operation. As a result, the control circuit 50 causes the time base counter 41 to stop the counting operation, and stores the time count value TC at that time in the count value register 42 as the set count value LM that defines the end of the measurement period. Further, the control circuit 50 resets the count control signal CC1 to a low level.

  Thereafter, in the second measurement period, the control circuit 50 activates the oscillation control signal OC2 to a high level and deactivates the oscillation control signal OC1 to a low level, whereby the oscillation circuit 30 causes the thermistor QTM to Start oscillation by using. When the control circuit 50 activates the count control signal CC1 to the high level, the measure counter 51 counts the pulses of the oscillation signal OS and outputs the measurement count value MC. Here, the major counter 51 activates the count control signal CC2 to a high level when counting the first pulse of the oscillation signal OS in the measurement period. As a result, the control circuit 50 causes the time base counter 41 to start a counting operation.

  When the oscillation operation continues and the time count value TC becomes equal to the set count value LM, the time base counter 41 activates the count control signal CC3 to a high level and stops the count operation. As a result, the gate signal generation circuit 46 deactivates the gate signal GS to the low level, and the measure counter 51 also stops the counting operation.

  Based on the measurement count value MC output from the major counter 51 and the time count value TC output from the time base counter 41 in the second measurement period, the data conversion circuit 54 determines that the major counter 51 is in the second measurement period. A composite count value including an integer part and a part less than an integer of the number of pulses of the oscillation signal OS from the time when the first pulse of the oscillation signal OS is counted until the end of the second measurement period is obtained. Further, the data conversion circuit 54 obtains a temperature corresponding to the obtained composite count value.

As described above, the count value based on the oscillation using the reference resistor REF and the capacitor CSH (preset target count value) N1, and the composite count based on the oscillation using the thermistor QTM and the capacitor CSH in the same measurement period. The value N2 is obtained. Here, assuming that the resistance value of the reference resistor REF is R1, the resistance value of the thermistor QTM is R2, and the capacitance of the capacitor CSH is C, the measurement period T uses the constant α, and the equations (1) and (2 ).
T = α · R1 · C · N1 (1)
T = α · R2 · C · N2 (2)
From the equations (1) and (2), the following equation (3) is obtained.
R2 = (N1 / N2) R1 (3)
For example, when the target count value N1 is 1000 and the resistance value R1 of the reference resistor REF is 100 kΩ, the following equation (4) is obtained.
R2 = 1000 × 100k / N2 (4)

Since the temperature characteristic of the resistance value R2 of the thermistor QTM is known, by correcting the above equation in consideration of the threshold of the Schmitt trigger circuit, delay in each circuit, etc., temperature data representing a plurality of reference temperatures and a plurality of Correspondence with count value data representing the reference count value is obtained, and the correspondence is stored in the temperature data LUT 60. According to the second operation example, even if the oscillation frequency of the oscillation circuit 30 varies due to variations in the power supply voltage (V _DD −V _SS ) or variations in the capacitance C of the capacitor CSH, measurement and measurement using the reference resistor REF are performed. By performing both the measurement using the Mr. QTM, the fluctuation of the oscillation frequency is canceled out, so that it is possible to perform highly accurate temperature measurement. Other points are the same as in the first operation example.

Next, a second configuration example of the present invention will be described.
FIG. 3 is a block diagram showing a second configuration example of the temperature measurement circuit using the counter circuit according to the embodiment of the present invention. In the second configuration example, an oscillation circuit 30a is used instead of the oscillation circuit 30 in the first configuration example shown in FIG. The other points are the same as in the first configuration example.

  The oscillation circuit 30a includes a NAND circuit 37, a P channel MOS transistor 38, a Schmitt trigger circuit 35, an N channel MOS transistor 36, a resistor RNW formed in the N well of the semiconductor substrate, and a capacitor formed in the semiconductor substrate. And oscillates to generate an oscillation signal.

An oscillation control signal OC is applied to one input terminal (non-inverting input terminal) of the NAND circuit 37. The output terminal of the NAND circuit 37 is connected to the gate of the transistor 38. The source of the transistor 38 is connected to the power supply potential V _DD, and the drain of the transistor 38 is connected to one end of the resistor RNW. The other end of the resistor RNW is connected to one end of the capacitor CSH and the input terminal of the Schmitt trigger circuit 35.

The other end of the capacitor CSH is connected to the power supply potential _{V SS.} The output terminal of the Schmitt trigger circuit 35 is connected to the other input terminal (inverted input terminal) of the NAND circuit 37 and the gate of the transistor 36. The drain of the transistor 36 is connected to an input terminal of the Schmitt trigger circuit 35, the source of the transistor 36 is connected to the power supply potential V _SS.

  When the oscillation control signal OC is activated to a high level, the high level oscillation control signal OC is applied to the non-inverting input terminal of the NAND circuit 37. The output signal of the NAND circuit 37 is inverted by the transistor 38 and applied to the input terminal of the capacitor CSH and the Schmitt trigger circuit 35 via the resistor RNW. The output signal of the Schmitt trigger circuit 35 is applied to the inverting input terminal of the NAND circuit 37. Thus, a CR type oscillation circuit 30a is formed. The oscillation frequency of the oscillation circuit 30a is determined in relation to the time constant between the resistance value of the resistor RNW and the capacitance value of the capacitor CSH.

  The resistance value of the resistor RNW formed in the N well of the semiconductor substrate has a temperature characteristic that depends on the manufacturing process of the semiconductor integrated circuit. Therefore, by preparing the temperature data LUT corresponding to the temperature characteristic, the oscillation frequency of the oscillation circuit 30a is set. Based on this, the temperature around the semiconductor substrate can be determined. In the second configuration example, since the reference resistor and the thermistor are not used, the operation of the temperature measuring circuit is the same as the first operation example in the first configuration example.

  DESCRIPTION OF SYMBOLS 10 ... Reference clock signal generation circuit, 100 ... Semiconductor integrated circuit, 20 ... Frequency dividing circuit, 30, 30a ... Oscillation circuit, 31, 32, 37 ... NAND circuit, 33, 34, 38 ... P channel MOS transistor, 35 ... Schmitt Trigger circuit 36 ... N channel MOS transistor 40 ... Counter circuit 41 ... Time base counter 42 ... Count value register 43,44 ... Sampling buffer 45,48 ... Delay circuit 46 ... Gate signal generation circuit 47 ... AND circuit, 50, 50a ... control circuit, 51 ... major counter, 52 ... count value register, 53 ... count value buffer, 54 ... data conversion circuit, 541 ... count fraction calculation circuit, 542 ... temperature data read circuit, 543 ... interpolation Circuit, 60 ... temperature data LUT, 70 ... EE ROM, REF ... reference resistor, QTM ... thermistor, CSH ... capacitor, resistor formed on RNW ... N-well

Claims (7)

A first counter that counts pulses of an input signal and outputs a measurement count value in a set measurement period;
A reference clock signal having a higher frequency than the input signal is supplied, and the first counter counts the first pulse of the input signal in the measurement period until the measurement period ends. A second counter that counts pulses and outputs a time count value;
Based on the measurement count value output from the first counter and the time count value output from the second counter in the measurement period, the first counter starts the first input signal in the measurement period. A data conversion circuit for obtaining a composite count value including an integer part and less than an integer part of the number of pulses of the input signal from the counting of the number of pulses until the measurement period ends,
A counter circuit comprising: The final value of the measurement count value in the measurement period is N (N is an integer of 2 or more), the time count value when the measurement count value is (N-2) is TC _N-2 , When the time count value when the measurement count value becomes (N−1) is TC _N−1 and the final value of the time count value in the measurement period is LM, the data conversion circuit ( The counter circuit according to claim 1, wherein a portion less than an integer of the composite count value is obtained based on LM-TC _N-1 ) / (TC _N-1 -TC _N-2 ). An oscillation circuit that generates an oscillation signal by oscillating at a frequency related to a time constant between the resistance value of the connected resistor or thermistor and the capacitance value of the capacitor;
The counter circuit according to claim 1 or 2, wherein the oscillation signal generated by the oscillation circuit is input;
And the data conversion circuit includes an integer part of the number of pulses of the oscillation signal from when the first counter counts the first pulse of the oscillation signal in the measurement period until the measurement period ends, and A semiconductor integrated circuit that obtains the composite count value including a portion less than an integer, and further obtains a temperature corresponding to the composite count value. The counter circuit is
A control circuit that controls the oscillation circuit to oscillate using a reference resistor in the first measurement period, and then controls the oscillation circuit to oscillate using a thermistor in the second measurement period. When,
A storage circuit that stores the time count value when the measurement count value becomes equal to a predetermined value in the first measurement period, as a set count value that defines the end of the measurement period;
Further comprising
The data conversion circuit obtains the composite count value based on the measurement count value output from the first counter and the time count value output from the second counter in the second measurement period. The semiconductor integrated circuit according to claim 3. An oscillation signal is generated by oscillating at a frequency related to a time constant between a resistance value of the resistor and a capacitance value of the capacitor, including a resistor formed in an N well of the semiconductor substrate and a capacitor formed in the semiconductor substrate. An oscillation circuit to generate,
The counter circuit according to claim 1 or 2, wherein the oscillation signal generated by the oscillation circuit is input;
And the data conversion circuit includes an integer part of the number of pulses of the oscillation signal from when the first counter counts the first pulse of the oscillation signal in the measurement period until the measurement period ends, and A semiconductor integrated circuit that obtains the composite count value including a portion less than an integer, and further obtains a temperature corresponding to the composite count value. Further comprising a look-up table for storing temperature data representing a plurality of reference temperatures and count value data representing a plurality of reference count values correspondingly;
The data conversion circuit refers to the lookup table based on the composite count value or an integer part thereof, and obtains a temperature corresponding to the composite count value based on temperature data read from the lookup table. The semiconductor integrated circuit according to claim 3.   The data conversion circuit includes first count value data representing a first reference count value closest to the composite count value or an integer part thereof, and corresponding first temperature data, and the composite count value or the same Second count value data representing a second reference count value that is second closest to the integer part and second temperature data corresponding to the second reference count value are read from the lookup table, and the composite count value and the first count data are read out. And the temperature corresponding to the composite count value by interpolating the first and second reference temperatures respectively represented by the first and second temperature data based on the relationship with the second reference count value. The semiconductor integrated circuit according to claim 6, wherein:

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