JP2012190413A - Controller for robot - Google Patents

Abstract

PROBLEM TO BE SOLVED: To more surely detect abnormality of a detection object while inhibiting addition of special hardware, in a controller for a robot.SOLUTION: A controller 20 for a robot comprises a main control substrate 21 and a first sub control substrate 22. Each FPGA 31 of the control substrates 21 and 22 comprises a time counter TC performing counting with a prescribed speed, separately calculates a reference value and a signal value POUT of one bit with a prescribed rule based on a value of the time counter TC and separately performs input of the signal value POUT of one bit and output of the signal value POUT of one bit when a value of the time counter TC becomes a prescribed value. The FPGA 31 of the control substrate 21 detects abnormality on condition that the signal value POUT does not match the reference value. A first CPU 34 makes the FPGA 31 of the control substrate 21 start detection of abnormality after matching the two values of the time counter TC.

Description

  The present invention relates to a robot controller.

  Conventionally, motor controllers, such as industrial robot controllers, have a main processor (CPU) that performs numerical calculations and transmits commands, a logic circuit that receives the commands and converts them into signals that drive the motor, and the signals And a power circuit controlled based on the above. The logic circuit is formed of gate logic and generally uses a gate array (G / A) such as an FPGA (Field Programmable Gate Array).

  When the CPU or G / A stops, an abnormal signal is transmitted to the power circuit, and the motor may perform an abnormal operation. Therefore, in order to prevent abnormal operation of the motor, it is necessary to detect the abnormality mutually with the CPU and the G / A, and when it is detected that there is an abnormality, it is necessary to immediately execute a process of stopping the motor.

  A watchdog circuit is generally used as a means for mutually detecting an abnormality. In the watchdog circuit, a detection interval can be easily set and the configuration is simple, so a time-up counter is used (for example, see Patent Documents 1 and 2). In the ones described in Patent Documents 1 and 2, when the detection target transmits a clear signal and clears the timer within a set time, it is determined to be normal, and the time-up is detected by counting up the timer (simple Timer clear method). Then, when the time-up counter reaches an overflow, it is determined that there is an abnormality.

JP 2000-237981 A JP 2007-265103 A

  However, with the simple timer clear method, even when an abnormality occurs in the detection target, the time-up counter may be periodically cleared due to external noise, switching noise, crosstalk, etc. is there. In this case, the watchdog circuit determines that it is normal, and it is difficult to determine that the detection target is abnormal.

  In particular, in a robot, if such a state continues, a problem may be induced. Therefore, it is necessary to reliably detect that the detection target is abnormal. However, adding special hardware in order to reliably detect that the detection target is abnormal will increase the cost.

  The present invention has been made in view of such circumstances, and is to more reliably detect that the detection target is abnormal while suppressing the addition of special hardware in the controller of the robot. .

  The present invention employs the following means in order to solve the above problems.

  A first invention is a robot controller, comprising a first time counter that counts at a predetermined speed, calculates a 1-bit reference value according to a predetermined rule based on the value of the first time counter, An abnormality detection circuit for detecting an abnormality on condition that the 1-bit signal value inputted when the value of the first time counter reaches a predetermined value and the reference value do not match, and counting at the predetermined speed A 1-bit signal value is calculated according to the predetermined rule based on the value of the second time counter, and when the value of the second time counter reaches the predetermined value, The detected circuit that outputs the calculated 1-bit signal value to the abnormality detection circuit, the value of the first time counter, and the value of the second time counter are matched, and then the abnormality detection circuit A CPU to start the serial anomaly detection, characterized in that it comprises a.

  According to the above configuration, counting is performed at the same predetermined speed by the first time counter of the abnormality detection circuit and the second time counter of the detected circuit. Then, a 1-bit reference value and a signal value are calculated by the abnormality detection circuit and the detected circuit based on the values of the respective time counters according to the same predetermined rule. Further, when the value of the first time counter reaches a predetermined value, a 1-bit signal value is input by the abnormality detection circuit, and when the value of the second time counter also reaches the predetermined value, the calculation is performed by the detected circuit. The 1-bit signal value thus output is output to the abnormality detection circuit.

  Here, since the value of the first time counter is matched with the value of the second time counter by the CPU, in the first time counter and the second time counter that count at the same predetermined speed, the counter values are equal to each other. Become. Therefore, the 1-bit reference value and signal value calculated according to the same predetermined rule are equal to each other based on the value of the time counter. After that, the value of the first time counter and the value of the second time counter simultaneously become a predetermined value, the detected circuit outputs a 1-bit signal value to the abnormality detection circuit, and the abnormality detection circuit inputs the 1-bit signal value. Is done. When the input 1-bit signal value does not coincide with the calculated 1-bit reference value, the abnormality detection circuit detects an abnormality. For this reason, when an abnormality occurs in the detected circuit and a signal value that matches the reference value is not calculated, or when the signal value is not properly output, it is detected that the circuit is abnormal. On the other hand, when the input 1-bit signal value matches the calculated 1-bit reference value, the abnormality is not detected.

  That is, unlike the simple timer clear method in which a constant clear signal (1 bit) that does not change is detected when it is not input within the set time, a reference value (1 bit) that changes depending on the value of the time counter. If the same signal value (1 bit) is not input at a predetermined time, it is detected that there is an abnormality. Even if external noise, switching noise, crosstalk, etc. occur, it is very unlikely that the noise will change in the same way as the reference value. Can be inhibited. In addition, in the above-described abnormality detection, a 1-bit reference value and a signal value are calculated using the value of the time counter, and a 1-bit clear signal is used to detect an abnormality when the values do not match. An abnormality can be detected by hardware similar to that used for processing. As a result, the controller of the robot can more reliably detect that the detected circuit is abnormal while suppressing the addition of special hardware.

  The detected circuit may calculate and output the signal value other than when the value of the second time counter reaches the predetermined value. The abnormality detection circuit may calculate the reference value and input the signal value other than when the value of the second time counter reaches the predetermined value.

  In the second invention, the predetermined value is a value having a constant value interval between the value of the first time counter and the value of the second time counter.

  According to the above configuration, when the value of the first time counter and the value of the second time counter reach the predetermined value at a constant value interval, the detected circuit outputs a 1-bit signal value to the abnormality detection circuit, The 1-bit signal value is input by the abnormality detection circuit. When the input 1-bit signal value does not coincide with the calculated 1-bit reference value, the abnormality detection circuit detects an abnormality. For this reason, it is not necessary to calculate a signal value or a reference value, output or input a signal value, or detect an abnormality each time counting is performed by each time counter. Therefore, it is possible to reduce the processing load and to prevent erroneous detection due to an abnormality detection interval being too short.

  In a third aspect of the invention, a first logic circuit that receives a command from the CPU and converts it into a signal for driving the first motor, and a second motor that is connected to the first logic circuit and receives the command from the CPU. A second logic circuit that converts the signal value into a signal for driving the first logic circuit, wherein the first logic circuit forms the abnormality detection circuit, inputs the signal value from the second logic circuit, and forms the detected circuit And outputting the signal value to the second logic circuit. The second logic circuit forms the detected circuit and outputs the signal value to the first logic circuit, and also detects the abnormality. A circuit is formed and the signal value is input from the first logic circuit.

  According to the above configuration, the first logic circuit as the abnormality detection circuit detects that the second logic circuit as the detected circuit is abnormal, and the second logic circuit as the abnormality detection circuit detects the detected It is detected that the first logic circuit as a circuit is abnormal. For this reason, in the controller of the robot, it is possible to detect an abnormality mutually with a plurality of logic circuits with a simple configuration.

  According to a fourth aspect of the invention, there is provided a third logic circuit that is connected to the second logic circuit, receives a command from the CPU, and converts it into a signal for driving a third motor, and the second logic circuit detects the abnormality. Forming a circuit and inputting the signal value from the third logic circuit, forming the detected circuit and outputting the signal value to the third logic circuit, the third logic circuit comprising: The detected circuit is formed and the signal value is output to the second logic circuit, and the abnormality detection circuit is formed and the signal value is input from the second logic circuit.

  According to the above configuration, the second logic circuit as the abnormality detection circuit detects that the third logic circuit as the detected circuit is abnormal, and the third logic circuit as the abnormality detection circuit detects the detected signal. It is detected that the second logic circuit as a circuit is abnormal. That is, it is detected by both the first and third logic circuits connected to the second logic circuit that the second logic circuit is abnormal. For this reason, when the first to third logic circuits are arranged in one row and connected to each other, the first and third logic circuits on both sides cause an abnormality in the second logic circuit arranged between them. It can be detected twice. As a result, it is possible to more reliably detect that the detected circuit is abnormal while efficiently arranging the first to third logic circuits.

  Specifically, as in the fifth invention, the predetermined rule is an operation for obtaining an exclusive OR (XOR) using all bits as input values for the value of the time counter expressed in binary number. Such a configuration can be adopted. For example, when the number of bits of the time counter expressed in binary number is 4 (0 to 15 in decimal number), the calculation result is as follows. That is, an exclusive OR (“1” when the number of “1” is an odd number, “0” when the number of “1” is an odd number, and “0”) with all bits as input values for a 4-bit binary number The binary number “0000” is “0”, the binary number “0001” is “1”, the binary number “0010” is “1”, and the binary number “0011” is “0”. According to such a configuration, the reference value is balanced between “0” and “1” while avoiding the simple repetition of the reference value (signal value) between “0” and “1” by simple processing. Can be set well.

The schematic diagram which shows the controller of a robot, and its periphery structure. The flowchart which shows the procedure of the process of an abnormality detection circuit, and the process of a to-be-detected circuit. The figure which shows the relationship between the value of a time counter, and a signal value. The timing chart which shows the relationship between the value of a time counter, a signal value, and an abnormal signal.

  Hereinafter, an embodiment will be described with reference to the drawings. The present embodiment is embodied as a robot system that assembles machines and the like in a machine assembly factory or the like.

  FIG. 1 is a schematic diagram showing a controller 20 of the robot and its peripheral configuration. As shown in the figure, the robot system (production equipment system) includes a motor 11 that drives each joint of the robot, a three-phase AC power source 12 (power source) that supplies power to each motor 11, and an AC current from the power source 12. A diode 13 and a capacitor 14 for rectifying to a direct current, a motor relay 15 for turning ON / OFF the power supply from the power source 12 to all the motors 11, and a robot controller 20 are provided. The motor relay 15 has a positive contact and a negative contact, and the positive contact and the negative contact are simultaneously switched ON or OFF.

  The controller 20 includes a main control board 21, a first sub control board 22, a second sub control board 23, three first connectors 25, three second connectors 26, and an end connector 24. The main control board 21 includes a first CPU 34, a second CPU 35, an arithmetic circuit 36, a photocoupler 37, and a transistor 38. The control boards 21, 22, and 23 each include an FPGA 31, a power circuit 32, and an arithmetic circuit 33.

  Each FPGA 31 (logic circuit) includes a control circuit 41 and a watchdog circuit 43. In each FPGA 31, a control circuit 41 and a watchdog circuit 43 are connected, and a watchdog circuit 43 and an arithmetic circuit 33 are connected. The control circuit 41 and the watchdog circuit 43 of each control board are connected in parallel to the first CPU 34, respectively.

  In adjacent control boards, the FPGAs 31 are connected by the first connector 25. The FPGA 31 of the main control board 21 and the FPGA 31 of the first sub control board 22 are connected by the first connector 25, and the FPGA 31 of the first sub control board 22 and the FPGA 31 of the second sub control board 23 are connected to the first connector 25. Connected by. In the second sub control board 23 which is a terminal sub-board in the controller 20, the end connector 24 is connected to the terminal-side first connector 25.

  Specifically, the watchdog circuits 43 are connected to each other by the first connector 25 in adjacent control boards. That is, the watch dog circuit 43 of the main control board 21 and the watch dog circuit 43 of the first sub control board 22 are connected, and the watch dog circuit 43 of the first sub control board 22 and the watch dog circuit of the second sub control board 23 are connected. 43 is connected. In the second sub-control board 23, a watchdog circuit 43 is connected to the first connector 25 on the end side.

  In addition, in the adjacent control boards, the power circuits 32 are connected by the second connector 26. The power circuit 32 of the main control board 21 and the power circuit 32 of the first sub control board 22 are connected by the second connector 26, and the power circuit 32 of the first sub control board 22 and the power circuit of the second sub control board 23 are connected. 32 is connected by a second connector 26. In the second sub-control board 23, the motor relay 15 is connected to the second connector 26 on the end side. Each power circuit 32 is connected in parallel to the motor relay 15 via the second connector 26. Each power circuit 32 is connected to each motor 11 described above.

  Each power circuit 32 includes a transistor, a diode, and the like, and switches a current supplied from the power supply 12 to each motor 11. Thereby, each motor 11 is driven to forward rotation and reverse rotation. Each power circuit 32 is controlled by a drive signal from each control circuit 41.

  Each control circuit 41 includes a transmission / reception circuit, a position detection circuit, a signal conversion circuit, and a watchdog control circuit. Each transmission / reception circuit receives a detection signal from an encoder provided in each motor 11 and transmits a drive signal to each power circuit 32. Each transmission / reception circuit transmits / receives a signal to / from each watchdog circuit 43. Each position detection circuit detects the rotation angle of each motor 11 based on the detection signal from each encoder. Each signal conversion circuit receives a command from the first CPU 34 and converts it into a drive signal for driving each motor 11. Each watchdog control circuit controls each watchdog circuit 43 based on a command from the first CPU 34.

  Each watchdog circuit 43 includes a transmission / reception circuit, a time counter TC, and the like. Each transmission / reception circuit receives a signal from each control circuit 41 and transmits the value of the time counter TC to each control circuit 41. Each transmission / reception circuit receives a command from the first CPU 34 and transmits / receives a signal to / from the watchdog circuit 43 of the adjacent control board. The time counter TC increments the counter value by 1 at a predetermined speed from 0 to 15 (increment). When the counter value reaches 15, the counter value is reset to 0 next.

  Each watchdog circuit 43 transmits a signal value POUT to a watchdog circuit that monitors itself (detects an abnormality). Each watchdog circuit 43 transmits the signal value POUT to the watchdog circuit 43 of the adjacent control board and receives the signal value POUT from the watchdog circuit 43 of the adjacent control board.

  Specifically, the watch dog circuit 43 of the main control board 21 transmits the signal value POUT to the watch dog circuit of the first CPU 34 and the watch dog circuit 43 of the first sub control board 22. On the other hand, the watch dog circuit 43 of the main control board 21 receives the signal value POUT from the watch dog circuit of the first CPU 34 and the watch dog circuit 43 of the first sub control board 22. The watchdog circuit 43 of the first sub control board 22 transmits the signal value POUT to the watchdog circuit 43 of the main control board 21 and the watchdog circuit 43 of the second sub control board 23. On the other hand, the watchdog circuit 43 of the first sub control board 22 receives the signal value POUT from the watchdog circuit 43 of the main control board 21 and the watchdog circuit 43 of the second sub control board 23. The watchdog circuit 43 of the second sub control board 23 transmits the signal value POUT to the watchdog circuit 43 of the first sub control board 22. On the other hand, the watchdog circuit 43 of the second sub control board 23 receives the signal value POUT from the watchdog circuit 43 of the first sub control board 22. At this time, the logic level (“H” or “L”) of the signal value POUT is controlled by each control circuit 41.

  Each watchdog circuit 43 is connected to one input terminal of each arithmetic circuit 33, and transmits a signal value TIMEUP to each input terminal. At this time, the logic level of the signal value TIMEUP is controlled by each control circuit 41 and indicates that an abnormality has occurred when the logic level is “H” (abnormal signal). The other input terminal of each arithmetic circuit 33 is connected to the output terminal of the arithmetic circuit 33 on the downstream control board. Specifically, the output terminal of the arithmetic circuit 33 on the first sub control board 22 is connected to one of the input terminals of the arithmetic circuit 33 on the main control board 21. The output terminal of the arithmetic circuit 33 on the second sub control board 23 is connected to one of the input terminals of the arithmetic circuit 33 on the first sub control board 22. One input terminal of the arithmetic circuit 33 in the second sub-control board 23 is grounded.

  The arithmetic circuit 33 is an AND circuit that operates with negative logic, and outputs “L” when both inputs from the two input terminals are “L”, and outputs “H” otherwise. . Here, in the second sub-control board 23, since one input terminal of the arithmetic circuit 33 is grounded, its input is always “L”. For this reason, the output of the arithmetic circuit 33 becomes “L” only when the signal value TIMEUP from the watchdog circuit 43 is “L”. In the first sub-control board 22, the output from the arithmetic circuit 33 of the second sub-control board 23 is “L”, and the arithmetic circuit 33 is only when the signal value TIMEUP from the watchdog circuit 43 is “L”. Becomes “L”. Further, in the main control board 21, the output from the arithmetic circuit 33 of the first sub control board 22 is “L” and the output from the arithmetic circuit 33 is only when the signal value TIMEUP from the watchdog circuit 43 is “L”. The output of the terminal A becomes “L”. That is, in all the watchdog circuits 43 on the control boards 21, 22, and 23, the output of the output terminal A of the arithmetic circuit 33 on the main control board 21 is "L" only when the signal value TIMEUP is "L". Note that a pull-up resistor is appropriately connected to the signal line for transmitting each signal.

  Each of the CPUs 34 and 35 has an internal memory, and executes a program stored in the internal memory. The CPUs 34 and 35 are connected to ROM, RAM, FPGA 31 and the like. The ROM stores a robot system program, an operation program, and the like. The RAM stores parameter values and the like when executing these programs. Then, the first CPU 34 transmits a command such as the position and speed of each motor 11 to each control circuit 41 based on the position information input from the position detection circuit of each control circuit 41 by executing the operation program. Then, the rotation angle of each joint of the robot is feedback controlled to the target rotation angle. Note that the first CPU 34 and the second CPU 35 are connected to each other via a data bus, and monitor each other so that if an abnormality occurs in one, the other compensates for it.

  The CPUs 34 and 35 are respectively connected to one input terminal of each arithmetic circuit 36. The other input terminal of each arithmetic circuit 36 is connected to the output terminal A of the arithmetic circuit 33 in the main control board 21. Each arithmetic circuit 36 is a logical product circuit that operates in negative logic, and outputs “H” when both inputs are “L”, and outputs “L” otherwise. The output terminal of each arithmetic circuit 36 is connected to the signal input terminal of the photocoupler 37.

  Each photocoupler 37 is connected to the base of each transistor 38, and when an “H” output is input from each arithmetic circuit 36, current flows between the emitter and base of each transistor 38. Thus, when a current flows between the emitter and collector of the two transistors 38, the motor relay 15 is turned on. That is, the motor relay 15 is turned on when the outputs of the two arithmetic circuits 36 are both “H”, and the motor relay 15 is turned off when the output of either one of the arithmetic circuits 36 is “L”. . When driving any one of the motors 11, the CPUs 34 and 35 output “L” to the respective arithmetic circuits 36. When not driving any of the motors 11, the CPUs 34 and 35 respectively output “H” to the respective arithmetic circuits 36. Output.

  Next, in the control boards 21, 22, and 23, the FPGA 31 of one control board forms an abnormality detection circuit that detects the abnormality of the FPGA 31 of the other control board, and the abnormality detection circuit detects the abnormality. A process when the FPGA 31 forms a circuit to be detected will be described. FIG. 2 is a flowchart showing a procedure of processing of the abnormality detection circuit and processing of the detected circuit. These processes are repeatedly executed in each FPGA 31 every time the time counter TC of the watchdog circuit 43 increments the counter value. In starting these processes, the first CPU 34 (CPU) resets the value of the time counter TC of each watchdog circuit 43 of the control boards 21, 22 and 23. That is, the values of the time counters TC are matched in all the watchdog circuits 43.

  As shown in the figure, first, the abnormality detection circuit determines whether or not it is time to detect abnormality (S11). Specifically, the control circuit 41 sets the value of the time counter TC (first time counter) to 4 (constant value) intervals starting from 0, that is, any value of 0, 4, 8, 12 (predetermined Value).

  In the above determination, when it is determined that it is not the timing for detecting the abnormality (S11: NO), the abnormality detection circuit once ends this series of processes (END). On the other hand, if it is determined in the above determination that it is time to detect an abnormality (S11: YES), the abnormality detection circuit calculates a 1-bit reference value according to a predetermined rule based on the value of the time counter TC. (S12).

  In parallel with this, the detected circuit calculates a 1-bit signal value POUT according to a predetermined rule based on the value of the time counter TC (S21). The detected circuit is not limited to the case where the value of the time counter TC (second time counter) is any one of 0, 4, 8, and 12 (predetermined value), and the value of the time counter TC is incremented. Each time the signal value POUT is calculated.

  As the predetermined rule, as shown in FIG. 3, the control circuit 41 obtains an exclusive OR (XOR) using all bits as input values for the value (4 bits) of the time counter TC expressed in binary numbers. . That is, the control circuit 41 sets the reference value (signal value POUT) to “1” when the number of “1” is an odd number in Bit0 to Bit3, and the reference value (signal value POUT) when the number is even. Is set to “0”. That is, the abnormality detection circuit and the detected circuit calculate the 1-bit reference value and the signal value POUT, respectively, according to the same predetermined rule based on the value of each time counter TC.

  Returning to FIG. 2, subsequently, the detected circuit outputs the signal value POUT to the abnormality detection circuit (S22), and the abnormality detection circuit inputs the signal value POUT from the detected circuit (S13). Specifically, the control circuit 41 of the detected circuit causes the watchdog circuit 43 to output the signal value POUT to the watchdog circuit 43 of the abnormality detection circuit. Further, the control circuit 41 of the abnormality detection circuit receives the signal value POUT from the watchdog circuit 43 of the detected circuit from the watchdog circuit 43. Here, the detected circuit outputs the signal value POUT every time the value of the time counter TC is incremented, not only when the value of the time counter TC is any of 0, 4, 8, and 12. To do. In contrast, the abnormality detection circuit inputs the signal value POUT from the detected circuit only when the value of the time counter TC is any one of 0, 4, 8, and 12. Thereafter, the detected circuit temporarily ends this series of processing (END).

  Subsequently, the control circuit 41 of the abnormality detection circuit determines whether or not the reference value and the signal value POUT are inconsistent (S14). In this determination, when it is determined that the reference value and the signal value POUT do not coincide with each other (S14: NO), the abnormality detection circuit once ends this series of processing (END). On the other hand, in this determination, when it is determined that the reference value and the signal value POUT do not match (S14: YES), the abnormality detection circuit outputs the signal value TIMEUP as “H” (outputs an abnormality signal). . Specifically, the control circuit 41 sets the logic level of the signal value TIMEUP to “H” and causes the watchdog circuit 43 to output the signal value TIMEUP to the arithmetic circuit 33. Thereafter, the abnormality detection circuit once ends this series of processing (END).

  In the controller 20, the processing of the abnormality detecting circuit and the processing of the detected circuit are performed between the plurality of FPGAs 31. Specifically, the FPGA 31 (first logic circuit) of the main control board 21 (control board of the first motor) forms an abnormality detection circuit, and the FPGA 31 (control board of the second motor) of the first sub control board 22 (control board of the second motor). The second logic circuit) forms a corresponding circuit to be detected. The FPGA 31 of the first sub control board 22 forms an abnormality detection circuit, and the FPGA 31 of the main control board 21 forms a detected circuit corresponding thereto. Further, the FPGA 31 of the first sub control board 22 forms an abnormality detection circuit, and the FPGA 31 (third logic circuit) of the second sub control board 23 (control board of the third motor) forms a detected circuit corresponding thereto. is doing. The FPGA 31 of the second sub-control board 23 forms an abnormality detection circuit, and the FPGA 31 of the first sub-control board 22 forms a corresponding circuit to be detected. Note that the first CPU 34 forms an abnormality detection circuit, and the FPGA 31 of the main control board 21 forms a detected circuit corresponding thereto. The FPGA 31 of the main control board 21 forms an abnormality detection circuit, and the first CPU 34 forms a corresponding circuit to be detected.

  Next, a mode of processing by the abnormality detection circuit and the detected circuit will be described. FIG. 4 is a timing chart showing the relationship among the value of the time counter TC, the signal value POUT, and the signal value TIMEUP. The processing by the abnormality detection circuit and the detection target circuit is started after the values of the respective time counters TC are matched by the first CPU 34.

  As shown in the figure, first, at the timing t1, the values of the time counters TC of both the abnormality detection circuit and the circuit to be detected are zero. As indicated by the arrows, the timing t1 is a check timing that is a timing for detecting an abnormality. For this reason, as shown in FIG. 3, the abnormality detection circuit and the detected circuit calculate the 1-bit reference value and the signal value POUT as “0”, respectively.

  Returning to FIG. 4, the detected circuit outputs “0” as the signal value POUT, and the abnormality detection circuit inputs this signal value POUT. If the detected circuit is normal, the signal value POUT input from the detected circuit matches the reference value calculated by the abnormality detecting circuit, and the signal value TIMEUP output from the abnormality detecting circuit is “0”. It becomes.

  Subsequently, each time the value of the time counter TC is incremented, the detected circuit calculates the signal value POUT according to the predetermined rule shown in FIG. 3, and outputs the signal value POUT to the abnormality detection circuit. However, the abnormality detection circuit does not input the signal value POUT and detect abnormality except for the check timing indicated by the arrow.

  At timing t2, the value of the time counter TC is 4, which corresponds to the check timing. Therefore, as shown in FIG. 3, the abnormality detection circuit and the detected circuit calculate the 1-bit reference value and the signal value POUT as “1”, respectively. In the same manner as described above, the detected circuit outputs “1” as the signal value POUT, and the abnormality detection circuit inputs this signal value POUT. Also in this case, if the detected circuit is normal, the signal value POUT input from the detected circuit matches the reference value calculated by the abnormality detecting circuit, and the signal value TIMEUP output from the abnormality detecting circuit is “0”. "

  In this way, at each check timing, the abnormality detection circuit detects abnormality of the detected circuit. After the value of the time counter TC reaches 15, the value of the time counter TC is returned to 0 at the timing t3.

  Here, when an abnormality occurs in the detected circuit at timing t4, the signal value POUT input from the detected circuit does not match the reference value calculated by the abnormality detecting circuit. For example, while the reference value calculated by the abnormality detection circuit is “1”, the signal value POUT input from the detected circuit is “0”. Therefore, the signal value TIMEUP output from the abnormality detection circuit is “1” (abnormal signal).

  As a result, on the main control board 21, the output of the output terminal A of the arithmetic circuit 33 becomes “H”, and the output of the arithmetic circuit 36 becomes “L”. For this reason, the motor relay 15 is turned off, and the power supply from the power source 12 to all the motors 11 is stopped. This state is maintained until a predetermined release process is executed by the first CPU 34 or the second CPU 35.

  The embodiment described above has the following advantages.

  Since the value of the time counter TC of the abnormality detection circuit and the value of the time counter TC of the detected circuit are matched by the first CPU 34, in these time counters TC that count at the same predetermined speed, the counter values are equal to each other Become. Therefore, the 1-bit reference value and the signal value POUT calculated according to the same predetermined rule are equal to each other based on the value of the time counter TC. Thereafter, the value of the time counter TC of the abnormality detection circuit and the value of the time counter TC of the detected circuit simultaneously become a predetermined value, and the detected circuit outputs a 1-bit signal value POUT to the abnormality detection circuit. A 1-bit signal value POUT is input. When the input 1-bit signal value POUT does not coincide with the calculated 1-bit reference value, the abnormality detection circuit detects an abnormality. For this reason, when an abnormality occurs in the detected circuit and the signal value POUT that matches the reference value is not calculated, or when the signal value POUT is not properly output, the abnormality is detected. On the other hand, if the input 1-bit signal value POUT matches the calculated 1-bit reference value, it is not detected that there is an abnormality.

  That is, unlike a simple timer clear method in which a constant clear signal (1 bit) that does not change is detected when it is not input within a set time, a reference value (1 bit) that changes according to the value of the time counter TC. ) Is detected as abnormal when the same signal value POUT (1 bit) is not input at a predetermined time. Even if external noise, switching noise, crosstalk, etc. occur, it is very unlikely that the noise will change in the same way as the reference value. Can be inhibited. In addition, in the above-described abnormality detection, the 1-bit reference value and the signal value POUT are calculated using the value of the time counter TC, and if the values do not match, the 1-bit clear is detected. An abnormality can be detected by hardware similar to that used when processing a signal. As a result, the robot controller 20 can more reliably detect that the detected circuit is abnormal while suppressing the addition of special hardware.

  When the value of the time counter TC of the abnormality detection circuit and the value of the time counter TC of the detection target circuit become 4 (constant value) intervals starting from 0, a 1-bit signal is sent from the detection target circuit to the abnormality detection circuit. The value POUT is output, and the 1-bit signal value POUT is input by the abnormality detection circuit. When the input 1-bit signal value POUT does not coincide with the calculated 1-bit reference value, the abnormality detection circuit detects an abnormality. For this reason, it is not necessary to calculate a reference value, input a signal value POUT, and detect an abnormality each time counting is performed by each time counter TC. Therefore, it is possible to reduce the processing load of the FPGA 31, and it is possible to suppress erroneous detection of abnormality due to an abnormality detection interval being too short.

  The FPGA 31 of the main control board 21 as the abnormality detection circuit detects that the FPGA 31 of the first sub control board 22 as the detected circuit is abnormal, and the first sub control board 22 as the abnormality detection circuit It is detected by the FPGA 31 that the FPGA 31 of the main control board 21 as the detected circuit is abnormal. For this reason, in the controller 20 of the robot, the abnormality can be detected mutually by the plurality of FPGAs 31 with a simple configuration.

  Further, the FPGA 31 of the first sub control board 22 as the abnormality detection circuit detects that the FPGA 31 of the second sub control board 23 as the detected circuit is abnormal, and the second sub as the abnormality detection circuit. It is detected by the FPGA 31 of the control board 23 that the FPGA 31 of the first sub-control board 22 as the detected circuit is abnormal. That is, it is detected that the FPGA 31 of the first sub control board 22 is abnormal by both the FPGA 31 of the control boards 21 and 23 connected to the FPGA 31 of the first sub control board 22. For this reason, when the FPGAs 31 of the control boards 21, 22, and 23 are arranged in a row and connected adjacent to each other, the first sub-control board arranged between them by the FPGAs 31 of the control boards 21 and 23 on both sides. It is possible to detect twice that 22 FPGAs 31 are abnormal. As a result, it is possible to more reliably detect that the detected circuit is abnormal while efficiently arranging the FPGAs 31 of the control boards 21, 22, and 23.

  As a predetermined rule, an exclusive OR (XOR) is obtained for all the bits as input values for the value of the time counter TC expressed in binary. According to such a configuration, the reference value (signal value POUT) is set to “0” and “1” while avoiding the simple repetition of the reference value “0” and “1” by simple processing. Balance can be set.

  In addition, it is not limited to the said embodiment, For example, it can also deform | transform as follows and can implement.

  In the above-described embodiment, as a predetermined rule, an operation for obtaining an exclusive OR with respect to the value of the time counter TC expressed in binary numbers using all bits as input values is adopted. However, as a predetermined rule, an operation that inverts the logic level after the above operation is performed, or other operations can be adopted.

  In the above embodiment, the control boards 21, 22, and 23 are arranged in one row. However, four or more control boards may be arranged in one row, or four or more control boards may be arranged in two rows. Good. Further, the second sub control board 23 may be omitted, and the main control board 21 and the first sub control board 22 may be provided.

  The abnormality detection circuit may calculate the reference value and input the signal value POUT other than when the value of the time counter TC reaches a value of 4 (constant value) intervals starting from 0.

  The time counter TC is not limited to incrementing the counter value, but may be a counter decrementing the counter value.

  DESCRIPTION OF SYMBOLS 11 ... Motor, 12 ... Three-phase alternating current power supply, 15 ... Motor relay, 20 ... Controller, 21 ... Main control board, 22 ... 1st sub control board, 23 ... 2nd sub control board, 31 ... FPGA (abnormality detection circuit, Detected circuit), 32 ... power circuit, 34 ... first CPU (CPU), 33, 36 ... arithmetic circuit, 41 ... control circuit, 43 ... watchdog circuit.

Claims (5)

A first time counter that counts at a predetermined speed, calculates a 1-bit reference value according to a predetermined rule based on the value of the first time counter, and when the value of the first time counter reaches a predetermined value An abnormality detection circuit for detecting an abnormality on condition that the input 1-bit signal value does not match the reference value;
A second time counter that counts at the predetermined speed, calculates a 1-bit signal value according to the predetermined rule based on the value of the second time counter, and sets the value of the second time counter to the predetermined value; A detected circuit that outputs the calculated 1-bit signal value to the abnormality detection circuit,
A CPU for causing the abnormality detection circuit to start detecting the abnormality after matching the value of the first time counter and the value of the second time counter;
A robot controller comprising:   2. The robot controller according to claim 1, wherein the predetermined value is a value having a constant value interval between the value of the first time counter and the value of the second time counter. A first logic circuit that receives a command from the CPU and converts it into a signal that drives the first motor, and a signal that is connected to the first logic circuit and receives a command from the CPU and converts it into a signal that drives the second motor A second logic circuit that
The first logic circuit forms the abnormality detection circuit and inputs the signal value from the second logic circuit, and forms the detected circuit and outputs the signal value to the second logic circuit. And
The second logic circuit forms the detected circuit and outputs the signal value to the first logic circuit, and forms the abnormality detection circuit and inputs the signal value from the first logic circuit. The robot controller according to claim 1 or 2. A third logic circuit connected to the second logic circuit for receiving a command from the CPU and converting it into a signal for driving a third motor;
The second logic circuit forms the abnormality detection circuit and inputs the signal value from the third logic circuit, and forms the detected circuit and outputs the signal value to the third logic circuit. And
The third logic circuit forms the detected circuit and outputs the signal value to the second logic circuit, and forms the abnormality detection circuit and inputs the signal value from the second logic circuit. The robot controller according to claim 3.   5. The robot controller according to claim 1, wherein the predetermined rule is an operation for obtaining an exclusive OR with respect to a value of a time counter expressed in a binary number using all bits as input values. 6. .

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