JP2012150876A - Architecture for three-dimensional memory array - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology which compensates variation in a cell characteristic in an array and to provide a three-dimensional integrated circuit memory reducing complexity caused by level difference.SOLUTION: The technology which compensates variation of threshold voltage of a memory cell in the array by applying a different bias condition to a selected bit line is disclosed. A technology which minimizes difference of capacitance between global bit lines by connecting the global bit lines to the memory cells having a variety levels in the three-dimensional array is also disclosed.

Description

  The present technology relates to a high-density memory device in which variations in cell characteristics vary within the array, such as a memory device that provides a three-dimensional (3D) array by arranging a plurality of levels of memory cells.

  As the minimum linewidth of integrated circuit devices is reduced to the limits of general memory cell technology and the array becomes larger, the memory cells in the array have characteristics that change to affect the sensing margin. There is a possibility. In one trend to achieve high density, designers have sought technologies that achieve higher storage capacity and lower cost per bit. For example, in Non-Patent Document 1 and Non-Patent Document 2, thin film transistor technology is applied to charge trap memory technology.

In Non-Patent Document 3, the intersection array technology is applied to an antifuse memory. In the design described in Non-Patent Document 3, a plurality of levels of word lines and bit lines are provided, and a storage element is provided at the intersection. The storage element includes a p ⁺ polysilicon anode connected to the word line and an n ⁻ polysilicon cathode connected to the bit line, the anode and cathode being separated by an antifuse material.

  In three-dimensional arrays, differences in the electrical properties of structures at different levels can cause differences in programming, erase, and charge storage dynamics, as well as threshold voltage variations that correspond to the memory states of different levels of memory cells. There is sex. Therefore, in order to achieve the same threshold voltage within an acceptable margin for each level, the programming and erasing steps must be varied in some way with the level of the target cell. Such variations can cause memory cell durability problems and other complex problems.

  In a three-dimensional array, an access line, such as a global bit line, arranged to access an array of various levels is the capacitance or inductance encountered by the circuit coupled to the access line, depending on the cell being accessed. The layout can be variable based on the position (for example, which level of the array, etc.). For example, the global bit line typically extends to a decoder circuit used to read and write memory cells. Differences between vertical connectors to various levels and other differences between levels can vary the capacitance between global bit lines. These variations in capacitance affect the global bit line voltage during read, program, and erase operations, increasing the margin between programmed and erased states, or worst case There is a possibility that the sensing time will be delayed due to the capacitance of the device, which may cause the specification requirements.

Lai et al., “A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-type Flash Memory”, American Institute of Electrical and Electronics Engineers International Electronic Device Conference (IEEE Int 'l Electron Devices Meeting), December 11-13, 2006 Jung et al., “Three Dimensionally Stacked NAND-Type Flash Memory Technology Using Stacking, using a three-dimensional stacked NAND-type flash memory technology using a TANOS structure for a single-crystal Si layer on an ILD and a 30 nm super node. "Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node", IEEE Int'l Electron Devices Meeting, December 11-13, 2006 Johnson et al., "512-Mb PROM with a Three-Dimensional Array of Diode / Anti-fuse Memory cells (512-Mb PROM) with a three-dimensional array of diode / antifuse memory cells", Institute of Electrical and Electronics Engineers of America IEEE J. of Solid-State Circuits, Vol. 38, No. 11, November 2003

  Therefore, it is desirable to provide a technique for compensating for variations in cell characteristics in the array and to provide a three-dimensional integrated circuit memory that reduces the complexity caused by the level difference.

  This specification describes a technique for compensating for variations in threshold voltage between memory cells of an array by applying different bias conditions to selected bit lines.

  The compensation technique can be deployed in a memory architecture that includes a three-dimensional array and a memory architecture that does not include a three-dimensional array to manage dynamic cell characteristics that cause variations in threshold voltage.

  In a three-dimensional array, a level-dependent read operation is described that compensates for variations in threshold voltage between levels by applying different bias conditions to bit lines at each level of the array, preferably local bit lines.

  Also described is a technique for minimizing the capacitance difference between global bit lines by connecting access lines including global bit lines to memory cells of various levels in a three-dimensional array.

1 is a simplified block diagram of an integrated circuit including a NAND flash memory array operable as described herein. FIG. 1 is a schematic view of a portion of a three-dimensional NAND flash memory array. 1 is an exemplary perspective view of a portion of a three-dimensional NAND flash memory array. FIG. An example is shown in which the thickness of the semiconductor material strip forming the memory cell region at the lower level is greater than the thickness at the upper level. Fig. 4 shows an exemplary distribution of threshold voltages of many programmed memory cells at four different levels. 6 is a flowchart of an operation sequence for performing a level-dependent read operation as described herein. FIG. 5 is a schematic diagram of a circuit suitable for use in performing a level-dependent read operation on a selected memory cell. FIG. 8 is an exemplary timing diagram for operating the circuit shown in FIG. 7 to perform a level-dependent read operation. FIG. 5 is a layout diagram exemplarily showing connection of global bit lines to a plurality of blocks having memory cells at a plurality of levels. FIG. 10 is a sectional view of the vertical connector in the structure shown in FIG. 9. FIG. 10 is a sectional view of the vertical connector in the structure shown in FIG. 9. FIG. 10 is a sectional view of the vertical connector in the structure shown in FIG. 9. FIG. 10 is a sectional view of the vertical connector in the structure shown in FIG. 9. FIG. 2 is a simplified block diagram of an integrated circuit including a three-dimensional memory array having global bit lines coupled to a plurality of levels of memory cells, respectively. FIG. 3 is a schematic diagram illustrating a method of connecting a global bit line to a page buffer in one decoding structure. 1 is a perspective view of a three-dimensional NAND flash memory array structure having global bit lines coupled to memory cells at a plurality of levels, respectively. FIG. FIG. 17 is a layout diagram exemplarily showing connection of global bit lines to a plurality of multi-level blocks having memory cells arranged in the configuration shown in FIG. 16.

  This specification describes a technique for compensating for variations in threshold voltage between memory cells in an array by applying different bias conditions to selected bit lines.

  Compensation techniques can be deployed in memory architectures that include a three-dimensional array and can also be deployed in memory architectures that do not include a three-dimensional array to manage dynamic cell characteristics that cause threshold voltage variations. It is to provide.

  An integrated circuit device as described herein includes a memory array and a plurality of bias circuits. The bias circuit is selected within the physical configuration of the memory array by applying different bias conditions to the bit line for the selected memory cell while performing a read operation or other operation on the cell. It compensates for variations in threshold voltage that correlate with the position of the memory cell and that corresponds to the memory state of the memory cell in the array. Variations in these threshold voltages that correlate with the location of selected memory cells within the physical array of the memory array, such as variations that correlate with the level or plane of the memory cells in a three-dimensional array, are less than one bit per cell. It is distinguished from threshold voltage variations induced to set multiple threshold levels for storing more.

  Different bias conditions can be applied to multiple bit lines simultaneously, such as during page accesses where multiple cells of a page can be placed at different locations in the array. For the purposes of this specification, where a bias condition is applied by providing data from multiple memory cells over time in a read access in response to a single read command, such as during a page read. Bias conditions are applied “simultaneously”.

  A level-dependent read operation that compensates for variations in threshold voltage between levels by applying different read bias conditions to the local bit lines at each level of the array in a three-dimensional array will be described. A level-dependent read operation can be developed without applying different word line WL voltages. Alternatively, it can be deployed by combining different WL voltages in an array architecture that allows its operation.

  The integrated circuit described herein includes a memory array that includes a plurality of levels of memory cells. The levels in the plurality of levels include a local bit line and a memory cell coupled to the local bit line. The global bit lines are coupled to a corresponding set of local bit lines in the array. The integrated circuit includes a decoding circuit for selecting a memory cell in the memory array. The integrated circuit further includes a bias circuit coupled to the global bit line for providing a selected bias voltage. The bias circuit selects a bias voltage for the global bit line corresponding to the selected memory cell in response to the control signal.

  The present specification also describes a technique that allows global bit lines to be connected to various levels of memory cells in a three-dimensional array to minimize the capacitance difference between the global bit lines. In one aspect, connectors to various levels are arranged on the global bit line such that the level index statistical function (eg, sum, average, etc.) of the level coupled to each of the global bit lines is equal to a constant. To do.

  The integrated circuit described herein includes a plurality of blocks. A block in the plurality of blocks includes a plurality of levels L (z). Each level L (z) in the plurality of levels includes a two-dimensional array of memory cells having a plurality of word lines along a row and a plurality of local bit lines along a column coupled to the corresponding memory cell. . The integrated circuit further includes a plurality of global bit lines. The global bit line in the plurality of global bit lines includes a plurality of connectors. Connectors in multiple connectors coupled to any global bit line are coupled to corresponding local bit lines in multiple blocks. In the embodiment described here, on any global bit line, a corresponding local bit line in one block of the plurality of blocks is replaced with a corresponding local bit line in another block of the plurality of blocks. Are on different levels L (z). By coupling the same global bit line to different levels in different blocks along the line, the capacitance of the global bit line can be adjusted. Further, by applying this design method to a set of global bit lines sharing a plurality of blocks of memory cells, the capacitance of each member of the set of global bit lines can be made close to each other. The bias circuit can be coupled to a plurality of global bit lines that compensate for variations in threshold voltage corresponding to the memory state of the selected memory cell based on the level L (z) of the selected memory cell.

  Embodiments of the present invention will be described in detail with reference to FIGS.

  FIG. 1 is a simplified block diagram of an integrated circuit 175 that includes a NAND flash memory array 160 operable as described herein. In some embodiments, the array 160 can include multiple levels of cells. Row decoder 161 is coupled to a plurality of word lines 162 arranged along a row of memory array 160. The column decoder of block 166 is coupled via data bus 167 to the set of page buffers in this example. Global bit line 164 is coupled to local bit lines (not shown) arranged along a column of memory array 160. Addresses are provided on the bus 165 to the column decoder (block 166) and the row decoder (block 161). Data is sent to other systems 174 (eg, input / output ports, etc.) on an integrated circuit, such as a general purpose processor or a dedicated application circuit, via a data input line 173 or a system on chip (system on chip) supported by the array 160. a chip) is supplied from a combination of modules providing the function. Data is supplied via line 173 to an input / output port or other data destination inside or outside integrated circuit 175.

  A controller implemented as a state machine 169 in this example provides a signal to control the application of a bias array supply voltage generated or provided by a single power supply or multiple power supplies at block 168, and Various operations described herein are performed. These operations include erasing, programming, and performing level dependent reading with different read bias conditions for each level of the array 160. The controller can be implemented using a dedicated logic circuit known in the art. In an alternative embodiment, the controller includes a general purpose processor that executes a computer program to control the operation of the device, which may be implemented on the same integrated circuit. In still other embodiments, a combination of dedicated logic circuits and general purpose processors may be used to implement the controller.

  For clarity, the term “program” as used herein refers to an operation that raises the threshold voltage of a memory cell. The data stored in the programmed memory cell can be represented as a logic “0” or a logic “1”. As used herein, the term “erase” refers to an operation that lowers the threshold voltage of a memory cell. The data stored in the erased memory cell can be represented as the inverse of the programmed state, such as logic “1” or logic “0”. Also, to satisfy the designer, the multi-bit cell can be programmed to various threshold levels and erased to a single minimum threshold level or a single maximum threshold level. Further, the term “write” described herein describes the operation of changing the threshold voltage of a memory cell and is intended to include both programming and erasing.

  FIG. 2 is a schematic diagram of a portion of a three-dimensional flash memory array that can be used in a device such as the device of FIG. In this example, three levels of memory cells are shown, representing a block of memory cells that can include many levels.

A plurality of word lines including the word lines WL _n−1 , WL _n , WL _{n + 1} extend in parallel along the first direction. The word line is in electrical communication with the row decoder 261. The word lines are connected to the gates of the memory cells arranged in series as NAND strings. The word line WL _n represents a word line. As shown in FIG. 2, the word line WL _n is vertically connected to the gates of the respective memory cells at various levels below the word line WL _n .

A plurality of local bit lines are arranged along the columns to form NAND strings at various levels of the memory array. As shown in FIG. 2, the array includes the local bit line BL ₃₁ at the third level, the local bit line BL ₂₁ at the second level, and the local bit line BL ₁₁ at the first level. The memory cell has a charge trap structure between a corresponding word line and a corresponding local bit line. In this explanatory diagram, three memory cells are shown in one NAND string for easy understanding. For example, the NAND string formed by the third-level local bit line BL ₃₁ includes memory cells 220, 222, and 224. In typical implementations, a NAND string can comprise 16, 32, or more memory cells.

A plurality of string selection lines including the string selection lines SSL _n−1 , SSL _n , SSL _{n + 1} are electrically connected to a group decoder 258 (which may be a part of the row decoder 261) for selecting a group of strings. I'm in touch. The string select line is connected to the gate of a string select transistor arranged at the first end of the memory cell NAND string. As shown in FIG. 2, each of the string select lines is connected vertically to the gate of the column of each string select transistor at various levels. For example, the string selection line SSL _{n + 1} is connected to three levels of string selection transistors 210, 212, and 214.

  Local bit lines at a particular level are selectively coupled to extensions at a particular level by corresponding string select transistors. For example, a third level local bit line is selectively coupled to extension 240 by a corresponding string select transistor at that level. Similarly, the second level local bit line is selectively coupled to extension 242 and the first level local bit line is selectively coupled to extension 244.

Each level extension includes a corresponding contact pad for contacting a vertical connector coupled to a corresponding global bit line. For example, the third level extension 240 is coupled to the global bit line GBL _n−1 via the contact pad 230 and the vertical connector 200. Second level extension 242 is coupled to global bit line GBL _n through contact pad 232 and vertical connector 202. First level extension 244 is coupled to global bit line GBL _{n + 1} .

Global bit lines GBL _n−1 , GBL _n , GBL _{n + 1} are coupled to additional blocks (not shown) of the array and extend to page buffer 263. In this way, a three-dimensional decoding network is established that accesses a page of selected memory cells using one word line, all or some bit lines and one string select line. .

  The block select transistor is arranged at the second end of the NAND string. For example, the block select transistor 260 is arranged at the second end of the NAND string formed by the memory cells 220, 222, 224. The ground selection line GSL is connected to the gate of the block selection transistor. The ground selection line GSL is in electrical communication with the row decoder 261 and receives a bias voltage during the operations described herein.

  A block select transistor is used to selectively couple the second ends of all NAND strings in the block to a reference voltage provided to the common source line CSL. The common source line CSL receives a bias voltage from a bias circuit (not shown here) during the operations described herein. Depending on the operation described herein, the common source line CSL may be coupled to the other end of the NAND string rather than serving as a more traditional “source” at or near ground. Biased to a larger reference voltage.

  FIG. 3 illustrates an example portion of a three-dimensional NAND flash memory array in which a level dependent bias can be applied during a read operation to account for threshold voltage variations correlated to the level of a selected cell. FIG. In FIG. 3, the filler material has been removed so that the word lines and bit lines forming the three-dimensional array are visible.

The memory array is formed on an insulating layer 310 that covers an underlying semiconductor or other structure (not shown). The memory array functions as word lines WL ₁ and WL ₂ and includes a plurality of conductive lines 325-1 and 325-2 arranged for connection to a row decoder. The silicide layer can be formed on the upper surfaces of the conductive lines 325-1 and 325-2.

  Conductive lines 325-1 and 325-2 are conformal with semiconductor material strips that function as local bit lines at various levels. For example, the semiconductor material strip 312 functions as a local bit line at the third level, the semiconductor material strip 313 functions as a local bit line at the second level, and the semiconductor material strip 314 is local at the first level. Functions as a bit line. The semiconductor material strips are separated by an insulating layer (not shown).

  The semiconductor material strip may be a p-type semiconductor material. The conductive lines 325-1 and 325-2 may be semiconductor materials having the same or different conductivity types, or other conductive word line materials. For example, the semiconductor material strip can be made using p-type polysilicon or p-type single crystal silicon. On the other hand, the conductive lines 325-1 and 325-2 can be formed using p + type polysilicon doped with a relatively high density.

Alternatively, the semiconductor material strip may be an n-type semiconductor material. The conductive lines 325-1 and 325-2 may be semiconductor materials having the same or different conductivity types. This arrangement of the n-type strip becomes a buried channel type depletion layer type charge trap memory. For example, the semiconductor material strip can be made using n-type polysilicon or n-type single crystal silicon. On the other hand, the conductive lines 325-1 and 325-2 can be formed using p + type polysilicon doped with a relatively high density. A typical doping concentration for an n-type semiconductor material strip may be approximately 10 ¹⁸ / cm ³ , and in an available embodiment, within the range of 10 ¹⁷ / cm ³ to 10 ¹⁹ / cm ^3. Can do. The use of n-type semiconductor material strips is particularly beneficial in non-junction embodiments and allows higher read currents by improving electrical conductivity along the NAND string.

  The memory cell has a charge storage structure between the conductive lines 325-1 and 325-2 and a semiconductor material strip functioning as a local bit line. For example, the memory cell 380 is formed between the conductive line 325-1 and a semiconductor material strip that functions as a local bit line at the third level. In this explanatory diagram, two memory cells are shown in one NAND string for easy understanding. In the described embodiment, each memory cell has a double gate field effect with active charge storage regions on either side of the interface between the corresponding semiconductor material strip and conductive lines 325-1 and 325-2. It is a transistor.

In this example, the charge storage structure includes a tunnel layer, a charge trap layer, and a blocking layer. In one embodiment, the tunnel layer is a silicon oxide film (O), the charge storage layer is a silicon nitride film (N), and the blocking layer is a silicon oxide film (O). Alternatively, the memory cell includes other charge storage structures including, for example, silicon oxynitride (Si _x O _y N _z ), silicon rich nitride, silicon rich oxide, trap layers containing embedded nanoparticles, and the like. But it ’s okay.

  In one embodiment, using a bandgap operated SONOS (BE-SONOS) charge storage structure that includes a dielectric tunnel layer that includes a composite of materials that form an inverted “U” shaped valence band under zero bias. it can. In some embodiments, the composite tunnel dielectric layer includes a first layer called a hole tunnel layer, a second layer called a band offset layer, and a third layer called an isolation layer. The hole tunnel layer of the layer in this embodiment is, for example, a semiconductor using in situ generated water vapor (ISSG) method with post-deposition NO annealing or any nitride formation by adding NO to the atmosphere during deposition. Contains silicon dioxide formed on the sides of the material strip. The thickness of the first layer of silicon dioxide is preferably less than 20 mm and not more than 15 mm. The thickness in the exemplary embodiment is 10 mm or 12 mm.

The string selection lines SSL _n and SSL _{n + 1} are connected to the gate of the string selection transistor at the first end of the memory cell NAND string. A string select transistor is formed between the semiconductor material strip of the corresponding NAND string and the multi-level string gate structure. For example, the string selection transistor 350 is formed between the semiconductor material strip 312 and the string selection gate structure 329, and the string selection gate structure 329 is coupled to the string selection line SSL _n via the contact plug 365.

  The semiconductor material strip is selectively coupled to another semiconductor material strip at the same level by the extension. For example, the third level semiconductor material strips are selectively coupled to each other via the extension 340. Similarly, the second level semiconductor material strips are selectively coupled to each other via an extension 342 and the first level semiconductor material strip is selectively coupled to the extension 344.

Third level extension 340 is coupled to global bit line GBL _n−1 through contact pad 330 and vertical connector 300. Second level extension 342 is coupled to global bit line GBL _n through contact pad 332 and vertical connector 302. Third level extension 344 is coupled to global bit line GBL _{n + 1} .

Global bit lines GBL _n−1 , GBL _n , GBL _{n + 1} are coupled to additional blocks (not shown) of the array and extend to page buffer 263.

  The block select transistor is arranged at the second end of the NAND string. For example, the block select transistor 351 is arranged at the second end of the NAND string formed by the semiconductor material strip 312. A gate structure 349 that functions as the ground selection line GSL is connected to the gate of the block selection transistor.

  A block select transistor is used to selectively couple the second ends of all NAND strings in the block to a reference voltage provided on a common source line CSL 370. The common source line CSL370 extends in parallel with the word line.

  The structure illustrated in FIG. 3 is, for example, U.S. Patent Application No. 13 filed January 31, 2011, which is incorporated herein by reference as if set forth in its entirety. / 018,110 can be used for manufacturing.

  In operation, each memory cell stores a data value based on its threshold voltage. Reading or writing the selected memory cell can be accomplished by applying an appropriate voltage to the word line, bit line, string select line, ground select line, common source line.

  In the programming operation, an appropriate voltage is applied to induce electron tunneling to the charge storage layer of the selected memory cell. The programming operation increases the threshold voltage of the selected memory cell. The selected memory cell may be programmed using, for example, the Fowler-Nordheim (FN) electron tunnel effect.

  In the erase operation, an appropriate voltage is applied to induce a hole tunnel phenomenon to the charge storage layer of the selected memory cell or an electron tunnel phenomenon from the charge storage layer. The erase operation reduces the threshold voltage of the selected memory cell.

  In the read operation, an appropriate read voltage is applied, so that a current flowing through the selected memory cell can be sensed. The data value can be determined based on the current flowing through the selected memory cell during the read operation. The read voltage is selected so that erased memory cells are turned on (ie, conducting current) during a read operation and programmed memory cells remain off (ie, passing little or no current). You may do it.

  In a three-dimensional array, the difference in level becomes a difference in charge storage dynamics, which can lead to variations in threshold voltages corresponding to the memory states of memory cells at various levels. FIG. 4 shows an example where the thickness of the semiconductor material strip that forms the channel region of the memory cell at the lower level is thicker than the thickness at the upper level. This difference in channel thickness may be caused by the etching process used to form the device.

  If the same programming and erasing operations are used for each level of the memory cell, the channel thickness difference and the level difference can widen the distribution of the threshold voltage of the memory cell at various levels. FIG. 5 exemplarily shows the threshold voltage distribution for a number of programmed memory cells at four different levels. In the example shown in FIG. 5, level 4 programmed memory cells have a threshold voltage within a distribution 500 that is generally higher than the distribution 510 of level 1 programmed memory cells.

  Thus, in order to achieve the same threshold voltage for a particular memory state for each level of memory cells, the programming and erasing steps should be configured to vary with the level of the memory cell selected in some way. Can do. This can cause memory cell durability problems and other complex problems.

  In addition, when the same read operation is used for each level, the read margin between the programmed state and the erased state is reduced due to variations in threshold voltages of memory cells at various levels. The narrower the read margin, the more complicated the circuit is required, and the read process may be delayed.

One technique to achieve a wider read margin is to apply a low word line voltage to read and verify lower level memory cells and to apply a high word line voltage to read and verify upper level memory cells There is something to do. This approach is represented in FIG. 5 by four different lines for the read voltage labeled V _READ and four different lines for the program verify voltage labeled V _PV . However, since the word lines are coupled to the memory cells at each level in the array configuration shown in FIGS. 2 and 3, applying different word line voltages based on the level of the selected memory cell allows Prevents simultaneous reading of memory cells.

  The level-dependent read operation described herein compensates for threshold voltage variations by applying different read bias conditions to the bit lines for accessing cells at each level of the array 160, thus providing different levels. Even if the threshold voltages for the memory cells at different levels are different, the current of the read operation bit line remains within a narrower distribution range. By doing so, the techniques described herein can keep the read margin between the programmed and erased states for each level relatively wide without requiring different read word line voltages. it can.

  FIG. 6 is a flowchart of an operation sequence 600 for performing a level-dependent read operation as described herein.

  In step 610, a read command for a particular address is received.

  In step 620, the address is decoded by the decoder circuit to identify the physical location of the selected memory cell associated with the address, such as the level in the three-dimensional embodiment. The decoder circuit generates a control signal indicating the position of the memory cell selected corresponding to the address.

  In step 630, the bias circuit precharges the bit line of the selected memory cell in response to the control signal to a voltage level that depends on the position or level of the selected memory cell.

  In step 640, a read operation is performed on the selected memory cell to determine the stored data value. In step 650, the data is output from the page buffer.

  FIG. 7 is a schematic diagram of a circuit suitable for use in performing a level dependent read operation on a selected memory cell 700. In this example, reading is level dependent. In another example, the read is a selected memory cell that is within the range of another sector or segment in a three-dimensional or two-dimensional array, with the read characteristic that cells within the sector or segment are within a specific range. Can depend on the position of.

  The selected memory cell 700 is part of a NAND string formed by local bit lines BL710 at a particular level of the array. The NAND string also includes a memory cell 702 and a memory cell 704. String select transistor 712 selectively couples bit line 710 to global bit line 720 via contact pad 714 and vertical connector 716. The gate of the string selection transistor 712 is connected to the string selection line SSL718.

  Block select transistor 706 couples the second end of the NAND string to common source line CSL 708.

  Global bit line 720 is coupled to sensing circuit 730 via a page buffer circuit for global bit line 720 by a column decoder circuit (not shown). The signals BLCLAMP, VBOOST, BLPWR, BLPRECHG, and PBEN control the timing and execution of the read operation including the power supply, the precharge interval, and the sensing interval, as described below with reference to the timing diagram of FIG. Provided by the control logic (represented schematically by boxes 750-754). Cell location information used to generate VBOOST and BLCLAMP signals as described below using a cell location decoder 760 based on the location of a selected memory cell or other sector or segment at a particular level in the array I will provide a. In some embodiments, cell position decoder 760 is the same circuit used for planar decoding for a three-dimensional array (see, eg, FIG. 15).

  Clamp transistor M1 is coupled between global bit line 720 and data line DLIB. The signal BLCLAMP is connected to the gate of the clamp transistor M1.

  Precharge transistor M2 has a first terminal connected to data line DLIB, a second terminal coupled to bit line power BLPWR signal, and a gate coupled to signal BLPRECHG. The controllable power supply 752 applies the BLPWR signal at a voltage level and timing determined by the control sequence being executed. The control circuit 753 applies the BLPRECHG signal at a voltage level and timing determined by the control sequence being executed.

  Signal VBOOST is also coupled to data line DLIB through capacitor C1. The controllable power source 751 applies the VBOOST signal at a voltage level and timing determined by the control sequence being executed.

  The enable transistor M3 is arranged between the data line DLIB and the amplifying circuit 740 based on the latch. The control signal PBEN is connected to the gate of the enable transistor M3. Control logic 754 applies the PBEN signal at a voltage level and timing determined by the control sequence being executed.

  FIG. 8 is an exemplary timing diagram for performing a level-dependent read operation on the selected memory cell 700 by operating the circuit shown in FIG. A control circuit on the integrated circuit is arranged to control a bias circuit, a word line, and other circuits of the memory array as shown in FIG. 8, thereby causing a sequence during a read operation.

  When the read operation is initialized, control signals BLCLAMP, VBOOST, BLPWR, BLPRECHG, and PBEN are applied to control the timing of the read operation.

  In time interval T0, word lines WL0 and WL2 coupled to the gates of unselected memory cells 704 and 702 are charged to a voltage value VPASSR sufficient to turn on unselected memory cells 704 and 702. Word line WL1 coupled to the gate of selected memory cell 700 is charged up to voltage value VREAD. VREAD is sufficient to turn on the selected memory cell 700 in the erased state (for one bit cell) and insufficient to turn on the selected memory cell 700 in the programmed state. . In the described embodiment, the voltage value VREAD is substantially the same for each level of the memory cell. Charging the string select line 718 to a high value turns on the string select transistor 712. The ground selection line GSL is set to a low value to turn off the block selection transistor 706.

  The selected local bit line 710 is discharged to ground through M1 and M2 by setting the controllable voltage BLCLAMP and the timing signal BLPRECHG to a high level and setting the controllable voltage BLPWR to ground. The common source line CSL is charged to a high level and charges an unselected local bit line (not shown). Unselected bit lines are precharged to the level of the common source line CSL via the respective bias circuits.

  In the time interval T1, the BLPWR signal is changed to an intermediate voltage value such as 2.3 volts and the data line DLIB is charged through M2. The BLCLAMP signal is biased to a voltage value VBLCLAMP1 based on the level of the selected memory cell 700. Different bias levels (in this architecture correspond to the selected memory cell) to provide different criteria determined by the selected memory cell, as represented by the four lines in the timing diagram for the value of VBLCLAMP1. Used) at each array level. That is, bit lines at different levels in the array are precharged to different voltage levels. In this way, different precharge bit line levels can compensate for threshold voltage differences between cells at different levels. The precharged bit line voltage level BL is given by the difference between VBLCLAMP1 and the threshold voltage of transistor M1 at time interval T1.

  In the time interval T2, the selected bit line 710 and data line DLIB are floated by setting the BLCLAMP signal and the BLPRECHG signal to a low level and turning off M1 and M2. By charging the ground selection line GSL to a high level and turning on the block selection transistor 706, the second end of the NAND string is coupled to the common source line CSL 708 (the level remains high). In the BL timing diagram, the selected bit line 710 has a branch line in a high threshold voltage HVT memory state (flat because the current is cut off) and a low threshold voltage LVT memory state (because current flows from CSL to DLIB). As shown by the four lines having the (increase) branch line, the battery is charged based on the cell current flowing through the selected memory cell 700. In part at time interval T2, the voltage level of data line DLIB is boosted to a higher voltage by applying a different voltage level (VBOOST1) to the VBOOST signal based on the level of selected memory cell 700. Also good. As a result, as represented by the four lines in the VBOOST and DLIB timing diagrams, the voltage swinging on the data line DLIB at the time interval T3 can be further increased.

  In part at the time interval T3, the control signal BLCLAMP is biased to the voltage value VBLCLAMP2. VBLCLAMP2 is also based on the level of the selected memory cell 700, as represented by the four lines in the VBLCLAMP2 timing diagram. The voltage value of VBLCLAMP2 can be larger than the value of the voltage value VBLCLAMP1 applied at the time interval T1. For example, VBLCLAMP2 may be 0.2 volts greater than VBLCLAMP1 for any selected memory cell.

  If after time interval T2, the selected bit line 710 is charged to a voltage lower than the value of VBLCLAMP2 minus the threshold voltage of M1, M1 is turned on when VBLCLAMP2 is applied. As a result, the selected bit line 710 is coupled to the data line DLIB, and the voltage level therebetween becomes equal as seen in the region 800 on the DLIB wiring in FIG. If after time interval T2, the selected bit line 710 is charged to a voltage higher than the value of VBLCLAMP2 minus the threshold voltage of M1, M1 turns off. As a result, the voltage level of the data line DLIB is maintained.

  After setting the voltage level on the data line DLIB, the signal VBOOST is set to a low value to provide a DLIB level suitable for latch setting at the sense amplifier. The sense amplifier can sense data based on the voltage of DLIB at the time interval just before or before the end of time interval T3.

  At time T4, all signals are restored to the initial state.

  Thus, the described integrated circuit includes a plurality of bit lines, each having a memory array coupled via a respective clamp transistor to a corresponding data line from a set of data lines coupled to a corresponding sensing circuit, The circuit responds to the timing signal during the read operation of the selected memory cell of the memory array, and applies a bias voltage to the control terminal of the precharge circuit connected to the data line and the clamp transistor depending on the selected memory cell. Includes bias power supply to be applied.

The memory array of this example includes a plurality of NAND strings each having a ground selection transistor and a string selection transistor, a ground selection line and a string selection line, and a word line, and includes a control circuit and a bias circuit coupled to the memory array. And a NAND array that initiates a sequence that can be simultaneously applied to a NAND string of a selected page of memory cells for a read operation of the selected cell in the selected NAND string. The sequence includes the following:
At the first time interval T0, the word line coupled to the NAND string selected to the target level for reading is charged, and the precharge circuit is activated while the ground selection transistor is off and the string selection transistor is on. The bit line to a low reference voltage via
At a second time interval T1, the data line and the selected NAND string are precharged by applying a first clamp voltage to the clamp transistor depending on the selected memory cell by precharging the data line to the read reference voltage. Are precharged to a level determined by the selected memory cell,
At a third time interval T2, the clamp transistor is turned off to disconnect the precharge circuit from the data line, the ground selection transistor is turned on while the read bias voltage is applied to the source line,
At a fourth time interval T3, a second clamp voltage greater than the first clamp voltage is applied to a clamp transistor depending on the selected memory cell to sense the level of the data line and to select the selected memory Indicates the value of the data stored in the cell.

  In the embodiment described here, the bias circuit includes a booster circuit that is responsive to a timing signal during a read operation and is capacitively boosted to the data line by a boost amount coupled to the data line. The boost power supply is coupled to the booster circuit to set the boost amount determined by the selected memory cell, and a boost voltage is applied to the sequence before sensing the data line level at or before the fourth time interval. Boosting the data line.

  The read operations described herein can be applied to memory architectures that include a three-dimensional array and memory architectures that do not include a three-dimensional array, in an array architecture that allows or does not apply different WL voltages. By combining with different WL voltages, it is possible to manage dynamic cell characteristics that cause variations in threshold voltage.

  As described above, in a three-dimensional array, global bit lines are coupled to local bit lines of various levels of memory cells through vertical connectors and contact pads.

  Differences in vertical connectors and contact pads to different levels and level differences can cause differences in overall capacitance between global bit lines. For example, referring back to FIG. 3, contact pad 330 and level 3 vertical connector 300 have different capacitances than contact pad 332 and level 2 vertical connector 302. These differences can cause variations in the overall capacitance of the global bit line, which in turn can reduce the read margin in terms of both speed and voltage and current magnitude, Other properties may be affected.

FIG. 9 is a layout diagram exemplarily showing connection of global bit lines GBL _{1 to} GBL ₈ to a plurality of blocks having memory cells of a plurality of levels. 10 to 13 show cross-sectional views of the vertical connector of each block.

  Each of the blocks includes a plurality of levels having a respective two-dimensional array of memory cells. Each two-dimensional array of memory cells includes a plurality of word lines and a plurality of bit lines coupled to corresponding memory cells of the array. For example, the two-dimensional array may be implemented in a NAND configuration as described above. Alternatively, other array configurations may be used.

  The block size and the number of blocks vary depending on the embodiment. Depending on the embodiment, the size of each block can be, for example, 2 KB (kilobytes), 4 KB, 8 KB, or 16 KB.

Global bit lines GBL ₁ -GBL ₈ are coupled to local bit lines (not shown) in blocks at various levels via vertical connectors. In this example, each of the blocks includes four levels for clarity. The level at which the vertical connector couples the global bit lines it covers is indicated by level indices 1, 2, 3, 4. For example, the global bit line GBL ₁ is coupled to a local bit line in the first level of the memory block BlockN-1 via a level 1 connector, and in the second level of the memory block BlockN via a level 2 connector. The local bit line is coupled to the local bit line in the third level of the memory block BlockN + 1 through the level 3 connector, and is coupled to the local bit line in the fourth level of the memory block BlockN + 2 through the level 4 connector. Combined.

  In this example, the vertical connector for each block can be implemented by arranging the contact pads at each level like a step of steps as shown in FIG. 3 "stepped connector structure to local bit line" ”In the area marked“

By coupling each of the global bit lines GBL _{1 to} GBL ₈ to various levels of the entire array, the capacitance difference between the global bit lines GBL _{1 to} GBL ₈ can be reduced.

In the illustrated embodiment, the connectors are arranged such that the sum of the level indices of the corresponding local bit lines for each of the global bit lines GBL ₁ -GBL ₈ is equal to a constant. Alternatively, the connectors may be arranged such that other statistical functions of the level index, such as the average, are equal to a constant. In general, the connectors may be arranged to select variations in capacitance between global bit lines to suit a particular embodiment.

Thus, the capacitance difference between the global bit lines GBL _{1 to} GBL ₈ can be reduced, or can be controlled within a selected limit range. Thereby, the read margin between the programmed state and the erased state can be widened.

  FIG. 14 is a simplified block diagram of an integrated circuit 1475 that includes a three-dimensional memory array 1460 having global bit lines coupled to a plurality of levels of memory cells, respectively. Row decoder 1466 is coupled to a plurality of word lines 1462 arranged along a row of memory array 1460. Column decoder 1466 is coupled to page buffer 1463 via data bus 1467 in this example. Planar decoder 1464 is coupled to page buffer 1463. Global bit line 1464 is coupled to local bit lines (not shown) arranged along various levels of columns of memory array 1460. The address is supplied to the column decoder 1466, the row decoder 1461, and the planar decoder 1464 on the bus 1465. Data is supplied via line 1473 from an input / output port or other data source internal or external to the integrated circuit. In the illustrated embodiment, other circuits 1474 are included in an integrated circuit, such as a general purpose processor or a dedicated application circuit, or a combination of modules that provide system-on-chip functionality supported by the array 1460. Data is supplied via line 1473 to an input / output port or other data destination inside or outside the integrated circuit.

  A controller implemented in this example as state machine 1469 provides a control signal to control the application of a bias array supply voltage generated or provided via a single power supply or multiple power supplies at block 1468. Various operations described herein are performed, such as erasing, programming, and level-dependent reading with different read bias conditions for each level of array 1460. In addition, the controller 1469 and block 1468 can include bias circuitry and logic represented by blocks 750-754 in FIG. The controller can be implemented using a dedicated logic circuit known in the art. In an alternative embodiment, the controller includes a general purpose processor that executes a computer program to control the operation of the device, which may be implemented on the same integrated circuit. In still other embodiments, a combination of dedicated logic circuits and general purpose processors may be used to implement the controller.

FIG. 15 is a schematic diagram showing a method of connecting the global bit lines GBL _{1 to} GBL ₈ to page buffers 1511 to 1518 whose combinations correspond to the page buffer 1463 of FIG. The page buffers 1511 to 1518 can include, for example, a circuit such as the circuit of FIG. In an embodiment that includes a bias circuit that compensates for a bit line that is biased against a cell location, the page buffer includes a clamp transistor, a boost capacitor, a latch, and a charging circuit for the bit line power supply.

  A planar decoder, such as planar decoder 1464 of FIG. 14, includes a switch circuit coupled to a plurality of global bit lines, and a global bit line selected based on the level L (Z) of the memory cell whose bias voltage is selected. Apply to. This switch circuit in this example includes voltage switches 1500, 1502, 1504, 1506. In this example, when a read operation is initialized for an address, planar decoder 1464 decodes the address and identifies the physical location, block, and level of the selected memory cell associated with the address. The switch circuit can be configured to simultaneously apply a bias voltage via a voltage switch to a global bit line selected to access a page of memory cells.

The voltage switches 1500, 1502, 1504, 1506 receive different voltage signals Vsource1, Vsource2, Vsource3, Vsource4 generated or provided through a single power supply or multiple power supplies in block 1468 (see FIG. 14). The voltage switches 1500, 1502, 1504, and 1506 output one of the voltage signals Vsource1, Vsource2, Vsource3, and Vsource4 as the control signal BLCLAMP that depends on the level described above. A level-dependent control signal BLCLAMP is provided to a clamp transistor (not shown) in the page buffer circuit coupled to the global bit lines GBL ₁ -GBL ₈ . As described above, the level-dependent control signal BLCLAMP precharges the global bit line and local bit line of the selected memory cell during the level-dependent read operation described herein.

  In FIG. 15, since each of the page buffers 1511 to 1518 is coupled to different global bit lines, a wide and parallel read operation is possible.

In the example described, the global bit lines GBL ₁ and GBL ₈ are connected to different sets of bit lines in the same level in each block. Therefore, the output of voltage switch 1500 is provided to both page buffer 1 (1511) coupled to global bit line GBL ₁ and page buffer 2 (1515) coupled to global bit line GBL ₈ .

  FIG. 16 shows another example of a three-dimensional flash memory array structure that has global bit lines coupled to memory cells at multiple levels, and can apply a level dependent bias as described herein. It is a perspective view. In this example, four levels of memory cells are shown, which is representative of a block of memory cells that can include many levels.

  The insulating material has been omitted from the drawing to make the additional structure visible. For example, the insulating layer is omitted between raised stacks of semiconductor strips and is also omitted between raised stacks of semiconductor strips.

A multilayer array is formed on the insulating layer, and the multilayer array includes word lines WL _n , WL _n−1 ,. . . As a plurality of raised stacks conforming to a plurality of raised stacks. . . , 1625-n-1, 1625-n. The plurality of raised stacks includes semiconductor strips that function as local bit lines. Semiconductor strips of the same level are electrically coupled together by an extension having contact pads arranged in a staircase pattern.

  The numbering indicated by the word lines in ascending order from 1 to N from the back to the front of the overall structure also applies to the memory page. For odd memory pages, the word line numbering is descending from N to 1 from the back to the front of the overall structure.

As shown, the extended portions 1602, 1603, 1604 and 1605 at the first end of the block are electrically connected to different global bit lines GBL _{1 to} GBL ₄ . Similarly, the extended portions 1652, 1653, 1654, and 1655 are electrically connected to different global bit lines GBL _{1 to} GBL ₄ .

  Any stack of semiconductor strips is coupled to either extension 1602, 1603, 1604, 1605 or extension 1652, 1653, 1654, 1655, but not to both. The stack of semiconductor strips has one of two opposite directions: the direction from the end of the bit line to the end of the source line and the direction from the end of the source line to the end of the bit line.

  A stack of semiconductor strips terminated at one end by extensions 1652, 1653, 1654, 1655 comprises an SSL gate structure 1619, a ground selection line GSL1626, word lines 1625-1WL-1625-NWL, and a ground selection line GSL1627. And terminated at the other end by a source line 1628. These stacks of semiconductor strips do not reach the extensions 1602, 1603, 1604, 1605.

  A stack of semiconductor strips terminated at one end by extensions 1602, 1603, 1604, 1605 comprises an SSL gate structure 1609, ground select lines GSL1627, word lines 1625-NWL to 1625-1WL, ground select lines GSL1626. And is terminated at the other end by a source line 1628 (hidden by other parts of the figure). These stacks of semiconductor strips do not reach the extensions 1652, 1653, 1654, 1655.

  The charge storage structure separates the word lines 1625-1 to 1625-n from the semiconductor strip. The ground select lines GSL 1626 and GSL 1627 are conformal to multiple raised stacks, similar to word lines.

The global bit lines GBL _{1 to} GBL ₄ are formed in the metal layers ML1, ML2, and ML3. Although hidden by the other parts of the figure, in the example shown, each global bit line GBL ₁ -GBL ₄ is coupled to a block of two different levels of memory cells. For example, in the figure, the global bit line GBL ₁ is coupled to an extension 1605 connected to a set of semiconductor strips that function as local bit lines at the fourth level, and functions as local bit lines at the first level. Coupled to an extension 1652 connected to a set of semiconductor strips. This is further discussed below in FIG.

FIG. 17 is a layout diagram exemplarily showing connection of global bit lines GBL _{1 to} GBL ₈ to a plurality of multi-level blocks having memory cells arranged in the configuration shown in FIG.

Global bit lines GBL ₁ -GBL ₈ are coupled to local bit lines (not shown) in various level blocks via vertical connectors. In this example, each of the blocks includes four levels for clarity. The level at which the vertical connector couples the global bit lines it covers is indicated by level indices 1, 2, 3, 4.

For example, the global bit line GBL ₁ is coupled to a set of local bit lines in the first level of the memory block BlockM via a level 1 connector, and is connected to the second level of the memory block BlockM via a level 2 connector. To a set of local bit lines in the memory block BlockM + 1 via a level 3 connector.

  The vertical connector for each block is described as “stepped connector structure to local bit line” that can be implemented by arranging the contact pads of each level like the steps of steps as shown in FIG. Is in the area.

In the example of FIGS. 16 and 17, the global bit lines GBL _{1 to} GBL ₈ are patterned on the third metal layer, and the string selection lines SSL _{1 to} SSL ₈ are patterned on the first and second metal layers. Is done. The string select line is coupled to the string select transistors at the alternating ends of the block via a first metal segment parallel to the underlying string and a second metal segment parallel to the word line. In the block M, the segments parallel to the word lines are denoted as SSL ₁ to SSL ₈ in the explanatory diagram. Vertical connections between metal layers are indicated by a “marked” box. The word lines WL _x and the even and odd ground selection lines GSL ₁ and GSL _{2 at} the top and bottom of each block are, in this example, patterned conductor layers such as polysilicon layers below the first metal layer. Implemented.

  While the invention has been disclosed with reference to the preferred embodiments and examples detailed, it is understood that these illustrations are intended to be illustrative rather than limiting. Those skilled in the art will readily be able to make modifications and combinations that are within the spirit of the invention and within the scope of the following claims.

160 NAND Flash Memory Array 161 Row Decoder 163 Page Buffer 165 Address 166 Column Decoder 168 Bias Array Supply Voltage 169 State Machine 174 for Program, Erase and Level Dependent Read Operations Other Circuits

Claims (12)

A memory array;
An integrated circuit device comprising: a bias circuit that compensates for variations in threshold voltage corresponding to the memory state of the memory cells in the array by applying different bias conditions to selected bit lines.   The memory array includes a plurality of bit lines coupled via a respective clamp transistor to a corresponding data line in a set of data lines coupled to a corresponding sensing circuit, and the bias circuit includes the memory array A bias voltage is applied to a precharge circuit connected to the data line and a control terminal of the clamp transistor depending on the selected memory cell in response to a timing signal during a read operation of the selected memory cell. The integrated circuit of claim 1 including a bias power supply. The memory array includes a plurality of NAND strings each having a ground selection transistor and a string selection transistor, a ground selection line and a string selection line, and a word line, and a control circuit and a bias circuit coupled to the memory array. Including a NAND array that initiates a sequence for the read operation of the selected cell in a selected NAND string, the sequence comprising:
Charging the word line coupled to the selected NAND string to a target level for reading at a first time interval T0, while the ground select transistor is off and the string select transistor is on Discharging the bit line through the precharge circuit to a low reference voltage;
At a second time interval T1, the data line is precharged to a read reference voltage and a first clamp voltage is applied to the clamp transistor depending on the selected memory cell, thereby allowing the data line and the data line Pre-charging the bit line of the selected NAND string to a level determined by the selected memory cell;
At a third time interval T2, the clamp transistor is turned off to disconnect the precharge circuit from the data line, and the ground selection transistor is turned on while a read bias voltage is applied to the source line,
At a fourth time interval T3, a second clamp voltage larger than the first clamp voltage is applied to the clamp transistor that depends on the selected memory cell to sense the level of the data line; The integrated circuit according to claim 2, wherein the integrated circuit indicates a value of data stored in the selected memory cell.   The bias circuit is responsive to a timing signal during the read operation and is coupled to the data line and capacitively boosts the voltage of the data line according to a boost amount, and is coupled to the boost circuit and the boost circuit. A boost power supply for setting the boost amount determined by the selected memory cell, and applying a boost voltage to the sequence before sensing the level of the data line at or before the fourth time interval The integrated circuit according to claim 3, further comprising boosting the data line.   The integrated circuit of claim 1, wherein the word line voltage applied to the memory cells of the array is substantially the same during the different bias conditions. A block therein has a plurality of levels L (z), each of the levels L (z) in the plurality of levels includes a two-dimensional array of memory cells, and each of the two-dimensional arrays is a corresponding in the array A plurality of blocks including a plurality of local bit lines coupled to memory cells to be
A global bit line in the plurality of connectors includes a plurality of connectors, and the connectors in the plurality of connectors are coupled to arbitrary global bit lines coupled to corresponding local bit lines in the plurality of blocks. A plurality of global bit lines in which the corresponding local bit line in one block is on a different level L (z) from the corresponding local bit line in the other block of the plurality of blocks;
An integrated circuit coupled to the plurality of global bit lines and configured to apply a respective bias voltage to the corresponding global bit line based on the level L (z) of the selected memory cell. circuit.   Each of the plurality of blocks has N levels L (z) (level index z = 1 to N), and the connector includes level index statistics for the level L (z) of the corresponding local bit line. The integrated circuit according to claim 6, wherein the function is arranged on each global bit line of the plurality of global bit lines so that a function is equal to a constant.   The bias circuit coupled to the switch circuit for compensating a variation in a threshold voltage corresponding to a memory state of the selected memory cell based on the level L (z) of the selected memory cell. An integrated circuit as described.   The integrated circuit of claim 6, comprising a buffer coupled to the plurality of global bit lines and the switch circuit. A memory array including a local bit line and a plurality of levels of memory cells including memory cells coupled to the local bit line;
A global bit line coupled to a corresponding set of local bit lines of the array;
A decoding circuit for selecting memory cells at the plurality of levels;
A bias circuit coupled to the global bit line to provide a selected bias voltage and selecting a bias voltage of the global bit line corresponding to the level of the selected memory cell in response to a control signal; Integrated circuit including.   The integrated circuit of claim 10, wherein the set of local bit lines coupled to any one of the global bit lines includes local bit lines at a plurality of levels of the memory array.   The global bit line is coupled to a corresponding data line in a set of data lines coupled to a corresponding sensing circuit via a respective clamp transistor, and the bias circuit is connected to a selected memory in the memory array. Bias power supply for applying a bias voltage to a precharge circuit connected to the data line and a control terminal of the clamp transistor depending on the level of the selected memory cell in response to a timing signal during a cell read operation The integrated circuit according to claim 10, comprising:

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