JP2012150723A - Design verification program, design verification device, and design verification method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve verification accuracy and reduce analysis man-hours in assertion-based verification.SOLUTION: In design verification processing for causing a computer to verify whether or not a result of logic simulation executed by a logic circuit described in a hardware description language complies with an assertion described as a design specification of the logic circuit, the computer executes: a test pattern generation step for generating a test pattern including at least one request; an expectation information generation step for, with respect to each generated request, generating expectation information where each request is associated with an assertion expected to be executed to each request; and a consistency determination step for, with respect to each generated request, determining consistency between the assertion executed to each request and the assertion in the expectation information set to each request.

Description

  The present invention relates to a technique for verifying design specifications of a logic circuit described in a hardware description language, and more particularly to a design verification program, a design verification apparatus, and a design verification method for verifying the design specifications of a logic circuit by assertion-based verification. .

  In designing a logic circuit using a hardware description language (HDL), design specifications are verified by logic simulation of the created RTL (Resister Transfer Level) description. For the specification verification, assertion-based verification for monitoring the violation operation with the design specification of the verification circuit as the expected operation is widely used.

  Assertion-based verification is a verification method that uses a function (assertion) to output an error when an operation that violates this is defined by using an assertion language to define circuit operations based on design specifications. It is determined whether a signal corresponding to the expected operation is output for the input operation (request). If the execution result of the assertion violates the expected operation, an error is output (for example, patent document) 1, 2, and 3).

JP 2009-41922 A JP 2008-158696A JP 2005-108007 A

  Since the test patterns for assertion become enormous in proportion to the increase in the scale and function of the verification circuit, a large number of test patterns are automatically generated by any parameter setting by the tool. An assertion is performed on the test pattern.

  However, conventionally, the operation of the test pattern and the operation of the assertion are not associated with each other and operate independently. For this reason, for example, since the assertion is determined by the input / output operation of the verification circuit based on the test pattern, verification regarding consistency such as whether the operation expected by the test pattern matches the input / output operation of the verification circuit is performed. However, sufficient verification accuracy is not ensured. Specifically, even if the operation expected by the test pattern is lost in the input / output operation of the verification circuit, an error cannot be detected based on the assertion determination result. For example, for 10 test patterns, if the output operation of one verification circuit is missing due to some error cause, and 9 normal judgments are made based on the assertion judgment result, the normal only assertion judgment result Cannot detect errors for omissions. In addition, when there are 11 assertion judgments including the output operation of an extra verification circuit for 10 test patterns due to some error cause, and all normal judgments are made, the result of the assertion judgment only for normality From the above, no extra error can be detected for the output of the verification circuit.

  In addition, among a large number of automatically generated test patterns, errors are analyzed only with a part of the operation results that are the locations where errors occurred. For this reason, the state of the verification circuit when an error occurs cannot be properly grasped, and it takes a lot of analysis steps to identify the cause of the error, resulting in a decrease in work efficiency. In particular, if there is a time lag between the cause of the error and the occurrence of the error due to the error, the man-hours for analysis further increase.

  Accordingly, an object of the present invention is to provide a design verification program, a design verification apparatus, and a design verification method capable of improving verification accuracy and reducing the number of analysis work steps in assertion-based verification.

  The design verification program, the design verification apparatus, and the design verification method for achieving the above object are such that the logic simulation execution result of the logic circuit described in the hardware description language matches the assertion described as the design specification of the logic circuit. In the design verification process in which the computer verifies, a test pattern generation process in which the computer generates a test pattern including at least one request, and an assertion expected to be executed for each request for each generated request An expected value information generation process for generating expected value information associated with the request, an assertion executed for each request for each generated request, and an assertion expected to be executed for each request in the expected value information The consistency determination process for determining the consistency of the output and the output process for outputting the consistency determination result It is required for the door.

  Furthermore, a design verification program, a design verification apparatus, and a design verification method for achieving the above-described object include an assertion in which a logic simulation execution result of a logic circuit described in a hardware description language is described as a design specification of the logic circuit. In the design verification process that allows the computer to verify whether it conforms to the test pattern generation process, the computer generates a test pattern including a plurality of ordered requests, and the execution order of the plurality of requests in the test pattern. It is a requirement to execute a consistency determination process for determining consistency with the execution order of the requested requests and an output process for outputting a consistency determination result.

  According to the disclosed design verification program, design verification device, and design verification method, it is possible to verify the execution of an assertion in association with a request for each test pattern request. Therefore, in the assertion-based verification, the verification accuracy is improved. Furthermore, the number of analysis work steps can be reduced.

It is a figure which shows the function structure of the design verification apparatus in this Embodiment. It is a flowchart of the design verification process in embodiment. It is a figure which shows the hardware structural example of the design verification apparatus in embodiment. It is a figure explaining the production | generation of the assertion expectation value table by the test pattern / assertion cooperation part 202. FIG. It is a figure explaining the production | generation of the sequence operation | movement table by the sequence control part 203. FIG. It is a figure explaining the consistency determination process by the consistency determination part. It is a figure explaining the consistency determination process by the consistency determination part. It is a figure explaining the consistency determination process by the consistency determination part. It is a figure which shows the example of a sequence of a consistency determination process. It is a figure which shows the example of a sequence of a consistency determination process.

  FIG. 1 is a diagram illustrating a functional configuration of the design verification apparatus according to the present embodiment, and FIG. 2 is a flowchart of the design verification processing according to the present embodiment. With reference to FIG. 1 and FIG. 2, an outline of the design verification processing in the design verification apparatus 100 of the present embodiment will be described.

  First, the operator inputs test constraint information 500 (for example, a prohibited operation, which is defined by read / write generation order, address, data, etc.) to the test pattern generation unit 201 according to the test item. (S101 in FIG. 2). The test pattern generation unit 201 automatically generates a test pattern that satisfies the conditions of the test constraint information 500 (S102 in FIG. 2). The generated test pattern is stored in the test pattern storage unit 502 and further notified to the test pattern / assertion link unit 202 and the sequence control unit 203.

  In addition, by operating the operator, assertion constraint information 501 is generated in advance and input to the test pattern / assertion link unit 202. The assertion constraint information 501 indicates whether or not to apply the assertion to each request of the test pattern for the assertion ID assigned to identify each of a plurality of pre-registered assertions (valid / Information having (invalid). The assertion constraint information 501 is illustrated in FIG.

  The test pattern / assertion linkage unit 202 associates the generated test pattern with the assertion using the assertion constraint information, and defines (types) the assertion that is valid for each request of the generated test pattern. And an assertion expectation value table including conditions (such as the number of executions of the request unit) for determining the consistency between the test pattern and the assertion is generated (S103 in FIG. 2). The assertion expectation value table is illustrated in FIG.

  The test pattern / assertion cooperation unit 202 notifies the consistency determination unit 207 of the expected assertion value table. The expected assertion value table will be described later. Requests that make up a test pattern are based on single access such as read or write, or multiple single access sequences (multiple access) to realize a specific circuit function.

  Further, the sequence control unit 204 generates a sequence operation table including the request issue order of the generated test patterns (S104 in FIG. 2), and monitors the request issue order. The sequence control unit 204 notifies the sequence determination table 207 of the sequence operation table. The sequence operation table is illustrated in FIG.

  The logic simulator 204 executes an assertion on the verification circuit 504 using the test pattern stored in the test pattern storage unit 502 and the assertion stored in the assertion storage unit 503 (S105 in FIG. 2).

  The state monitoring unit 205 monitors the state of the verification circuit 504 (S106 in FIG. 2). Specifically, the state monitoring unit 205 monitors whether or not a test pattern request is generated, and notifies the consistency determination unit 207 of the generated request when the request is generated. Furthermore, the state monitoring unit 205 monitors the assertion to be executed and the conditions for establishment thereof, and notifies the assertion determination unit 206 and the consistency determination unit 207 of the executed assertion and the execution result.

  The assertion determination unit 206 determines the execution result for each executed assertion (S107 in FIG. 2), and stores the determination (OK or NG) for the execution result of the assertion in the assertion determination storage unit 505. The assertion determination unit 206 notifies the consistency determination unit 207 of the determination on the execution result of the assertion and the number of executions of the assertion.

  The consistency determination unit 207 includes the expected assertion operation for the test pattern obtained from the expected assertion value table, the expected test pattern operation obtained from the sequence operation table, and information notified from the state monitoring unit 205 ( Based on the comparison of the actual assertion operation and test pattern operation obtained from the generated request, the assertion executed and its execution result), the determination information notified from the assertion determination unit 206, and the execution frequency information of the assertion, The consistency determination of the assertion operation and the consistency determination of the test pattern operation are performed (S108 in FIG. 2). Further, the consistency determination unit 207 determines the assertion error when an NG determination (assertion error) occurs in the assertion determination. The request for the corresponding test pattern is detected. The consistency determination unit 207 stores the consistency determination result and the detection result in the consistency determination storage unit 506.

  The design verification process is repeated until the design verification process for all test patterns is completed (S109 in FIG. 2).

  FIG. 3 is a diagram illustrating a hardware configuration example of the design verification apparatus according to the present embodiment. 3, the design verification apparatus 100 includes a CPU 102, a ROM 104, a RAM 106, a storage medium access device 108, an input device 110, and an output device 112. The CPU 102 performs overall control of the design verification apparatus 100 and executes a design verification program. The ROM 104 stores various computer programs such as a design verification program. The RAM 106 is a memory used as a work area for the CPU 102.

  The storage medium access device 108 is a magnetic disk drive, an optical disk drive, or the like, and reads and writes data by accessing the storage medium 109 such as a magnetic disk or an optical disk under the control of the CPU 102. The input device 110 is a keyboard or a mouse, for example, and enables an external operation for the execution of the verification support program. The output device 112 is, for example, a display or a printer device. The display displays the execution result of the design verification program, and the printer device prints out the execution result of the design verification program. Each component is connected via a bus 120. Moreover, you may provide other functional elements, such as a communication interface for connecting and communicating with a network.

  Each function unit (test pattern generation unit 201, test pattern / assertion linkage unit 202, sequence control unit 203, logic simulator 204, state monitoring unit 205, assertion determination unit 206, consistency of the design verification apparatus 100 shown in FIG. The determination unit 207) is provided as a design verification program stored in a storage area such as the ROM 104, RAM 106, and storage medium 109 shown in FIG. 3, and the function of each functional unit is executed by the CPU 102 executing the design verification program. Is realized.

  The data storage unit (the test pattern storage unit 502, the assertion storage unit 503, the verification circuit storage unit 504, the assertion determination storage unit 505, and the consistency determination storage unit 506) of the design verification apparatus 100 illustrated in FIG. Provided as storage areas such as the ROM 104, RAM 106, and storage medium 109 shown in FIG. 3, and the data is read from and written to the storage area when the CPU 102 accesses the storage area when the design verification program is executed. .

  The assertion expectation value table generation process (S103), the sequence operation table generation process (S104), and the consistency determination process (S108) will be described in more detail below.

  FIG. 4 is a diagram for explaining generation of an expected assertion value table by the test pattern / assertion cooperation unit 202. By operator operation, assertion constraint information 501 is generated in advance and input to the test pattern / assertion link unit 202. The assertion constraint information is whether or not to apply the assertion to each request of the test pattern for the assertion ID given to identify each of a plurality of pre-registered assertions (valid / invalid) ) And the number of executions when it is executed (when it is valid) as an expected value. For example, in the assertion constraint information 501 in FIG. 4, by asserting the assertion IDs (A) to (D) and invalidating the assertion ID (E) and later, the assertion IDs (A) to (A) ( Only the assertion of D) is executed. Only the assertions necessary for the current verification can be selected from a plurality of registered assertions.

  Also, in the assertion constraint information 600 of FIG. 4, the numerical value set as the correspondence relationship between the assertion ID and the request is the number of times each assertion is executed when the test pattern operation of each request is performed. For example, since the expected value “1” is set as the correspondence between the assertion ID (A) and the request (1), the assertion ID (A) is executed when the test pattern operation of the request (1) is performed. Is performed once. Similarly, since the expected value “2” is set as the correspondence between the assertion ID (B) and the request (3), the assertion ID (B) is executed when the test pattern operation of the request (3) is performed. The number of times it is done is two times. When the expected value “0” is set, the assertion of the corresponding assertion ID is not executed when the test pattern operation of the corresponding request is performed. For example, since the expected value “0” is set as the correspondence relationship between the assertion ID (B) and the request (1), even if the assertion ID (B) is set valid, the test pattern operation of the request (1) For, the assertion ID (B) is not executed.

  The test pattern / assertion cooperation unit 202 receives the test pattern generated by the test pattern generation unit 201, and the test pattern generated by the test pattern generation unit 201 for the assertion ID that is set valid from the assertion constraint information 501. A set value of each assertion ID corresponding to the request is extracted, and this is used as an assertion expected value table 602. The expected assertion value table 602 is a table in which the expected number of assertions executed is associated with the generated test pattern in request units.

  FIG. 5 is a diagram for explaining generation of a sequence operation table by the sequence control unit 203. The sequence control unit 203 receives the test pattern generated by the test pattern generation unit 201. The test pattern requests are ordered in the execution order, and the sequence control unit 203 generates a sequence operation table 604 in which the requests are recorded in the execution order. For example, in FIG. 5, when the execution order of the generated test pattern requests is in the order of request (1), request (2), request (1), request (1), the sequence control unit 203 A sequence operation table 604 in which requests are arranged according to the execution order is generated.

  Note that, depending on the circuit, switching of the execution order of requests may be permitted. In this case, since an error does not occur when requests are not executed in the order set in the test pattern, the sequence control unit 203 sets the number of executions for each request included in the test pattern instead of the execution order of the requests. A sequence operation table 604 recorded as an expected value is generated. For example, in FIG. 5, when the requests executed in the generated test pattern are request (1), request (2), request (1), request (1) in the execution order, the sequence control unit 203 Record the number of executions of (1) three times and the number of executions of request (2) once as a sequence operation table. When switching of the execution order of requests is permitted, switching constraint information for defining the number of executions of the request as an expected value is defined in advance for the sequence control unit 203.

  6 to 8 are diagrams for explaining consistency determination processing by the consistency determination unit 207. FIG. In FIG. 6, the consistency determination unit 207 receives the assertion expectation value table 602 from the test pattern / assertion cooperation unit 202, and the consistency between the assertion expected in the assertion expectation value table 602 and the actually executed assertion. (Match / mismatch) is determined. For example, the consistency determination unit 207 receives the actual information obtained from the information notified from the state monitoring unit 205 (the generated request, the executed assertion, and the execution result) and the determination information notified from the assertion determination unit 206. Get information about assertion operations and test patterns. The consistency determination unit 207 compares the actually executed assertion with respect to the actually executed request and the number of executions (set value) of the assertion ID for the request set in the expected assertion value table 602. And determine whether they match. For example, as illustrated in FIG. 6, when the assertion ID (A) is executed twice in the execution of the request (1), or the assertion ID (D) is executed in the execution of the request (2). If not, the consistency determination unit 207 detects a mismatch with the set value of the expected assertion value table 602. When the consistency determination unit 207 detects a mismatch, it outputs an error (NG).

  In FIG. 7, the consistency determination unit 207 receives the sequence operation table 604 from the sequence control unit 203, and matches the execution order of requests expected in the sequence operation table 604 with the execution order of requests actually executed. Determine sex. For example, each time a request is generated, the consistency determination unit 207 acquires information on the request that has actually occurred from the state monitoring unit 205 and records the request that has actually occurred and the sequence operation table 604. Compare the execution order of the requests to determine consistency. For example, in FIG. 7, in the sequence operation table 604, the execution order of requests is actually executed when the request (1) is expected to be executed first and then the request (2) is expected to be executed next. When the request (1) is executed first and then the request (1) is executed again after that, the consistency determination unit 207 determines that the execution order recorded in the sequence operation table 604 is the same as the execution order. Detect mismatches. When the consistency determination unit 207 detects a mismatch, it outputs an error (NG).

  When the sequence operation table 604 records the number of executions for each request instead of the execution order, the consistency determination unit 207 obtains the expected number of executions and the actual number of executions for each request. Compare and judge consistency (match / mismatch). In the example shown in FIG. 7, for the request (1), the expected number of executions is 3, whereas the actual number of executions is 2. Therefore, the consistency determination unit 207 detects a mismatch. .

  In FIG. 8, when the consistency determination unit 207 receives an assertion error (NG) occurrence notification as determination information from the assertion determination unit 206, the assertion corresponding to the assertion error detects a request at the time of execution. Specifically, the consistency determination unit 207 determines at which request execution time of the test pattern the assertion error occurred. The consistency determination unit 207 acquires information on the number of executions of the assertion from the assertion determination unit 206, sequentially acquires information on requests executed from the state monitoring unit 205, and requests that are executed when an assertion error occurs from the information Is identified. In the example of FIG. 8, the consistency determination unit 207 determines that the request executed when the assertion error occurs for the execution of the assertion ID (A) is the second request (1) executed after the first request (1). ). Thereby, the state of the verification circuit when the assertion error occurs can be specified on a request basis.

  9 and 10 are diagrams illustrating a sequence example of consistency determination processing. In FIG. 9, request (1) is executed first as a test pattern, and then request (2) is executed. In addition, as the expected operation set in the assertion expectation value table 600, one assertion ID (A) is asserted with the request (1), and each assertion ID (B), (C), ( Assume that the assertion in D) is expected to be executed in request (2). The logic simulator 204 executes an assertion on the verification circuit 504 according to the request (1). The state monitoring unit 205 notifies the consistency determination unit 207 of execution of the request (1). The assertion determination unit 206 notifies the consistency determination unit 207 of the execution result of the assertion. At this time, the assertion determination unit 206 performs two assertion IDs (in the effective range (valid period) of the request (1). The execution result of A) is notified. The consistency determination unit 207 determines that the execution of the assertion of the second assertion ID (A) executed during the validity period of the request (1) does not match the expected operation, and outputs an error (NG). Furthermore, the assertion determination unit 206 notifies the execution results of the assertion IDs (B) and (C) once each during the valid range (valid period) of the request (2), but the assertion ID (D) If the execution result is not notified, the consistency determination unit 207 determines that the assertion ID (D) has not been executed during the validity period of the request (2), determines that it does not match the expected operation, and outputs an error. To do.

  In FIG. 10, as in FIG. 9, the request (1) is first executed as the test pattern, and then the request (2) is executed. In addition, as the expected operation set in the assertion expectation value table 600, one assertion ID (A) is asserted with the request (1), and each assertion ID (B), (C), ( Assume that the assertion in D) is expected to be executed in request (2). The logic simulator 204 executes an assertion on the verification circuit 504 according to the request (1). The state monitoring unit 205 notifies the consistency determination unit 207 of execution of the request (1). The assertion determination unit 206 notifies the execution result of the assertion to the consistency determination unit 207. At this time, the assertion determination unit 206 executes the assertion ID (A) once during the validity period of the request (1). In addition to the result, the execution result of one assertion ID (E) is notified. The consistency determination unit 207 determines that the execution of the assertion of the assertion ID (E) executed during the validity period of the request (1) does not match the expected operation, and outputs an error. Further, the assertion determination unit 206 notifies the execution results of the assertion IDs (B) and (C) once each during the validity period of the request (2), and further asserts during the validity period of the next request. The execution result of ID (D) is notified. The consistency determination unit 207 receives the execution result of the assertion ID (D), but does not receive it during the validity period of the request (2), so the assertion ID (D) is executed during the validity period of the request (2). It is determined that there was no match, and it is determined that the expected operation does not match, and an error is output.

  As described above, in this embodiment, an automatically generated test pattern is associated with an assertion, and an expected value table including an expected assertion operation is generated for each request of the generated test pattern. To do. Then, for each request unit, the type of assertion that is actually executed, the number of executions, and the execution timing are determined, and for each request unit, the match / mismatch between the expected assertion operation and the actually executed assertion operation is determined. If a mismatch occurs, an error is output. Furthermore, using the request issuance order of the generated test pattern as an expected value, a match / mismatch with the actual request issuance order is determined, and an error is output if there is a mismatch. As a result, it is possible to verify the execution of the assertion in association with the request in the request unit of the test pattern, thereby improving the verification accuracy and easily analyzing which request the assertion error corresponds to. It becomes like this.

  The design verification program in the present embodiment is a program for causing a computer apparatus (including a personal computer and a workstation) to execute the design verification process described above. This is realized by being executed by an apparatus (design verification apparatus).

  The main technical features of the embodiment described above are as follows.

(Appendix 1)
In a design verification program for causing a computer to verify whether a logic simulation execution result of a logic circuit described in a hardware description language matches an assertion described as a design specification of the logic circuit,
Said computer,
Test pattern generation means for generating a test pattern including at least one requirement;
Expected value information generating means for generating expected value information that associates each request with an assertion that is expected to be executed for each request for each generated request;
Consistency determination means for determining the consistency between the assertion executed for each request and the assertion in the expected value information set for each request for each generated request;
An output means for outputting the consistency determination result;
Design verification program characterized by functioning as

(Appendix 2)
In Appendix 1,
The design verification program, wherein the consistency determination means determines an error when an assertion different from the assertion in the expected value information is executed for each request.

(Appendix 3)
In Appendix 1,
The design verification program characterized in that the consistency determination means determines an error when assertion in the expected value information is not executed within a certain period for each request.

(Appendix 4)
In Appendix 1,
The expected value information includes the number of assertions that are expected to be executed for each request,
The design verification program characterized in that the consistency determination means determines an error when the number of assertions executed for each request is different from the number of assertions executed in the expected value information.

(Appendix 5)
In Appendix 1,
The test pattern generates a test pattern including a plurality of ordered requests;
The design verification program characterized in that the consistency determination means determines an error when the execution order of the plurality of requests in the test pattern is different from the execution order of the requests actually executed.

(Appendix 6)
In a design verification program for causing a computer to verify whether a logic simulation execution result of a logic circuit described in a hardware description language matches an assertion described as a design specification of the logic circuit,
Said computer,
Test pattern generation means for generating a test pattern including a plurality of ordered requests;
Consistency determining means for determining consistency between the execution order of the plurality of requests in the test pattern and the execution order of the requests actually executed;
An output means for outputting the consistency determination result;
Design verification program characterized by functioning as

(Appendix 7)
In a design verification device for verifying whether a logic simulation execution result of a logic circuit described in a hardware description language matches an assertion described as a design specification of the logic circuit,
Test pattern generation means for generating a test pattern including at least one requirement;
For each generated request, expected value information generating means for generating expected value information in association with an assertion expected to be executed for each request;
Consistency determining means for determining the consistency between the assertion executed for each request and the assertion expected to be executed for each request in the expected value information for each generated request;
The design verification apparatus comprising: output means for outputting the consistency determination result.

(Appendix 8)
In a design verification method for causing a computer to verify whether a logic simulation execution result of a logic circuit described in a hardware description language matches an assertion described as a design specification of the logic circuit,
The computer is
A test pattern generation step for generating a test pattern including at least one requirement;
For each generated request, an expected value information generating step for generating expected value information in association with an assertion expected to be executed for each request;
For each generated request, a consistency determining step for determining consistency between an assertion executed for each request and an assertion expected to be executed for each request in the expected value information;
An output step of outputting the consistency determination result is executed.

(Appendix 9)
In a design verification apparatus for causing a computer to verify whether a logic simulation execution result of a logic circuit described in a hardware description language is compatible with an assertion described as a design specification of the logic circuit,
A test pattern generating means for generating a test pattern including a plurality of ordered requests;
Consistency determining means for determining consistency between the execution order of the plurality of requests in the test pattern and the execution order of the requests actually executed;
A design verification program comprising: output means for outputting the result of the consistency determination.

(Appendix 10)
In a design verification method for causing a computer to verify whether a logic simulation execution result of a logic circuit described in a hardware description language matches an assertion described as a design specification of the logic circuit,
The computer is
A test pattern generation process for generating a test pattern including a plurality of ordered requests;
A consistency determination step for determining consistency between the execution order of the plurality of requests in the test pattern and the execution order of the requests actually executed;
An output step of outputting the consistency determination result is executed.

  201: Test pattern generation unit, 202: Test pattern / assertion cooperation unit, 203: Sequence control unit, 204: Logic simulator, 205: State monitoring unit, 206: Assertion determination unit, 207: Consistency determination unit, 500: Test constraint Information, 501: Assertion constraint information, 502: Test pattern storage unit, 503: Assertion storage unit, 504: Verification circuit, 505, Assertion determination storage unit, 506: Consistency determination storage unit, 602: Assertion expected value table, 604: Sequence operation table

Claims (5)

In a design verification program for causing a computer to verify whether a logic simulation execution result of a logic circuit described in a hardware description language matches an assertion described as a design specification of the logic circuit,
Said computer,
Test pattern generation means for generating a test pattern including at least one requirement;
Expected value information generating means for generating expected value information that associates each request with an assertion that is expected to be executed for each request for each generated request;
Consistency determination means for determining the consistency between the assertion executed for each request and the assertion in the expected value information set for each request for each generated request;
An output means for outputting the consistency determination result;
Design verification program characterized by functioning as In claim 1,
The test pattern generates a test pattern including a plurality of ordered requests;
The design verification program characterized in that the consistency determination means determines an error when the execution order of the plurality of requests in the test pattern is different from the execution order of the requests actually executed. In a design verification program for causing a computer to verify whether a logic simulation execution result of a logic circuit described in a hardware description language matches an assertion described as a design specification of the logic circuit,
Said computer,
Test pattern generation means for generating a test pattern including a plurality of ordered requests;
Consistency determining means for determining consistency between the execution order of the plurality of requests in the test pattern and the execution order of the requests actually executed;
An output means for outputting the consistency determination result;
Design verification program characterized by functioning as In a design verification device for verifying whether a logic simulation execution result of a logic circuit described in a hardware description language matches an assertion described as a design specification of the logic circuit,
Test pattern generation means for generating a test pattern including at least one requirement;
For each generated request, expected value information generating means for generating expected value information in association with an assertion expected to be executed for each request;
Consistency determining means for determining the consistency between the assertion executed for each request and the assertion expected to be executed for each request in the expected value information for each generated request;
The design verification apparatus comprising: output means for outputting the consistency determination result. In a design verification method for causing a computer to verify whether a logic simulation execution result of a logic circuit described in a hardware description language matches an assertion described as a design specification of the logic circuit,
The computer is
A test pattern generation step for generating a test pattern including at least one requirement;
For each generated request, an expected value information generating step for generating expected value information in association with an assertion expected to be executed for each request;
For each generated request, a consistency determining step for determining consistency between an assertion executed for each request and an assertion expected to be executed for each request in the expected value information;
An output step of outputting the consistency determination result is executed.

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