JP2012114566A - Signal multiplexing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal multiplexing circuit (parallel/serial conversion circuit) which multiplexes, in time division manner, N pieces of low speed signals into a single high speed signal, in which, especially, a high speed clock is not used at a final stage of the multiplexing circuit to abolish timing constraint.SOLUTION: By pre-coding, for example, a parallel signal by taking an exclusive OR between signals adjoining each other, the pre-coded parallel signal is delayed stepwise using flip flop. N pieces of signals, or delayed signal, are inputted into an exclusive OR circuit of N-input to generate an eventual serial output. Since, in this manner, the exclusive OR circuit at a final stage does not require input of a clock signal, the difficulty in timing design is eliminated, and further, no high speed clock is required, for reduced power consumption.

Description

  The present invention relates to a signal multiplexing circuit that multiplexes a plurality of low-speed signals into one high-speed signal by time division, and more particularly to a signal multiplexing circuit (parallel / serial conversion) used in a transmission unit of an optical communication system. The present invention relates to a technology that is useful when applied to a circuit.

For example, Patent Document 1 discloses a 1/2 ⁿ parallel-serial conversion circuit configured by using a 1/2 parallel-serial conversion circuit as a conversion unit and connecting the conversion units in a tree-like manner. As a result, even if the serial number increases, the clock skew can be suppressed and the formation of a critical path can be prevented.

JP 2002-9629 A

  In recent years, high-speed communication exceeding several tens of Gbps is performed in an optical communication system, and signal multiplexing processing (parallel / serial) synchronized with a high-speed clock signal CLKin is performed in a signal multiplexing circuit (parallel / serial conversion circuit). Conversion). FIG. 1 is a block diagram showing a configuration example of an optical communication system including a signal multiplexing circuit (parallel / serial conversion circuit) based on time division, which is a premise of the present invention. The optical communication system shown in FIG. 1 includes an optical / electrical conversion block OFE_BLK, a parallel / serial conversion block (SerDes: SERializer / DESerializer) SD_BLK, and an upper layer logical block PU. OFE_BLK is, for example, an optical / electrical conversion circuit OEC that converts an optical input data signal IN_OP into an electrical signal via a photodiode or the like, and an electrical / optical conversion that converts an electrical signal into an optical output data signal OUT_OP via a semiconductor laser or the like. A circuit EOC is provided.

  SD_BLK is an input circuit IF_I that amplifies a minute data signal from the OEC to a data signal of a predetermined voltage level as an input system circuit, and signal reproduction that reproduces the data signal Dout and the clock signal CLKout from the output data signal Din. A circuit CDR and a serial / parallel conversion circuit SPC that converts Dout as serial data into a parallel data signal DATo using CLKout and outputs a divided clock signal CLKoutDiv of CLKout are provided. The upper layer logical block PU receives the CLKoutDiv and DATo and performs predetermined information processing. The SD_BLK includes a signal multiplexing circuit (parallel / serial conversion circuit) PSC as an output system circuit and an output circuit IF_O that drives the electrical / optical conversion circuit EOC by a predetermined electrical signal based on the serial data signal. ing. The PSC converts the parallel data signal DATi from the PU into a serial data signal synchronized with the clock signal CLKin generated by the clock generation circuit CLK_GEN, and outputs a divided clock signal CLKinDiv of CLKin to the PU.

  2A and 2B show an example of operation of the signal multiplexing circuit (parallel / serial conversion circuit) PSC in FIG. 1, and FIG. 2A is an operation timing chart in the case of 4: 1. FIG. 2B is an operation timing chart in the case of 2: 1. In the case of 4: 1 shown in FIG. 2A, the four parallel signals P0 to P3 are converted into one serial signal Sout in accordance with the time division multiplexing processing by the signal multiplexing circuit. At this time, parallel signals are output in the order of P0, P1, P2, and P3 as the serial signal Sout. Due to the time division multiplexing, the time width of one symbol of the serial signal Sout becomes 1/4 of the time width of the parallel signals P0 to P3. Similarly, in the case of 2: 1 shown in FIG. 2B, two parallel signals P0 and P1 are converted into one serial signal Sout by time division multiplexing processing by the signal multiplexing circuit. . The time width of one symbol of the serial signal Sout is ½ of the time width of the parallel signals P0 and P1.

  FIG. 3 is a circuit block diagram showing a configuration example of a signal multiplexing circuit (parallel / serial conversion circuit) studied as a premise of the present invention. The signal multiplexing circuit shown in FIG. 3 is composed of seven 2: 1 signal multiplexing circuits (parallel / serial conversion circuits) PS21 and three divide-by-2 circuits DIV2, thereby converting 8: 1. I do. Seven PSs 21 are arranged in a tree structure having a three-stage configuration, and eight parallel signals P0 to P7 are multiplexed in the order of 8 → 4 → 2 → 1 in this order to obtain serial signals from P0 to P7. Sout is generated.

  4A and 4B are circuit diagrams showing different configuration examples of each 2: 1 signal multiplexing circuit (parallel / serial conversion circuit) PS21 in FIG. 3, and FIG. 4 is an operation timing chart showing an operation example of (a) and (b). The 2: 1 signal multiplexing circuit PS21 shown in FIG. 4A includes two edge trigger flip-flop circuits FF1 and FF2, a level trigger latch circuit LT, a 2: 1 selector circuit SEL2, and a delay circuit CK_DLY. As shown in FIG. 4C, the delay circuit CK_DLY outputs CLKd obtained by delaying the clock signal CLK by about ¼ period. The two edge trigger flip-flop circuits FF1 and FF2 operating in synchronization with the clock CLKd output signals A and B with the timings of the parallel signals P0 and P1 aligned with the rising edge of CLKd, respectively. Further, the level trigger latch circuit LT realigns the signal B with the rising edge of CLKd and outputs the signal C. As a result, the signals A and C have phases shifted from each other by a half cycle of CLKd, and are input to the 2: 1 selector circuit SEL2, respectively.

  The 2: 1 selector circuit SEL2 selects one of the signals A and C using the undelayed clock signal CLK before passing through the delay circuit CK_DLY as a selection signal, and outputs a serial signal Sout. At this time, as shown in the timing chart of FIG. 4C, the signal A is a constant value that does not change during the period when CLK is “0”, and the signal C that does not change during the period when CLK is “1”. Therefore, the serial signal Sout output from the SEL2 is a signal having a time width of one symbol of Tsym and a shaped signal without glitch. In the actual circuit, since the edge trigger flip-flop circuits FF1 and FF2 and the level trigger latch circuit LT have a finite propagation delay time, the delay circuit CK_DLY is omitted and CLKd is the same signal as CLK. Even so, the signals A and C are delayed from the rising edge of CLK. For this reason, in the actual circuit, the delay circuit CK_DLY can be omitted in many cases.

  On the other hand, the 2: 1 signal multiplexing circuit (parallel / serial conversion circuit) PS21 shown in FIG. 4B has two edge trigger flip-flop circuits FF1 and FF2 in FIG. The configuration is replaced with LT2. This configuration can be used when it is guaranteed that the parallel signals P0 and P1 are constant values during the period when CLKd is “1”. In the 8: 1 signal multiplexing circuit configured by arranging the 2: 1 signal multiplexing circuit in a tree shape as shown in FIG. 3, the configuration of FIG. 4B is used as the 2: 1 signal multiplexing circuit. Can also be used. In general, since the level trigger latch circuit can be realized with a simpler circuit than the edge trigger flip-flop circuit, the configuration of FIG. 4B is used as a 2: 1 signal multiplexing circuit (parallel / serial conversion circuit). If possible, the layout area can be reduced and power can be saved by using the configuration shown in FIG. 4B instead of the configuration shown in FIG.

As described above, according to the configuration shown in FIGS. 3 and 4, by arranging the 2: 1 signal multiplexing circuit (parallel / serial conversion circuit) PS21 in a tree shape, n is an integer and 2 ⁿ : 1 signal multiplexing circuit (parallel / serial conversion circuit) can be easily realized. However, when the frequency of the clock signal CLK increases with the high-speed communication exceeding several tens of Gbps as described above, in the configuration example of FIGS. 4A and 4B, the 2: 1 selector of the 2: 1 signal multiplexing circuit. There is a possibility that the timing design between the signal A and the signal C input to the circuit SEL2 and the CLK serving as the select signal may be difficult.

  FIG. 5 (a) shows the 2: 1 signal multiplexing circuit (parallel / serial conversion circuit) of FIG. 4 (a) again, and FIG. 5 (b) shows an operation timing showing an example of the problem. It is a chart. In FIG. 5A, the delay circuit CK_DLY is omitted for the reason described above. In FIG. 5B, the period of the clock signal CLK is TCLK, and the propagation delay time of the edge trigger flip-flop circuits FF1 and FF2 and the level trigger latch circuit LT is TpdFF. TCLK is twice the time width Tsym of one symbol of the serial signal Sout. When the communication speed increases, the time width Tsym of one symbol of the serial signal Sout decreases, while the propagation delay time TpdFF of FF1, FF2, and LT is determined by the circuit configuration and is constant regardless of the communication speed. Therefore, at a high communication speed, the propagation delay time TpdFF of FF1, FF2, and LT may be longer than the time width Tsym of one symbol of the serial signal Sout. In the example of FIG. 5B, a case where TpdFF is larger than Tsym = TCLK / 2 is shown. In this case, since the input signals A and C to the 2: 1 selector circuit SEL2 are delayed with respect to CLK as the select signal, it is understood that an unnecessary glitch is generated in the serial signal Sout.

  In order to solve this problem, for example, a method of optimally adjusting the clock phase using a phase interpolator can be considered. 6A is a circuit diagram showing a configuration example in which a phase interpolator is applied to the 2: 1 signal multiplexing circuit (parallel / serial conversion circuit) shown in FIG. 4A, and FIG. These are operation | movement timing charts which show the operation example of Fig.6 (a). The 2: 1 signal multiplexing circuit in FIG. 6A has a configuration in which a phase interpolator PI is arranged instead of the delay circuit CK_DLY in the 2: 1 signal multiplexing circuit in FIG. The phase interpolator PI rotates the phase of the clock signal CLK based on the control signal PH_CTRL from the phase control block CTRL_BLK and outputs it as CLKd.

  CTRL_BLK includes an edge trigger flip-flop circuit FF3 that operates in synchronization with CLKd, a phase comparator PD, a low-pass filter LPF, and control logic. A pattern signal PDin having a value of 0101... Is input to FF3 in synchronization with the parallel signals P0 and P1. This FF3 has the same circuit configuration as the edge trigger flip-flop circuits FF1 and FF2 of the 2: 1 signal multiplexing circuit body, and the propagation delay times of these FF1 to FF3 are equal to each other. The phase comparator PD compares the phase between the output D of the FF 3 and the clock signal CLK, and whether the “0” pulse of CLK is shifted in the front or back direction from the center of the period during which the signal D is a constant value. Is output. This determination result is averaged by the LPF and then input to the control logic. Based on this, the control logic outputs a control signal PH_CTRL to the phase interpolator PI. As a result, the phase of CLKd is controlled so that the “0” pulse of CLK is positioned at the center of the period in which signal D is a constant value regardless of the propagation delay time of FF1, FF2, and LT, regardless of TpdFF. Become. Therefore, the 2: 1 selector circuit SEL2 outputs a clean waveform without glitches.

  When the 2: 1 signal multiplexing circuit (parallel / serial conversion circuit) shown in FIG. 6 (a) is used, the 2: 1 signal can be stably output even when the power supply voltage or the environmental temperature fluctuates during operation. Multiplexing operations can be performed. That is, even if the propagation delay time TpdFF of FF1, FF2, and LT changes, the phase control block CTRL_BLK is always optimal with respect to the phase of the CLK of the signals A and C input to the 2: 1 selector circuit SEL2. Feedback control is performed so that However, the 2: 1 signal multiplexing circuit shown in FIG. 6 (a) has a problem that the power consumption is very large compared to the 2: 1 signal multiplexing circuit shown in FIGS. 4 (a) and 4 (b). is there. In particular, the phase interpolator PI and the phase comparator PD operate with a high-speed clock signal CLK and consume large power. Furthermore, since the phase interpolator PI normally requires a four-phase clock of 0 °, 90 °, 180 °, and 270 °, a four-phase clock generation circuit that generates a four-phase clock from the clock signal CLK is required. . This four-phase clock generation circuit also needs to be operated with a high-speed clock signal CLK and consumes a large amount of power.

  The present invention has been made in view of the above, and one of its purposes is to provide a signal multiplexing circuit (parallel / serial conversion circuit) capable of realizing high speed and low power consumption. It is in. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of a typical embodiment will be briefly described as follows.

  The signal multiplexing circuit according to the present embodiment includes a pre-encoder circuit, a delay circuit block provided in the subsequent stage, and a decode circuit provided in the subsequent stage. The pre-encoder circuit pre-codes the first to N-th (N is an integer of 2 or more) parallel signals with a predetermined combinational logic every first cycle time, and the first to N-th pre-coded signals every first cycle time. Are output in parallel. The delay circuit block outputs the first precoded signal as the first signal starting from the second timing, and the Kth (K is an integer of 2 or more and N or less) precoded signal starting from the second timing. After adding a delay of (first cycle time / N) × (K−1) ”, it is output as the Kth signal. The decoding circuit converts the first to Nth parallel signals into serial signals by decoding the first to Nth signals with combinational logic corresponding to the precode, and outputs the serial signals.

  Specifically, for example, in the case of N = 2, the pre-encoder circuit latches two parallel signals pre-coded by two exclusive OR circuits by two edge trigger flip-flop circuits. To do. Here, the output of one edge trigger flip-flop circuit is delayed by a half clock cycle via a delay circuit block (for example, a level trigger latch circuit). The decoding circuit outputs a final serial signal by performing an exclusive OR operation between the output of the edge trigger flip-flop circuit and the output of the level trigger latch circuit. That is, the exclusive OR circuit in the final stage decodes the precoded parallel signal at the same time as time division multiplexing, and outputs a correct serial signal.

  Thus, the signal multiplexing circuit according to the present embodiment does not require the final stage selector circuit normally required in the signal multiplexing circuit, and uses an exclusive OR circuit instead. The last stage selector circuit in a normal signal multiplexing circuit outputs a multiplexed signal by inputting a total of three signals of two input signals and a clock signal as a select signal. In contrast, the exclusive OR circuit at the final stage in the signal multiplexing circuit according to the present embodiment outputs a signal multiplexed from only two input signals. This is because the signal multiplexing circuit according to the present embodiment does not have the problem of the timing constraint between the signal input to the selector circuit and the selector signal, which is particularly problematic during high-speed operation in the normal signal multiplexing circuit. Means that. For this reason, it is not necessary to construct a feedback system for timing adjustment that is complicated and consumes a large amount of power, and a signal multiplexing circuit that can be operated simply and at low power consumption and at high speed can be realized.

  In the signal multiplexing circuit according to the present embodiment, an exclusive OR circuit capable of high-speed operation is required instead of the selector circuit required in the normal signal multiplexing circuit. At this time, there is a concern that the exclusive OR circuit is difficult to operate at high speed as compared with the selector circuit. However, in a circuit having a differential configuration common to high-speed communication, the exclusive OR circuit can be realized with the same circuit configuration as that of the selector circuit. Can be planned.

  For example, in the 2: 1 signal multiplexing circuit according to the present embodiment described above, the final serial signal timing is determined by the delay of a half clock cycle by the level trigger latch circuit. At this time, for example, by accurately adjusting the phase of the clock signal using a delay locked loop circuit (DLL) or the like, an accurate half clock cycle delay can be realized, and timing jitter of the output serial signal can be suppressed. it can.

  The effects obtained by typical embodiments of the invention disclosed in the present application will be briefly described. In the signal multiplexing circuit (parallel / serial conversion circuit), high speed and low power consumption can be realized.

1 is a block diagram showing a configuration example of an optical communication system including a signal multiplexing circuit (parallel / serial conversion circuit) based on time division, which is a premise of the present invention. FIG. (A), (b) shows the operation example of the signal multiplexing circuit (parallel / serial conversion circuit) in FIG. 1, (a) is an operation timing chart in the case of 4: 1, (b) is It is an operation timing chart in the case of 2: 1. It is a circuit block diagram showing an example of composition of a signal multiplexing circuit (parallel / serial conversion circuit) examined as a premise of the present invention. (A), (b) is a circuit diagram which shows the example of a respectively different structure of each 2: 1 signal multiplexing circuit (parallel / serial conversion circuit) in FIG. 3, (c) is (a), (b) It is an operation | movement timing chart which shows the operation example of). (A) shows the 2: 1 signal multiplexing circuit (parallel / serial conversion circuit) of FIG. 4 (a) again, and (b) is an operation timing chart showing an example of the problem. (A) is a circuit diagram showing a configuration example in which a phase interpolator is applied to the 2: 1 signal multiplexing circuit (parallel / serial conversion circuit) shown in FIG. 4 (a), and (b) is (a). It is an operation | movement timing chart which shows the example of operation | movement. 1 is a circuit diagram showing a configuration example of an n: 1 signal multiplexing circuit (parallel / serial conversion circuit) according to Embodiment 1 of the present invention; FIG. FIG. 8 is a schematic diagram illustrating a detailed operation example of the n: 1 signal multiplexing circuit (parallel / serial conversion circuit) of FIG. 7. FIG. 8 is a circuit diagram illustrating a detailed configuration example of a multiplexing / decoding circuit in FIG. 7. FIG. 8 is a circuit diagram showing another detailed configuration example of the multiplexing / decoding circuit in FIG. 7. FIG. 8 is a circuit diagram illustrating a detailed configuration example of a stepped delay circuit in FIG. 7. FIG. 12 is a waveform diagram showing an operation example of a delay locked loop in FIG. 11. FIG. 5 is a circuit diagram showing a configuration example of an n: 1 signal multiplexing circuit (parallel / serial conversion circuit) according to a second embodiment of the present invention. FIG. 14 shows details of the 1 / n frequency divider in FIG. 13, (a) is a circuit diagram showing a configuration example thereof, (b) is a circuit diagram showing a configuration example of each clocked inverter circuit in (a), (C) is a wave form diagram which shows the operation example of (a). A circuit block diagram showing a detailed configuration example of a 2-input exclusive OR circuit included in a multiplexing / decoding circuit in an n: 1 signal multiplexing circuit (parallel / serial conversion circuit) according to a third embodiment of the present invention. It is. FIGS. 15A and 15B show details of the 2-input exclusive OR circuit in FIG. 15, wherein FIG. 15A is a circuit diagram showing a configuration example thereof, and FIG. 15B is a waveform diagram showing a schematic operation example of FIG. FIG. 6 is a circuit diagram showing a detailed configuration example of a 2-input exclusive OR circuit included in the multiplexing / decoding circuit in an n: 1 signal multiplexing circuit (parallel / serial conversion circuit) according to Embodiment 4 of the present invention; is there.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant, and one is the other. Some or all of the modifications, details, supplementary explanations, and the like exist. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  The circuit elements constituting each functional block of the embodiment are not particularly limited, but are formed on a semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as a CMOS (complementary MOS transistor). . Note that, in the embodiment, a MOS (Metal Oxide Semiconductor) transistor is used as an example of a MISFET (Metal Insulator Semiconductor Field Effect Transistor). In the drawing, a P-channel MOS transistor (PMOS transistor) is distinguished from an N-channel MOS transistor (NMOS transistor) by adding a circle symbol to the gate. Although the connection of the substrate potential of the MOS transistor is not particularly specified in the drawing, the connection method is not particularly limited as long as the MOS transistor can operate normally.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 7 is a circuit diagram showing a configuration example of the n: 1 signal multiplexing circuit (parallel / serial conversion circuit) according to the first embodiment of the present invention. The n: 1 signal multiplexing circuit (parallel / serial conversion circuit) shown in FIG. 7 includes a pre-encoder circuit PREENC, a stepped delay circuit SDLY_LAD, and a multiplexing / decoding circuit MUX_DEC. The pre-encoder circuit PREENC receives n parallel signals P0 to Pn-1 and a low-speed clock signal CLK_SL, and outputs precoded parallel signals E0 to En-1 synchronized with the low-speed clock signal CLK_SL.

  The staircase delay circuit SDLY_LAD outputs n precoded parallel signals E0 to En-1 delayed in a staircase pattern by the 1-symbol delay circuit SDLY. Specifically, E0 is output as A0 without any delay, E1 is output as A1 after a delay of one symbol time Tsym, and E2 is output as A2 after a delay of twice as long as Tsym. Similarly, Ej is output as Aj after a delay of time j times Tsym, where j is an integer. The multiplexing / decoding circuit MUX_DEC takes combinational logic between the input signals A0 to An-1, thereby decoding the data precoded by the pre-encoder circuit PREENC and simultaneously time-division-multiplexing the data.

  Here, in the signal multiplexing circuit according to the present embodiment, when the pre-encoder circuit PREENC and the multiplexing / decoding circuit MUX_DEC decode the data pre-encoded with PREENC with MUX_DEC, the relationship is such that the original data is restored. There is a need. As an example for realizing such a relationship, PREENC in FIG. 7 includes n two-input exclusive OR circuits EOR0 to EORn-1 and n edge trigger flip-flop circuits FF0 to FFn-1. . EOR0 calculates and outputs an exclusive OR between the output of FFn-1, that is, precoded data En-1 one cycle before by the low-speed clock signal CLK_SL and the parallel input P0 in the current cycle. The 2-input exclusive OR circuit EORj calculates and outputs an exclusive OR between the output of EORj-1 and the parallel input Pj in the current cycle, where j is an integer greater than or equal to 1 and less than n.

  On the other hand, the edge trigger flip-flop circuit FFk retimes the output of the 2-input exclusive OR circuit EORk in synchronization with the low-speed clock signal CLK_SL, where k is an integer between 0 and less than n, and the precoded parallel Output as signal Ek. Note that all n edge trigger flip-flop circuits FF0 to FFn-1 are not reset. Therefore, there is a possibility that the initial state of the n edge trigger flip-flop circuits FF0 to FFn-1 may be determined at random depending on the power-on state. There are two possible combinations of parallel signals E0 to En-1 that are precoded according to the initial state of the flip-flop circuit FFn-1. However, the signal multiplexing circuit operates normally in both cases. Naturally, an edge trigger flip-flop circuit with reset can be used as the edge trigger flip-flop circuit, and the initial value can be reset by an external reset signal.

  Note that the n: 1 signal multiplexing circuit (parallel / serial conversion circuit) according to the present embodiment is assumed to be applied to an input / output circuit of a large scale integrated circuit (LSI) such as a CPU or a network processor. These large scale integrated circuits (LSIs) usually output the result of performing some operation on the input data. In this case, it is also possible to use a configuration in which a large scale integrated circuit (LSI) performs the pre-encoding necessary for the n: 1 signal multiplexing circuit simultaneously with the original arithmetic processing. That is, for example, the upper layer logical block PU in FIG. 1 realizes the same function as the pre-encoder circuit PREENC in FIG. 7, and the parallel output (DATi) from the PU is encoded parallel data E0 to En-1 in FIG. And By doing so, it becomes possible to optimize the logic by integrating the original arithmetic processing of a large scale integrated circuit (LSI) and the encoding processing necessary for the n: 1 signal multiplexing circuit. Compared with a configuration in which PREENC is arranged in a multiplexing circuit (parallel / serial conversion circuit), the circuit scale and power consumption can be reduced as a whole.

  As described above, the pre-encoder circuit PREENC and the multiplexing / decoding circuit MUX_DEC need to be in a relationship in which the data pre-encoded by PREENC is restored to the original data when decoded by MUX_DEC. When the operation is determined, the operation of MUX_DEC is determined. In the configuration example of PREENC illustrated in FIG. 7, the corresponding MUX_DEC receives n precoded data A0 to An-1 shifted in timing via the step-like delay circuit SDLY_LAD, and receives A0 to An−1. Of these, “0” is output when the number of “1” is an even number, and “1” is output when the number of “1” is an odd number among A0 to An−1. Such MUX_DEC can be realized by an exclusive OR circuit of A0 to An-1, as shown in FIG.

  FIG. 8 is a schematic diagram showing a detailed operation example of the n: 1 signal multiplexing circuit (parallel / serial conversion circuit) of FIG. Here, taking the case of n = 4 as an example, time-series changes in the precode data A0 to A3 and the serial output SLout from the multiplexing / decoding circuit MUX_DEC are shown. As shown in FIG. 8, when n = 4, the delay time of the 1-symbol delay circuit SDLY in FIG. 7 is set to ¼ time of one period (TCLK) of CLK_SL. Here, in the mth cycle of CLK_SL, the values of the parallel signals P0 to P3 that define the latch inputs of FF0 to FF3 are P0 [m] to P3 [m], and the values of the latch outputs E0 to E3 of FF0 to FF3 are E0. [M] to E3 [m]. In this case, from the rising edge of the mth cycle of CLK_SL, E0 [m] becomes A0 as it is, E1 [m] becomes A1 after passing through the delay time of SDLY, and E2 [m] is the delay time of SDLY × 2 E3 [m] becomes A3 after SDLY delay time × 3.

  Further, as shown in FIG. 8, (A0, A1, A2, A3) becomes, for example, (E0 [1], E1 [0], E2 [0], E3 [0]) in a certain symbol cycle, and SDLY It becomes (E0 [1], E1 [1], E2 [0], E3 [0]) in the symbol cycle after the delay time, and (E0 [1], E1 [1] in the symbol cycle after the SDLY delay time. , E2 [1], E3 [0]). Here, when (E0 [1], E1 [0], E2 [0], E3 [0]) is calculated by MUX_DEC, only P0 [1] included in E0 [1] remains. Similarly, when (E0 [1], E1 [1], E2 [0], E3 [0]) is calculated, only P1 [1] included in E1 [1] remains, and (E0 [1], E1 When [1], E2 [1], E3 [0]) are calculated, only P2 [1] included in E2 [1] remains. Therefore, SLout transitions in the order of P0 [1] → P1 [1] → P2 [1] → (P3 [1] → P0 [2] →...) For each symbol cycle, thereby converting the parallel signal into a serial signal. It becomes possible to convert.

  FIG. 9 is a circuit diagram showing a detailed configuration example of the multiplexing / decoding circuit MUX_DEC in FIG. Here, taking the 8: 1 signal multiplexing circuit (parallel / serial conversion circuit) as an example, the multiplexing / decoding circuit MUX_DEC in FIG. 9 is composed of a total of seven 2-input exclusive OR circuits arranged on the tree. It is configured. As described above, when the number n of inputs is a power of 2, by arranging a total of n−1 2-input exclusive OR circuits on the tree in the same manner as the configuration example of FIG. 9, A0 to An. Multiplex / decode circuit MUX_DEC that outputs “0” if the number of “1” s is even among −1, and “1” if the number of “1” s is odd among A0 to An−1. It is possible to configure. In the configuration example of FIG. 9, the first-stage 2-input exclusive OR circuit calculates exclusive OR of adjacent signals such as A0 and A1, A2 and A3, etc. It is not necessary to input A7 in this order. Actually, the two-input exclusive OR operation can be exchanged and the combination rule is established, so that the order of the inputs A0 to A7 in the MUX_DEC in FIG. 9 can be arbitrarily changed.

  In the n: 1 signal multiplexing circuit (parallel / serial conversion circuit) according to the first embodiment, the transition timing of the serial output SLout is generated by the step-like delay circuit SDLY_LAD. Therefore, the multiplexing / decoding circuit MUX_DEC needs to have the same propagation delay from the inputs A0 to An-1 to the serial output SLout so as not to destroy the timing created by SDLY_LAD. The multiplexing / decoding circuit MUX_DEC shown in FIG. 9 has the same number of two-input exclusive OR circuits passing from the inputs A0 to An-1 to the serial output SLout, and satisfies this condition.

  Based on the multiplexing / decoding circuit MUX_DEC in FIG. 9, the multiplexing / decoding circuit MUX_DEC in the case where n is not a power of 2 can be easily configured. FIG. 10 is a circuit diagram showing another detailed configuration example of the multiplexing / decoding circuit MUX_DEC in FIG. 7, and shows a configuration example when n = 5. The multiplexing / decoding circuit MUX_DEC in the case of n = 5 is based on the multiplexing / decoding circuit MUX_DEC (FIG. 9) in the case of n = 8 which is 5 or more and the smallest power of 2, and extra A5 A7 can be realized by fixing at “0”. At this time, the 2-input exclusive OR circuit having A6 and A7 as inputs always outputs “0” and can be omitted. Note that the 2-input exclusive OR circuit indicated by DMY_EOR in FIG. 10 is not logically necessary, but as described above, the number of stages from the input A0 to A4 to the serial signal Sout to be output is aligned, and Inserted to make all propagation delays the same.

  FIG. 11 is a circuit diagram showing a detailed configuration example of the staircase delay circuit SDLY_LAD in FIG. FIG. 12 is a waveform diagram showing an operation example of the delay locked loop in FIG. SDLY_LAD shown in FIG. 11 includes a retiming block RETMR and a delay locked loop DLL_LAD. The RETMR retimes the precoded parallel signals E0 to En-1 and outputs them as A0 to An-1. DLL_LAD generates n−1 phase clock signals CLK_SL_M [1] to CLK_SL_M [n−1] required for the retiming operation in RETMR based on the low speed clock signal CLK_SL.

  As shown in FIG. 12, the DLL_LAD receives n_l phase clock signals CLK_SL_M [1] to CLK_SL_M [n−1] having the same frequency as the CLK_SL and having a phase difference of 2π / n. Generate. The configuration is the same as a well-known delay lock loop, and includes n variable delay circuits VDLY [0] to VDLY [n−1], a phase comparator PD_DLL, and a low-pass filter LPF_DLL that are connected in cascade. . PD_DLL compares the phase of CLK_SL with the output phase of VDLY [n−1], averages this phase comparison result via LPF_DLL, and outputs this averaged signal to VDLY [0] to VDLY [n−1]. ] Is output as a control signal DLL_CTRL for controlling the delay time. By this feedback loop, the delay time of VDLY [0] to VDLY [n−1] is always controlled to be 1 / n of the period of CLK_SL.

  The retiming block RETMR includes n−1 edge trigger flip-flop circuits FF_LAD1 to FF_LAD1 that operate in synchronization with the n−1 phase clock signals CLK_SL_M [1] to CLK_SL_M [n−1] output from the delay lock loop DLL_LAD, respectively. FF_LADn−1 is provided. FF_LAD1 to FF_LADn-1 retime the precoded parallel signals E0 to En-1 with CLK_SL_M [1] to CLK_SL_M [n-1], respectively, and output output signals A0 to An-1. As a result, the output signal Aj is obtained by delaying the input signal Ej by a time j times the one symbol time Tsym, where j is an integer between 0 and less than n.

  The main effects obtained by using the n: 1 signal multiplexing circuit (parallel / serial conversion circuit) according to the first embodiment are summarized as follows. First, as shown in FIG. 7, since the final stage for outputting a serial signal is realized by a combinational logic circuit (multiplexing / decoding circuit MUX_DEC) that does not use a clock signal, as described in FIG. In the final stage selector circuit, the more difficult timing design becomes more prominent as the speed increases. In this case, since the difficulty in timing design is eliminated without using the phase interpolator PI as shown in FIG. 6, an increase in power consumption can be suppressed. Further, as shown in FIG. 11, by implementing the step-like delay circuit SDLY_LAD using the delay lock loop DLL_LAD, a high-speed clock signal having two symbol times as shown in FIGS. 5 and 6 as one cycle. CLK becomes unnecessary, and a low-speed clock signal CLK_SL is sufficient. As a result, the power consumption can be further reduced. For this reason, typically, it is possible to realize high speed and low power consumption in a signal multiplexing circuit (parallel / serial conversion circuit).

(Embodiment 2)
FIG. 13 is a circuit diagram showing a configuration example of an n: 1 signal multiplexing circuit (parallel / serial conversion circuit) according to the second embodiment of the present invention. In the n: 1 signal multiplexing circuit according to the second embodiment, the high-speed clock signal CLKin is input instead of the low-speed clock signal CLK_SL of the n: 1 signal multiplexing circuit according to the first embodiment. Here, CLKin has a period equal to one symbol time Tsym of the serial output SLout. In many cases, the high-speed clock signal CLKin can be used in the transmitter of the optical communication system as shown in FIG. 1 useful as an application destination of the n: 1 signal multiplexing circuit (parallel / serial conversion circuit) of the present embodiment.

  The n: 1 signal multiplexing circuit (parallel / serial conversion circuit) shown in FIG. 13 includes a 1 / n frequency divider DIVN_M, a pre-encoder circuit PREENC, a retiming block RETMR, and a multiplexing / decoding circuit MUX_DEC. ing. DIVN_M receives the high-speed clock signal CLKin, and generates low-speed n-phase clock signals CLKinDIV_M [0] to CLKinDIV_M [n−1] having a cycle of 1 / n of CLKin and the number of clock phases of n-phase. PREENC, RETMR, and MUX_DEC can use the same configurations as those in the first embodiment.

  The n-phase clock signals CLKinDIV_M [0] to CLKinDIV_M [n−1] generated by DIVN_M have a period of 1 / n of CLKin and a phase difference between adjacent clock phases of 2π / n. Such DIVN_M can be easily configured using, for example, a frequency divider provided with a shift register. In the n: 1 signal multiplexing circuit (parallel / serial conversion circuit) according to the second embodiment, an n-phase clock signal for retiming is generated based on the high-speed clock signal CLKin. The phase difference between adjacent clock phases of CLKinDIV_M [0] to CLKinDIV_M [n−1] can be accurately 2π / n. Therefore, in the signals A0 to An-1 input to the multiplexing / decoding circuit MUX_DEC, the timing difference between adjacent signals is exactly equal to one symbol time Tsym, so that the jitter included in the serial output SLout is reduced. be able to.

  14 shows details of the 1 / n frequency divider DIVN_M in FIG. 13. FIG. 14A is a circuit diagram showing a configuration example thereof, and FIG. 14B is a diagram showing each clock in FIG. 14A. FIG. 14C is a waveform diagram showing an operation example of FIG. 14A. FIG. 14A shows a configuration example of DIVN_M that generates 8-phase (n = 8) clock signals CLKinDIV_M [0] to CLKinDIV_M [7]. Here, a configuration example is shown in which four clocked inverter circuits CIV are cascaded in order, and the output of the final stage is fed back to the input of the first stage via the inverter circuit IV.

  As shown in FIG. 14B, the clocked inverter circuit CIV includes two PMOS transistors connected in series between the output node Out and the power supply voltage, and 2 connected in series between Out and the ground power supply voltage. It is composed of NMOS transistors. CLKin and its inverted clock signal / CLKin are input to the gates of the NMOS and PMOS transistors on the Out side, respectively, and signals from the input node In are input to the gates of the remaining NMOS and PMOS transistors. Such a CIV functions as a shift register. Therefore, from the output node of each CIV in FIG. 14 (a), a signal having a different phase is output for each cycle of CLKin, and its inverted output is also used, as shown in FIG. 14 (c). The 8-phase clock signals CLKinDIV_M [0] to CLKinDIV_M [7] can be generated.

  As described above, the n: 1 signal multiplexing circuit (parallel / serial conversion circuit) according to the second embodiment is typically included in the serial output SLout in addition to the various effects described in the first embodiment. A signal multiplexing circuit with low jitter can be realized.

(Embodiment 3)
In the third embodiment, a detailed configuration example of each 2-input exclusive OR circuit shown in FIG. 9 and the like of the first embodiment will be described. In the n: 1 signal multiplexing circuit (parallel / serial conversion circuit) according to the present embodiment, in order to increase the speed and reduce the jitter in the serial output SLout, in addition to the performance of the stepped delay circuit SDLY_LAD described above, The performance of the decoding circuit MUX_DEC is also important. As for the jitter reduction of MUX_DEC, as described in FIGS. 9 and 10, it is beneficial to make the number of stages from the input to the output uniform, but in addition to this, each 2-input exclusive OR circuit unit It is beneficial to reduce jitter.

  FIG. 15 shows a detailed configuration example of the 2-input exclusive OR circuit included in the multiplexing / decoding circuit MUX_DEC in the n: 1 signal multiplexing circuit (parallel / serial conversion circuit) according to the third embodiment of the present invention. FIG. The 2-input exclusive OR circuit shown in FIG. 15 includes two 2: 1 selector circuits SELP_EOR and SELN_EOR and a P / N mixing circuit MIX_EOR. This two-input exclusive OR circuit takes a first differential input signal (Ap (positive), An (negative)) and a second differential input signal (Bp (positive), Bn (negative)) as two inputs. The exclusive OR operation result is output as a differential output signal (OutP (positive electrode), OutN (negative electrode)).

  SELP_EOR takes Ap and An as two inputs and selects and outputs one of them according to the logic levels of Bp and Bn. Conversely, SELN_EOR takes Bp and Bn as two inputs and one of them as Ap and An. Depending on the selection and output. For example, SELP_EOR outputs Ap (ie, “0”) when (Ap, Bp) is (0, 0), and outputs An (ie, “1”) when (0, 1). In the case of (1, 0), Ap (ie, “1”) is output, and in the case of (1, 1), An (ie, “0”) is outputted. In this way, an exclusive OR operation can be performed by using one selector circuit. Since the selector circuit can be realized by a switch circuit as will be described later, the speed can be increased. However, when the exclusive OR operation is realized with one selector circuit, there is a possibility that the rising speed and the falling speed of the output are different (that is, there is a risk of jitter). Therefore, here, SELN_EOR that performs an operation opposite to SELP_EOR and outputs the opposite is provided, and OutP and OutN are generated by mixing (averaging) the output of SELP_EOR and the output of SELN_EOR with MIX_EOR.

  16 shows details of the 2-input exclusive OR circuit in FIG. 15. FIG. 16 (a) is a circuit diagram showing a configuration example thereof, and FIG. 16 (b) is a schematic diagram of FIG. 16 (a). It is a wave form diagram which shows an example of operation. As shown in FIG. 16A, each of the 2: 1 selector circuits SELP_EOR and SELN_EOR in FIG. 15 has two CMOS switch circuits that select and output one of the two inputs, and a common output node as an input. An inverter circuit that outputs the inverted signal is provided. In the case of SELP_EOR, on / off of the two CMOS switch circuits is controlled by Bp and Bn, and in the case of SELN_EOR, on / off of the two CMOS switch circuits is controlled by An and Ap. By configuring the selector circuit using the CMOS switch circuit in this manner, the speed can be increased as compared with a case where a logic gate such as a NAND operation circuit is combined. The P / N mixing circuit MIX_EOR includes an inverter circuit that receives the output of SELP_EOR and outputs the output of SELN_EOR, and conversely, an inverter circuit that receives the output of SELN_EOR and outputs the output of SELP_EOR.

  In the 2: 1 selector circuit as shown in FIG. 16A, for example, when SELP_EOR is taken as an example, Ap and An change when Bp and Bn are fixed until an output reflecting the change is output from SELP_EOR. And Bp and Bn change when Ap and An are fixed, and there is a possibility that the time until the output reflecting this changes from SELP_EOR is different. Specifically, when Bp and Bn change, it is necessary to drive the gate of the CMOS switch circuit, and therefore, the output may be delayed compared to when Ap and An change. In this case, as described above, since the complementary operation is performed between SELP_EOR and SELN_EOR, the SELP_EOR output and the SELN_EOR output have different timings as shown in FIG. A situation may occur in which the width and the “L” level pulse width are different.

  Therefore, the P / N mixing circuit MIX_EOR in FIG. 16A generates OutP by mixing the output timing of SELN_EOR with the inverter circuit at the output timing of SELP_EOR, and generates the output timing of SELP_EOR at the output timing of SELN_EOR. To generate OutN. As a result, as shown in FIG. 16B, OutP and OutN become differential signals with the same timing, and the “H” level pulse width and “L” level pulse width at OutP and OutN are also uniform. Become.

  As described above, by using the n: 1 signal multiplexing circuit (parallel / serial conversion circuit) according to the third embodiment, typically, in addition to the various effects described in the first and second embodiments, an even higher speed is achieved. And further reduction of jitter included in the serial output. In the 2: 1 selector circuits SELP_EOR and SELN_EOR in FIG. 16A, the output of the CMOS switch circuit is output via an inverter circuit. For example, Bp and Bn are switched in SELP_EOR, and An and Ap are switched in SELN_EOR. It is possible to delete the inverter circuit.

(Embodiment 4)
In the fourth embodiment, a configuration example different from that in FIG. 15 of each 2-input exclusive OR circuit shown in FIG. 9 and the like of the first embodiment will be described. FIG. 17 shows a detailed configuration example of the 2-input exclusive OR circuit included in the multiplexing / decoding circuit MUX_DEC in the n: 1 signal multiplexing circuit (parallel / serial conversion circuit) according to the fourth embodiment of the present invention. FIG. The 2-input exclusive OR circuit shown in FIG. 17 outputs the output signal OUT according to the positive side (Ap) of the first differential input signal and the second differential input signal (Bp (positive electrode), Bn (negative electrode)). A first circuit block to be generated, a negative circuit side (An) of the second differential input signal, and a second circuit block to generate OUT according to Bp and Bn are provided.

  The first circuit block includes PMOS transistors MP1 to MP4 and NMOS transistors MN1 to MN4. In MP1 and MP2, the power supply voltage is supplied to the source, and the drain is commonly connected to the gate of MP4. In MN1 and MN2, the ground power supply voltage is supplied to the source, and the drain is commonly connected to the gate of MN4. In MP3 and MN3, a source / drain path is connected between the gate of MP4 and the gate of MN4. MP4 is supplied with power supply voltage at the source and outputs OUT from the drain, and MN4 is supplied with ground power supply voltage at the source and outputs OUT from the drain. Ap is input to the gates of MP1 and MN1, Bn is input to the gates of MP2 and MN3, and Bp is input to the gates of MN2 and MP3. The second circuit block has the same circuit configuration as the first circuit block, but the gate signal of each transistor is different from that of the first circuit block, and each gate signal is a complementary signal of each gate signal in the first circuit block. It has become.

  In the first circuit block, first, when Bn is “1” (Bp is “0”), MP3 and MN3 are turned on, MP2 and MN2 are turned off, and MP4 is placed in the subsequent stage of the CMOS inverter circuit composed of MP1 and MN1. , MN4 CMOS inverter circuit is connected. As a result, when Ap is “1”, OUT is “1”, and when Ap is “0”, OUT is “0”. On the other hand, when Bn is “0” (Bp is “1”), MP3 and MN3 are off and MP2 and MN2 are on. As a result, MP4 and MN4 are driven off regardless of the state of Ap, and OUT is determined by the second circuit block. In the second circuit block, an operation reverse to that of the first circuit block is performed, and when Bp is “1” (Bn is “0”) and An is “1” (Ap is “0”). OUT is “1”, and when An is “0” (Ap is “1”), OUT is “0”. When Bp is “0” (Bn is “1”), OUT is determined by the first circuit block. As a result, an exclusive OR operation result of Ap and Bp is obtained from OUT.

  When such a configuration example is used, for example, when Ap transitions in a state where Bn is “1” (Bp is “0”), in the first circuit block, MP1, MN1, MP4, and MN4 are driven through two-stage driving. OUT is generated according to Ap. In parallel with this, in the second circuit block, OUT becomes a high impedance state through two-stage driving of MP2, MN2 and MP4, MN4. On the other hand, when Ap is “1” or “0” and Bn transitions to “0” (Bp is “1”), the first circuit block passes through the two-stage driving of MP2, MN2, MP4, and MN4. OUT becomes a high impedance state, and in parallel with this, OUT corresponding to An is generated through two-stage driving of MP1, MN1 and MP4, MN4 in the second circuit block. In this way, when the configuration example of FIG. 17 is used, OUT is generated after driving the same number of stages when Ap or Bp transitions. Therefore, the 2: 1 selector circuits SELP_EOR and SELN_EOR in FIG. Jitter that may occur can be reduced. That is, jitter can be reduced without using a P / N mixing circuit MIX_EOR or the like as shown in FIG.

  As described above, by using the n: 1 signal multiplexing circuit (parallel / serial conversion circuit) according to the fourth embodiment, it is typically described in the first and second embodiments as in the third embodiment. In addition to the various effects, it is possible to further increase the speed and further reduce the jitter included in the serial output. In the configuration example of FIG. 17, similarly to the case of FIG. 16A, for example, it is possible to replace Bn and Bp and add an inverter circuit to OUT.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.

  The signal multiplexing circuit according to the present embodiment is particularly effective when applied to the circuit of the transmission section in an optical communication system having a communication speed exceeding several tens of Gbps.

OFE_BLK Optical / electrical conversion block SD_BLK Parallel / serial conversion block PU Upper layer logic block OEC Optical / electrical conversion circuit EOC Electric / optical conversion circuit IF_I input circuit CDR signal regeneration circuit SPC serial / parallel conversion circuit PSC signal multiplexing circuit (parallel / Serial conversion circuit)
IF_O output circuit CLK_GEN clock generation circuit PS 2: 1 signal multiplexing circuit DIV2 divide-by-2 circuit FF edge trigger flip-flop circuit LT level trigger latch circuit CK_DLY delay circuit SEL2 2: 1 selector circuit CTRL_BLK phase control block PD, PD_DLL phase comparator LPF, LPF_DLL Low-pass filter PI Phase interpolator PREENC Pre-encoder circuit SDLY_LAD Stepwise delay circuit EOR, DMY_EOR 2-input exclusive OR circuit SDLY 1 symbol delay circuit MUX_DEC Multiplex / decode circuit RETMR Retiming block DLL_LAD Delay lock loop Delay Circuit DIVN_M 1 / n frequency divider CIV clocked inverter circuit IV inverter circuit SELP_E OR, SELN_EOR 2: 1 selector circuit MIX_EOR P / N mixing circuit MP PMOS transistor MN NMOS transistor

Claims (8)

First to Nth (N is an integer greater than or equal to 2) parallel signals are precoded with a predetermined combinational logic every first cycle time, and the first to Nth precoded signals are output in parallel at each first cycle time. A pre-encoder circuit to
The first precoded signal is output as a first signal starting from the second timing, and the Kth (K is an integer of 2 or more and N or less) precoding signal is output from the second timing as “(the first A delay circuit block that outputs the first to Nth signals by adding a delay of (cycle time / N) × (K−1) ”and outputting as the Kth signal;
And a decoding circuit that converts the first to Nth parallel signals into serial signals by decoding the first to Nth signals with combinational logic corresponding to the precode. Multiplexing circuit. The signal multiplexing circuit according to claim 1, wherein
The pre-encoder circuit is
A first to Nth holding circuit for performing a latch operation in synchronization with a first clock signal having the first cycle time and outputting the first to Nth precoded signals in parallel;
A first to Nth exclusive OR circuit;
The first exclusive OR circuit receives the first parallel signal and the output signal of the Nth holding circuit as inputs, and outputs the exclusive OR operation result to the first holding circuit,
The Kth exclusive OR circuit receives the Kth parallel signal and the output signal of the (K−1) th exclusive OR circuit as inputs, and outputs the exclusive OR operation result to the Kth holding circuit,
The signal multiplexing circuit, wherein the decoding circuit performs an exclusive OR operation with the first to Nth signals as inputs. The signal multiplexing circuit according to claim 2, wherein
When N is a power of 2, the decoding circuit is configured by cascading 2-input exclusive OR circuits in (log ₂ N) stages, where N is not a power of 2 In this case, it is configured by cascading 2-input exclusive OR operation circuits with the number of stages based on the smallest power of 2 that is greater than or equal to N, and a part of the input of the first stage is set to a fixed value. A signal multiplexing circuit characterized by the above. The signal multiplexing circuit according to claim 3, wherein
The two inputs of the two-input exclusive OR circuit are the first and second differential input signals,
The two-input exclusive OR circuit is
A first transistor switch circuit having one end input with a first polarity of the first differential input signal and being controlled to be turned on and off by the second differential input signal;
The second polarity of the first differential input signal is input to one end and the other end is connected in common with the other end of the first transistor switch circuit, and the second differential input signal is turned on / off by the second differential input signal. A signal multiplexing circuit comprising: a first transistor switch circuit; and a second transistor switch circuit controlled in a complementary manner. 5. The signal multiplexing circuit according to claim 4, wherein
The two-input exclusive OR circuit further includes:
A third transistor switch circuit that is input at one end with the first polarity of the second differential input signal and is controlled to be turned on and off by the first differential input signal;
The second polarity of the second differential input signal is input to one end, and the other end is commonly connected to the other end of the third transistor switch circuit, and the first differential input signal is turned on / off by the first differential input signal. A fourth transistor switch circuit controlled in a complementary manner to the three-transistor switch circuit;
And a mixing circuit,
The other ends of the first and second transistor switch circuits are coupled to the first polarity of the differential output signal,
The other ends of the third and fourth transistor switch circuits are coupled to a second polarity of the differential output signal,
The mixing circuit shapes the waveform of the first polarity of the differential output signal by synthesizing an inverted signal of the second polarity of the differential output signal with the first polarity of the differential output signal. A signal multiplexing circuit that shapes the waveform of the second polarity of the differential output signal by synthesizing the inverted signal of the first polarity of the differential output signal with the second polarity of the output signal. The signal multiplexing circuit according to claim 3, wherein
The two inputs of the two-input exclusive OR circuit are the first and second differential input signals,
The two-input exclusive OR circuit is
A first circuit block that outputs to the output node with the first polarity of the first differential input signal and the first polarity and the second polarity of the second differential input signal as inputs; and
A second circuit block that outputs the second polarity of the first differential input signal and the second differential input signal to the output node with the second polarity and the first polarity as inputs;
The first circuit block includes:
A first MIS transistor of a first conductivity type having a power supply voltage supplied to a source and a drain connected to the output node;
A second MIS transistor of the second conductivity type having a ground power supply voltage supplied to a source and a drain connected to the output node;
Third and fourth MIS transistors of the first conductivity type, the source voltage being supplied to the source and the drain connected to the gate of the first MIS transistor;
Fifth and sixth MIS transistors of the second conductivity type, the ground power supply voltage being supplied to the source and the drain connected to the gate of the second MIS transistor;
A first conductivity type seventh MIS transistor and a second conductivity type eighth MIS transistor, each having a source / drain path connected between the gate of the first MIS transistor and the gate of the second MIS transistor;
The first polarity of the first differential input signal is input to the gates of the third and fifth MIS transistors,
One of the first polarity and the second polarity of the second differential input signal is input to the gates of the fourth and eighth MIS transistors,
The other of the first polarity and the second polarity of the second differential input signal is input to the gates of the sixth and seventh MIS transistors,
The second circuit block has the same circuit configuration as the first circuit block, and the polarity of the gate signal of each MIS transistor is opposite to that of the first circuit block. Circuit. The signal multiplexing circuit according to claim 2, wherein
The delay circuit block is:
The first clock signal having the first cycle time is input, and second to N-phase clock signals having the first cycle time and having a phase difference of “the first cycle time / N” unit are respectively obtained. A delay lock loop circuit to generate;
A second phase to an Nth phase holding circuit for performing a latch operation in synchronization with the second phase to the Nth phase clock signal and outputting the second to Nth signals, respectively.
The delay lock loop circuit includes:
A plurality of variable delay circuits for sequentially delaying the output of the preceding stage and outputting the output to the subsequent stage with the first clock signal as the first stage input;
A phase comparator that compares the phase of the first clock signal with the phase of the output signal from the final stage of the plurality of variable delay circuits and controls the delay time of the plurality of variable delay circuits according to the comparison result; A signal multiplexing circuit comprising: The signal multiplexing circuit according to claim 2, wherein
The delay circuit block is:
A second clock signal including a shift register and having a second cycle time of “the first cycle time / N” is input, and has the first cycle time and a phase difference in units of the second cycle time. A counter circuit for generating a second phase to an Nth phase clock signal;
A signal having a second phase to an Nth phase holding circuit for performing a latch operation in synchronization with the second phase to the Nth phase clock signal and outputting the second to Nth signals, respectively. Multiplexing circuit.

Images