JP2012105277A - Level shifter, system-on-chip including the same, and multimedia device including the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a level shifter having improved reliability, a system-on-chip including the same, and a multimedia device including the same.SOLUTION: The level shifter includes first and second voltage shifter circuits configured to generate an output clock of a second voltage domain in response to an input clock of a first voltage domain input via an input node. The first and second voltage shifter circuits have the same structure and are connected in parallel between the input node and an output node.

Description

  The present invention relates to electronic circuits, and more particularly to level converters, system-on-chip including the same, and multimedia devices including the same.

  The level shifter is an element that receives a first voltage domain signal and outputs a second voltage domain signal different from the first voltage. Level translators are used between multiple voltage domains that use different voltages.

  A system on chip (SOC, System-On-Chip) includes a plurality of IPs (Intellectual Properties) and processors. The processor has a faster operating speed than IP. In order to improve the operating performance of the processor, the voltage level of the clock supplied to the processor can be set higher than the voltage level of the clock supplied to the IP. A level converter can be used in the system on chip (SOC) to raise the voltage level of the clock supplied to the processor.

Korean Patent Publication No. 10-2006-0119667

  An object of the present invention is to provide a level converter having improved reliability, a system-on-chip including the level converter, and a multimedia device including the level converter.

  A level converter according to an embodiment of the present invention is configured to generate an output clock of a second voltage domain in response to an input node and an input clock of the first voltage domain received through the input node. A second voltage conversion circuit and an output node for outputting the output clock, wherein the first and second voltage conversion circuits have the same structure and are connected in parallel between the input node and the output node Is done.

  As an embodiment, the first voltage conversion circuit includes at least two inverters operating in the second voltage domain.

  As an embodiment, the second voltage conversion circuit includes at least one inverter operating in the first voltage domain and at least one inverter operating in the second voltage domain.

  As an embodiment, at least one inverter operating in the second voltage domain is configured to receive an output of at least one inverter operating in the first voltage domain.

  As an embodiment, the first voltage converter circuit outputs a second voltage or a ground voltage according to the voltage of the input node, and the second voltage or the ground voltage as an output node according to the output of the first inverter. A second inverter for outputting, wherein the second voltage conversion circuit outputs the first voltage or the ground voltage according to the voltage of the input node, and the second voltage or ground according to the output of the third inverter. A fourth inverter for outputting a voltage to the output node;

  As an embodiment, the first to fourth inverters are CMOS inverters.

  A system-on-chip according to an embodiment of the present invention includes a phase-locked loop (PLL) configured to generate a first clock of a first voltage domain, a peripheral block that operates according to the first clock, an audio block, A display block, a graphics block, an image processing block, and a codec block; a level converter that generates a second clock of a second voltage domain based on the first clock; and a processor that operates according to the second clock. The level converter includes first and second voltage conversion circuits connected in parallel between an input node and an output node and having the same structure.

  As an embodiment, the first voltage conversion circuit operates in the second voltage domain and includes first and second inverters connected in series, and the second voltage conversion circuit operates in the first voltage domain. And a fourth inverter that operates in response to the output of the third inverter in the second voltage domain.

  As an embodiment, the voltage level of the second voltage domain is higher than the voltage level of the first voltage domain.

  A multimedia device according to an embodiment of the present invention stores a processor, an operating memory of the processor, a modem configured to communicate with the outside according to the control of the processor, and stores data according to the control of the processor. A storage unit configured to display an image through a display unit according to control of the processor and a user interface configured to detect and transmit an external signal to the processor. A display control unit configured, a sound control unit configured to output sound through a speaker according to the control of the processor, and a codec unit performing encoding and decoding according to the control of the processor A clock generator configured to generate a clock according to an output of the oscillator; a phase-locked loop that generates a first clock of a first voltage domain synchronized with the clock; and a first according to the first clock. A level converter configured to generate a second clock in a two voltage domain, wherein the processor operates in response to the second clock, the level converter being in parallel between an input node and an output node And first and second voltage conversion circuits having the same structure.

  As an embodiment, a first inverter that outputs the second voltage or the ground voltage of the second voltage domain according to the voltage of the input node, and the second voltage or the ground voltage according to the output of the first inverter as an output node A second inverter that outputs, a third inverter that outputs the first voltage or ground voltage of the first voltage domain according to the voltage of the input node, and the second voltage or ground voltage according to the output of the third inverter. Is output to the output node.

  As an embodiment, the processor, operation memory, display control unit, sound control unit, codec unit, and phase lock loop are included in a system-on-chip, and the operation memory, display control unit, sound control unit, and codec unit are Operates according to the first clock.

  The image processing unit may further include an image processing unit configured to process image data acquired from the camera according to the control of the processor.

  As an embodiment, the processor, display control unit, sound control unit, image processing unit, operation memory, codec unit, and phase lock loop are included in the system on chip, the display control unit, sound control unit, image processing unit, The operation memory and the codec unit operate according to the first clock.

  As an embodiment, the processor, the display control unit, the sound control unit, the modem, the image processing unit, the operation memory, the codec unit, and the phase lock loop are included in a system on chip, the display control unit, the sound control unit, the modem, The image processing unit, the operation memory, and the codec unit operate according to the first clock.

  As an embodiment, the processor, the display control unit, the sound control unit, the operation memory, the codec unit, and the phase lock loop are included in a system-on-chip, and the display control unit, the sound control unit, the operation memory, and the codec unit are Operates according to the first clock.

  As an embodiment, the processor, the display control unit, the sound control unit, the operation memory, and the phase lock loop are included in a system on chip, and the display control unit, the sound control unit, and the operation memory are in accordance with the first clock. Operate.

  As an embodiment, the processor, the display control unit, the operation memory, and the phase lock loop are included in a system-on-chip, and the display control unit and the operation memory operate according to the first clock.

  In one embodiment, the processor, the operation memory, and the phase locked loop are included in a system on chip, and the operation memory operates in response to the first clock.

  As an embodiment, the processor, the sound control unit, the operation memory, and the phase lock loop are included in a system on chip, and the sound control unit and the operation memory operate according to the first clock.

  As an embodiment, the processor, operation memory, modem, storage unit, user interface, display control unit, display unit, sound control unit, speaker, oscillator, clock generation unit, camera, image processing unit, codec unit, and phase lock The loop is included in the mobile device.

  As an embodiment, the processor, operation memory, modem, storage unit, user interface, display control unit, display unit, sound control unit, speaker, oscillator, clock generation unit, camera, image processing unit, codec unit, and phase lock The loop is included in a smart television.

  The level converter according to an embodiment of the present invention includes a first voltage conversion circuit, and a second voltage conversion circuit connected in parallel with the first voltage conversion circuit between an input node and an output node, and the input node A second clock of the second voltage domain is output from the output node in response to the first clock of the first voltage domain input to the first voltage domain, and a delay time between the rising edge of the first clock and the rising edge of the second clock Is the same as the delay time between the falling edge of the first clock and the falling edge of the second clock.

  According to the present invention, the width of the high level section and the width of the low level section of the output clock of the level converter are leveled. Accordingly, a level translator with improved reliability, a system on chip including the same, and a multimedia device including the same are provided.

It is a block diagram which shows the level converter by embodiment of this invention. It is a circuit diagram which shows the level converter by embodiment of this invention. 3 is a diagram illustrating operations of first to fourth inverters described with reference to FIG. 2 when a first clock rises. 3 is a diagram illustrating operations of first to fourth inverters described with reference to FIG. 2 when a first clock falls. FIG. 5 is a timing diagram illustrating an input clock and an output clock of the level converter described with reference to FIGS. 1 to 4. FIG. 6 is a block diagram illustrating a system-on-chip including the level converter described with reference to FIGS. 1 to 5. 1 is a block diagram illustrating a first example of a multimedia device including a level converter according to an embodiment of the present invention. FIG. 6 is a block diagram illustrating a second example of a multimedia device including a level converter according to an embodiment of the present invention. FIG. 6 is a block diagram illustrating a third example of a multimedia device including a level converter according to an embodiment of the present invention. FIG. 6 is a block diagram illustrating a fourth example of a multimedia device including a level converter according to an embodiment of the present invention. FIG. 10 is a block diagram illustrating a fifth example of a multimedia device including a level converter according to an embodiment of the present invention. FIG. 10 is a block diagram illustrating a sixth example of a multimedia device including a level converter according to an embodiment of the present invention. FIG. 9 is a block diagram illustrating a seventh example of a multimedia device including a level converter according to an embodiment of the present invention. FIG. 10 is a block diagram illustrating an eighth example of a multimedia device including a level converter according to an embodiment of the present invention. 1 is a diagram illustrating a smartphone according to an embodiment of the present invention. 1 is a diagram illustrating a tablet computer according to an embodiment of the present invention. 1 is a diagram illustrating a mobile computer according to an embodiment of the present invention. 1 is a diagram illustrating a computer according to an embodiment of the present invention. 1 is a diagram illustrating a television according to an embodiment of the present invention.

  DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art to which the present invention pertains can easily implement the technical idea of the present invention. I will explain.

  FIG. 1 is a block diagram illustrating a level converter 100 according to an embodiment of the present invention. Referring to FIG. 1, the level converter 100 includes a first voltage conversion circuit 110 and a second voltage conversion circuit 120. The first and second voltage conversion circuits 110 and 120 are connected in parallel between the input node A and the output node F.

  The first voltage conversion circuit 110 receives the first clock CLK1 of the first voltage domain corresponding to the first voltage V1 through the input node A. The first clock CLK1 may have a swing width of the first voltage V1. The first voltage conversion circuit 110 generates a second voltage domain signal corresponding to the second voltage V2 based on the received first clock CLK1. The second clock CLK2 may have a swing width of the second voltage V2.

  The first voltage conversion circuit 110 includes first and second inverters 111 and 113. The first inverter 111 is configured to output one of the second voltage V2 and the ground voltage VSS according to the first clock CLK1. The second inverter 113 is configured to output one of the second voltage V2 and the ground voltage VSS according to the output of the first inverter 111. That is, the second inverter 113 outputs a second voltage domain signal synchronized with the first clock CLK1.

  The second voltage conversion circuit 120 receives the first clock CLK1 of the first voltage domain through the input node A. The first voltage conversion circuit 110 generates a second voltage domain signal based on the received first clock CLK1.

  The second voltage conversion circuit 120 has the same structure as the first voltage conversion circuit 110. The second voltage conversion circuit 120 includes third and fourth inverters 121 and 123. The third inverter 121 is configured to output one of the first voltage V1 and the ground voltage VSS according to the first clock CLK1. The fourth inverter 123 is configured to output one of the second voltage V2 and the ground voltage VSS according to the output of the third inverter 121. That is, the fourth inverter 123 outputs a second voltage domain signal synchronized with the first clock CLK1.

  The first and second voltage conversion circuits 110 and 120 are mixed at the output node F. The first voltage conversion circuit 110 outputs a second voltage domain signal synchronized with the first clock CLK1. The second voltage conversion circuit 120 also outputs a second voltage domain signal synchronized with the first clock CLK1. In other words, a signal in the second voltage domain synchronized with the first clock CLK1 is generated at the output node F. The signal at the output node F is output to the second clock CLK2 in the second voltage domain.

  FIG. 2 is a circuit diagram illustrating a level converter 100 according to an embodiment of the present invention. Illustratively, the internal circuits of the first to fourth inverters 111, 113, 121, and 123 described with reference to FIG. 1 are illustrated. For example, each of the first to fourth inverters 111, 113, 121, and 123 may be a CMOS inverter. However, the internal circuits of the first to fourth inverters 111, 113, 121, and 123 are not limited to the circuit illustrated in FIG.

  Referring to FIGS. 1 and 2, the first inverter 111 includes a first PMOS transistor P1 and a first NMOS transistor N1. The gate of the first PMOS transistor P1 is connected to the input node A. The second voltage V2 is supplied to one end of the first PMOS transistor P1, and the other end is connected to the output node B. The gate of the first NMOS transistor N1 is connected to the input node A. One end of the first NMOS transistor N1 is connected to the ground node, and the other end is connected to the output node B.

  The second inverter 113 has the same structure as the first inverter 111. The second inverter 113 includes a second PMOS transistor P2 and a second NMOS transistor N2. The gate of the second PMOS transistor P2 is connected to the output node B of the first inverter 111. The second voltage V2 is supplied to one end of the second PMOS transistor P2, and the other end is connected to the output node C. The gate of the second NMOS transistor N2 is connected to the output node B of the first inverter 111. One end of the second NMOS transistor N2 is connected to the ground node, and the other end is connected to the output node C.

  The third inverter 121 has the same structure as the first inverter 111. The third inverter 121 includes a third PMOS transistor P3 and a third NMOS transistor N3. The gate of the third PMOS transistor P3 is connected to the input node A. The first voltage V1 is supplied to one end of the third PMOS transistor P3, and the other end is connected to the output node D. The gate of the third NMOS transistor N3 is connected to the input node A. One end of the third NMOS transistor N3 is connected to the ground node, and the other end is connected to the output node D.

  The fourth inverter 123 has the same structure as the first inverter 111. The fourth inverter 123 includes a fourth PMOS transistor P4 and a fourth NMOS transistor N4. The gate of the fourth PMOS transistor P4 is connected to the output node D of the third inverter 121. The second voltage V2 is supplied to one end of the fourth PMOS transistor P4, and the other end is connected to the output node E. The gate of the fourth NMOS transistor N4 is connected to the output node D of the third inverter 121. One end of the fourth NMOS transistor N4 is connected to the ground node, and the other end is connected to the output node E.

  FIG. 3 illustrates operations of the first to fourth inverters 111, 113, 121, and 123 described with reference to FIG. 2 when the first clock CLK1 rises. 2 and 3, the first clock CLK1 rises from the ground voltage VSS to the first voltage V1. When the first clock CLK1 is the first voltage V1, the first PMOS transistor P1 of the first inverter 111 is turned off and the first NMOS transistor N1 is turned on. That is, the output node B of the first inverter 111 is connected to the ground node.

  When the first clock CLK1 is the ground voltage VSS, the second voltage V2 is supplied to the output node B of the first inverter 111 through the first PMOS transistor P1. Accordingly, when the first clock CLK1 rises from the ground voltage VSS to the first voltage V1, the voltage at the output node B of the first inverter 111 is discharged from the second voltage V2 to the ground voltage VSS.

  Specifically, the channel of the first NMOS transistor N1 is applied with the second voltage V2 applied to the drain D1 of the first NMOS transistor N1, the first voltage V1 applied to the gate G1, and the ground voltage VSS applied to the source S1. Through which the voltage at the output node B is discharged. At this time, the time required for the voltage at the output node B of the first inverter 111 to be discharged to the ground voltage VSS may be the first time T1. The first time T1 may be a delay time until the voltage of the output node B of the first inverter 111 falls in synchronization with the rising edge of the first clock CLK1.

  When the output voltage of the first inverter 111 is the ground voltage VSS, the second NMOS transistor N2 of the second inverter 113 is turned off and the second PMOS transistor P2 is turned on. That is, the second voltage V2 is supplied to the output node C of the second inverter 113.

  When the output voltage of the first inverter 111 is the second voltage V2, the ground voltage VSS is supplied to the output node C of the second inverter 113 through the second NMOS transistor N2. Therefore, when the output voltage of the first inverter 111 drops from the second voltage V2 to the ground voltage VSS, the voltage at the output node C of the second inverter 113 is charged from the ground voltage VSS to the second voltage V2.

  Specifically, the second voltage V2 is applied to the source S2 of the second PMOS transistor P2, the ground voltage VSS is applied to the gate G2, and the ground voltage VSS is applied to the drain D2, through the channel of the second PMOS transistor P2. The voltage at the output node C is charged. At this time, the time required for the voltage of the output node C of the second inverter 113 to be charged to the second voltage V2 may be the second time T2. The second time T2 may be a delay time until the voltage of the output node C of the second inverter 113 rises in synchronization with the falling edge of the output voltage of the first inverter 111.

  The first clock CLK1 rises from the ground voltage VSS to the first voltage V1. When the first clock CLK1 is the first voltage V1, the third PMOS transistor P1 of the third inverter 121 is turned off and the third NMOS transistor N3 is turned on. That is, the ground voltage VSS is supplied to the output node D of the third inverter 121.

  When the first clock CLK1 is the ground voltage VSS, the first voltage V1 is supplied to the output node D of the third inverter 121 through the third PMOS transistor P3. Accordingly, when the first clock CLK1 rises from the ground voltage VSS to the first voltage V1, the voltage at the output node D of the third inverter 121 is discharged from the first voltage V1 to the ground voltage VSS.

  Specifically, the channel of the third NMOS transistor N3 is applied with the first voltage V1 applied to the drain D3 of the third NMOS transistor N3, the first voltage V1 applied to the gate G3, and the ground voltage VSS applied to the source S3. The voltage of the output node D is discharged through. At this time, the time required for the voltage at the output node D of the third inverter 121 to be discharged to the ground voltage VSS may be a third time T3. The third time T3 may be a delay time until the voltage of the output node D of the third inverter 121 falls in synchronization with the rising edge of the first clock CLK1.

  When the output of the third inverter 121 is the ground voltage VSS, the fourth NMOS transistor N4 of the fourth inverter 123 is turned off and the fourth PMOS transistor P4 is turned on. That is, the second voltage V2 is supplied to the output node E of the fourth inverter 123.

  When the output voltage of the third inverter 121 is the first voltage V1, the ground voltage VSS is supplied to the output node E of the fourth inverter 123 through the fourth NMOS transistor N4. Accordingly, when the output voltage of the third inverter 121 drops from the first voltage V1 to the ground voltage VSS, the voltage at the output node E of the fourth inverter 123 is charged from the ground voltage VSS to the second voltage V2.

  Specifically, the second voltage V2 is applied to the source S4 of the fourth PMOS transistor P4, the ground voltage VSS is applied to the gate G4, and the ground voltage VSS is applied to the drain D4, and the channel of the fourth PMOS transistor P4. The voltage at the output node E is charged. At this time, the bias condition of the fourth PMOS transistor P4 of the fourth inverter 123 is the same as the bias condition of the second PMOS transistor P2 of the second inverter 113. Therefore, the time required for the voltage of the output node E of the fourth inverter 123 to be charged to the second voltage V2 may be the second time T2. The second time T2 may be a delay time until the voltage at the output node E of the fourth inverter 123 rises in synchronization with the falling edge of the output voltage of the third inverter 121.

  FIG. 4 illustrates operations of the first to fourth inverters 111, 113, 121, and 123 described with reference to FIG. 2 when the first clock CLK1 falls. 2 and 4, the first clock CLK1 falls from the first voltage V1 to the ground voltage VSS. When the first clock CLK1 is at the ground voltage VSS, the first NMOS transistor N1 of the first inverter 111 is turned off and the first PMOS transistor P1 is turned on. That is, the second voltage V2 is supplied to the output node B of the first inverter 111.

  When the first clock CLK1 is the first voltage V1, the ground voltage VSS is supplied to the output node B of the first inverter 111 through the first NMOS transistor N1. Accordingly, when the first clock CLK1 falls from the first voltage V1 to the ground voltage VSS, the voltage at the output node B of the first inverter 111 is charged from the ground voltage VSS to the second voltage V2.

  Specifically, the second voltage V2 is applied to the source S5 of the first PMOS transistor P1, the ground voltage VSS is applied to the gate G6, and the ground voltage VSS is applied to the drain D6, and the channel of the first PMOS transistor P1. The voltage at the output node B is charged. The bias condition of the first PMOS transistor P1 is the same as the bias condition of the second PMOS transistor P2 of the second inverter 113 described with reference to FIG. Therefore, the time required for the voltage at the output node B of the first inverter 111 to be charged to the second voltage V2 may be the second time T2. The second time T2 may be a delay time until the voltage at the output node B of the first inverter 111 rises in synchronization with the falling edge of the first clock CLK1.

  When the output voltage of the first inverter 111 is the second voltage V2, the second PMOS transistor P2 of the second inverter 113 is turned off and the second NMOS transistor N2 is turned on. That is, the ground voltage VSS is supplied to the output node C of the second inverter 113.

  When the output voltage of the first inverter 111 is the ground voltage VSS, the second voltage V2 is supplied to the output node C of the second inverter 113 through the second PMOS transistor P2. Therefore, when the output voltage of the first inverter 111 rises from the ground voltage VSS to the second voltage V2, the voltage at the output node C of the second inverter 113 is discharged from the second voltage V2 to the ground voltage VSS.

  Specifically, the channel of the second NMOS transistor N2 is applied with the second voltage V2 applied to the drain D7 of the second NMOS transistor N2, the second voltage V2 applied to the gate G7, and the ground voltage VSS applied to the source S7. The voltage of the output node C is discharged through.

  At this time, except that the type of transistor is an NMOS transistor, the bias condition of the second NMOS transistor N2 is the same as the bias condition of the first PMOS transistor P1 of the first inverter 111. The gate-source voltage difference of the second NMOS transistor N2 is the second voltage V2, and the gate-source voltage difference or the second voltage V2 of the first PMOS transistor P1. The drain-source voltage difference of the second NMOS transistor N2 is the second voltage V2, and the drain-source voltage difference or the second voltage V2 of the first PMOS transistor P1.

  Each of the first to fourth inverters 111, 113, 121, and 123 includes one PMOS transistor and one NMOS transistor. When the input voltages of the first to fourth inverters 111, 113, 121, and 123 are at a low level, the output voltages of the first to fourth inverters 111, 113, 121, and 123 are generated by the PMOS transistors P1 to P4. When the input voltages of the first to fourth inverters 111, 113, 121, and 123 are at a high level, the output voltages of the first to fourth inverters 111, 113, 121, and 123 are generated by the NMOS transistors N1 to N4.

  The first to fourth inverters 111, 113, 121, and 123 may be formed to have a low level output and a high level output. For example, the first to fourth inverters 111, 113, 121, and 123 are formed so that when a high level is output, the amount of current to be charged is equalized with the amount of current that is discharged when a low level is output. obtain. The first to fourth NMOS transistors N1 to N4 may be formed to operate in the same manner as the first to fourth PMOS transistors P1 to P4 under the same bias condition. Under the same bias condition, the amount of current flowing through the second NMOS transistor N2 may be the same as the amount of current flowing through the first PMOS transistor P1.

  Since the bias condition of the second NMOS transistor N2 is the same as the bias condition of the first PMOS transistor P1, the time required for the voltage at the output node C of the second inverter 113 to be discharged to the ground voltage VSS is the second time T2. It can be. The second time T2 may be a delay time until the voltage of the output node C of the second inverter 113 falls in synchronization with the rising edge of the output voltage of the first inverter 111.

  When the first clock CLK1 is at the ground voltage VSS, the third NMOS transistor N1 of the third inverter 121 is turned off and the third PMOS transistor P3 is turned on. That is, the first voltage V <b> 1 is supplied to the output node D of the third inverter 121.

  When the first clock CLK1 is the first voltage V1, the ground voltage VSS is supplied to the output node D of the third inverter 121 through the third NMOS transistor N3. Therefore, when the first clock CLK1 falls from the first voltage V1 to the ground voltage VSS, the voltage at the output node D of the third inverter 121 is charged from the ground voltage VSS to the first voltage V1.

  Specifically, the first voltage V1 is applied to the source S7 of the third PMOS transistor P3, the ground voltage VSS is applied to the gate G7, and the ground voltage VSS is applied to the drain D7, and the channel of the third PMOS transistor P3 is applied. The voltage at the output node D is charged.

  At this time, except that the type of transistor is a PMOS transistor, the bias condition of the third PMOS transistor P2 is the same as the bias condition of the third NMOS transistor N3 described with reference to FIG. The gate-source voltage difference of the third PMOS transistor P3 is the first voltage V1, and the gate-source voltage difference or the first voltage V1 of the third NMOS transistor N3. The drain-source voltage difference of the third PMOS transistor P3 is the first voltage V1, and the drain-source voltage difference or the first voltage V1 of the third NMOS transistor N3.

  Therefore, the time required for the voltage at the output node D of the third inverter 121 to be charged to the first voltage V1 may be the third time T3. The third time T3 may be a delay time until the voltage at the output node D of the third inverter 121 rises in synchronization with the falling edge of the first clock CLK1.

  When the output voltage of the third inverter 121 is the first voltage V1, the fourth PMOS transistor P4 of the fourth inverter 123 is turned off and the fourth NMOS transistor N4 is turned on. That is, the ground voltage VSS is supplied to the output node E of the fourth inverter 123.

  When the output voltage of the third inverter 121 is the ground voltage VSS, the second voltage V2 is supplied to the output node E of the fourth inverter 123 through the fourth PMOS transistor P4. Accordingly, when the output voltage of the third inverter 121 rises from the ground voltage VSS to the first voltage V1, the voltage at the output node E of the fourth inverter 123 is discharged from the second voltage V2 to the ground voltage VSS.

  Specifically, the channel of the fourth PMOS transistor P4 is applied with the second voltage V2 applied to the drain D8 of the fourth NMOS transistor N4, the first voltage V1 applied to the gate G8, and the ground voltage VSS applied to the source S8. The voltage of the output node E is discharged through.

  At this time, the bias condition of the fourth NMOS transistor N4 of the fourth inverter 123 is the same as the bias condition of the first NMOS transistor N1 described with reference to FIG. Accordingly, the time required for the voltage at the output node E of the fourth inverter 123 to be discharged to the ground voltage VSS may be the first time T1. The first time T1 may be a delay time until the voltage at the output node E of the fourth inverter 123 falls in synchronization with the rising edge of the output voltage of the third inverter 121.

  FIG. 5 is a timing diagram showing the input clock CLK1 and the output clock CLK2 of the level converter 100 described with reference to FIGS. Referring to FIGS. 1 to 5, the first clock CLK <b> 1 is input to the level converter 100. The first clock CLK1 has a swing width of the first voltage V1. The first clock CLK1 has a rising edge and a falling edge that are periodically repeated.

  The second clock CLK2 is output from the level converter 100. The second clock CLK2 has a swing width of the second voltage V2. The second clock CLK2 rises in synchronization with the rising edge of the first clock CLK1. The second clock CLK2 is increased by charging and discharging the first and second inverters 111 and 113 of the first voltage conversion circuit 110 and charging and discharging of the third and fourth inverters 121 and 123 of the second voltage conversion circuit 120. .

  As described with reference to FIG. 3, the first clock CLK1 rises, and after the first time T1, the output voltage of the first inverter 111 decreases and reaches the ground voltage VSS. The output voltage of the first inverter 111 decreases, and after the second time T2, the output voltage of the second inverter 113 increases and reaches the second voltage V2. The first clock CLK1 rises, and after the third time T3, the output voltage of the third inverter 121 falls and reaches the ground voltage VSS. The output voltage of the third inverter 121 decreases, and after the second time T2, the output voltage of the fourth inverter 123 increases and reaches the second voltage V2.

  The output voltages of the second and fourth inverters 113 and 123 are mixed to form the second clock CLK2. That is, the delay D1 between the rising edge of the first clock CLK1 and the rising edge of the second clock CLK2 is generated by adding the first time T1, the second time T2, and the third time T3.

  As described with reference to FIG. 4, the first clock CLK1 falls, and after the second time T2, the output voltage of the first inverter 111 rises and reaches the second voltage V2. The output voltage of the first inverter 111 increases, and after the second time T2, the output voltage of the second inverter 113 decreases and reaches the ground voltage VSS. The first clock CLK1 falls, and after the third time T3, the output voltage of the third inverter 121 rises and reaches the first voltage V1. The output voltage of the third inverter 121 increases, and after the first time T1, the output voltage of the fourth inverter 123 decreases and reaches the ground voltage VSS.

  The output voltages of the second and fourth inverters 113 and 123 are mixed to form the second clock CLK2. That is, the delay D2 between the falling edge of the first clock CLK and the falling edge of the second clock CLK2 is generated by adding the first time T1, the second time T2, and the third time T3.

  As described above, the time factors T1, T2, and T3 that generate the delay D1 between the rising edges of the first and second clocks CLK1 and CLK2 are the time factors T1, T2, and T2, that generate the delay D2 between the falling edges. It is the same as T3. Accordingly, the delay D1 between the rising edges of the first and second clocks CLK1 and CLK2 and the delay D2 between the falling edges may be the same.

  When the delay D1 between the rising edges and the delay D2 between the falling edges are different from each other, the ratio between the high level section and the low level section of one cycle of the second clock CLK2 can be varied.

  Exemplarily, when the delay D1 between the rising edges is larger than the delay D2 between the falling edges, the ratio of the high level interval of one cycle of the second clock CLK2 is the ratio of the high level interval of one cycle of the first clock CLK1. Decrease from the ratio. On the contrary, when the delay D2 between the falling edges is larger than the delay D1 between the rising edges, the ratio of the low level section of one cycle of the second clock CLK2 is the ratio of the low level section of one cycle of the first clock CLK1. Decrease more. According to the embodiment of the present invention, the level converter 100 maintains a ratio between a high level and a low level interval and generates a first clock CLK1 and a second clock CLK2 of another voltage domain. it can. Therefore, the reliability of the output clock of the level converter 100 can be improved.

  For example, the second voltage V2 may be lower or higher than the first voltage V1.

  FIG. 6 is a block diagram illustrating a system-on-chip 500 (SOC, System-On-Chip) including the level converter 100 described with reference to FIGS. Referring to FIG. 6, the system-on-chip 500 includes a processor 510, a phase lock loop 520, a peripheral block 530, an audio block 540, a display block 550, a graphic block 560, an image processing block 570, and a codec block 580.

  The processor 510 includes first to eighth flip-flops 512 to 519. The processor 510 may further include or be coupled to the level converter 100. The level converter 100 receives the first clock CLK1 from the phase locked loop 520. The first clock CLK1 may have a swing of the first voltage V1. The level converter 100 maintains a ratio between the high level and the low level period, and generates the second clock CLK2 synchronized with the first clock CLK1. The second clock CLK2 may have a swing of the second voltage V1. The second voltage V2 can be greater than the first voltage V1.

  The second clock CLK2 generated by the level converter 100 is supplied to the flip-flops 512 to 519 of the processor 510. The flip-flops 512 to 519 of the processor 510 operate according to the second clock CLK2.

  The phase lock loop 520 receives the clock CLK from the outside. The phase locked loop 520 generates a first clock CLK1 that is synchronized with the received clock CLK. The first clock CLK1 is supplied to the level converter 100, the peripheral block 530, the audio block 540, the display block 550, the graphic block 560, the image processing block 570, and the codec block 580 of the processor 510.

  The peripheral block 530, the audio block 540, the display block 550, the graphic block 560, the image processing block 570, and the codec block 580 operate according to the first clock CLK1. The peripheral block 530, the audio block 540, the display block 550, the graphic block 560, the image processing block 570, and the codec block 580 may be IP (Intellectual Property).

  Audio block 540 can process audio data. Display block 550 can generate signals that control a display device, such as a monitor (not shown). The graphic block 560 can process graphic data displayed on a display device such as a monitor (not shown). The image processing block 570 can process image data captured by an imaging device such as a camera (not shown). The codec 580 can perform encoding or decoding of audio data. The codec 580 can perform encoding or decoding of graphic data.

  As shown in FIG. 6, the peripheral block 530, the audio block 540, the display block 550, the graphic block 560, the image processing block 570, and the codec block 580 of the system on chip 500 operate according to the first clock CLK1. The processor 510 can operate according to the second clock CLK2 of the second voltage domain converted from the first clock CLK1 of the first voltage domain. The second voltage V2 can be higher than the first voltage V1.

  The level converter 100 may be the level converter 100 described with reference to FIGS. For example, the level converter 100 may include first and second voltage conversion circuits 110 and 120 connected in parallel between the input node A and the output node F and having the same structure. The delay D1 between the rising edges of the input clock CLK1 and the output clock CLK2 of the level converter 100 and the delay D2 between the falling edges may be the same. Therefore, the reliability of the processor 510 that operates according to the second clock CLK2 and the reliability of the system-on-chip 500 including the processor 510 are improved.

  When the processor 510 is designed to operate at high speed, the processor 510 can operate in synchronization with all the rising and falling edges of the second clock CLK2. The level converter 100 according to the embodiment of the present invention maintains the ratio between the high level section and the low level section, and converts the first clock CLK1 of the first voltage domain to the second clock CLK2 of the second voltage domain. If the ratio between the high level period and the low level period is maintained, the margin between the rising edge and the falling edge of the second clock CLK2 may be optimized and maintained. Accordingly, when the level converter 100 according to the embodiment of the present invention is provided, the reliability of the processor 510 and the system on chip 500 operating in synchronization with all the rising and falling edges of the second clock CLK2 is improved. Can be done.

  FIG. 7 is a block diagram illustrating a first example of a multimedia device 1000 including a level converter 100 according to an embodiment of the present invention. Referring to FIG. 7, the multimedia apparatus 1000 includes an oscillator 1010, a clock generator 1020, a phase lock loop 1030, a processor 1040, a memory 1050, a display controller 1060, a display unit 1070, a sound controller 1080, a speaker 1090, and a storage unit. 1100, modem 1110, image processing unit 1120, camera 1130, user interface 1140, and codec unit 1150.

  The oscillator 1010 generates an oscillation signal that oscillates according to a specific frequency. The oscillation signal is supplied to the clock generator 1020.

  The clock generator 1020 generates a clock 1020 according to the oscillation signal supplied from the oscillator 1010. Clock CLK may be provided to phase lock loop 1030.

  The phase locked loop 1030 is configured to generate the first clock CLK1 according to the clock CLK received from the clock generator 1020. The first clock CLK1 may be synchronized with the received clock CLK. The first clock CLK1 may be supplied to the processor 1040.

  The processor 1040 is configured to control various operations of the multimedia device 1000. The processor 1040 controls the hardware components of the multimedia device 1000. The processor 1040 drives the software components of the multimedia device 1000.

  The processor 1040 may include or be coupled to the level converter 100 according to an embodiment of the present invention. The level converter 100 generates the second clock CLK2 of the second voltage domain based on the first clock CLK1 of the first voltage domain supplied from the phase locked loop 1030. The second clock CLK2 is used as an internal clock of the processor 1010.

  Memory 1050 may be the operating memory of processor 1040. For example, the memory 1050 may be volatile memory such as SRAM (Static RAM), DRAM (Dynamic RAM), SDRAM (Synchronous DRAM), or the like, or flash memory, PRAM (Phase-change RAM), MRAM (Magnetic RAM), Non-volatile memories such as RRAM (Resistive RAM) (registered trademark), FRAM (Ferroelectric RAM) (registered trademark), and the like can be included.

  The display control unit 1060 operates according to the control of the processor 1040. The display controller 1060 is configured to generate and control an image displayed through the display unit 1070. The display controller 1060 may include a graphics processing unit (GPU).

  The display unit 1070 is configured to display an image generated by the display control unit 1060. The display unit 1070 includes a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an active matrix organic light emitting diode (AMOLED), an active matrix organic electronic display (AMOLED), an organic light emitting diode (AMOLED), and an organic light emitting diode (AMOLED). Etc. can be included.

  The sound control unit 1080 operates according to the control of the processor 1040. The sound control unit 1080 can generate and control sound output through the speaker 1090. The speaker 1090 operates according to the control of the processor 1040. The sound control unit 1080 of the sound control unit 1080 operates. The sound control unit 1080 can generate and control sound output through the speaker 1090. The speaker 1090 can output sound according to the control of the sound control unit 1080.

  The storage unit 1100 is configured to store data under the control of the processor 1040. The storage unit 1100 can include a nonvolatile memory such as a flash memory, a PRAM (Phase-change RAM), an MRAM (Magnetic RAM), an RRAM (Resistive RAM) (registered trademark), an FRAM (Ferroelectric RAM) (registered trademark), or the like. . The storage unit 1100 may include a hard disk drive HDD, a hard disk drive (SSD), and a solid state drive (SSD).

  The modem 1110 can communicate with the outside according to the control of the processor 1040. For example, the modem 1110 may communicate with the outside through a wireless channel or a wired channel. The modem 1110 is CDMA (Code Division Multiple Access), GSM (Global System for Mobile and Communications (registered trademark)), CDMA 2000, WCDMA (Wideband Code Division L), and CDMA 2000. It can communicate with the outside according to a wireless protocol such as Mobile WiMAX (World Interoperability), WiFi, and the like. The modem 1110 can communicate with ADSL (Asymmetric Digital Subscriber Line), VDSL (Very high data rate Digital Subscriber Line), ISDN (Integrated Services Digit) such as ISDN (Integrated Services Digit).

  The image processing unit 1130 operates according to the control of the processor 1040. The image processing unit 1130 is configured to process image data captured or recorded by the camera 1140.

  The user interface 1140 is configured to transmit an externally sensed signal to the processor 1140. For example, the user interface 1120 may include a microphone, a touch pad, a touch screen, a button, a mouse, a keyboard, and the like.

  The codec unit 1150 can encode or decode audio data. The codec unit 1150 can encode or decode video data.

  For example, the phase lock loop 1030, the processor 1040, the memory 1050, the display control unit 1060, the sound control unit 1080, the image processing unit 1120, and the codec unit 1150 may constitute the system-on-chip 1200. The system on chip 1200 may have the structure described with reference to FIG. The processor 1040 may correspond to the processor 510 of FIG. The memory 1050 may correspond to the peripheral block 530 of FIG. The display control unit 1060 may correspond to the display block 550 and the graphic block 560 of FIG. The sound control unit 1080 may correspond to the audio block 540 of FIG. The image processing unit 1120 may correspond to the image processing block 570 of FIG. The codec unit 1150 can correspond to the codec block 580 of FIG.

  The clock generation unit 1020 can supply the generated clock CLK to the system-on-chip 1200 and can supply the clock CLK to other components that require the clock CLK among the components of the multimedia apparatus 1000.

  The phase-locked loop 1030 of the system on chip 1200 generates a first clock CLK1 that is synchronized with the received clock CLK. As described with reference to FIGS. 1 to 5, the level converter 100 may maintain the ratio between the high level period and the low level period and generate the second clock CLK2 based on the first clock CLK1. The processor 1040 can operate based on the second clock CLK2. Other components of the system-on-chip 1200, that is, the memory 1050, the display control unit 1060, the sound control unit 1080, the image processing unit 1120, and the codec unit 1150 can operate according to the first clock CLK1.

  FIG. 8 is a block diagram illustrating a second embodiment of a multimedia device 2000 including a level converter 100 according to an embodiment of the present invention. Referring to FIG. 8, the multimedia device 2000 includes an oscillator 2010, a clock generation unit 2020, a phase lock loop 2030, a processor 2040, a memory 2050, a display control unit 2060, a display unit 2070, a sound control unit 2080, a speaker 2090, and a storage unit. 2100, modem 2110, image processing unit 2120, camera 2130, user interface 2140, and codec unit 2150.

  Compared with the multimedia device 1000 described with reference to FIG. 7, the multimedia device 2000 includes a phase lock loop 2030, a processor 2040, a memory 2050, a display control unit 2060, a sound control unit 2080, a modem 2110, and an image processing unit. 2120 and the codec unit 2150 can constitute the system-on-chip 2200. The system on chip 2200 may have the structure described with reference to FIG. The processor 2040 may correspond to the processor 510 of FIG. Memory 2050 and modem 2110 may correspond to peripheral block 530 of FIG. The display control unit 2060 may correspond to the display block 550 and the graphic block 560 of FIG. The sound control unit 2080 can correspond to the audio block 540 of FIG. The image processing unit 2120 may correspond to the image processing block 570 of FIG. The codec unit 2150 can correspond to the codec block 580 of FIG.

  The clock generation unit 2020 can supply the generated clock CLK to the system-on-chip 2200 and can supply the clock CLK to other components that require the clock CLK among the components of the multimedia apparatus 2000.

  The phase-locked loop 2030 of the system on chip 2200 generates a first clock CLK1 that is synchronized with the received clock CLK. As described with reference to FIGS. 1 to 5, the level converter 100 may maintain the ratio between the high level period and the low level period and generate the second clock CLK2 based on the first clock CLK1. The processor 2040 can operate based on the second clock CLK2. Other components of the system-on-chip 2200, that is, the memory 2050, the display control unit 2060, the sound control unit 2080, the modem 2110, the image processing unit 2120, and the codec unit 2150 can operate according to the first clock CLK1.

  FIG. 9 is a block diagram illustrating a third embodiment of a multimedia device 3000 including a level converter 100 according to an embodiment of the present invention. Referring to FIG. 9, the multimedia device 3000 includes an oscillator 3010, a clock generation unit 3020, a phase lock loop 3030, a processor 3040, a memory 3050, a display control unit 3060, a display unit 3070, a sound control unit 3080, a speaker 3090, and a storage unit. 3100, modem 3110, image processing unit 3120, camera 3130, user interface 3140, and codec unit 3150.

  Compared with the multimedia apparatus 1000 described with reference to FIG. 7, the multimedia apparatus 3000 includes a phase lock loop 3030, a processor 3040, a memory 3050, a display control unit 3060, a sound control unit 3080, and a codec unit 3150. An on-chip 2200 can be configured.

  The clock generator 3020 can supply the generated clock CLK to the system-on-chip 3200 and can supply the clock CLK to other components that require the clock CLK among the components of the multimedia device 3000.

  The phase lock loop 3030 of the system on chip 3200 generates a first clock CLK1 that is synchronized with the received clock CLK. As described with reference to FIGS. 1 to 5, the level converter 100 may maintain the ratio between the high level period and the low level period and generate the second clock CLK2 based on the first clock CLK1. The processor 3040 can operate based on the second clock CLK2. Other components of the system-on-chip 3200, that is, the memory 3050, the display control unit 3060, the sound control unit 3080, and the codec unit 3150 can operate according to the first clock CLK1.

  FIG. 10 is a block diagram illustrating a fourth embodiment of a multimedia device 4000 including a level converter 100 according to an embodiment of the present invention. Referring to FIG. 10, the multimedia device 4000 includes an oscillator 4010, a clock generation unit 4020, a phase lock loop 4030, a processor 4040, a memory 4050, a display control unit 4060, a display unit 4070, a sound control unit 4080, a speaker 4090, and a storage unit. 4100, modem 4110, image processing unit 4120, camera 4130, user interface 4140, and codec unit 4150.

  Compared with the multimedia device 1000 described with reference to FIG. 7, the phase locked loop 4030, the processor 4040, the memory 4050, the display control unit 4060, and the sound control unit 4080 in the multimedia device 4000 include the system on chip 4200. Can be configured.

  The clock generation unit 4020 can supply the generated clock CLK to the system-on-chip 4200, and can supply the clock CLK to other components that require the clock CLK among the components of the multimedia device 4000.

  The phase-locked loop 4030 of the system on chip 4200 generates a first clock CLK1 that is synchronized with the received clock CLK. As described with reference to FIGS. 1 to 5, the level converter 100 may maintain the ratio between the high level period and the low level period and generate the second clock CLK2 based on the first clock CLK1. The processor 4040 can operate based on the second clock CLK2. The other components of the system-on-chip 4200, that is, the memory 4050, the display controller 4060, and the sound controller 4080 can operate according to the first clock CLK1.

  FIG. 11 is a block diagram illustrating a fifth embodiment of a multimedia device 5000 including a level converter 100 according to an embodiment of the present invention. Referring to FIG. 11, the multimedia device 5000 includes an oscillator 5010, a clock generation unit 5020, a phase lock loop 5030, a processor 5040, a memory 5050, a display control unit 5060, a display unit 5070, a sound control unit 5080, a speaker 5090, and a storage unit. 5100, modem 5110, image processing unit 5120, camera 5130, user interface 5140, and codec unit 5150.

  Compared with the multimedia device 1000 described with reference to FIG. 7, the phase locked loop 5030, the processor 5040, the memory 5050, and the display control unit 5060 can constitute the system-on-chip 5200 in the multimedia device 5000. .

  The clock generation unit 5020 can supply the generated clock CLK to the system-on-chip 5200, and can supply the generated clock CLK to other components that require the clock CLK among the components of the multimedia device 5000.

  The phase-locked loop 5030 of the system on chip 5200 generates a first clock CLK1 that is synchronized with the received clock CLK. As described with reference to FIGS. 1 to 5, the level converter 100 may maintain the ratio between the high level period and the low level period and generate the second clock CLK2 based on the first clock CLK1. The processor 5040 can operate based on the second clock CLK2. The other components of the system-on-chip 5200, that is, the memory 5050 and the display controller 5060 can operate according to the first clock CLK1.

  FIG. 12 is a block diagram illustrating a sixth embodiment of a multimedia device 6000 including a level converter 100 according to an embodiment of the present invention. Referring to FIG. 12, the multimedia device 6000 includes an oscillator 6010, a clock generation unit 6020, a phase lock loop 6030, a processor 6040, a memory 6050, a display control unit 6060, a display unit 6070, a sound control unit 6080, a speaker 6090, and a storage unit. 6100, modem 6110, image processing unit 6120, camera 6130, user interface 6140, and codec unit 6150.

  Compared with the multimedia apparatus 1000 described with reference to FIG. 7, the phase locked loop 6030, the processor 6040, and the memory 6050 can constitute the system-on-chip 6200 in the multimedia apparatus 6000.

  The clock generation unit 6020 can supply the generated clock CLK to the system-on-chip 6200, and can supply the generated clock CLK to other components that require the clock CLK among the components of the multimedia device 6000.

  The phase-locked loop 6030 of the system on chip 6200 generates a first clock CLK1 that is synchronized with the received clock CLK. As described with reference to FIGS. 1 to 5, the level converter 100 may maintain the ratio between the high level period and the low level period and generate the second clock CLK2 based on the first clock CLK1. The processor 6040 can operate based on the second clock CLK2. The other components of the system-on-chip 6200, that is, the memory 6050, can operate according to the first clock CLK1.

  FIG. 13 is a block diagram illustrating a seventh embodiment of a multimedia device 7000 including a level converter 100 according to an embodiment of the present invention. Referring to FIG. 13, the multimedia device 7000 includes an oscillator 7010, a clock generation unit 7020, a phase lock loop 7030, a processor 7040, a memory 7050, a display control unit 7060, a display unit 7070, a sound control unit 7080, a speaker 7090, and a storage unit. 7100, a modem 7110, an image processing unit 7120, a camera 7130, a user interface 7140, and a codec unit 7150.

  Compared with the multimedia device 1000 described with reference to FIG. 7, the phase locked loop 7030, the processor 7040, the memory 7050, and the sound control unit 7080 can constitute the system-on-chip 7200 in the multimedia device 7000. .

  The clock generation unit 7020 can supply the generated clock CLK to the system-on-chip 7200, and can supply the generated clock CLK to other components that require the clock CLK among the components of the multimedia device 7000.

  The phase-locked loop 7030 of the system on chip 7200 generates a first clock CLK1 that is synchronized with the received clock CLK. As described with reference to FIGS. 1 to 5, the level converter 100 may maintain the ratio between the high level period and the low level period and generate the second clock CLK2 based on the first clock CLK1. The processor 7040 can operate based on the second clock CLK2. Other components of the system-on-chip 7200, that is, the memory 7050 and the sound control unit 7080 can operate according to the first clock CLK1.

  FIG. 14 is a block diagram illustrating an eighth embodiment of a multimedia device 8000 including a level converter 100 according to an embodiment of the present invention. Referring to FIG. 14, the multimedia device 8000 includes an oscillator 8010, a clock generation unit 8020, a phase lock loop 8030, a processor 8040, a memory 8050, a display control unit 8060, a display unit 8070, a sound control unit 8080, a speaker 8090, and a storage unit. 8100, a modem 8110, a user interface 8140, and a codec unit 8150.

  Compared to the multimedia apparatus 1000 described with reference to FIG. 7, the multimedia apparatus 8000 may not provide the image processing unit 1120 and the camera 1130. The phase-locked loop 8030, the processor 8040, the memory 8050, the display control unit 8060, the sound control unit 8080, and the codec unit 8150 can constitute the system-on-chip 7200.

  The clock generation unit 8020 can supply the generated clock CLK to the system-on-chip 8200, and can supply the generated clock CLK to other components that require the clock CLK among the components of the multimedia device 8000.

  The phase-locked loop 8030 of the system on chip 8200 generates a first clock CLK1 that is synchronized with the received clock CLK. As described with reference to FIGS. 1 to 5, the level converter 100 may maintain the ratio between the high level period and the low level period and generate the second clock CLK2 based on the first clock CLK1. The processor 8040 can operate based on the second clock CLK2. Other components of the system-on-chip 8200, that is, the memory 8050 and the sound control unit 8080 can operate according to the first clock CLK1.

  Except that the image processing units 2120 to 7120 and the cameras 2130 to 7130 are not provided, the components constituting the system-on-chip 8200 among the components of the multimedia device 8000 will be described with reference to FIGS. 8 to 13. As can be done.

  7 to 14, the multimedia apparatus according to the embodiment of the present invention has been described, but the multimedia apparatus according to the embodiment of the present invention may be implemented in various products. Illustratively, a multimedia device according to an embodiment of the present invention may be a computer, a UMPC (Ultra Mobile PC), a workstation, a net-book, a PDA (Personal Digital Assistant), a portable computer, a tablet computer ( tablet computer, wireless phone, mobile phone, smart phone, e-book, PMP (portable multimedia player), portable game device, navigation (navigation device) , Black box, digital camera (Digital camera), DMB (Digital Multimedia Broadcasting) player, 3D television (3-dimension television), smart television (digital television recorder), digital audio player (digital audio player), digital audio player (digital audio player) , A digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting and receiving information in a wireless environment Homene One of various electronic devices constituting a network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, RFID device, or computing One of various components constituting the system can be configured.

  FIG. 15 illustrates a smartphone 9100 according to an embodiment of the present invention. Referring to FIG. 15, the smartphone 9100 includes an external case 9110, a screen 9120, a camera 9130, a speaker 9140, and an operation button 9150.

  The screen 9120 may constitute the display units 1070 to 8070 described with reference to FIGS. The camera 9130 can constitute the cameras 1130 to 7130 described with reference to FIGS. The action button 9150 may constitute the user interface 1140-8140 described with reference to FIGS. When the screen 9120 is formed by a touch screen, the screen 9120 and the user interfaces 1140 to 8140 can be configured. The speaker 9140 may correspond to the speakers 1090-8090 described with reference to FIGS.

  Inside the external case 9110 are oscillators 1010 to 8010, clock generators 1020 to 8020, phase locked loops 1030 to 8030, processors 1040 to 8040, memories 1050 to 8050, display controllers 1060 to 8060, sound controllers 1080 to 8080, Storage units 1100-8100, modems 1110-8110, and codec units 1150-8150 may be provided. Image processing units 1120 to 7120 may be further provided in the outer case 9110. At least one of the memory 1050-8050, the display control unit 1060-8060, the sound control unit 1080-8080, the storage unit 1100-8100, the modem 1110-8110, the image processing unit 1120-7120, and the codec unit 1150-7150 System-on-chip 1200-8200 can be configured with phase-locked loops 1030-8030 and processors 1040-8040.

  Clock generators 1020 to 8020 can generate clock CLK according to the oscillation signals received from oscillators 1010 to 8010. The clock CLK may be supplied to the system on chip 1200 to 8200. The phase lock loop 1030-8030 can generate the first clock CLK1 synchronized with the clock CLK. The first clock CLK1 may be supplied to the components of the system on chip 1200-8200. The processors 1040-8040 may include or be coupled to the level converter 100 according to embodiments of the present invention. The level converter 100 maintains the ratio of the high level section and the ratio of the low level section, and converts the first clock CLK1 of the first voltage domain to the second clock CLK2 of the second voltage domain. The processors 1040 to 8040 operate according to the second clock CLK2. Other components of the system-on-chip 1200 to 8200 operate in response to the first clock CLK1.

  Although not shown in FIG. 15, a display unit 1070 to 8070, a speaker 1090 to 8090, and a user interface 1140 to 8140 are additionally provided on at least one of the rear surface, the upper surface, the lower surface, and the side surface of the smartphone 9100. obtain. In addition, display units 1070 to 8070, speakers 1090 to 8090, and user interfaces 1140 to 8140 may be additionally provided as accessories connected to the smartphone 9100.

  FIG. 16 illustrates a tablet computer 9200 according to an embodiment of the present invention. Referring to FIG. 16, the tablet computer 9200 includes an outer case 9210, a screen 9220, a camera 9230, and an operation button 9240.

  The screen 9220 may constitute the display units 1070 to 8070 described with reference to FIGS. The camera 9230 can constitute the cameras 1130 to 7130 described with reference to FIGS. The action button 9240 may constitute the user interface 1140-8140 described with reference to FIGS. When the screen 9220 is formed by a touch screen, the screen 9220 and the user interfaces 1140 to 8140 can be configured.

  Inside the external case 9210 are oscillators 1010 to 8010, clock generators 1020 to 8020, phase lock loops 1030 to 8030, processors 1040 to 8040, memories 1050 to 8050, display controllers 1060 to 8060, sound controllers 1080 to 8080, Storage units 1100-8100, modems 1110-8110, and codec units 1150-8150 may be provided. Image processing units 1120 to 7120 may be further provided in the outer case 9210. At least one of the memory 1050-8050, the display control unit 1060-8060, the sound control unit 1080-8080, the storage unit 1100-8100, the modem 1110-8110, the image processing unit 1120-7120, and the codec unit 1150-7150 System-on-chip 1200-8200 can be configured with phase-locked loops 1030-8030 and processors 1040-8040.

  Clock generators 1020 to 8020 can generate clock CLK according to the oscillation signals received from oscillators 1010 to 8010. The clock CLK may be supplied to the system on chip 1200 to 8200. The phase lock loop 1030-8030 can generate the first clock CLK1 synchronized with the clock CLK. The first clock CLK1 may be supplied to the components of the system on chip 1200-8200. The processors 1040-8040 may include or be coupled to the level converter 100 according to embodiments of the present invention. The level converter 100 maintains the ratio of the high level section and the ratio of the low level section, and converts the first clock CLK1 of the first voltage domain to the second clock CLK2 of the second voltage domain. The processors 1040 to 8040 operate according to the second clock CLK2. Other components of the system-on-chip 1200 to 8200 operate in response to the first clock CLK1.

  Although not shown in FIG. 16, display units 1070 to 8070, speakers 1090 to 8090, and user interfaces 1140 to 8140 are additionally provided to at least one of the rear surface, upper surface, lower surface, and side surface of the tablet computer 9200. Can be done. In addition, a display unit 1070-8070, speakers 1090-8090, and user interfaces 1140-8140 may be additionally provided as accessories connected to the tablet computer 6200.

  FIG. 17 illustrates a mobile computer 9300 according to an embodiment of the present invention. Referring to FIG. 17, the mobile computer 9300 includes an outer case 9310, a screen 9320, a camera 9330, a speaker 9340, a keyboard 9350, and a touch pad 9360.

  The screen 9320 may constitute the display units 1070 to 8070 described with reference to FIGS. The camera 9330 can constitute the cameras 1130 to 7130 described with reference to FIGS. The keyboard 9350 and the touch pad 9360 may constitute the user interfaces 1140 to 8140 described with reference to FIGS. When the screen 9320 is formed with a touch screen, the screen 9320 and the user interfaces 1140-8140 can be configured. The speaker 9340 can correspond to the speakers 1090 to 8090 described with reference to FIGS.

  Inside the external case 9310 are oscillators 1010 to 8010, clock generators 1020 to 8020, phase lock loops 1030 to 8030, processors 1040 to 8040, memories 1050 to 8050, display controllers 1060 to 8060, sound controllers 1080 to 8080, Storage units 1100-8100, modems 1110-8110, and codec units 1150-8150 may be provided. Image processing units 1120 to 7120 may be further provided in the outer case 9310. At least one of the memory 1050-8050, the display control unit 1060-8060, the sound control unit 1080-8080, the storage unit 1100-8100, the modem 1110-8110, the image processing unit 1120-7120, and the codec unit 1150-7150 System-on-chip 1200-8200 can be configured with phase-locked loops 1030-8030 and processors 1040-8040.

  Clock generators 1020 to 8020 can generate clock CLK according to the oscillation signals received from oscillators 1010 to 8010. The clock CLK may be supplied to the system on chip 1200 to 8200. The phase lock loop 1030-8030 can generate the first clock CLK1 synchronized with the clock CLK. The first clock CLK1 may be supplied to the components of the system on chip 1200-8200. The processors 1040-8040 may include or be coupled to the level converter 100 according to embodiments of the present invention. The level converter 100 maintains the ratio of the high level section and the ratio of the low level section, and converts the first clock CLK1 of the first voltage domain to the second clock CLK2 of the second voltage domain. The processors 1040 to 8040 operate according to the second clock CLK2. Other components of the system-on-chip 1200 to 8200 operate in response to the first clock CLK1.

  Mobile computer 9300 can be a notebook computer computer or a netbook. Although not shown in FIG. 17, display units 1070 to 8070, speakers 1090 to 8090, and user interfaces 1140 to 8140 are additionally provided to at least one of the rear surface, the upper surface, the lower surface, and the side surface of the mobile computer 9300. Can be done. In addition, as accessories connected to the mobile computer 9300, a display unit 1070-8070, speakers 1090-8090, and user interfaces 1140-8140 may be additionally provided.

  FIG. 18 illustrates a computer 9400 according to an embodiment of the present invention. Referring to FIG. 18, the computer 9400 includes a main body 9410, a monitor 9420, and a keyboard 9430.

  The monitor 9420 can constitute the display units 1070 to 8070 described with reference to FIGS. The keyboard 9430 may constitute the user interfaces 1140 to 8140 described with reference to FIGS. When the monitor 9420 is formed with a touch screen, the monitor 9420 and the user interfaces 1140-8140 can be configured.

  In the main body 9410, oscillators 1010 to 8010, clock generation units 1020 to 8020, phase lock loops 1030 to 8030, processors 1040 to 8040, memories 1050 to 8050, display control units 1060 to 8060, sound control units 1080 to 8080, and storage Units 1100-8100, modems 1110-8110, and codec units 1150-8150 may be provided. Image processing units 1120 to 7120 may be further provided in the main body 9410. At least one of the memory 1050-8050, the display control unit 1060-8060, the sound control unit 1080-8080, the storage unit 1100-8100, the modem 1110-8110, the image processing unit 1120-7120, and the codec unit 1150-7150 System-on-chip 1200-8200 can be configured with phase-locked loops 1030-8030 and processors 1040-8040.

  Clock generators 1020 to 8020 can generate clock CLK according to the oscillation signals received from oscillators 1010 to 8010. The clock CLK may be supplied to the system on chip 1200 to 8200. The phase lock loop 1030-8030 can generate the first clock CLK1 synchronized with the clock CLK. The first clock CLK1 may be supplied to the components of the system on chip 1200-8200. The processors 1040-8040 may include or be coupled to the level converter 100 according to embodiments of the present invention. The level converter 100 maintains the ratio of the high level section and the ratio of the low level section, and converts the first clock CLK1 of the first voltage domain to the second clock CLK2 of the second voltage domain. The processors 1040 to 8040 operate according to the second clock CLK2. Other components of the system-on-chip 1200 to 8200 operate in response to the first clock CLK1.

  Although not shown in FIG. 18, display units 1070 to 8070, speakers 1090 to 8090, and user interfaces 1140 to 8140 are additionally provided to at least one of the rear surface, the upper surface, the lower surface, and the side surface of the computer 9400. obtain. In addition, display units 1070 to 8070, speakers 1090 to 8090, and user interfaces 1140 to 8140 may be additionally provided as accessories connected to the computer 6400.

  FIG. 19 illustrates a television 9500 according to an embodiment of the present invention. Referring to FIG. 19, the television 9500 includes an outer case 9510, a screen 9520, and an operation button 9530.

  The screen 9520 may constitute the display units 1070 to 8070 described with reference to FIGS. The action button 9530 may constitute the user interface 1140-8140 described with reference to FIGS. When the screen 9520 is formed with a touch screen, the screen 9520 and the user interfaces 1140-8140 can be configured.

  Inside the external case 9510 are oscillators 1010-8010, clock generators 1020-8020, phase lock loops 1030-8030, processors 1040-8040, memories 1050-8050, display controllers 1060-8060, sound controllers 1080-8080, Storage units 1100-8100, modems 1110-8110, and codec units 1150-8150 may be provided. Image processing units 1120 to 7120 may be further provided in the outer case 9510. At least one of the memory 1050-8050, the display control unit 1060-8060, the sound control unit 1080-8080, the storage unit 1100-8100, the modem 1110-8110, the image processing unit 1120-7120, and the codec unit 1150-7150 System-on-chip 1200-8200 can be configured with phase-locked loops 1030-8030 and processors 1040-8040.

  Clock generators 1020 to 8020 can generate clock CLK according to the oscillation signals received from oscillators 1010 to 8010. The clock CLK may be supplied to the system on chip 1200 to 8200. The phase lock loop 1030-8030 can generate the first clock CLK1 synchronized with the clock CLK. The first clock CLK1 may be supplied to the components of the system on chip 1200-8200. The processors 1040-8040 may include or be coupled to the level converter 100 according to embodiments of the present invention. The level converter 100 maintains the ratio of the high level section and the ratio of the low level section, and converts the first clock CLK1 of the first voltage domain to the second clock CLK2 of the second voltage domain. The processors 1040 to 8040 operate according to the second clock CLK2. Other components of the system-on-chip 1200 to 8200 operate in response to the first clock CLK1.

  Television 9500 can be a three-dimensional television and a smart television. Although not shown in FIG. 19, display units 1070 to 8070, speakers 1090 to 8090, and user interfaces 1140 to 8140 are additionally provided to at least one of the rear surface, the upper surface, the lower surface, and the side surface of the television 9500. obtain. In addition, display units 1070 to 8070, speakers 1090 to 8090, and user interfaces 1140 to 8140 may be additionally provided as accessories connected to the television 6500. Illustratively, a remote controller that communicates with the television 9500 may additionally be provided at the user interface 1140-8140.

  Although the detailed description of the present invention has been described with reference to specific embodiments, various modifications can be made without departing from the scope and technical idea of the present invention. Therefore, the scope of the present invention is not limited to the above-described embodiments, but should be determined not only by the claims described below but also by the equivalents of the claims of the present invention.

100 level converter 110 first voltage conversion circuit 111 first inverter 113 second inverter 120 second voltage conversion circuit 121 third inverter 123 fourth inverter N1 to N4 NMOS transistor P1 to P4 PMOS transistor 500 system on chip (SOC)
510 processor 512 to 519 flip-flop 520 phase lock loop 530 peripheral block 540 audio block 550 display block 560 graphic block 570 image processing block 580 codec block 1000 to 8000 multimedia device 11010 to 8010 oscillator 1020 to 8020 clock generation unit 1030 to 8030 phase Lock loop 1040-8040 Processor 1050-8050 Memory 1060-8060 Display control unit 1070-8070 Display unit 1080-8080 Sound control unit 1090-8090 Speaker 1100-8100 Storage unit 1110-8110 Modem 1120-7120 Image processing unit 1130-813 Camera 1140-8140 user interface 1150-8150 codec unit 9100 smartphone 9200 tablet computer 9300 mobile computer 9400 computer 9500 TV

Claims (23)

An input node;
First and second voltage conversion circuits configured to generate an output clock of a second voltage domain in response to an input clock of the first voltage domain received through the input node;
An output node that outputs the output clock, and
The first and second voltage conversion circuits have the same structure and are connected in parallel between the input node and the output node.   The level converter according to claim 1, wherein the first voltage conversion circuit includes at least two inverters operating in the second voltage domain.   2. The level converter according to claim 1, wherein the second voltage conversion circuit includes at least one inverter operating in the first voltage domain and at least one inverter operating in the second voltage domain.   4. The level converter of claim 3, wherein at least one inverter operating in the second voltage domain is configured to receive an output of at least one inverter operating in the first voltage domain. The first voltage conversion circuit outputs a second voltage or a ground voltage according to the voltage of the input node, and a second inverter outputs the second voltage or the ground voltage to an output node according to the output of the first inverter. Including inverter,
The second voltage conversion circuit outputs the first voltage or the ground voltage according to the voltage of the input node, and outputs the second voltage or the ground voltage to the output node according to the output of the third inverter. The level converter according to claim 1, comprising a fourth inverter.   The level converter according to claim 1, wherein the first to fourth inverters are CMOS inverters. A phase locked loop configured to generate a first clock of a first voltage domain;
A peripheral block, an audio block, a display block, a graphic block, an image processing block, and a codec block that operate according to the first clock;
A level converter for generating a second clock in a second voltage domain based on the first clock;
A processor that operates in response to the second clock,
The level converter is connected in parallel between an input node and an output node, and includes a first voltage conversion circuit and a second voltage conversion circuit having the same structure (SOC, System-On-Chip). The first voltage conversion circuit operates in the second voltage domain and includes first and second inverters connected in series;
8. The system-on according to claim 7, wherein the second voltage conversion circuit includes a third inverter that operates in the first voltage domain, and a fourth inverter that operates in accordance with an output of the third inverter in the second voltage domain. Chip.   The system on chip of claim 7, wherein the voltage level of the second voltage domain is higher than the voltage level of the first voltage domain. A processor;
An operating memory of the processor;
A modem configured to communicate with the outside according to the control of the processor;
A storage configured to store data according to control of the processor;
A user interface configured to sense and communicate external signals to the processor;
A display control unit configured to display an image through the display unit according to the control of the processor;
A sound control unit configured to output sound through a speaker according to the control of the processor;
A codec unit that performs encoding and decoding according to the control of the processor;
A clock generator configured to generate a clock according to an output of the oscillator;
A phase locked loop for generating a first clock in a first voltage domain synchronized to the clock;
A level converter configured to generate a second clock in a second voltage domain in response to the first clock;
The processor operates in response to the second clock;
The level converter is connected in parallel between an input node and an output node and includes first and second voltage conversion circuits having the same structure. The level converter is
A first inverter that outputs a second voltage of the second voltage domain or a ground voltage according to a voltage of the input node;
A second inverter that outputs the second voltage or ground voltage to an output node according to the output of the first inverter;
A third inverter that outputs a first voltage of the first voltage domain or a ground voltage according to a voltage of the input node;
The multimedia device according to claim 10, further comprising: a fourth inverter that outputs the second voltage or the ground voltage to the output node according to an output of the third inverter. The processor, operation memory, display control unit, sound control unit, codec unit, and phase lock loop constitute a system on chip,
The multimedia apparatus according to claim 10, wherein the operation memory, the display control unit, the sound control unit, and the codec unit operate according to the first clock.   The multimedia apparatus of claim 10, further comprising an image processing unit configured to process image data obtained from a camera according to control of the processor. The processor, display control unit, sound control unit, image processing unit, operation memory, codec unit, and phase lock loop constitute a system-on-chip,
The multimedia apparatus according to claim 13, wherein the display control unit, sound control unit, image processing unit, operation memory, and codec unit operate according to the first clock. The processor, display control unit, sound control unit, modem, image processing unit, operation memory, codec unit, and phase lock loop are included in the system on chip,
The multimedia apparatus according to claim 13, wherein the display control unit, sound control unit, modem, image processing unit, operation memory, and codec unit operate according to the first clock. The processor, display control unit, sound control unit, operation memory, codec unit, and phase lock loop are included in the system on chip,
The multimedia apparatus according to claim 13, wherein the display control unit, the sound control unit, the operation memory, and the codec unit operate according to the first clock. The processor, display controller, sound controller, operation memory, and phase lock loop are included in the system on chip,
The multimedia apparatus according to claim 13, wherein the display control unit, the sound control unit, and the operation memory operate in accordance with the first clock. The processor, display controller, operating memory, and phase lock loop are included in the system on chip,
14. The multimedia apparatus according to claim 13, wherein the display control unit and the operation memory operate according to the first clock. The processor, operating memory, and phase lock loop are included in the system on chip,
The multimedia apparatus according to claim 13, wherein the operation memory operates in accordance with the first clock. The processor, sound controller, operating memory, and phase lock loop are included in the system on chip,
The multimedia apparatus according to claim 13, wherein the sound control unit and the operation memory operate in accordance with the first clock.   The processor, operation memory, modem, storage unit, user interface, display control unit, display unit, sound control unit, speaker, oscillator, clock generation unit, camera, image processing unit, codec unit, and phase lock loop are mobile devices The multimedia device according to claim 10, which is included in the list.   The processor, operating memory, modem, storage unit, user interface, display control unit, display unit, sound control unit, speaker, oscillator, clock generation unit, camera, image processing unit, codec unit, and phase lock loop are smart TVs The multimedia device according to claim 10, which is included in (Smart Television). A first voltage conversion circuit;
A second voltage conversion circuit connected in parallel with the first voltage conversion circuit between an input node and an output node;
A second clock of the second voltage domain is output from the output node in response to a first clock of the first voltage domain input to the input node;
The level converter, wherein a delay time between the rising edge of the first clock and the rising edge of the second clock is the same as the delay time between the falling edge of the first clock and the falling edge of the second clock.

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