JP2012073166A - Testing apparatus and testing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform voltage margin testing for DUTs having multilevel interface.SOLUTION: A pattern generator PG generates a pattern signal Sthat describes a test signal S1 to be applied to a DUT1. A driver DR generates the test signal S1 having a level corresponding to the pattern signal S, and outputs it to the DUT1. A voltage modulator 10 changes the voltage level of the test signal S1 that is output from the driver DR, within a predetermined voltage range. For example, the voltage modulator 10 superimposes an offset component on the test signal S1.

Description

  The present invention relates to a test apparatus.

A voltage margin test is performed on a semiconductor device having a high-speed transmission interface. The voltage margin test is a test for inspecting whether or not a device under test (DUT) has a sufficient margin against a change in voltage level of an input signal. For example, in a binary interface, a signal input to a semiconductor device can take two voltage levels V _H and V _L , a high level and a low level. For each of the two voltage levels, an upper limit value (V _{H, max} , V _{L, max} ) and a lower limit value (V _{H, min} , V _{L, min} ) are given, or the upper limit value A _max A lower limit A _min is given. In the voltage margin test, the DUT has an allowable margin of an upper limit value V _{H, max} to a lower limit value V _{H, min} for the high level fluctuation of the input signal, and the upper limit value for the low level fluctuation of the input signal. It is inspected whether or not it has an allowable margin of V _{L, max} to lower limit value V _{L, min} . Alternatively, it is checked whether the DUT has a margin of an upper limit value A _max to a lower limit value A _min with respect to the amplitude fluctuation of the input signal. FIG. 1 is a diagram illustrating a voltage tolerance margin of a binary interface.

Normally, in the case of a binary signal, a bit error is likely to occur when the voltage level of the input signal is close to the voltage level (reference level) V _ref that serves as a reference for binary logic determination, that is, when the amplitude is small. Therefore, a voltage margin test by a conventional test apparatus has been performed using a test pattern signal having a combination of voltage levels (V _Hmin , V _Lmax ) that minimizes the amplitude.

JP 2003-98230 A Japanese Utility Model Publication No. 5-87578 JP 58-79171 A U.S. Pat. No. 7,162,672 JP-A-8-313592 JP-A-6-235754

  In recent years, as the amount of data handled by semiconductor devices has increased, the speed of interfaces has been increasing, and multi-value digital interfaces having more than two values have begun to be implemented. At present, there is no test apparatus capable of performing a voltage margin test on a semiconductor device having such a multi-value interface.

FIGS. 2A and 2B are diagrams showing a voltage allowable margin of the multi-value interface. Here, quaternary signals are considered. Also in the case of a multilevel signal, an upper limit value and a lower limit value can be considered for each of a plurality of voltage levels V _{0 to} V ₃ , as in the case of a binary signal. Alternatively, an upper limit value and a lower limit value can be considered for the amplitude.

When the DUT adaptively sets the reference levels V _{ref0 to} V _ref2 that are the determination criteria of the logic level according to the amplitude of the input signal, the amplitude of the input signal is set to the minimum value as shown in FIG. The voltage margin test can be realized by changing between 2 and the maximum value.

On the other hand, depending on the DUT, the reference levels V _{ref0 to} V _ref2 may be fixed. In this case, as shown in FIG. 2 (b), the voltage levels V _{0 to} V ₃ of the input signal with respect to the DUT are set to the upper limit values V _{0, max to} V _{3, max} , and the test is performed (FIG. 2 (b)). (Left) Separately, it is necessary to perform a test by setting the voltage levels V _{0 to} V ₃ of the input signal to the lower limit values V _{0, min to} V _{3, min} (FIG. 2 (b) right). That is, there is a problem that the test time increases because the voltage margin test needs to be performed twice.

  Even if a certain DUT passes both tests when the voltage level of the input signal is set to the upper limit value and when it is set to the lower limit value, a certain level takes the upper limit value, It is not possible to guarantee that an input signal that takes a lower limit value can be correctly received, which is insufficient as a voltage margin test.

  The present invention has been made in view of such a situation, and one of exemplary objects of an aspect thereof is to provide a test apparatus capable of performing a voltage margin test for a DUT having a multi-value interface.

  One embodiment of the present invention relates to a test apparatus that supplies a test signal to a device under test. The test apparatus includes a pattern generator that generates a pattern signal describing a test signal to be supplied to the device under test, a driver that generates a test signal having a level corresponding to the pattern signal, and outputs the test signal to the device under test; And a voltage modulator that changes the voltage level of the test signal output from a predetermined voltage range.

  According to this aspect, by changing the voltage level of the test signal by the voltage modulator over a certain test period, the eye opening of the signal applied to the device under test can be closed, and the voltage margin test can be performed.

  Note that any combination of the above-described components, or a conversion of the expression of the present invention between methods, apparatuses, and the like is also effective as an aspect of the present invention.

  According to an aspect of the present invention, a voltage margin test of a DUT having a multi-value interface can be realized.

It is a figure which shows the voltage tolerance margin of a binary interface. FIGS. 2A and 2B are diagrams showing a voltage allowable margin of the multi-value interface. It is a block diagram which shows the structure of the test apparatus which concerns on embodiment. 4A and 4B are waveform diagrams of test signals generated by the test apparatus. 5A to 5D are diagrams illustrating specific examples of offset components. FIGS. 6A and 6B are waveform diagrams showing a test signal on which an offset voltage synchronized with the test rate is superimposed. It is a circuit diagram which shows the 1st structural example of a threshold voltage generator and a voltage modulator. It is a circuit diagram which shows the 2nd structural example of a driver and a voltage modulator. FIGS. 9A to 9C are waveform diagrams of differential test signals generated by the test apparatus. FIGS. 10A and 10B are circuit diagrams illustrating configuration examples of a differential driver and a voltage modulator. FIGS. 11A and 11B are circuit diagrams showing another configuration example of the differential driver and the voltage modulator. It is a block diagram which shows the structure of the test apparatus which concerns on a modification. FIGS. 13A and 13B are waveform diagrams of test signals generated by the test apparatus of FIG.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  FIG. 3 is a block diagram illustrating a configuration of the test apparatus 2 according to the embodiment. The DUT 1 to be tested by the test apparatus 2 has a multi-value interface. The test apparatus 2 supplies a test signal S1 having a multilevel level to the DUT 1. Then, in response to the test signal S1, the signal S2 generated by the DUT1 is read, and compared with the expected value EXP, the quality of the DUT1 is determined.

  The test apparatus 2 includes a pattern generator PG, a timing generator TG, a format controller FC, a driver DR, a voltage modulator 10, a timing comparator TC, a digital comparator DC, and a fail memory FM.

The pattern generator PG generates a pattern signal _SPTN that describes the test signal S1 to be supplied to the DUT1. Specifically, the pattern signal _SPTN is data that describes the level of the test signal S1 and the timing at which it transitions.

The timing generator TG is a unit for controlling the timing of the test sequence, generates a timing signal _STMG synchronized with the test rate, and outputs it to the pattern generator PG. The pattern generator PG in synchronization with the timing signal _{S TMG,} generating a pattern signal _{S PTN.}

The waveform shaper (format controller) FC serves as an interface between the driver DR and the pattern generator PG. Format controller FC receives the pattern signal _{S PTN} and timing signals _{S TMG,} and outputs it to convert the data format suitable to the driver DR.

The driver DR is controlled by the format controller FC, generates a test signal S1 having a level corresponding to the pattern signal _SPTN , and outputs the test signal S1 to the DUT1. Hereinafter, in order to simplify the description and facilitate understanding, a case where the DUT 1 includes a four-value interface will be described. That test signal S1 driver DR occurs, take one of four voltage levels _V 0 ~V _3.

  The timing comparator TC receives the test signal S2 output from the DUT 1 in response to the test signal S1, and compares it with a reference threshold voltage to determine the voltage level of the test signal S2. For example, the timing comparator TC includes at least one voltage comparator and a pair of latch circuits that latch the comparison result by the voltage comparator at the strobe timing.

In addition to the pattern signal S _PTN , the pattern generator PG generates an expected value signal S _EXP indicating an expected value of the level of the test signal S2 that the DUT 1 should generate in response to the test signal S1. The digital comparator DC compares the output value of the timing comparator TC with the expectation signal S _EXP and determines a match (Pass) or a mismatch (Fail). The fail information detected by the digital comparator DC is stored in the fail memory FM together with the occurrence location.

The above is the basic configuration of the test apparatus 2. In addition to this configuration, the test apparatus 2 includes a voltage modulator 10. The voltage modulator 10 changes the voltage levels V _{0 to} V ₃ of the test signal S1 output from the driver DR in a predetermined voltage range. This is also referred to herein as voltage level “modulation”.

4A and 4B are waveform diagrams of the test signal S1 generated by the test apparatus 2. FIG. FIG. 4A shows a waveform when the voltage levels V _{0 to} V ₃ of the test signal S1 are not modulated, that is, when the voltage modulator 10 is not operated. At this time, the driver DR generates four voltage levels V _{0 to} V ₃ according to the symbol values 00, 01, 10, and 11 indicated by the pattern signal _SPTN .

Next, refer to FIG. FIG. 4B shows how the test signal S 1 is modulated by the voltage modulator 10. The voltage level V ₀ changes in the range of V _{0, min to} V _{0, max} , respectively. Similarly, the voltage levels V ₁ , V ₂ , V ₃ also change within a certain range. The voltage level modulation method will be described later.

Figure 4 a test signal S1 (b), DUT1 is a level determined by the strobe timing _{t 0, t} 1 _.... The voltage level of the DUT _{1 at} each strobe timing t ₀ , t ₁ ... Changes within a predetermined range. That is, a level near the upper limit of the voltage range can be taken at a certain timing, a level near the lower limit can be taken at another timing, and an intermediate level can be taken at another timing.

With the voltage level modulated in this way, the DUT 1 is tested using the test signal S1 including a test pattern that is somewhat long. Then, the eye opening of the test signal S1 is closed as shown in FIG. When the path determination is obtained in all cycles at the stage where the test is completed, the DUT 1 at that time is V _{0, min to} V _{0, max} as shown in the right diagram of FIG. , V1 _{, min to} V1 _{, max} , V2 _{, min to} V2 _{, max} , _and V3 _{, min to} V3 _{, max} are guaranteed to have voltage margins.

If the same test is performed without using the voltage modulator 10, the test is performed once with the voltage level sets V ₀ , V ₁ , V ₂ , and V ₃ being fixed. It is required to repeat the same test while changing the value. In this method, as the level of the multilevel signal increases, the number of tests increases and the total test time also increases.

  On the other hand, according to the test apparatus 2 of FIG. 3, the voltage margin test of the DUT 1 including the multi-value interface can be performed in real time by one test.

Next, a method for modulating the voltage level of the test signal S1 by the voltage modulator 10 will be described. Voltage modulator 10, the voltage level corresponding to the pattern signal _{S PTN,} the pattern signal _{S PTN} may be superimposed uncorrelated offset component _{V OFS.} It can be understood that the test signal S1 in FIG. 4B is obtained by superimposing the offset voltage V _OFS oscillating at a speed faster than the test rate on the test signal S1 shown in FIG.

FIGS. 5A to 5D are diagrams illustrating specific examples of the offset component V _OFS . FIG. 5A shows the offset voltage V _OFS that is faster than the test rate. The offset voltage V _OFS is generated so that positive and negative are alternately repeated regardless of the pattern signal _SPTN . As for the offset voltage V _{OFS in} FIG. 5B, positive and negative are randomly generated. The values of the offset voltage V _{OFS in} FIGS. 5C and 5D change in synchronization with the test rate. That is, it takes a certain level during one cycle of the test signal S1. In FIG. 5C, positive and negative are alternately generated, and in FIG. 5D, positive and negative are randomly generated.

The offset component V _OFS is not limited to that described above, and may be other waveforms. For example, the offset component V _OFS may have a frequency that is even lower than the test rate. That is, it is only necessary that the voltage level of the test signal S1 changes within a predetermined range at the strobe timing of the DUT 1 when observed over a long period.

FIGS. _{6A and} 6B are waveform diagrams showing the test signal S1 on which the offset voltage V _OFS synchronized with the test rate is superimposed. FIG. _6A shows a case where an offset component V _OFS uncorrelated with the pattern signal _SPTN is superimposed. When the offset component V _OFS is synchronized with the test rate, each voltage level of the test signal S1 changes so as to take the upper limit value or the lower limit value at the strobe timing, so that the eye opening can be closed.

This FIG. 6 (b) with respect to show the case where the offset component _{V OFS} correlated with the pattern signal _{S PTN} is superimposed. When the symbol value of the pattern signal S _PTN , in other words, the voltage level (V _{0 to} V ₃ ) of the test signal S 1 transitions from a high value to a low value, the voltage modulator 10 changes the voltage level after the transition, For example, the upper level is offset to take the upper limit level. Conversely, when the symbol value of the pattern signal _SPTN , in other words, the voltage level of the test signal S1 transitions from a low value to a high value, the voltage modulator 10 sets the voltage level after the transition to the low level side, for example, the lower limit. Offset to take a level. Thereby, since the modulation can be performed so that the eye opening becomes narrow, the DUT 1 can be tested under more severe conditions.

  Next, the configuration of the driver DR and the voltage modulator 10 will be described. FIG. 7 is a circuit diagram showing a first configuration example of the threshold voltage generator and the voltage modulator. The driver DR may be composed of a current mode logic type voltage driver.

The driver DR includes a termination voltage generator 20, a resistor R1, a plurality of current sources 24 _{1 to} 24 ₃ , and a plurality of D / A converters 26 _{1 to} 26 ₃ . The number of the current sources 24 is arbitrary, and is designed according to the resolution of the voltage level of the test signal S1. Termination voltage generator 20 generates a termination voltage _{V T.} A termination voltage V _T generated by the termination voltage generator 20 is applied to one end of the resistor R1. A plurality of current sources 24 _{1 to} 24 ₃ are connected to the other end of the resistor R1. The current sources 24 _{1 to} 24 ₃ generate constant currents I _{1 to} I ₃ set by the D / A converters 26 _{1 to} 26 ₃ .

The format controller FC controls on / off of the currents I _{1 to} I ₃ generated by the current sources 24 _{1 to} 24 ₃ in accordance with the pattern signal _SPTN from the pattern generator PG. Although not shown, the format controller FC is input the timing signal _{S TMG} from the timing generator TG, by utilizing this timing signal _{S TMG,} switching timing of the current _I 1 ~I ₃ is controlled. On the current _I 1 ~I _3, off may be controlled by the switch ₂₈ 1 to 28 ₃ provided on a path of the current _I 1 ~I _3. If the current sources 24 _{1 to} 24 ₃ can realize a zero current state, these switches can be omitted.

The driver DR outputs the voltage _VOUT generated at the other end of the resistor R1 as the test signal S1 corresponding to the pattern signal _SPTN .

The currents I _{1 to} I ₃ generated by the current sources 24 _{1 to} 24 ₃ may be equal. In this case, the format controller FC converts the pattern signal _SPTN into a thermometer code. The number of current sources 24 and switches 28 required in the driver DR that generates the quaternary test signal S1 is three. When the number of switches to be turned on is n (0 ≦ n ≦ 3), the output voltage _VOUT of the driver DR is I when the current value generated by the current sources 24 _{1 to} 24 ₃ is I.
V _OUT = V _T −R1 × n × I
It becomes.

The current I generated by the plurality of current sources 24 may be binary weighted. In this case, the format controller FC converts the pattern signal _SPTN into a binary code, and controls on / off of the switch according to the binary code. For example, the number of current sources 24 and switches 28 required in the driver DR that generates the quaternary test signal S1 is two. When the upper bit of the 2-bit binary code is a ₁ , the lower bit is a _2, and I ₁ = 2 × I and I ₂ = I, the output voltage _VOUT of the driver DR is
V _OUT = V _T −R1 × (2 × I × a ₁ + I × a ₂ )
It becomes.

The voltage modulator 10 switches the set values of the D / A converters 26 _{1 to} 26 _m , thereby causing the current values I _{1 to} I _m of the current sources 24 _{1 to} 24 _m to be uncorrelated with the pattern signal _SPTN . Or change with correlation. As a result, an offset is given to the value of the current flowing through the resistor R1, and the voltage level of the test signal S1 can be changed.

FIG. 8 is a circuit diagram illustrating a second configuration example of the driver and the voltage modulator. The driver DR includes a switch 29 controlled by the voltage modulator 10 in addition to the switch 28 controlled according to the pattern signal _SPTN . The current source 25 generates a current I _Δ corresponding to the offset component. The D / A converter 27 sets a current I _Δ , that is, a voltage level fluctuation range.

Voltage modulator 10 is uncorrelated with the pattern signal S _PTN, or have a correlation, on the switch 29, by switching off the current flowing through the resistor R1 is offset by I _delta, the voltage level of the test signal S1 Can be changed.

  The above is the case where the test signal S1 is a single-ended signal, but the present invention is also applicable when the test signal S1 is a differential signal.

  9A to 9C are waveform diagrams of the differential test signal S1 generated by the test apparatus 2. FIG. FIG. 9A shows a case where the positive logic component and the negative logic component of the differential signal are modulated uncorrelated with each other. As a result, the voltage modulation component can be superimposed on the differential test signal S1, and the eye opening in the level direction of the differential signal can be closed.

FIG. 9B shows a state in which an offset component V _OFS having a reverse phase, that is, opposite in polarity is superimposed on each of the positive logic component and the negative logic component of the differential signal. In this case, the voltage modulation component can be superimposed on the test signal S1 while the common mode voltage of the differential signal is kept constant, and the eye opening in the level direction of the differential signal can be closed.

FIG. 9C shows a state where an offset component V _OFS having the same phase, that is, the same polarity is superimposed on each of the positive logic component and the negative logic component of the differential signal. In this case, a voltage modulation component can be superimposed on the common mode voltage of the differential signal. In the case of FIG. 9C, there is no change in the eye opening in the level direction of the differential signal. Thereby, the fluctuation tolerance test of the common mode voltage of the DUT 1 can be performed in real time.

Also when modulating the differential test signal S1, the modulation rate may be the same as the test rate, higher or lower. Further, the offset component V _OFS may be uncorrelated with the pattern signal _SPTN or may have a correlation.

FIGS. 10A and 10B are circuit diagrams illustrating configuration examples of a differential driver and a voltage modulator. The driver shown in FIG. 10A is obtained by modifying the CML driver shown in FIG. 7 into a differential format. Voltage modulator 10, by changing the current value of the current source 26 ₁ to 26 _3, modulates the voltage level of the differential of the test signal S1.

The driver shown in FIG. 10B is obtained by modifying the driver shown in FIG. 8 into a differential type. The switches 29 _P and 29 _N and the current sources 25 _P and 25 _N are provided for the positive logic component and the negative logic component, respectively. The voltage modulator 10 modulates the voltage level of the test signal S1 by switching on and off the switches 29 _P and 29 _N. By independently controlling the switches 29 _P and 29 _N , the positive logic component S1 _P and the negative logic component S1 _N of the test signal S1 can be modulated uncorrelated as shown in FIG.

FIGS. 11A and 11B are circuit diagrams showing another configuration example of the differential driver and the voltage modulator. In the driver DR shown in FIGS. 11A and 11B, a single current source 25 is provided in common for the switches 29 _P and 29 _N. In FIG. 11A, the switches 29 _P and 29 _N are controlled in reverse phase by the inverter 30. As a result, it superimposes the anti-phase offset component in positive logic component S1 _P and the negative logic component S1 _N of the test signal S1. In FIG. 11B, the switches 29 _P and 29 _N are controlled in phase. As a result, it superimposes the offset component of phase with positive logic component S1 _P and the negative logic component S1 _N of the test signal S1.

FIG. 12 is a block diagram illustrating a configuration of a test apparatus 2a according to a modification. The test apparatus 2a in FIG. 12 includes a timing modulator 12 in addition to the test apparatus 2 in FIG.
The timing modulator 12 changes the timing at which the level of the test signal S1 transitions. For example timing modulator 12 acts on the pattern signal S _PTN to the pattern generator PG generates may change the transition timing indicated by the pattern signal S _PTN. In this case, the timing modulator 12 can be incorporated in the pattern generator PG.

Some test apparatuses include a variable delay circuit that gives a delay amount corresponding to the transition timing indicated by the pattern signal _SPTN to a reference timing signal. The delayed timing signal is supplied to the format controller FC, and the output level of the driver DR is switched at the edge timing of the delayed timing signal. In this case, the timing modulator 12 may be composed of a variable delay circuit that gives a delay corresponding to the modulation to a reference timing signal. In this case, the timing modulator 12 can be incorporated in the format controller FC. In some test apparatuses, the timing modulator 12 may be configured as a part of the timing generator TG. That is, the timing generator TG may have the function of the timing modulator 12.

  The timing modulator 12 may modulate the transition timing of the test signal S1 in an uncorrelated or correlated manner with the voltage modulator 10. Specifically, the timing modulator 12 may change the transition timing for each test cycle in synchronization with the voltage modulator 10. The modulation of the transition timing may be performed randomly or according to a certain pattern.

  FIGS. 13A and 13B are waveform diagrams of the test signal S1 generated by the test apparatus 2a of FIG.

  FIG. 13A shows a waveform when the voltage modulator 10 and the timing modulator 12 perform modulation in the amplitude direction and the time axis direction uncorrelated with each other. By modulating the transition timing by the timing modulator 12, the aperture ratio in the time axis direction can be reduced in addition to the aperture ratio in the amplitude direction of the eye opening. Alternatively, the modulation in the amplitude direction by the voltage modulator 10 may be stopped, and the modulation in the time axis direction may be performed only by the timing modulator 12.

When the voltage level of the test signal S1 is modulated by the voltage modulator 10, the timing at which the test signal S1 _{crosses the} reference voltage level _Vrefk is shifted. The left figure of FIG.13 (b) has shown this time-axis direction shift (timing error). That is, when modulation is performed by the voltage modulator 10, a timing error due to the modulation occurs. Therefore, time-axis direction modulation by the timing modulator 12 may be used to correct timing errors. The right figure of FIG.13 (b) shows a mode that a timing error is compensated by changing the level transition timing of the test signal S1.

  Thus, by providing the timing modulator 12, the transition timing of the test signal S1 can be positively changed, or the timing error caused by the modulation by the voltage modulator 10 can be compensated.

  In the embodiment, the case where the test signal S1 having three or more values, that is, a multilevel voltage level is generated has been described. However, the present invention is also applicable to a binary interface.

  Although the present invention has been described based on the embodiments, the embodiments merely show the principle and application of the present invention, and the embodiments depart from the idea of the present invention defined in the claims. Many modifications and changes in the arrangement are allowed within the range not to be performed.

DESCRIPTION OF SYMBOLS 1 ... DUT, 2 ... Test apparatus, 10 ... Voltage modulator, 12 ... Timing modulator, TC ... Timing comparator, PG ... Pattern generator, TG ... Timing generator, FC ... Format controller, DR ... Driver, DC ... Digital Comparator, FM ... Fail memory, S1, S2 ... Test signal, S1 ... Pattern signal.

Claims (19)

A test apparatus for supplying a test signal to a device under test,
A pattern generator for generating a pattern signal describing a test signal to be supplied to the device under test;
A driver that generates the test signal having a level corresponding to the pattern signal and outputs the test signal to the device under test;
A voltage modulator that changes a voltage level of the test signal output from the driver in a predetermined voltage range;
A test apparatus comprising: The device under test comprises a multi-value interface;
2. The test according to claim 1, wherein the driver generates the test signal having a level of three or more values according to the pattern signal generated by the pattern generator and outputs the test signal to the device under test. apparatus.   The test apparatus according to claim 1, wherein the voltage modulator superimposes an offset component on the test signal.   The test apparatus according to claim 3, wherein the voltage modulator superimposes an offset component uncorrelated with the pattern signal.   The test apparatus according to claim 1, wherein the voltage modulator superimposes an offset component that varies at a predetermined period.   4. The test apparatus according to claim 3, wherein the voltage modulator superimposes an offset component having a constant level during one cycle of the test signal, and switches the offset component in units of the cycle of the test signal. .   The test apparatus according to claim 3, wherein the voltage modulator superimposes an offset component corresponding to the pattern signal.   When the voltage level to be taken by the test signal indicated by the pattern signal transits from a high value to a low value, the voltage modulator offsets the voltage level after the transition to a high level side, and the pattern signal The test apparatus according to claim 7, wherein when the voltage level to be taken by the test signal to be shown transits from a low value to a high value, the voltage level after the transition is offset to a low level side. The driver includes a current mode logic voltage driver,
The test apparatus according to claim 1, wherein the voltage modulator changes a current value of the voltage driver. The driver includes a current mode logic voltage driver,
The test apparatus according to claim 1, wherein the voltage modulator switches a switch provided on a path of a current generated in the voltage driver. The driver includes a differential driver;
The test apparatus according to claim 1, wherein the voltage modulator changes a positive logic output and a negative logic output of the differential driver in an uncorrelated manner. The driver includes a differential driver;
The test apparatus according to claim 1, wherein the voltage modulator changes a positive logic output and a negative logic output of the differential driver in opposite phases and with the same amplitude. The driver includes a differential driver;
The test apparatus according to claim 1, wherein the voltage modulator changes a positive logic output and a negative logic output of the differential driver in the same phase and with the same amplitude.   The test apparatus according to claim 1, further comprising a timing modulator that modulates a timing at which the test signal transitions.   The test apparatus according to claim 14, wherein the timing modulator modulates a transition timing of the test signal in a non-correlated manner with the voltage modulator.   The timing modulator modulates the transition timing of the test signal so as to cancel a shift in timing caused by the voltage modulator when the test signal crosses a reference voltage level. The test apparatus described in 1.   The test apparatus according to claim 14, wherein the timing modulator modulates a transition timing of the test signal in synchronization with the voltage modulator. A test method for a device under test,
Generating a pattern signal describing a test signal to be supplied to the device under test;
Generating the test signal having a level corresponding to the pattern signal and outputting the test signal to the device under test;
Changing the voltage level of the test signal in a predetermined voltage range;
A method comprising the steps of: The device under test comprises a multi-value interface;
The method according to claim 18, wherein the test signal has a level of three or more values according to the pattern signal.

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