JP2012059195A - Multi-thread processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that, in a conventional multi-thread processor, the throughput cannot be sufficiently brought out.SOLUTION: A multi-thread processor has: an instruction supply section 10 including a first instruction buffer 231 for storing a first instruction code and second instruction buffers 232-23m for storing second instruction codes; an instruction selector 11 for selecting an instruction code issued from the first and second instruction buffers; an instruction decoder 12 for decoding the instruction code selected by the instruction selector 11; and an instruction execution section 13 for performing information processing based on a decode result. The instruction supply selection 10 has a thread control part 24 for storing a first instruction code in the first instruction buffer preferentially and, when the number of first instruction codes stored in the first instruction buffer becomes more than twice of a maximum value for the number of instruction codes which can be issued in parallel by the instruction supply section 10, storing a second instruction code in the second instruction buffer.

Description

  The present invention relates to a multi-thread processor, and more particularly to a multi-thread processor that executes a high-priority thread and a low-priority thread.

  The processor reads the program and the processing target data from the external memory and performs data processing. Such a processor advances data processing by processing instruction codes serially. The processor includes an instruction supply unit, an instruction decoder, and an instruction execution unit. The instruction supply unit fetches a program from the external memory. The instruction decoder decodes an instruction supplied from the instruction supply unit and generates control information for the instruction execution unit. The instruction execution unit processes data stored in the external memory based on the control information.

  However, the processor is strongly required to improve the processing capability. For this reason, many methods have been proposed for improving the processing capability. Examples of this technique include a VLIW (Very Long Instruction Word) processor and a multi-thread processor.

  The VLIW processor processes a plurality of instructions in parallel. The VLIW processor has an instruction supply unit, an instruction decoder, and an instruction execution unit. That is, the basic configuration is the same as a general processor. However, in the VLIW processor, the instruction supply unit fetches a plurality of instructions from the external memory, and the instruction decoder decodes the plurality of instructions to generate a plurality of control information. Then, the instruction execution unit processes a plurality of data in parallel based on the plurality of control information. Since this VLIW processor has a limit of average instruction-parallelism (ILP), its performance improvement is limited.

  The multi-thread processor can exceed the ILP limit of the VLIW processor by executing a plurality of independent programs (threads) in parallel. The multi-thread processor has an instruction selector in addition to an instruction supply unit, an instruction decoder, and an instruction execution unit. In the multi-thread processor, the instruction supply unit fetches instructions of a plurality of independent threads. Then, the instruction supply unit extracts instructions that can be executed simultaneously at runtime from the instructions of the plurality of threads to be supplied. The instruction selector supplies the instruction read from the instruction supply unit to the instruction decoder unit.

  In the multithread processor, an instruction cache and an instruction buffer are provided. The instruction cache stores instructions fetched from the external memory. The instruction buffer is provided with an instruction buffer corresponding to the number of threads. The instruction buffer receives the instruction of the corresponding thread from the instruction cache. In other words, the instruction buffer stores instructions to be processed for each thread. The multi-thread processor appropriately processes a plurality of threads by reading instructions from the instruction buffer. In this multi-thread processor, the processing performance can be improved by improving the processing efficiency of the instructions stored in the instruction buffer.

  Patent Document 1 proposes a method of selecting a processing target thread based on a frequency defined by a software program. Non-Patent Document 1 proposes a round-robin method for cyclically selecting a plurality of threads, a method for selecting a thread for which a branch is determined, and a method for selecting a thread with a small number of instructions held in the instruction buffer. ing.

  Also, in Patent Document 2, in a multi-thread processor, in order to prevent a program stop (memory stall) due to an instruction read wait from the memory, a management unit is provided in the instruction fetch buffer and stored in the fetch buffer. A technique is disclosed in which when the number of instructions decreases, the urgency of reading the instruction corresponding to the fetch buffer is increased.

JP 2010-86130 A JP 2006-195705 A

"Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor", International Symposium on Computer Architecture, 1996

  However, the thread selection methods described in Patent Document 1 and Non-Patent Document 1 have a problem that a sufficient processing capability cannot be realized in a VLIW processor capable of multi-thread operation. For example, one program is composed of a main process (main thread) that takes a long time for processing, and a sub-process (sub thread) that uses the result of the main thread and can be processed in a short time. This is the case. In this case, in order to realize optimum performance, it is desirable that the main thread and the secondary thread are terminated at the same time.

  In Patent Document 1, a thread to be selected is determined based only on the frequency with which each thread is selected. Therefore, in the thread selection method described in Patent Document 1, when the number of instructions simultaneously executed by a high priority thread is small, the number of instructions fetched into the instruction buffer is larger than the number of instructions to be executed. Thus, instructions waiting for processing are accumulated in the instruction buffer. In other words, the time for which the instruction is stored in the instruction buffer is unnecessarily long, and the instruction that cannot be stored in the instruction buffer is wasted. In other words, the thread selection method described in Patent Document 1 has a problem that the instruction supply capability of the instruction cache is wasted.

  Further, in the thread selection method described in Patent Document 1, even when there are not enough instructions to be executed in the instruction buffer corresponding to the high priority thread, the instruction buffer corresponding to the low priority thread is used. There are cases where instructions are accumulated. In that case, there is no instruction to be executed in the instruction buffer corresponding to the high priority thread, the process is stalled, and there is a problem that the execution of the high priority thread is excessively suppressed.

  The thread selection method described in Non-Patent Document 1 is premised on treating all threads equally. Therefore, when there is a difference in processing time (or the number of threads to be processed) between the main thread and the sub thread, there is a problem that efficient processing cannot be performed.

  Also in Patent Document 2, since priority is not taken into consideration for each thread and each fetch buffer, a low priority instruction is processed with priority, and there is a problem that processing of a high priority thread is delayed. This problem is particularly noticeable when the ratio of instruction codes is extremely biased, such as when the number of instruction codes processed in a high-priority thread is far greater than the number of instruction codes in a low-priority thread. .

  In other words, in the techniques described in Patent Documents 1 and 2 and Non-Patent Document 1, in a VLIW processor capable of multi-thread operation, when trying to execute a program having a main thread and a secondary thread, the processing performance is sufficiently exhibited. There is a problem that can not be.

  One aspect of the multi-thread processor according to the present invention is a first instruction buffer that stores a first instruction code belonging to a first thread, and a second instruction code that stores a second instruction code belonging to a second thread. An instruction supply unit comprising: an instruction buffer; an instruction selector for selecting an instruction code to be transmitted to a subsequent circuit among instruction codes issued from the first and second instruction buffers; and the instruction selected by the instruction selector An instruction decoder that decodes a code to generate execution instruction information; and an instruction execution unit that performs information processing based on the execution instruction information, wherein the instruction supply unit preferentially stores in the first instruction buffer The first instruction code is stored, and the number of the first instruction codes stored in the first instruction buffer is the maximum number of instruction codes that can be issued in parallel by the instruction supply unit. Having a thread control unit to store the second instruction code to said second instruction buffer when it becomes equal to or greater than 2 times the value.

  Another aspect of the multi-thread processor according to the present invention is a multi-thread processor that executes, in a time division manner, a first instruction code belonging to the first thread and a second instruction code belonging to the second thread. A first instruction buffer that stores a first instruction code belonging to a first thread, a second instruction buffer that stores a second instruction code belonging to a second thread, and the first The first instruction code is stored in the instruction buffer, and the number of the first instruction codes stored in the first instruction buffer is the maximum number of instructions that can be issued in parallel by the first buffer. And a thread control unit that stores the second instruction code in the second instruction buffer when the number of the second instruction buffers exceeds two.

  In the multi-thread processor according to the present invention, the thread control unit causes the number of first instruction codes stored in the first instruction buffer to be twice the maximum number of instructions that can be issued in parallel by the first buffer. The second instruction code is stored in the second instruction buffer when the number is larger. As a result, the multithread processor according to the present invention can prevent the instruction code stored in the first instruction buffer from stalling even if the instruction code is stored in the second instruction buffer.

  According to the multithread processor of the present invention, it is possible to improve the processing performance by efficiently storing the instruction code in the instruction buffer.

1 is a block diagram of a multithread processor according to a first embodiment; 3 is a conceptual diagram showing a data storage structure of an instruction cache according to the first embodiment; FIG. 3 is a timing chart illustrating an instruction fetch procedure of the instruction cache according to the first embodiment; FIG. 3 is a block diagram of a thread control unit according to the first exemplary embodiment. 4 is a timing chart showing an instruction issue sequence of an instruction supply unit according to the first exemplary embodiment; FIG. 6 is a block diagram showing a multi-thread processor in an operating state corresponding to the thread 3 in FIG. 5. FIG. 6 is a block diagram showing a multi-thread processor in an operating state corresponding to the thread 4 in FIG. 5. FIG. 6 is a block diagram showing a multi-thread processor in an operating state corresponding to the thread 5 in FIG. 5. 4 is a timing chart showing an instruction issue sequence of an instruction supply unit according to the first exemplary embodiment; FIG. 10 is a block diagram showing a multi-thread processor in an operating state corresponding to the thread 3 of FIG. 9. FIG. 10 is a block diagram showing a multi-thread processor in an operating state corresponding to the thread 4 of FIG. 9. FIG. 10 is a block diagram showing a multi-thread processor in an operating state corresponding to the thread 5 of FIG. 9. It is a timing chart which shows the instruction issue sequence of the instruction supply part by a general thread control part. FIG. 6 is a block diagram of a thread control unit according to the second embodiment. 6 is a timing chart showing an instruction issue sequence of an instruction supply unit according to the second exemplary embodiment; FIG. 6 is a block diagram of a multithread processor according to a third exemplary embodiment. FIG. 10 is a block diagram of a waiting control unit according to the third embodiment. FIG. 9 is a block diagram of a control signal generation unit according to a third exemplary embodiment. FIG. 9 is a block diagram of a control signal generation unit according to a third exemplary embodiment. FIG. 9 is a block diagram of a thread control unit according to a third embodiment. 10 is a timing chart illustrating an instruction issue sequence of an instruction supply unit according to the third embodiment; FIG. 10 is a sequence diagram showing a switching state of threads fetched by the multithread processor according to the third embodiment.

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. The multi-thread processor according to the present invention is a VLIW processor including a plurality of instruction codes in instructions fetched at a time. The VLIW processor can process a plurality of instruction codes in parallel. In the following description, a VLIW processor that simultaneously executes a maximum of two instructions in one cycle will be described as an example.

  FIG. 1 shows a block diagram of a multithread processor 1 according to the first exemplary embodiment. As shown in FIG. 1, the multithread processor 1 includes an instruction supply unit 10, an instruction selector 11, an instruction decoder 12, and an instruction execution unit 13. In the multithread processor 1, the instruction supply unit 10 reads a program from an external memory. The instruction supply unit 10 issues an instruction code related to the read program. The multi-thread processor 1 performs data processing by processing data stored in the external memory based on the instruction code issued from the instruction supply unit 10.

  The instruction supply unit 10 includes a first instruction buffer that stores a first instruction code that belongs to a first thread (for example, a first program), and a second instruction that belongs to a second thread (for example, a second program). A second instruction buffer for storing two instruction codes. The instruction supply unit 10 issues a plurality of instruction codes at a time. The plurality of instruction codes may be configured only by those belonging to the first thread, or instruction codes belonging to the first and second threads may be mixed. In the present embodiment, it is assumed that the first thread is a main thread that requires a long time to complete the process, and the second thread is a secondary thread that completes the process in a short time. The secondary thread uses the calculation result of the main thread or prepares a process necessary for the calculation of the main thread. Furthermore, the secondary thread may be composed of a plurality of threads. Details of the instruction supply unit 10 will be described later.

  The instruction selector 11 selects an instruction code to be transmitted to the subsequent circuit from the instruction codes issued from the first and second instruction buffers. More specifically, the instruction selector 11 selects an instruction code to be transmitted to the subsequent circuit in consideration of a combination of instruction codes in which a plurality of instruction codes issued by the instruction supply unit 10 do not use the same arithmetic unit. To do.

  The instruction decoder 12 decodes the instruction code selected by the instruction selector 11 and generates execution instruction information. The instruction execution unit 13 reads data for processing from the external memory. The instruction execution unit 13 processes the read data based on the execution instruction information decoded by the instruction decoder 12. Thereafter, the instruction execution unit 13 writes the processing result back to the external memory.

  The multi-thread processor 1 according to the first embodiment has one feature in a method for controlling the number of instruction codes stored in the instruction buffer in the instruction supply unit 10. The instruction supply unit 10 will be described in detail below.

  As illustrated in FIG. 1, the instruction supply unit 10 includes program counters 201 to 20m, an address selector 21, an instruction cache 22, instruction buffers 231 to 23m, and a thread control unit 24. The program counter is provided according to the number of executable threads (for example, programs). In the example shown in FIG. 1, it corresponds to m threads (m is an integer). Each of the program counters 201 to 20m increases the count value in accordance with the progress of the thread. This count value functions as a pointer that occupies the address of the instruction cache in which the instruction code belonging to the thread is stored. In the following description, it is assumed that the program counter 201 is provided corresponding to the first thread (for example, the main thread), and the count value of the program counter 201 is the first count value. The program counters 202 to 20m are provided corresponding to the second thread (for example, the secondary thread), and the count value of the program counters 202 to 20m is set as the second count value.

  The address selector 21 selects and outputs either the first count value or the second count value in accordance with the address selection signal AdSel.

  The instruction cache 22 reads and stores a program related to the thread from the external memory. The program is composed of a plurality of instruction codes. Here, in the following description, an instruction code constituting a program related to the first thread is referred to as a first instruction code, and an instruction code constituting a program related to the second thread is referred to as a second instruction code. Call it. The instruction cache 22 fetches the first instruction code to the first instruction buffer 231 according to the first count value, and the second instruction code according to the second count value to the second instruction buffer 232-2. Fetch to 23m.

  The instruction cache 22 fetches a plurality of instruction codes according to the input count value. The plurality of instruction codes are instruction codes belonging to the same thread, and are stored at consecutive addresses on the instruction cache 22. In the multithread processor 1 according to the first embodiment, 2 is set as the maximum number NMI of instruction codes that can be issued simultaneously by the instruction supply unit 10. Therefore, in the multithread processor 1, the instruction cache 22 fetches two instruction codes. Here, a conceptual diagram of the data storage structure of the instruction cache 22 is shown in FIG. As shown in FIG. 2, the instruction cache 22 stores an instruction code for each thread. In the example shown in FIG. 2, the first thread (for example, thread 1) is configured by instruction codes Im1 to Im16, the second thread (for example, thread 2) is configured by instruction codes Isa1 to Isa6, and the second A thread (for example, thread m) is constituted by instruction codes Isx1 to Isx8. Then, the instruction cache 22 uses the input count value as a pointer, and fetches data stored at an address indicated by the pointer and an address subsequent to the address.

  The instruction buffers 231 to 23m are provided corresponding to the threads. Here, in the present embodiment, the instruction buffer 231 functions as a first instruction buffer provided corresponding to the first thread. The instruction buffers 232 to 23m function as a second instruction buffer provided corresponding to the second thread. In the multi-thread processor 1 according to the first embodiment, the capacity of the first instruction buffer is set to at least twice the maximum number NMI of instruction codes that can be issued simultaneously by the instruction supply unit 10. In the example shown in FIG. 1, the maximum number NMI of instruction codes that can be issued simultaneously by the instruction supply unit 10 is set to 2. Therefore, in the example shown in FIG. 1, the instruction buffer 231 used as the first instruction buffer is set so as to be able to store four instructions. The first and second instruction buffers may be set to have the same capacity, but the capacity of the second instruction buffer may be set to be smaller than that of the first instruction buffer.

  Since the multi-thread processor 1 according to the first embodiment is a VLIW processor, the method of fetching an instruction from the instruction cache to the instruction buffer is different from a general method of fetching a single instruction code. Therefore, FIG. 3 shows a timing chart showing the instruction fetch procedure when the multi-thread processor 1 has one thread to be processed. The instruction fetch procedure when the processing target thread is one thread will be described with reference to FIG. In the multi-thread processor 1, it is assumed that the process proceeds every operation cycle. FIG. 3 shows an example in which only the thread 1 is set as a processing target thread and the count value of the program counter 201 increases.

  In the example shown in FIG. 3, the program counter 201 is reset at cycle 0. Then, in cycle 1, the count value of the program counter 201 becomes 1. At this time, no instruction code is stored in the instruction buffer 231. Therefore, the instruction cache 22 fetches two instruction codes. In the example shown in FIG. 3, the instruction cache 22 fetches the instruction code Im1 corresponding to the count value “1” and the instruction code Im2 following the instruction code Im1. The instruction cache 22 fetches two instruction codes at the same time because the maximum number NMI of simultaneously issued instructions of the instruction supply unit 10 is two. Further, the bandwidth between the instruction cache 22 and the instruction buffer 231 is set to a band that can sufficiently transfer instruction codes fetched at the same time.

  Subsequently, in cycle 2, the count value of the program counter 201 increases. The maximum value of the count increment is set to 2 corresponding to the number of simultaneous fetch instruction codes in the instruction cache 22. In addition, the count increment is Hmax as the maximum number of instructions that can be held in the instruction buffer 231, HMI as the number of instructions held in the instruction buffer 231, and NII as the number of instruction codes issued by the instruction supply unit 10. , Count increase number = Hmax− (HNI−NII). In the example shown in FIG. 3, the count increase in cycle 1 is 4, so the count increase in cycle 2 is 2. Therefore, in cycle 2, the count value of the program counter 201 is 3. The instruction cache 22 fetches the instruction codes Im3 and Im4 corresponding to the count value “3”. In cycle 2, the instruction codes Im1 and Im2 fetched in cycle 1 are stored in the instruction buffer 231 and the instruction code Im1 is issued.

  Subsequently, in cycle 3, since the count increase number in cycle 2 is 3, the count value of the program counter 201 increases by 2 which is the maximum increase number to 5. Then, instruction codes Im5 and Im6 are fetched from the instruction cache 22 corresponding to the count value “5”. In cycle 2, instruction code Im1 is issued, and instruction codes Im3 and Im4 are fetched. Therefore, the instruction codes stored in the instruction buffer 231 in cycle 3 are the three instruction codes Im2, Im3, and Im4. In the example shown in FIG. 3, the instruction code Im2 is issued in cycle 3. As a result, the count increment when the operation of cycle 3 is completed becomes 2.

  Subsequently, in cycle 4, since the number of increments in cycle 3 is 2, the count value of program counter 201 is incremented by 2 to 7. The instruction codes Im7 and Im8 are fetched from the instruction cache 22 corresponding to the count value “7”. In cycle 3, instruction code Im2 is issued, and instruction codes Im5 and Im6 are fetched. Therefore, the instruction codes stored in the instruction buffer 231 in cycle 4 are four instruction codes Im3, Im4, Im5, and Im6. In the example shown in FIG. 3, the instruction code Im3 is issued in cycle 4. As a result, the count increment when the operation of cycle 4 is completed becomes 1.

  Subsequently, in cycle 5, since the count increment in cycle 4 is 1, the count value of program counter 201 is incremented by 1 to 8. Then, the instruction codes Im8 and Im9 are fetched from the instruction cache 22 corresponding to the count value “8”. In cycle 4, instruction code Im3 is issued, and instruction codes Im7 and Im8 are fetched. However, in cycle 5, the instruction buffer 231 can hold only one instruction. Therefore, the instruction code Im8 is discarded in the cycle 5. The instruction codes stored in the instruction buffer 231 in cycle 5 are four instruction codes Im4, Im5, Im6, and Im7. In the example shown in FIG. 3, the instruction code Im4 is issued in cycle 5. As a result, the count increment when the operation of cycle 5 is completed becomes 1.

  Subsequently, in cycle 6, since the count increment in cycle 5 is 1, the count value of program counter 201 is incremented by 1 to 9. Then, the instruction codes Im9 and Im10 are fetched from the instruction cache 22 corresponding to the count value “9”. In cycle 5, instruction code Im4 is issued, and instruction codes Im8 and Im9 are fetched. However, in cycle 6, the instruction buffer 231 can hold only one instruction. Therefore, the instruction code Im9 is discarded in the cycle 6. The instruction codes stored in the instruction buffer 231 in cycle 6 are four instruction codes Im5, Im6, Im7, and Im8. In the example shown in FIG. 3, instruction codes Im5 and Im6 are issued in cycle 6. As a result, the count increment when the operation of cycle 6 is completed becomes 2.

  Subsequently, in cycle 7, since the count increment in cycle 6 is 2, the count value of program counter 201 is increased by 2 to 11. Then, the instruction codes Im11 and Im12 are fetched from the instruction cache 22 corresponding to the count value “11”. In cycle 6, instruction codes Im5 and Im6 are issued, and instruction codes Im9 and Im10 are fetched. Therefore, the instruction codes stored in the instruction buffer 231 in cycle 7 are four instruction codes Im7, Im8, Im9, and Im10. In the example shown in FIG. 3, instruction codes Im7 and Im8 are issued in cycle 7. As a result, the count increment when the operation of cycle 7 is completed becomes 2.

  Subsequently, in cycle 8, since the count increment in cycle 7 is 2, the count value of program counter 201 is increased by 2 to 13. Then, the instruction codes Im13 and Im14 are fetched from the instruction cache 22 corresponding to the count value “13”. In cycle 7, instruction codes Im7 and Im8 are issued, and instruction codes Im11 and Im12 are fetched. Therefore, the instruction codes stored in the instruction buffer 231 in cycle 8 are four instruction codes Im9, Im10, Im11, and Im12. In the example shown in FIG. 3, the instruction code Im9 is issued in cycle 8. As a result, the count increment when the operation of cycle 8 is completed becomes 1.

  Thus, the program counter 201 advances the count value according to the maximum number of instructions Hmax stored in the instruction buffer 231 and the number of instruction codes issued by the instruction supply unit 10. Further, the instruction cache 22 always fetches the maximum number of instruction codes that can be fetched regardless of whether or not the fetched instruction code is held in the instruction buffer 231. Note that the instruction cache 22 may be configured to fetch instructions equal to or less than the maximum number of instruction codes depending on whether or not the fetched instruction code is held in the instruction buffer 231. The control method of the program counter 201 and the instruction cache 22 described above is an example, and other control methods can be applied.

  Next, the thread control unit 24 that controls which instruction code belongs to which thread in the instruction buffers 231 to 23m in the instruction supply unit 10 will be described in detail. The thread control unit 24 according to the first embodiment preferentially stores the first instruction code (instruction code belonging to the thread 1) in the first instruction buffer (for example, the instruction buffer 231) and stores it in the instruction buffer 231. Second instruction buffer (for example, instruction buffers 232 to 23m) when the number of first instruction codes to be executed is twice or more the maximum value of the number of instruction codes that can be issued in parallel by the instruction supply unit 10 The second instruction code (instruction code belonging to thread 2 to thread m) is stored in. In the present embodiment, the address selection signal AdSel output from the thread control unit 24 is output to the address selector 21. The thread control unit 24 switches whether the count value output from the address selector is the first count value or the second count value according to the number of instruction codes stored in the first instruction buffer. Switching of the output count value is controlled by switching the program counter designated by the address selection signal AdSel. Through such control, the thread control unit 24 controls the accumulation state of the instruction code in the instruction buffer.

  In the multithread processor 1 according to the first embodiment, the fetch number signal NFI indicating the number of instruction codes fetched by the instruction cache 22 is output, indicating the number of instruction codes held in the instruction buffers 231 to 23m. The instruction holding number signal NHI is output, and the instruction decoder 12 outputs an instruction issue number signal NII indicating the number of instruction codes issued from the instruction supply unit. Then, the thread control unit 24 switches the state of the address selection signal AdSel based on the fetch number signal NFI, the instruction holding number signal NHI, and the instruction issue number signal NII. In this embodiment, it is assumed that the fetch number signal NFI, the instruction holding number signal NHI, and the instruction issue number signal NII all indicate the number of instruction codes belonging to the main thread (for example, thread 1).

  A block diagram of the thread control unit 24 is shown in FIG. As illustrated in FIG. 4, the thread control unit 24 includes a high thread selection unit 30, a round robin selection unit 31, and a low thread selection unit 32. In the present embodiment, the address selection signal AdSel output from the thread control unit 24 is composed of a plurality of signals corresponding to the number of program counters. Then, the thread control unit 24 controls the address selector 21 by setting the address selection signal corresponding to the thread to transmit the count value to the instruction cache to a high level (for example, 1).

The high thread selection unit 30 outputs the address selection signal during a period in which the number of instruction codes stored in the first instruction buffer is less than twice the maximum number NMI of instructions that the instruction supply unit 10 can issue in parallel. It is assumed that the count value of 1 (for example, the count value of the program counter 201) is selected (for example, the address selection signal AdSel [1] is 1). More specifically, the high thread selection unit 30 supplies the value indicated by the fetch number signal NFI as NFI, the value indicated as the instruction holding number signal NHI as NHI, and the value indicated as the instruction issue number signal NII as NII. When the maximum number of instructions that can be issued simultaneously by the unit 10 is NMI, the address selection signal AdSel [1] corresponding to the main thread is set to 1 (for example, selected state) when the condition of the expression (1) is satisfied.
NFI + NHI ≧ NII + 2 × NMI (1)

  The round robin selection unit 31 cyclically selects the threads 2 to m defined as the secondary threads. An address selection signal AdSel [1] of the main thread (for example, thread 1) is input to the round robin selection unit 31. The round robin selection unit 31 switches a thread to be selected every time the address selection signal AdSel [1] indicates a non-selected state (for example, 0).

  The low thread selection unit 32 selects the second count value from the address selection signals AdSel [2] to AdSel [m] when the address selection signal AdSel [1] sets the first count value to the non-selected state. And More specifically, the low thread selection unit 32 has an AND circuit corresponding to the number of sub threads as a gating circuit. This AND circuit outputs the output signal of the round robin selection unit 31 as the address selection signals AdSel [2] to AdSel [m] while the address selection signal AdSel [1] is 0.

  Next, the operation of the multithread processor 1 according to the first embodiment having the thread control unit 24 will be described. The multi-thread processor 1 has at least two effects by controlling the accumulation state of the instruction code belonging to the main thread in the instruction buffer by the thread control unit 24. The first effect is to improve the execution efficiency of the main thread. The second effect is to improve the fetch efficiency of the instruction code from the instruction cache to the instruction buffer. Therefore, in the following description, first, the first effect will be described.

  FIG. 5 shows a timing chart showing the operation of the multi-thread processor 1 for explaining the first effect. FIG. 5 shows the thread selected by the address selection signal AdSel and the number of instruction code fetches, the number of instructions held, and the number of instructions issued for each cycle from cycle 0 to cycle 8. Further, in the example shown in FIG. The numbers shown in each column of the timing chart shown in FIG. 5 are the number of instruction codes of thread 1 / thread 2 / thread 3. Note that thread 1 is a main thread, and threads 2 and 3 are secondary threads. In the example shown in FIG. 5, the maximum number NMI of instruction codes that can be issued simultaneously by the instruction supply unit 10 is set to 2.

  In FIG. 5, the operation starts at cycle 0. In cycle 0, the instruction code is not fetched from the instruction cache 22, and there is no instruction code held in the instruction buffers 231 to 233. In cycle 0, if the above equation (1) is calculated based on the fetch number NFI, the instruction holding number NHI, and the instruction issue number NII corresponding to the thread 1, the condition of the equation (1) is not satisfied. Therefore, in cycle 0, thread 1 is selected by the address selection signal AdSel.

  In cycle 1, the instruction cache 22 fetches two instruction codes belonging to the thread 1 based on the fact that the thread 1 is selected by the address selection signal AdSel in the cycle 0. That is, the fetch number NFI is 2/0/0. In cycle 1, the instruction code fetched by the instruction cache 22 is not stored in the instruction buffer. In cycle 1, when the above-described expression (1) is calculated based on the fetch number NFI, instruction holding number NHI, and instruction issue number NII corresponding to thread 1, the condition of expression (1) is not satisfied. Therefore, in cycle 1, thread 1 is selected by address selection signal AdSel.

  In cycle 2, the instruction cache 22 fetches two instruction codes belonging to the thread 1 based on the fact that the thread 1 is selected by the address selection signal AdSel in cycle 1. That is, the fetch number NFI is 2/0/0. In cycle 2, the instruction code fetched by instruction cache 22 in cycle 1 is stored in instruction buffer 231 provided corresponding to thread 1. Therefore, the instruction holding number NHI is 2/0/0. Furthermore, in cycle 2, since one instruction code belonging to the thread 1 is issued from the instruction supply unit 10, the instruction issue number NII is 1/0/0. Here, the number of instructions issued by the instruction supply unit 10 is determined based on the type of arithmetic unit used by the instruction codes held in the instruction buffers 231 to 233, with the maximum value of the simultaneous issue number being 2. That is, when the first two instruction codes of the instruction buffer 231 use the same arithmetic unit, the simultaneous issue number is 1, and when different arithmetic units are used, the simultaneous issue number is two. In the cycle 2, when the above equation (1) is calculated based on the fetch number NFI, the instruction holding number NHI, and the instruction issue number NII corresponding to the thread 1, the condition of the equation (1) is not satisfied. Therefore, in cycle 2, thread 1 is selected by the address selection signal AdSel.

  In cycle 3, the instruction cache 22 fetches two instruction codes belonging to the thread 1 based on the fact that the thread 1 is selected by the address selection signal AdSel in cycle 2. That is, the fetch number NFI is 2/0/0. In cycle 3, the fetch number NFI of cycle 2 is 2/0/0, the instruction holding number NHI is 2/0/0, and the instruction issue number NII is 1/0/0. Therefore, the instruction holding number NHI of cycle 3 is 3/0/0. Further, in cycle 3, since one instruction code belonging to the thread 1 is issued from the instruction supply unit 10, the instruction issue number NII is 1/0/0. In the cycle 3, when the above equation (1) is calculated based on the fetch number NFI, the instruction holding number NHI, and the instruction issue number NII corresponding to the thread 1, the condition of the equation (1) is satisfied. Therefore, in cycle 3, thread 2 is selected by address selection signal AdSel.

  In cycle 4, the instruction cache 22 fetches two instruction codes belonging to the thread 2 based on the selection of the thread 2 by the address selection signal AdSel in the cycle 3. That is, the fetch number NFI is 0/2/0. In cycle 4, the fetch number NFI in cycle 3 is 2/0/0, the instruction holding number NHI is 3/0/0, and the instruction issue number NII is 1/0/0. Therefore, the instruction holding number NHI in cycle 4 is 4/0/0. Furthermore, in cycle 4, since the instruction supply unit 10 issues two instruction codes belonging to the thread 1, the instruction issue count NII is 2/0/0. Further, in the cycle 4, when the above-described expression (1) is calculated based on the fetch number NFI, the instruction holding number NHI, and the instruction issue number NII corresponding to the thread 1, the condition of the expression (1) is not satisfied. Therefore, in cycle 4, the thread 1 is selected by the address selection signal AdSel.

  In cycle 5, the instruction cache 22 fetches two instruction codes belonging to the thread 1 based on the fact that the thread 1 is selected by the address selection signal AdSel in cycle 4. That is, the fetch number NFI is 2/0/0. In cycle 5, the fetch number NFI in cycle 4 is 0/2/0, the instruction holding number NHI is 4/0/0, and the instruction issue number NII is 2/0/0. Therefore, the instruction holding number NHI in cycle 5 is 2/2/0. Further, in cycle 5, since the instruction code belonging to the thread 1 and the instruction code belonging to the thread 2 are issued one by one from the instruction supply unit 10, the instruction issue number NII is 1/1/0. In cycle 5, when the above-described equation (1) is calculated based on the fetch number NFI, the instruction holding number NHI, and the instruction issue number NII corresponding to the thread 1, the condition of the equation (1) is not satisfied. Therefore, in cycle 5, the thread 1 is selected by the address selection signal AdSel.

  In cycle 6, the instruction cache 22 fetches two instruction codes belonging to the thread 1 based on the fact that the thread 1 is selected by the address selection signal AdSel in the cycle 5. That is, the fetch number NFI is 2/0/0. In cycle 6, the fetch number NFI in cycle 5 is 2/0/0, the instruction holding number NHI is 2/2/0, and the instruction issue number NII is 1/1/0. Therefore, the instruction holding number NHI in cycle 6 is 3/1/0. Further, in cycle 6, since the instruction code belonging to the thread 1 and the instruction code belonging to the thread 2 are issued one by one from the instruction supply unit 10, the instruction issue number NII is 1/1/0. Further, in the cycle 6, when the above equation (1) is calculated based on the fetch number NFI, the instruction holding number NHI, and the instruction issue number NII corresponding to the thread 1, the condition of the equation (1) is satisfied. Therefore, in cycle 6, the thread 3 is selected by the address selection signal AdSel.

  In cycle 7, the instruction cache 22 fetches two instruction codes belonging to the thread 3 based on the fact that the thread 3 is selected by the address selection signal AdSel in the cycle 6. That is, the fetch number NFI is 0/0/2. In cycle 7, the fetch number NFI in cycle 6 is 1/1/0, the instruction holding number NHI is 3/1/0, and the instruction issue number NII is 1/1/0. Therefore, the instruction holding number NHI in cycle 7 is 4/0/0. Further, in cycle 7, two instruction codes belonging to the thread 1 are issued from the instruction supply unit 10, so that the instruction issue count NII is 2/0/0. Further, when the above expression (1) is calculated based on the fetch number NFI, the instruction holding number NHI, and the instruction issue number NII corresponding to the thread 1 in the cycle 7, the condition of the expression (1) is not satisfied. Therefore, in cycle 7, the thread 1 is selected by the address selection signal AdSel.

  In cycle 8, the instruction cache 22 fetches two instruction codes belonging to the thread 1 based on the fact that the thread 1 is selected by the address selection signal AdSel in the cycle 7. That is, the fetch number NFI is 2/0/0. In cycle 8, the fetch number NFI in cycle 7 is 0/0/2, the instruction holding number NHI is 4/0/0, and the instruction issue number NII is 2/0/0. Therefore, the instruction holding number NHI in cycle 8 is 2/0/2. Further, in cycle 8, since the instruction code belonging to the thread 1 and the instruction code belonging to the thread 3 are issued one by one from the instruction supply unit 10, the instruction issue number NII is 1/0/1. In cycle 8, if the above-described equation (1) is calculated based on the fetch number NFI, the instruction holding number NHI, and the instruction issue number NII corresponding to the thread 1, the condition of the equation (1) is not satisfied. Therefore, in cycle 8, the thread 1 is selected by the address selection signal AdSel.

  In the example shown in FIG. 5, the instruction code belonging to the thread 2 defined as the secondary thread in the cycle 4 is fetched. The multi-thread processor 1 achieves the first effect of improving the execution efficiency of the main thread by realizing the operations of cycle 3 to cycle 5 by the thread control unit 24. Therefore, the operations of cycle 3 to cycle 5 will be described more specifically using the block diagram of the multithread processor 1. 6 to 8 are block diagrams of the multi-thread processor 1 showing the operations of cycle 3 to cycle 5 in FIG.

  FIG. 6 is a block diagram of the multi-thread processor 1 in a state where the operation of the cycle 3 in FIG. 5 is performed. As shown in FIG. 6, in cycle 3, instruction codes Im2, Im3, and Im4 are stored in the instruction buffer 231. The instruction supply unit 10 issues an instruction code Im2. The instruction cache 22 fetches instruction codes Im5 and Im6 based on the count value of the program counter 201.

  Next, FIG. 7 is a block diagram of the multi-thread processor 1 in a state where the operation of the cycle 4 in FIG. 5 is performed. In cycle 3, when the above equation (1) is calculated based on the fetch number NFI, the instruction holding number NHI, and the instruction issue number NII corresponding to the thread 1, the condition of the equation (1) is satisfied. That is, in cycle 4, the instruction buffer 231 is in a state where instruction codes twice as large as the maximum number NMI issued are accumulated. Therefore, the thread control unit 24 controls the thread so that the instruction codes Isa1 and Isa2 belonging to the thread 2 are accumulated in the instruction buffer 232 in the cycle 4 by the address selection signal AdSel. On the other hand, in cycle 4, the instruction supply unit 10 issues instruction codes Im3 and Im4.

  Next, FIG. 8 is a block diagram of the multi-thread processor 1 in a state where the operation of the cycle 5 in FIG. 5 is performed. As shown in FIG. 8, in the multithread processor 1, the instruction code is not fetched into the instruction buffer 231 in cycle 4 (the operation cycle shown in FIG. 7). However, in the operation up to the cycle 3, the instruction buffer 231 stores instruction codes twice as many as the maximum number NMI issued. Therefore, even when the same number of instruction codes as the maximum number NMI issued is issued in cycle 4, instruction codes satisfying the maximum number of instruction codes that may be issued in the next cycle are stored in the instruction buffer 231. Maintain the accumulated state. That is, the execution of the secondary thread has no influence on the execution of the main thread. Then, the multi-thread processor 1 stores the instruction codes Im7 and Im8 belonging to the thread 1 in the instruction buffer 231 in the cycle 5 in response to the address selection signal AdSel being in the state of selecting the thread 1 in the cycle 4. In cycle 5, instruction code Im 5 is issued from instruction buffer 231, and instruction code Isa 1 is issued from instruction buffer 232. However, since the instruction codes Im7 and Im8 are accumulated in the instruction buffer 231 in the cycle 5, an instruction code that satisfies the maximum number of instruction codes that can be issued is stored in the instruction buffer 231 even after the cycle 6. The accumulated state can be maintained.

  Next, a second effect of improving the instruction code fetch efficiency from the instruction cache to the instruction buffer will be described. A timing chart showing the operation of the multi-thread processor 1 for explaining the second effect is shown in FIG. FIG. 9 shows the thread selected by the address selection signal AdSel and the number of instruction code fetches, the number of instructions held, and the number of instructions issued for each cycle from cycle 0 to cycle 8. Further, in the example shown in FIG. The numbers shown in each column of the timing chart shown in FIG. 9 are the number of instruction codes of thread 1 / thread 2 / thread 3. Note that thread 1 is a main thread, and threads 2 and 3 are secondary threads. In the example shown in FIG. 9, the maximum number NMI of instruction codes that can be issued simultaneously by the instruction supply unit 10 is set to 2.

  In FIG. 9, the operation starts at cycle 0. In cycle 0, the instruction code is not fetched from the instruction cache 22, and there is no instruction code held in the instruction buffers 231 to 233. In cycle 0, if the above equation (1) is calculated based on the fetch number NFI, the instruction holding number NHI, and the instruction issue number NII corresponding to the thread 1, the condition of the equation (1) is not satisfied. Therefore, in cycle 0, thread 1 is selected by the address selection signal AdSel.

  In cycle 1, the instruction cache 22 fetches two instruction codes belonging to the thread 1 based on the fact that the thread 1 is selected by the address selection signal AdSel in the cycle 0. That is, the fetch number NFI is 2/0/0. In cycle 1, the instruction code fetched by the instruction cache 22 is not stored in the instruction buffer. In cycle 1, when the above-described expression (1) is calculated based on the fetch number NFI, instruction holding number NHI, and instruction issue number NII corresponding to thread 1, the condition of expression (1) is not satisfied. Therefore, in cycle 1, thread 1 is selected by address selection signal AdSel.

  In cycle 2, the instruction cache 22 fetches two instruction codes belonging to the thread 1 based on the fact that the thread 1 is selected by the address selection signal AdSel in cycle 1. That is, the fetch number NFI is 2/0/0. In cycle 2, the instruction code fetched by instruction cache 22 in cycle 1 is stored in instruction buffer 231 provided corresponding to thread 1. Therefore, the instruction holding number NHI is 2/0/0. Further, in cycle 2, since two instruction codes belonging to the thread 1 are issued from the instruction supply unit 10, the instruction issue number NII is 2/0/0. Here, the number of instructions issued by the instruction supply unit 10 is determined based on the type of arithmetic unit used by the instruction codes held in the instruction buffers 231 to 233, with the maximum value of the simultaneous issue number being 2. That is, when the first two instruction codes of the instruction buffer 231 use the same arithmetic unit, the simultaneous issue number is 1, and when different arithmetic units are used, the simultaneous issue number is two. In the cycle 2, when the above equation (1) is calculated based on the fetch number NFI, the instruction holding number NHI, and the instruction issue number NII corresponding to the thread 1, the condition of the equation (1) is not satisfied. Therefore, in cycle 2, thread 1 is selected by the address selection signal AdSel.

  In cycle 3, the instruction cache 22 fetches two instruction codes belonging to the thread 1 based on the fact that the thread 1 is selected by the address selection signal AdSel in cycle 2. That is, the fetch number NFI is 2/0/0. In cycle 3, the fetch number NFI in cycle 2 is 2/0/0, the instruction holding number NHI is 2/0/0, and the instruction issue number NII is 2/0/0. Therefore, the instruction holding number NHI in cycle 3 is 2/0/0. Further, in cycle 3, since one instruction code belonging to the thread 1 is issued from the instruction supply unit 10, the instruction issue number NII is 1/0/0. In the cycle 3, when the above equation (1) is calculated based on the fetch number NFI, the instruction holding number NHI, and the instruction issue number NII corresponding to the thread 1, the condition of the equation (1) is not satisfied. Therefore, in cycle 3, thread 1 is selected by address selection signal AdSel.

  In cycle 4, the instruction cache 22 fetches two instruction codes belonging to the thread 1 based on the fact that the thread 1 is selected by the address selection signal AdSel in the cycle 3. That is, the fetch number NFI is 2/0/0. In cycle 4, the fetch number NFI of cycle 3 is 2/0/0, the instruction holding number NHI is 2/0/0, and the instruction issue number NII is 1/0/0. Therefore, the instruction holding number NHI in cycle 4 is 3/0/0. Furthermore, in cycle 4, since the instruction supply unit 10 issues two instruction codes belonging to the thread 1, the instruction issue number NII is 1/0/0. In the cycle 4, when the above equation (1) is calculated based on the fetch number NFI, the instruction holding number NHI, and the instruction issue number NII corresponding to the thread 1, the condition of the equation (1) is satisfied. Therefore, in cycle 4, the thread 2 is selected by the address selection signal AdSel.

  In cycle 5, the instruction cache 22 fetches two instruction codes belonging to the thread 2 based on the fact that the thread 2 is selected by the address selection signal AdSel in the cycle 4. That is, the fetch number NFI is 0/2/0. In cycle 5, the fetch number NFI in cycle 4 is 2/0/0, the instruction holding number NHI is 3/0/0, and the instruction issue number NII is 1/0/0. Therefore, the instruction holding number NHI in cycle 5 is 4/0/0. Further, in cycle 5, since two instruction codes belonging to the thread 1 are issued from the instruction supply unit 10, the instruction issue number NII is 2/0/0. In cycle 5, when the above-described equation (1) is calculated based on the fetch number NFI, the instruction holding number NHI, and the instruction issue number NII corresponding to the thread 1, the condition of the equation (1) is not satisfied. Therefore, in cycle 5, the thread 1 is selected by the address selection signal AdSel.

  In cycle 6, the instruction cache 22 fetches two instruction codes belonging to the thread 1 based on the fact that the thread 1 is selected by the address selection signal AdSel in the cycle 5. That is, the fetch number NFI is 2/0/0. In cycle 6, the fetch number NFI in cycle 5 is 0/2/0, the instruction holding number NHI is 4/0/0, and the instruction issue number NII is 2/0/0. Therefore, the instruction holding number NHI in cycle 6 is 2/2/0. Further, in cycle 6, since two instruction codes belonging to the thread 2 are issued from the instruction supply unit 10, the instruction issue number NII is 0/2/0. Further, in the cycle 6, when the above equation (1) is calculated based on the fetch number NFI, the instruction holding number NHI, and the instruction issue number NII corresponding to the thread 1, the condition of the equation (1) is satisfied. Therefore, in cycle 6, the thread 3 is selected by the address selection signal AdSel.

  In cycle 7, the instruction cache 22 fetches two instruction codes belonging to the thread 1 based on the selection of the thread 3 by the address selection signal AdSel in the cycle 6. That is, the fetch number NFI is 0/0/2. In cycle 7, the fetch number NFI in cycle 6 is 2/0/0, the instruction holding number NHI is 2/2/0, and the instruction issue number NII is 0/2/0. Therefore, the instruction holding number NHI in cycle 7 is 4/0/0. Further, in cycle 7, two instruction codes belonging to the thread 1 are issued from the instruction supply unit 10, so that the instruction issue count NII is 2/0/0. Further, when the above expression (1) is calculated based on the fetch number NFI, the instruction holding number NHI, and the instruction issue number NII corresponding to the thread 1 in the cycle 7, the condition of the expression (1) is not satisfied. Therefore, in cycle 7, the thread 1 is selected by the address selection signal AdSel.

  In cycle 8, the instruction cache 22 fetches two instruction codes belonging to the thread 1 based on the fact that the thread 1 is selected by the address selection signal AdSel in the cycle 7. That is, the fetch number NFI is 2/0/0. In cycle 8, the fetch number NFI in cycle 7 is 2/0/0, the instruction holding number NHI is 4/0/0, and the instruction issue number NII is 2/0/0. Therefore, the instruction holding number NHI in cycle 8 is 2/0/2. Further, in cycle 8, since the instruction code belonging to the thread 1 and the instruction code belonging to the thread 3 are issued one by one from the instruction supply unit 10, the instruction issue number NII is 1/0/1. In cycle 8, if the above-described equation (1) is calculated based on the fetch number NFI, the instruction holding number NHI, and the instruction issue number NII corresponding to the thread 1, the condition of the equation (1) is not satisfied. Therefore, in cycle 8, the thread 1 is selected by the address selection signal AdSel.

  In the example shown in FIG. 9, the instruction code belonging to the thread 2 defined as the secondary thread in the cycle 4 is fetched. The multi-thread processor 1 achieves the second effect of improving the fetch efficiency of the instruction code from the instruction cache to the instruction buffer by realizing the operations of cycle 3 to cycle 5 by the thread control unit 24. Therefore, the operations of cycle 3 to cycle 5 will be described more specifically using the block diagram of the multithread processor 1. FIG. 10 to FIG. 12 are block diagrams of the multi-thread processor 1 showing the operations of cycle 3 to cycle 5 in FIG.

  FIG. 10 is a block diagram of the multi-thread processor 1 in the state where the operation of the cycle 3 in FIG. 9 is performed. As shown in FIG. 10, in cycle 3, instruction codes Im3 and Im4 are stored in the instruction buffer 231. The instruction supply unit 10 issues an instruction code Im3. The instruction cache 22 fetches instruction codes Im5 and Im6 based on the count value of the program counter 201.

  Next, FIG. 11 is a block diagram of the multi-thread processor 1 in a state where the operation of the cycle 4 in FIG. 9 is performed. In cycle 3, if the above equation (1) is calculated based on the fetch number NFI, the instruction holding number NHI, and the instruction issue number NII corresponding to the thread 1, the condition of the equation (1) is not satisfied. Therefore, the thread control unit 24 controls the thread so that the instruction codes Im7 and Im8 belonging to the thread 1 are accumulated in the instruction buffer 231 in the cycle 4 by the address selection signal AdSel. On the other hand, in cycle 4, the instruction supply unit 10 issues an instruction code Im4.

  Next, FIG. 12 is a block diagram of the multi-thread processor 1 in a state where the operation of the cycle 5 in FIG. 9 is performed. In cycle 4, when the above equation (1) is calculated based on the fetch number NFI, the instruction holding number NHI, and the instruction issue number NII corresponding to the thread 1, the condition of the equation (1) is satisfied. That is, in cycle 5, the instruction buffer 231 is in a state where instruction codes twice as large as the maximum number NMI issued are accumulated. Therefore, the thread control unit 24 controls the thread so that the instruction codes Isa1 and Isa2 belonging to the thread 2 are accumulated in the instruction buffer 232 in the cycle 5 by the address selection signal AdSel. On the other hand, in cycle 5, the instruction supply unit 10 issues instruction codes Im5 and Im6.

  In general, there is a limit to the instruction parallelism (ILP) of an instruction code generated from one thread. Due to this instruction parallelism, the average number of instructions fetched is greater than the number of issued instructions. Therefore, in the multithread processor 1 according to the first embodiment, as described above, the instruction code related to the difference between the fetch number and the instruction issue number is accumulated. Further, in the multi-thread processor 1, an instruction corresponding to the main thread is stored until a sufficient number of instruction codes are stored even if the maximum number of instruction issuing cycles continues twice in the instruction buffer provided corresponding to the main thread. Continue fetching instruction code into buffer. By such an operation, the multi-thread processor 1 allows the main thread to perform fetching to the instruction buffer provided corresponding to the sub thread instead of fetching to the instruction buffer provided corresponding to the main thread. It is possible to prevent the issuance of the instruction code to which it belongs from stalling. That is, the multi-thread processor 1 can efficiently use the fetch capability of the instruction cache.

  In general, when one thread is considered in a VLIW processor capable of multi-thread operation, the number of instruction fetches is larger than the number of instruction issuances on average. From the above description, the multithread processor 1 according to the first embodiment accumulates, in the instruction buffer, the number of instruction codes corresponding to the difference between the instruction fetch number and the instruction issue number for the main thread. In addition, the multi-thread processor 1 supports the secondary thread only when the thread control unit 24 can continue issuing the instruction code for a period of at least two cycles without fetching the instruction code. The instruction code is stored in the instruction buffer.

  With the configuration and control described above, the multithread processor 1 does not stop issuing instruction codes even when instruction code fetching to the instruction buffer corresponding to the main thread is stopped. That is, the multithread processor 1 can improve the processing efficiency of the main thread. Further, the multi-thread processor 1 can bring the number of issued instructions close to the number of fetched instructions by the configuration and control as described above, so that the fetch efficiency of the instruction cache can be improved.

  Here, the effect of improving the processing efficiency of the multi-thread processor 1 will be quantitatively described. In a general multi-thread processor, the number of instruction codes stored in the instruction buffer is set to the same number as the maximum number of issued instructions. Further, the general multi-thread processor 1 selects a thread to be processed according to a predetermined selection order (for example, round robin method). FIG. 13 shows a timing chart showing the operation of such a general multi-thread processor.

  In the example shown in FIG. 13, the thread 1 is a main thread, and the threads 2 and 3 are secondary threads. In the example illustrated in FIG. 13, the thread selection sequence is repeated in which the thread 2 is selected after the thread 1 is selected twice, and then the thread 3 is selected after the thread 1 is further selected twice. In the example shown in FIG. 13, the maximum value of the instruction holding number is limited to 2.

  In the example shown in FIG. 13, two instruction codes belonging to thread 1 are fetched in cycle 1. In cycle 2, two instruction codes belonging to the thread 1 are held in the instruction buffer, and one of the held instruction codes is issued. In cycle 2, two instruction codes belonging to thread 1 are fetched.

  In cycle 3, the instruction code belonging to thread 1 fetched in cycle 2 is stored in the instruction buffer. At this time, the instruction code not issued in cycle 2 remains in the instruction buffer. Therefore, in cycle 3, one of the instruction codes fetched in cycle 2 is stored in the instruction buffer, but the other one is discarded. In cycle 3, one instruction code belonging to thread 1 is issued. Further, in cycle 3, two instruction codes belonging to the thread 2 are fetched. In cycle 4, the number of instructions held is 1/2/0.

  In this cycle 4, when two instruction codes belonging to the thread 1 are issued and used, the number of instructions held for the thread 1 is 1. Therefore, in cycle 4, a stall state in which the instruction code of thread 1 cannot be issued occurs. Since the number of instruction codes belonging to the thread 1 fetched in the period up to the cycle 4 is 6 and the number of instruction codes that could not be issued is 1, in the conventional multithread processor until the cycle 4, A performance degradation of 16% (= 1/6) occurs for 1.

  In addition, the number of instruction fetches is larger than the number of issued instructions due to an average instruction parallelism (ILP) limit. In the example shown in FIG. 13, in cycle 2, the number of instruction fetches is 1, while the number of instruction issuances is 1. That is, in the example shown in FIG. 13, one name code fetched in cycle 2 is wasted. In the conventional multi-thread processor, 16 instruction codes are fetched by cycle 4 and 2 instruction codes are discarded, so that the instruction fetch capability is reduced by 12.5% (= 2/16). Occurs.

  In the multithread processor 1 according to the first embodiment, an instruction code can be issued to the instruction buffer corresponding to the main thread for two cycles or more without fetching the instruction code. There is no performance degradation.

  In the multi-thread processor 1 according to the first embodiment, the circuit area related to the instruction buffers corresponding to a plurality of red is reduced by reducing the capacity of the instruction buffer corresponding to the sub thread rather than the capacity of the instruction buffer corresponding to the main thread. Can be reduced.

Embodiment 2
In the second embodiment, another form of the thread control unit 24 will be described. A block diagram of a thread control unit 24a showing another form of the thread control unit 24 is shown in FIG. As shown in FIG. 14, the thread control unit 24 a is obtained by adding a low thread forcible processing unit to the thread control unit 24. The low thread forcible processing unit counts the number of operation cycles in which the address selection signal AdSel [1] indicates the state of selecting the first count value, and the address selection signal in response to the number of operation cycles reaching a specified number. It is assumed that AdSel [2] to AdSel [m] have selected the second count value. In the thread control unit 24 a, the low thread forcible processing unit includes a counter 33 and an AND circuit 34.

  The counter 33 counts the number of operation cycles in which the address selection signal AdSel [1] indicates a selected state. Then, the counter 33 asserts a suppression signal (a state in which the address selection signal AdSel [1] specifies a non-selected state) in response to the number of operation cycles reaching the specified number. The AND circuit 34 sets the address selection signal AdSel [1] to the non-selected state during the period when the suppression signal is asserted, and outputs the output signal of the high thread selection unit 30 as the address selection signal during the period when the suppression signal is negated. Let AdSel [1].

  Next, the operation of the multithread processor 1a having the thread control unit 24a will be described. FIG. 15 is a timing chart showing the operation of the multithread processor 1a. In the example shown in FIG. 15, 2 is set as the specified number of times for the counter 33. As shown in FIG. 15, the thread control unit 24a selects the secondary thread in the operation cycle in which the count value CNT reaches 2 regardless of the values of the fetch number NFI, the instruction holding number NHI, and the instruction issue number NII. .

  When the thread control unit 24 switches the selected thread by the address selection signal AdSel considering only the values of the fetch number NFI, the instruction holding number NHI, and the instruction issue number NII, the instruction code belonging to the sub thread may not be fetched. Arise. However, when the thread control unit 24a according to the second embodiment is used, the instruction code belonging to the sub thread is fetched every predetermined number of operation cycles. That is, in the multithread processor 1a according to the second embodiment, it is possible to prevent the processing of the secondary thread from being left unprocessed.

Embodiment 3
In the third embodiment, a description will be given of a multi-thread processor that performs a waiting operation in which one thread waits for the end of calculation of another thread and proceeds with processing when a plurality of threads are executed. This waiting process is effective, for example, when the main thread uses the operation result of the secondary thread. In the following description, as an example of the operation and the multi-thread processor, an example will be described in which the thread 1 (main thread) waits for the computation of the thread 2 (secondary thread) to end and the process proceeds.

  FIG. 16 is a block diagram of the multithread processor 2 according to the third embodiment. As shown in FIG. 16, the multi-thread processor 2 is obtained by adding a waiting control unit 25 to the multi-thread processor 1 and using a thread control unit 24 b instead of the thread control unit 24.

  The queuing control unit 25 outputs a control signal SC that suppresses the address selection signal AdSel from selecting a predetermined address value to the thread control unit 24b, and the first count value PC1 is set to a first value set in advance. When the switching threshold C1 is reached, the control signal SC is set to a thread suppression state that prevents the address selection signal AdSel from selecting a thread corresponding to the first count value PC1, and then the second count value is set. When the PC2 reaches the preset second switching threshold C2, the thread suppression state of the control signal SC is canceled. In the example shown in FIG. 16, the count value PC1 of the program counter 201 is used as the first count value, and the count value PC2 of the program counter 202 is used as the second count value.

  Here, a block diagram of the waiting control unit 25 is shown in FIG. As illustrated in FIG. 17, the waiting control unit 25 includes comparators 401 and 402 and control signal generation units 411 and 412. The comparator 401 receives the count value PC1 and the switching threshold C1. The comparator 402 receives the count value PC2 and the switching threshold C2. The comparators 401 and 402 assert the thread switching notification signal CR (for example, 1) when the input count value matches the switching threshold. The switching threshold values C1 and C2 are set by another circuit (not shown). In the example shown in FIG. 17, the comparator 401 outputs a thread switching notification signal CR1, and the comparator 402 outputs a thread switching notification signal CR2. Further, the thread switching notification signal CR1 is output to the control signal generation unit 411, and the thread switching notification signal CR2 is output to the control signal generation units 411 and 412.

  If the thread to which the comparator corresponds does not require the waiting process, the waiting process for the corresponding thread can be invalidated by setting a value that cannot be counted as the switching threshold. For example, when the initial value of the count value of the program counter is 1, 0 may be set as the switching threshold.

  The control signal generator 411 receives the thread switching notification signals CR1 and CR2 and generates a control signal SC [1]. The control signal SC [1] is a control signal corresponding to the thread 1. Then, the control signal generation unit 411 asserts the control signal SC [1] in response to the thread switching notification signal CR1 being asserted. Further, the control signal generation unit 411 changes the control signal SC [1] from the asserted state to the negated state in response to the thread switching notification signal CR2 being asserted during the period in which the thread switching notification signal CR1 is in the asserted state. .

  Here, a detailed circuit diagram of the control signal generator 411 is shown in FIG. As illustrated in FIG. 18, the control signal generation unit 411 includes AND circuits 511, 512, and 61. The AND circuit 511 outputs a logical product of the thread switching notification signal CR1 and the waiting set value S1. The AND circuit 512 outputs a logical product of the inverted value of the thread switching notification signal CR2 and the waiting set value S2. The AND circuit 61 outputs a logical product of the output value of the AND circuit 511 and the output value of the AND circuit 512 as the control signal SC [1].

  The control signal generator 412 receives the thread switching notification signal CR2 and generates the control signal SC [2]. The control signal SC [2] is a control signal corresponding to the thread 2. Then, the control signal generation unit 412 asserts the control signal SC [2] in response to the thread switching notification signal CR2 being asserted.

  Here, a detailed circuit diagram of the control signal generator 412 is shown in FIG. As illustrated in FIG. 19, the control signal generation unit 412 includes an AND circuit 521. The AND circuit 521 outputs a logical product of the thread switching notification signal CR2 and the waiting set value S2 as the control signal SC [2].

  The waiting set values S1 and S2 are values indicating, for example, 0 or 1, and are set depending on what waiting process the threads 1 and 2 perform. In the present embodiment, when the count value PC1 of the thread 1 has reached the switching threshold value C1 and the count value PC1 of the thread 2 has not reached the switching threshold value C2, fetching of instruction codes related to the thread 1 is suppressed, and the thread Wait for process 2 Therefore, 1 is set as the waiting setting values S1 and S2. When the waiting process is not performed, the waiting setting values S1 and S2 are set to zero. The waiting set values S1 and S2 are set by another circuit (not shown).

  Next, the thread control unit 24b will be described. The thread control unit 24b is obtained by adding a control function of the address selection signal AdSel based on the control signal SC to the thread control unit 24a. Specifically, when the control signal SC is asserted, the thread control unit 24b controls the address selection signal AdSel so that only threads other than the thread corresponding to the asserted control signal SC are selected.

  A block diagram of the thread control unit 24b is shown in FIG. As shown in FIG. 20, the thread control unit 24b includes a round robin selection unit 35 instead of the round robin selection unit 31 of the thread control unit 24a, and includes an AND circuit 36 instead of the AND circuit 34.

  The round robin selection unit 35 generates a signal for cyclically selecting a thread belonging to the secondary thread in response to the address selection signal AdSel [1]. The round robin selection unit 35 receives the control signal SC [2]. If the control signal SC [2] is in the asserted state, the round robin selecting unit 35 cyclically selects signals corresponding to the threads other than the thread 2.

  The AND circuit 36 receives the suppression signal output from the counter 33, the output signal from the high thread selection unit 30, and the control signal SC [1]. The AND circuit 36 sets the address selection signal AdSel [1] in a non-selected state during the period when the suppression signal is asserted or the period when the control signal SC [1] is asserted, and the suppression signal and the control signal SC [ 1] is negated, the output signal of the high thread selection unit 30 is the address selection signal AdSel [1].

  Next, the operation of the multithread processor 2 according to the third embodiment will be described. FIG. 21 shows a timing chart showing the operation of the multi-thread processor 2. In the example shown in FIG. 21, the number of threads to be processed is 3, thread 1 is a main thread, and threads 2 and 3 are secondary threads. The predetermined value of the counter 33 is 7, the switching threshold C1 is p (p is an integer), the switching threshold C2 is q (q is an integer), and the waiting setting values S1 and S2 are 1. In other words, the example shown in FIG. 21 shows a state in which the fetch of the thread 1 is suppressed when the thread 1 is terminated and the thread 2 has not finished the predetermined calculation at the time of termination.

  In the example shown in FIG. 21, thread 1 is activated in cycle 0. In cycle 0, the instruction code is not fetched from the instruction cache 22, and there is no instruction code held in the instruction buffers 231 to 233. In cycle 0, if the above equation (1) is calculated based on the fetch number NFI, the instruction holding number NHI, and the instruction issue number NII corresponding to the thread 1, the condition of the equation (1) is not satisfied. Therefore, in cycle 0, thread 1 is selected by the address selection signal AdSel.

  In cycle 1, the instruction cache 22 fetches two instruction codes belonging to the thread 1 based on the fact that the thread 1 is selected by the address selection signal AdSel in the cycle 0. That is, the fetch number NFI is 2/0/0. In cycle 1, the instruction code fetched by the instruction cache 22 is not stored in the instruction buffer. In cycle 1, when the above-described expression (1) is calculated based on the fetch number NFI, instruction holding number NHI, and instruction issue number NII corresponding to thread 1, the condition of expression (1) is not satisfied. Therefore, in cycle 1, thread 1 is selected by address selection signal AdSel. In cycle 1, since the address selection signal AdSel [1] is in the selected state, the count value CNT of the counter 33 increases by 1.

  In cycle 2, the instruction cache 22 fetches two instruction codes belonging to the thread 1 based on the fact that the thread 1 is selected by the address selection signal AdSel in cycle 1. That is, the fetch number NFI is 2/0/0. In cycle 2, the instruction code fetched by instruction cache 22 in cycle 1 is stored in instruction buffer 231 provided corresponding to thread 1. Therefore, the instruction holding number NHI is 2/0/0. Furthermore, in cycle 2, since one instruction code belonging to the thread 1 is issued from the instruction supply unit 10, the instruction issue number NII is 1/0/0. Here, the number of instructions issued by the instruction supply unit 10 is determined based on the type of arithmetic unit used by the instruction codes held in the instruction buffers 231 to 233, with the maximum value of the simultaneous issue number being 2. That is, when the first two instruction codes of the instruction buffer 231 use the same arithmetic unit, the simultaneous issue number is 1, and when different arithmetic units are used, the simultaneous issue number is two. In the cycle 2, when the above equation (1) is calculated based on the fetch number NFI, the instruction holding number NHI, and the instruction issue number NII corresponding to the thread 1, the condition of the equation (1) is not satisfied. Therefore, in cycle 2, thread 1 is selected by the address selection signal AdSel.

  From cycle 2 to cycle n, the multithread processor 2 according to the third embodiment proceeds by the same operation as the multithread processor 1a according to the second embodiment. When the processing reaches cycle n, the multithread processor 2 fetches two instruction codes belonging to the thread 1. That is, the number of fetches in cycle n is 2/0/0. In cycle n, the instruction holding number NHI becomes 2/0/0 by the processing up to cycle n-1. Further, in cycle n, since two instruction codes belonging to the thread 1 are issued from the instruction supply unit 10, the instruction issue count NII is 2/0/0. In the cycle n, when the above equation (1) is calculated based on the fetch number NFI, the instruction holding number NHI, and the instruction issue number NII corresponding to the thread 1, the condition of the equation (1) is not satisfied. Therefore, in cycle n, the thread 1 is selected by the address selection signal AdSel. In cycle n, since the address selection signal AdSel [1] is in the selected state, the count value CNT is increased by 1 to 2.

  In cycle n + 1, the instruction cache 22 fetches two instruction codes belonging to the thread 1 based on the fact that the thread 1 is selected by the address selection signal AdSel in the cycle n. That is, the fetch number NFI is 2/0/0. In cycle n + 1, the fetch number NFI of cycle n is 2/0/0, the instruction holding number NHI is 2/0/0, and the instruction issue number NII is 2/0/0. Therefore, the instruction holding number NHI of cycle n + 1 is 2/0/0. Further, in cycle n + 1, since the instruction supply unit 10 issues two instruction codes belonging to the thread 1, the instruction issue number NII is 2/0/0. In the cycle n + 1, if the above equation (1) is calculated based on the fetch number NFI, the instruction holding number NHI, and the instruction issue number NII corresponding to the thread 1, the condition of the equation (1) is not satisfied. Therefore, in cycle n + 1, thread 1 is selected by the address selection signal AdSel. In cycle n, since the address selection signal AdSel [1] is in the selected state, the count value CNT is increased by 1 to 2.

  In cycle n + 2, the instruction cache 22 fetches two instruction codes belonging to the thread 1 based on the fact that the thread 1 is selected by the address selection signal AdSel in the cycle n + 1. That is, the fetch number NFI is 2/0/0. In cycle n + 2, the fetch number NFI of cycle n + 1 is 2/0/0, the instruction holding number NHI is 2/0/0, and the instruction issue number NII is 2/0/0. Therefore, the instruction holding number NHI of cycle n + 2 is 2/0/0. Furthermore, in cycle n + 2, since the instruction supply unit 10 issues instruction codes belonging to the thread 1 one by one, the instruction issue count NII is 1/0/0.

  In the example shown in FIG. 21, it is assumed that the count value PC1 (for example, the first address value) of the program counter 201 reaches p in the cycle n + 2. Therefore, in the cycle n + 2, when the above equation (1) is calculated based on the fetch number NFI, the instruction holding number NHI, and the instruction issue number NII corresponding to the thread 1, the condition of the equation (1) is not satisfied, but in the cycle n + 2 The control signal SC [1] is asserted, and the state in which the thread 1 is selected by the address selection signal AdSel is suppressed. In the example shown in FIG. 21, the address selection signal AdSel [2] for selecting the second count value is 1 instead of the address selection signal AdSel [1]. That is, in cycle n + 2, thread 2 is selected. In cycle n + 2, the count value CNT of the counter 33 has not reached the specified value of 7, but the AND circuit 36 is in the state of the suppression signal of the counter 33 if the control signal SC [1] is asserted. First, the address selection signal AdSel [1] is set to a non-selected state. In cycle n + 2, since the address selection signal AdSel [1] is in a non-selected state, the count value CNT is reset.

  In cycle n + 3, the instruction cache 22 fetches two instruction codes belonging to the thread 2 based on the fact that the thread 2 is selected by the address selection signal AdSel in the cycle n + 2. That is, the fetch number NFI is 0/2/0. In cycle n + 3, the fetch number NFI of cycle n + 2 is 2/0/0, the instruction holding number NHI is 2/0/0, and the instruction issue number NII is 1/0/0. Therefore, the instruction holding number NHI of cycle n + 3 is 3/0/0. Further, in the cycle n + 3, two instruction codes belonging to the thread 1 are issued from the instruction supply unit 10, so that the instruction issue number NII is 2/0/0. Further, since the control signal SC [1] is in the asserted state in the cycle n + 3, the thread 3 is selected by the address selection signal AdSel in the cycle n + 3.

  In cycle n + 4, the instruction cache 22 fetches two instruction codes belonging to the thread 3 based on the fact that the thread 3 is selected by the address selection signal AdSel in the cycle n + 3. That is, the fetch number NFI is 0/0/2. In cycle n + 4, the fetch number NFI of cycle n + 3 is 0/2/0, the instruction holding number NHI is 3/0/0, and the instruction issue number NII is 2/0/0. Therefore, the instruction holding number NHI of cycle n + 4 is 1/2/0. Further, in cycle n + 4, the instruction supply unit 10 issues one instruction code belonging to the thread 1 and one instruction code belonging to the thread 2, so the instruction issue count NII is 1/1/0. In cycle n + 4, thread 2 is selected based on the fact that control signal SC [1] is asserted and that the selected thread in cycle n + 3 is thread 3.

  In cycle n + 5, the instruction cache 22 fetches two instruction codes belonging to the thread 2 based on the fact that the thread 2 is selected by the address selection signal AdSel in the cycle n + 4. That is, the fetch number NFI is 0/2/0. In cycle n + 5, the fetch number NFI of cycle n + 4 is 0/0/2, the instruction holding number NHI is 1/2/0, and the instruction issue number NII is 1/1/0. Therefore, the instruction holding number NHI in cycle n + 5 is 0/1/2. Further, in cycle n + 5, since the instruction code belonging to thread 2 and the instruction code belonging to thread 3 are issued one by one from the instruction supply unit 10, the number NII of issued instructions is 0/1/1.

  In the example shown in FIG. 21, the count value PC2 (for example, the second count value) reaches q by fetching the instruction code belonging to the thread 2 in the cycle n + 5. Therefore, in cycle n + 5, the thread switching notification signal CR2 is asserted during the period in which the thread switching notification signal CR1 is asserted. Therefore, in response to the thread cut notification signal CR2 being switched to the asserted state, the control signal SC [1] is switched to the negated state, and the control signal SC [2] is switched to the asserted state. For this reason, in cycle n + 5, it becomes possible to select the thread 1 by the address selection signal AdSel, and the above description is based on the fetch number NFI, the instruction holding number NHI, and the instruction issue number NII corresponding to the thread 1. When formula (1) is calculated, the condition of formula (1) is not satisfied. Accordingly, in cycle n + 5, thread 1 is selected by the address selection signal AdSel.

  Here, FIG. 22 shows a sequence diagram showing switching of threads selected during cycles n to n + 5 in FIG. As shown in FIG. 22, when the count value PC1 reaches p in cycle n + 1, the selection of the main thread is suppressed, and the thread for processing is selected from the secondary thread. In the present embodiment, the secondary thread is selected by the round robin method. Therefore, the thread 2 and the thread 3 are cyclically selected during the period of the cycles n + 2 to n + 3. Then, when the count value PC2 reaches q in the cycle n + 5, the control signal SC [1] is negated, so that the thread 1 is selected. By performing such processing, the multi-thread processor 2 can fetch the instruction code after the instruction code corresponding to the count value PC1 having the value p after the processing of the thread 2 is completed.

  From the above description, the multithread processor 2 according to the third exemplary embodiment includes the waiting control unit 25. The waiting control unit 25 generates a control signal SC that suppresses selection of a specific thread based on the count value of the program counter. As a result, the multithread processor 2 can suppress selection of some threads according to the progress of each thread.

  In a multi-thread processor, the main thread may advance processing on the condition that the secondary thread ends. In such a case, the main thread performs an infinite loop process to detect the end of the secondary thread. Conventionally, in order to perform this infinite loop processing, it has been necessary to fetch an instruction code for executing the infinite loop. This infinite loop processing hinders fetching of instruction codes belonging to the secondary thread.

  However, the multithread processor 2 according to the third embodiment can execute the waiting process on the condition that the secondary thread is terminated without fetching the instruction code related to the infinite loop in the main thread. That is, the multithread processor 2 according to the third embodiment can improve the instruction fetch capability for the thread that is the target of the waiting process.

  If the instruction code of the secondary thread is fetched based only on the number of instruction codes stored in the instruction buffer corresponding to the main thread, the instruction is stored in the instruction buffer corresponding to the main thread when the instruction code of the main thread ends. The code is not accumulated. Therefore, in such a case, there is a problem that the thread control unit cannot generate the address selection signal AdSel that selects the second count value corresponding to the secondary thread. However, in the multithread processor 2 according to the third embodiment, the end of the main thread is detected based on the count value of the program counter 201, and after the main thread ends, the selection of the main thread is suppressed and the secondary thread is executed. be able to.

  In the third embodiment, the example in which the thread 1 waits for the end of the thread 2 has been described. However, the waiting control unit 25 can set the count value that the thread 1 needs to wait for and the count value at which the processing of the threads 2 and 3 ends, and perform the waiting process. In this case, the thread 1 can restart the process on the condition that the two threads of the thread 2 and the thread 3 are terminated (or on the condition that one of the threads is terminated). That is, various changes can be made to the waiting method and the setting method of the waiting condition.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

AdSel Address selection signal NFI Fetch number NHI Instruction holding number NII Instruction issue number NMI Issue maximum number C1, C2 Switching threshold S1, S2 Wait setting value SC Control signal 1, 1a, 2 Multithread processor 10 Instruction supply unit 11 Instruction selector 12 Instruction Decoder 13 Instruction execution unit 21 Address selector 22 Instruction caches 24, 24a, 24b Thread control unit 25 Wait control unit 30 High thread selection unit 31, 35 Round robin selection unit 32 Low thread selection unit 33 Counters 34, 36, 61 AND circuit 511 512, 521 AND circuit 201-20m Program counter 231-23m Instruction buffer 231 Instruction buffer 232 Instruction buffer 401-402 Comparator 411-412 Control signal generator

Claims (10)

An instruction supply unit comprising: a first instruction buffer for storing a first instruction code belonging to the first thread; and a second instruction buffer for storing a second instruction code belonging to the second thread;
An instruction selector for selecting an instruction code to be transmitted to a subsequent circuit among instruction codes issued from the first and second instruction buffers;
An instruction decoder that decodes the instruction code selected by the instruction selector to generate execution instruction information;
An instruction execution unit that performs information processing based on the execution instruction information,
The command supply unit
The first instruction code is preferentially stored in the first instruction buffer, and the number of the first instruction codes stored in the first instruction buffer can be issued in parallel by the instruction supply unit A multi-thread processor having a thread control unit for storing the second instruction code in the second instruction buffer when the maximum value of the number of instruction codes becomes twice or more. The command supply unit
A first program counter provided in accordance with the first thread and increasing a first count value in accordance with the progress of the first thread;
A second program counter provided in accordance with the second thread and increasing a second count value in accordance with the progress of the second thread;
An address selector that selects and outputs one of the first count value and the second count value in response to an address selection signal;
The first and second instruction codes are read from an external memory and stored, the first instruction code is output to the first instruction buffer according to the first count value, and the second count value is output. An instruction cache that outputs the second instruction code to the second instruction buffer in response to
A thread control unit that switches which of the first count value and the second count value is instructed by the address selection signal according to the number of instruction codes stored in the first instruction buffer;
The multi-thread processor according to claim 1.   The thread control unit receives the address selection signal during a period in which the number of instruction codes stored in the first instruction buffer is less than twice the maximum number of instructions that the instruction supply unit can issue in parallel. The multithread processor according to claim 2, further comprising a high thread selection unit configured to select the first count value.   The thread control unit includes a low thread selection unit that sets the address selection signal in a state of selecting the second count value when the address selection signal sets the first count value to a non-selected state. The multi-thread processor according to 2 or 3.   The thread control unit counts the number of operation cycles in which the address selection signal indicates a state in which the first count value is selected. The multi-thread processor according to claim 4, further comprising a low-thread forcible processing unit that selects a count value of 2.   When the control signal for suppressing the address selection signal from selecting a predetermined address value is output to the thread control unit, and the first count value reaches a preset first switching threshold value The control signal is set to a thread suppression state for preventing the address selection signal from selecting a thread corresponding to the first count value, and then the second count value is set to a second value set in advance. 6. The multi-thread processor according to claim 3, further comprising a waiting unit that releases the thread suppression state of the control signal when the switching threshold is reached.   The first thread is a main thread, the second thread is a sub thread, and the sub thread performs an operation using a calculation result by the main thread. The multithread processor according to item.   The multi-thread processor according to any one of claims 1 to 7, wherein the second instruction buffer is set to have a storage capacity smaller than that of the first instruction buffer.   The first instruction buffer stores a plurality of first instruction codes in parallel, the second instruction buffer stores a plurality of second instruction codes in parallel, and the instruction execution unit includes a plurality of instruction execution units. The multi-thread processor according to claim 1, wherein a plurality of pieces of execution instruction information decoded from the instruction code are processed in parallel. A multi-thread processor that executes, in a time division manner, a first instruction code belonging to a first thread and a second instruction code belonging to a second thread,
A first instruction buffer for storing a first instruction code belonging to the first thread;
A second instruction buffer for storing a second instruction code belonging to the second thread;
The first instruction code is preferentially stored in the first instruction buffer, and the number of the first instruction codes stored in the first instruction buffer can be issued in parallel by the first buffer. A thread control unit that stores the second instruction code in the second instruction buffer when the number of instructions is more than twice the maximum value of the number of instructions,
A multi-thread processor.

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