JP2012054317A - Substrate provided with piezoelectric thin film and manufacturing method thereof - Google Patents

Substrate provided with piezoelectric thin film and manufacturing method thereof Download PDF

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JP2012054317A
JP2012054317A JP2010194132A JP2010194132A JP2012054317A JP 2012054317 A JP2012054317 A JP 2012054317A JP 2010194132 A JP2010194132 A JP 2010194132A JP 2010194132 A JP2010194132 A JP 2010194132A JP 2012054317 A JP2012054317 A JP 2012054317A
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thin film
piezoelectric thin
substrate
lower electrode
electrode layer
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Kazutoshi Watanabe
和俊 渡辺
Kenji Shibata
憲治 柴田
Kazufumi Suenaga
和史 末永
Akira Nomoto
明 野本
Fumimasa Horikiri
文正 堀切
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Hitachi Cable Ltd
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Abstract

PROBLEM TO BE SOLVED: To provide a substrate provided with a piezoelectric thin film capable of performing non-destructive characteristic evaluation of the piezoelectric thin film, and provide a manufacturing method of the substrate.SOLUTION: In a substrate provided with a piezoelectric thin film, a lower electrode layer 6 is formed on a substrate 5, and a piezoelectric thin film 2 having a perovskite structure is formed on the lower electrode layer 6. A lower electrode exposure part 3 in which a portion of the lower electrode layer 6 is exposed from the piezoelectric thin film 2 is provided on the lower electrode layer 6 without removing the piezoelectric thin film 2 because the piezoelectric thin film 2 formed on the lower electrode layer 6 is formed on a area narrower than that of the lower electrode layer 6.

Description

本発明は、ペロブスカイト構造の圧電薄膜が付いた圧電薄膜付き基板及びその製造方法に関するものである。   The present invention relates to a substrate with a piezoelectric thin film provided with a piezoelectric thin film having a perovskite structure and a method for manufacturing the same.

圧電体は種々の目的に応じて様々な圧電素子に加工され、特に圧電素子に電圧を加えて変形を生じさせるアクチュエータや、逆に圧電素子の変形により発生する電圧を検知するセンサなどの機能性電子部品として広く利用されている。アクチュエータやセンサの用途に利用されている圧電体としては、優れた圧電特性を有する鉛系材料の誘電体、特に組成式:Pb(Zr1−xTi)Oで表されるPZT系のペロブスカイト型強誘電体がこれまで広く用いられており、通常個々の元素からなる酸化物を焼結することにより形成されている。現在、各種電子部品の小型化、高性能化が進むにつれ、圧電素子においても小型化、高性能化が強く求められるようになった。 Piezoelectric materials are processed into various piezoelectric elements according to various purposes, and in particular, functionality such as an actuator that applies a voltage to the piezoelectric element to cause deformation, and conversely, a sensor that detects a voltage generated by the deformation of the piezoelectric element. Widely used as electronic components. As a piezoelectric material used for actuators and sensors, a lead-based material dielectric material having excellent piezoelectric characteristics, particularly a PZT-based material represented by a composition formula: Pb (Zr 1-x Ti x ) O 3 is used. Perovskite ferroelectrics have been widely used so far, and are usually formed by sintering oxides composed of individual elements. At present, as various electronic components have been reduced in size and performance, there has been a strong demand for miniaturization and high performance in piezoelectric elements.

しかしながら、従来からの製法である焼結法を中心とした製造方法により作製した圧電材料は、その厚さを薄くするにつれ、特に厚さが10μm程度の厚さに近づくにつれて、材料を構成する結晶粒の大きさに近づき、その影響が無視できなくなる。そのため、特性のばらつきや劣化が顕著になるといった問題が発生し、それを回避するために、焼結法に変わる薄膜技術等を応用した圧電薄膜の形成法が近年研究されるようになってきた。最近、シリコン基板上にスパッタリング法で形成したPZT薄膜が、高速高精細のインクジェットプリンタヘッド用アクチュエータの圧電薄膜として実用化されている。   However, a piezoelectric material manufactured by a manufacturing method centering on a sintering method, which is a conventional manufacturing method, is a crystal that forms the material as the thickness decreases, particularly as the thickness approaches 10 μm. Approaching the size of the grain, the effect can not be ignored. For this reason, problems such as significant variations in characteristics and deterioration occur, and in order to avoid such problems, methods for forming piezoelectric thin films that apply thin film technology instead of sintering methods have recently been studied. . Recently, a PZT thin film formed on a silicon substrate by a sputtering method has been put into practical use as a piezoelectric thin film for an actuator for a high-speed, high-definition inkjet printer head.

PZTから成る圧電薄膜は、鉛を60〜70重量%程度含有しているので、生態学的見地および公害防止の面から好ましくない。そこで、環境への配慮から鉛を含有しない圧電薄膜の開発が望まれている。現在、様々な非鉛圧電材料が研究されているが、その中に、組成式:(K1−xNa)NbO(0<x<1)で表されるニオブ酸カリウムナトリウム(以降、「KNN」とも記す)がある(例えば、特許文献1、特許文献2参照)。KNN薄膜も、スパッタリング法、PLD法等の成膜方法で、MgO基板、SrTiO基板、Si基板等の基板上への成膜が試されている。このKNNは、ペロブスカイト構造を有する材料であり、非鉛の材料としては比較的良好な圧電特性を示すため、非鉛圧電材料の有力な候補として期待されている。 A piezoelectric thin film made of PZT contains about 60 to 70% by weight of lead, which is not preferable from the viewpoint of ecological viewpoint and pollution prevention. Therefore, development of a piezoelectric thin film that does not contain lead is desired in consideration of the environment. Currently, various lead-free piezoelectric materials have been studied. Among them, potassium sodium niobate represented by the composition formula: (K 1-x Na x ) NbO 3 (0 <x <1) (Also referred to as “KNN”) (see, for example, Patent Document 1 and Patent Document 2). The KNN thin film has also been attempted to be deposited on a substrate such as an MgO substrate, a SrTiO 3 substrate, or a Si substrate by a deposition method such as sputtering or PLD. This KNN is a material having a perovskite structure and exhibits relatively good piezoelectric characteristics as a non-lead material, and thus is expected as a promising candidate for a non-lead piezoelectric material.

ところで、薄膜技術によって圧電薄膜を成膜した場合、装置構造や成膜条件、装置や原料の経時的な変化によって、同一基板の面内や成膜の各ロット間、多数枚同時成膜の場合はロット内の基板間で、膜の特性にばらつきが出ることがある。特に基板径が大きくなると基板の中心から径方向への特性分布が大きくなる可能性がある。このような同一基板の面内に特性分布があると、素子化したときの基板1枚からの素子取得率が低下し、コストの面で大きな問題になる。同様に基板間に特性分布がある場合も、歩留りの低下を招き、問題となる。そこで、圧電薄膜の特性評価が重要になる。   By the way, when a piezoelectric thin film is formed by thin film technology, a large number of sheets can be formed simultaneously on the same substrate or between lots of film formation due to changes in equipment structure, film formation conditions, equipment and raw materials over time. In some cases, the film characteristics may vary among substrates in a lot. In particular, when the substrate diameter is increased, the characteristic distribution in the radial direction from the center of the substrate may be increased. If there is such a characteristic distribution in the plane of the same substrate, the element acquisition rate from one substrate when it is made into an element is lowered, which becomes a big problem in terms of cost. Similarly, when there is a characteristic distribution between the substrates, the yield is lowered, which causes a problem. Therefore, it is important to evaluate the characteristics of the piezoelectric thin film.

圧電薄膜の特性評価は、圧電薄膜の上下に電極を付け、その電極間に電圧を印加し、絶縁特性や誘電率特性、圧電特性を測定する。しかしながら、従来の圧電薄膜付きの基板は、下部電極が圧電薄膜に覆われているため、そのまま評価することは困難である。したがって、評価に必要な領域を基板から切り出して簡易的な素子を作製して測定したり(特許文献2)、圧電薄膜成膜後にフォトリソグラフィーやエッチング処理を用いて圧電薄膜の一部分を除去し、下部電極が露出するような構造を作製して測定したりしていた。   In the characteristic evaluation of the piezoelectric thin film, electrodes are attached to the top and bottom of the piezoelectric thin film, a voltage is applied between the electrodes, and the insulation characteristic, dielectric constant characteristic, and piezoelectric characteristic are measured. However, it is difficult to evaluate a conventional substrate with a piezoelectric thin film as it is because the lower electrode is covered with the piezoelectric thin film. Therefore, a region required for evaluation is cut out from the substrate and a simple element is manufactured and measured (Patent Document 2), or a part of the piezoelectric thin film is removed using photolithography or etching after the piezoelectric thin film is formed, A structure in which the lower electrode is exposed is fabricated and measured.

特開2007−184513号公報JP 2007-184513 A 特開2008−159807号公報(段落0038、図6参照)JP 2008-159807 A (see paragraph 0038, FIG. 6)

しかしながら、上述した従来の圧電薄膜評価のための作業は、工程が長く、またそれぞれに熟練やノウハウが必要であるため、基板径が大きくなり測定点が増えると、作業量が多くなり大きな負担となる。また、従来技術の評価方法は、破壊検査となるので、評価した圧電体薄膜付き基板は、そのまま製品として売ることが出来なくなってしまう。非破壊で作業量の少ない簡易的な評価方法を必要とするのは、PZT薄膜のみならずKNN薄膜にも共通する。   However, the above-described conventional work for piezoelectric thin film evaluation requires a long process, and requires skill and know-how for each. Therefore, if the substrate diameter increases and the number of measurement points increases, the amount of work increases and the burden is large. Become. Moreover, since the evaluation method of the prior art is a destructive inspection, the evaluated substrate with a piezoelectric thin film cannot be sold as a product as it is. The need for a simple evaluation method that is non-destructive and requires a small amount of work is common to not only PZT thin films but also KNN thin films.

本発明の目的は、非破壊で圧電薄膜の特性評価を可能にする圧電薄膜付き基板及びその製造方法を提供することにある。   An object of the present invention is to provide a substrate with a piezoelectric thin film that enables non-destructive characteristics evaluation of the piezoelectric thin film and a method for manufacturing the same.

本発明の一実施の態様によれば、基板上に下部電極層が形成され、前記下部電極層上にペロブスカイト構造の圧電薄膜が形成された圧電薄膜付き基板において、前記下部電極層上に形成される前記圧電薄膜が前記下部電極層よりも狭い面積で形成され、前記下部電極層上に下部電極露出部が設けられる圧電薄膜付き基板が提供される。   According to an embodiment of the present invention, in a substrate with a piezoelectric thin film in which a lower electrode layer is formed on a substrate and a piezoelectric thin film having a perovskite structure is formed on the lower electrode layer, the substrate is formed on the lower electrode layer. There is provided a substrate with a piezoelectric thin film in which the piezoelectric thin film is formed with a smaller area than the lower electrode layer, and a lower electrode exposed portion is provided on the lower electrode layer.

この場合、前記下部電極層の外周部が露出するよう前記下部電極露出部が設けられるのが好ましい。さらに、前記外周部に形成される前記下部電極露出部の幅が、前記基板の外径Dに対して、0.005×D以上0.05×D以下であることが好ましい。また、前記ペロブスカイト構造の圧電薄膜が、一般式(K1−xNa)NbO(0<x<1)で表されるニオブ酸カリウムナトリウムであることが好ましい。 In this case, it is preferable that the lower electrode exposed portion is provided so that the outer peripheral portion of the lower electrode layer is exposed. Furthermore, it is preferable that the width | variety of the said lower electrode exposure part formed in the said outer peripheral part is 0.005 * D or more and 0.05 * D or less with respect to the outer diameter D of the said board | substrate. The piezoelectric thin film having a perovskite structure is preferably potassium sodium niobate represented by the general formula (K 1-x Na x ) NbO 3 (0 <x <1).

また、本発明の他の態様によれば、上述した圧電薄膜付き基板の製造方法であって、前記圧電薄膜上に幅が0.5mm以上5.0mm以下の上部電極を形成し、下部電極露出部と前記上部電極との間に電圧を印加することで、前記圧電薄膜の特性を検査する工程を含む圧電薄膜付き基板の製造方法が提供される。   According to another aspect of the present invention, there is provided a method for manufacturing a substrate with a piezoelectric thin film as described above, wherein an upper electrode having a width of 0.5 mm or more and 5.0 mm or less is formed on the piezoelectric thin film, and the lower electrode is exposed. A method for manufacturing a substrate with a piezoelectric thin film is provided, which includes a step of inspecting characteristics of the piezoelectric thin film by applying a voltage between a portion and the upper electrode.

この場合、前記上部電極は、前記圧電薄膜の中央部に形成される第1上部電極と、前記第1上部電極から等間隔の距離に形成される複数の第2上部電極とからなることが好ましい。   In this case, it is preferable that the upper electrode includes a first upper electrode formed at a central portion of the piezoelectric thin film and a plurality of second upper electrodes formed at equal intervals from the first upper electrode. .

また、本発明の別な態様によれば、前記下部電極層上の一部を遮蔽治具により覆い、前記遮蔽治具に覆われていない前記下部電極層の他部にペロブスカイト構造の圧電薄膜を形成することで、前記下部電極層の一部に圧電薄膜が形成されない下部電極露出部を形成し、前記圧電薄膜の形成後、前記遮蔽治具を除去することで、前記下部電極層の一部に形成されている下部電極露出部を露出させる圧電薄膜付き基板の製造方法が提供される。   According to another aspect of the present invention, a part of the lower electrode layer is covered with a shielding jig, and a perovskite structure piezoelectric thin film is formed on the other part of the lower electrode layer not covered with the shielding jig. Forming a lower electrode exposed portion where a piezoelectric thin film is not formed on a part of the lower electrode layer, and removing the shielding jig after forming the piezoelectric thin film, thereby forming a part of the lower electrode layer; A method for manufacturing a substrate with a piezoelectric thin film that exposes the exposed portion of the lower electrode formed on the substrate is provided.

この場合、前記外周部に形成される前記下部電極露出部の幅が、前記基板の外径Dに対して、0.005×D以上0.05×D以下であることが好ましい。また、前記圧電薄膜の形成温度の範囲における前記遮蔽治具の線膨張係数αと前記基板の線膨張係数αが、1≦α/α≦4であることが好ましい。さらに、前記ペロブスカイト構造の圧電薄膜が、一般式(K1−xNa)NbO(0<x<1)で表されるニオブ酸カリウムナトリウムであるのがよい。 In this case, it is preferable that the width of the exposed portion of the lower electrode formed on the outer peripheral portion is 0.005 × D or more and 0.05 × D or less with respect to the outer diameter D of the substrate. Moreover, it is preferable that the linear expansion coefficient α w of the shielding jig and the linear expansion coefficient α b of the substrate in the range of the formation temperature of the piezoelectric thin film are 1 ≦ α w / α b ≦ 4. Furthermore, the piezoelectric thin film having the perovskite structure may be potassium sodium niobate represented by the general formula (K 1-x Na x ) NbO 3 (0 <x <1).

本発明によれば、非破壊で圧電薄膜の特性評価を行うことができる。   According to the present invention, characteristics of a piezoelectric thin film can be evaluated nondestructively.

本発明の一実施の形態に係る圧電体薄膜付き基板の説明図であって、(a)は平面図、(b)はA−A断面図である。It is explanatory drawing of the board | substrate with a piezoelectric thin film which concerns on one embodiment of this invention, Comprising: (a) is a top view, (b) is AA sectional drawing. 本発明の一実施の形態に係る圧電体薄膜付き基板の製造工程の概略を示す工程フロー図である。It is a process flowchart which shows the outline of the manufacturing process of the board | substrate with a piezoelectric thin film which concerns on one embodiment of this invention. 本発明の実施例1〜6で作製した圧電体薄膜付き基板の平面図である。It is a top view of the board | substrate with a piezoelectric material thin film produced in Examples 1-6 of this invention. 比較例4を適用したときの下部電極露出部幅に対する基板表面の有効利用率を示した図である。It is the figure which showed the effective utilization factor of the board | substrate surface with respect to the width | variety exposed part of a lower electrode when the comparative example 4 is applied. 比較例5を適用したときの上部電極幅に対する基板表面の有効利用率を示した図である。It is the figure which showed the effective utilization factor of the substrate surface with respect to the upper electrode width when the comparative example 5 is applied. 本発明の実施例の成膜方式の説明図であって、(a)は実施例1〜6のフェイスダウン方式の説明図、(b)は実施例7によるフェイスアップ方式の説明図である。It is explanatory drawing of the film-forming system of the Example of this invention, Comprising: (a) is explanatory drawing of the face-down system of Examples 1-6, (b) is explanatory drawing of the face-up system by Example 7. FIG. 本発明の実施例8で作製した圧電体薄膜付き基板の平面図である。It is a top view of the board | substrate with a piezoelectric thin film produced in Example 8 of this invention.

以下に本発明の一実施の形態について述べる。   An embodiment of the present invention will be described below.

[実施の形態]
本実施の形態の圧電薄膜付き基板は、基板上に下部電極層が形成され、前記下部電極層の上にペロブスカイト構造の圧電薄膜が形成されている。前記下部電極層の上に形成される前記圧電薄膜が前記下部電極層よりも狭い面積で形成されることにより、前記下部電極層の上に前記圧電薄膜が形成されていない下部電極露出部が設けられている。
[Embodiment]
In the substrate with a piezoelectric thin film of the present embodiment, a lower electrode layer is formed on the substrate, and a piezoelectric thin film having a perovskite structure is formed on the lower electrode layer. The piezoelectric thin film formed on the lower electrode layer is formed with a smaller area than the lower electrode layer, thereby providing a lower electrode exposed portion on which the piezoelectric thin film is not formed on the lower electrode layer. It has been.

ペロブスカイト構造の圧電薄膜は、各種電子部品の小型化、高性能化の要請に応えるために、その膜厚が0.3μm以上10μm以下であるのがよい。ペロブスカイト構造の圧電薄膜は、PZT系のペロブスカイト型強誘電体薄膜であっても良いが、KNN系のペロブスカイト型強誘電体薄膜であると、鉛フリーの見地からより好ましい。特に、ペロブスカイト構造の圧電薄膜がKNNから構成されていると、鉛を含有しない大口径(例えば4インチサイズ以上)の圧電薄膜付き基板を得ることが可能である。   The piezoelectric thin film having a perovskite structure preferably has a film thickness of 0.3 μm or more and 10 μm or less in order to meet the demand for miniaturization and high performance of various electronic components. The perovskite-structured piezoelectric thin film may be a PZT-based perovskite ferroelectric thin film, but a KNN-based perovskite-type ferroelectric thin film is more preferable from a lead-free viewpoint. In particular, when the piezoelectric thin film having a perovskite structure is made of KNN, it is possible to obtain a substrate with a piezoelectric thin film having a large diameter (for example, 4 inches or more) that does not contain lead.

上述した実施の形態によれば、圧電薄膜付き基板には、その後加工処理等することなく、圧電薄膜が形成されていない下部電極露出部が既に設けられているので、圧電薄膜評価のために圧電薄膜付き基板からさらに必要な領域を切り出して素子を簡易的に作製したり、圧電薄膜の一部分を除去して露出させたりすることなく、圧電薄膜付き基板の形状のままで、圧電薄膜付き基板の特性を確実に非破壊で評価することが可能となる。また、非破壊検査となるので、評価した圧電体薄膜付き基板は、そのまま製品として売ることも可能となる。   According to the above-described embodiment, the substrate with the piezoelectric thin film is already provided with the lower electrode exposed portion on which the piezoelectric thin film is not formed without performing a processing process or the like. Without cutting out the necessary area from the substrate with a thin film and simply manufacturing the element, or removing a portion of the piezoelectric thin film and exposing it, the shape of the substrate with the piezoelectric thin film remains unchanged. The characteristics can be reliably evaluated non-destructively. Further, since the non-destructive inspection is performed, the evaluated substrate with the piezoelectric thin film can be sold as a product as it is.

なお、下部電極露出部は、実施の形態によっては、下部電極層の外周部に露出するように設けられることもある。下部電極層の外周部に設けられる場合、その外周部は下部電極層の外周全域であることも、外周の一部の領域であることもある。下部電極露出部が、下部電極層の外周部が露出するよう設けられていると、圧電薄膜付き基板の特性をより確実に非破壊で評価することが可能となる。また、圧電薄膜付き基板の有効使用率の低下を抑えられ、素子取得面積が減少するのを防止できる。   Depending on the embodiment, the lower electrode exposed portion may be provided so as to be exposed at the outer peripheral portion of the lower electrode layer. When provided on the outer peripheral portion of the lower electrode layer, the outer peripheral portion may be the entire outer periphery of the lower electrode layer or may be a partial region of the outer periphery. If the lower electrode exposed portion is provided so that the outer peripheral portion of the lower electrode layer is exposed, it becomes possible to more reliably and non-destructively evaluate the characteristics of the substrate with the piezoelectric thin film. In addition, it is possible to suppress a decrease in the effective usage rate of the substrate with the piezoelectric thin film and to prevent the element acquisition area from decreasing.

また、外周部に形成される前記下部電極露出部の幅は、前記基板の外径Dに対して、0
.005×D以上0.05×D以下であることが好ましい。ここで下部電極露出部の幅とは、下部電極露出部の輪郭幅を意味する。下部電極露出部の幅が0.005×D以上あると、より確実に非破壊で評価することが可能となる。また、0.05×D以下であると、圧電薄膜付き基板の有効使用率の低下を抑えられ、素子取得面積がより減少するのを防止できる。
The width of the exposed portion of the lower electrode formed on the outer peripheral portion is 0 with respect to the outer diameter D of the substrate.
. It is preferable that it is 005 × D or more and 0.05 × D or less. Here, the width of the lower electrode exposed portion means the contour width of the lower electrode exposed portion. When the width of the exposed portion of the lower electrode is 0.005 × D or more, it becomes possible to more reliably perform nondestructive evaluation. Moreover, the fall of the effective usage rate of a board | substrate with a piezoelectric thin film can be suppressed as it is 0.05xD or less, and it can prevent that an element acquisition area reduces more.

[実施の形態の具体例]
次に、下部電極露出部が、下部電極層の外周部全域に露出するように設けられている実施の形態の具体例について図面を用いて説明する。
[Specific example of embodiment]
Next, a specific example of the embodiment in which the lower electrode exposed portion is provided so as to be exposed in the entire outer peripheral portion of the lower electrode layer will be described with reference to the drawings.

図1は、本発明の実施の形態に係る圧電体薄膜付き基板の説明図であって、図1(a)は平面図、図1(b)は断面図である。   1A and 1B are explanatory views of a substrate with a piezoelectric thin film according to an embodiment of the present invention, in which FIG. 1A is a plan view and FIG. 1B is a cross-sectional view.

本実施の形態に係る圧電体薄膜付き基板1は、基板5と、基板5の第一面側の略全面に形成された下部電極層6と、下部電極層6の基板1側とは反対の第一面側に形成された圧電薄膜2と、圧電薄膜2の下部電極層6と反対の第一面側に部分的に形成された上部電極4とから構成される。   The substrate 1 with a piezoelectric thin film according to the present embodiment includes a substrate 5, a lower electrode layer 6 formed on substantially the entire first surface side of the substrate 5, and the opposite side of the lower electrode layer 6 from the substrate 1 side. The piezoelectric thin film 2 is formed on the first surface side, and the upper electrode 4 is partially formed on the first surface side opposite to the lower electrode layer 6 of the piezoelectric thin film 2.

上記基板は、例えば熱酸化膜付き(001)面Si基板を用いる。下部電極には例えばPtを用い、下部電極層6と圧電薄膜2との間に介挿される密着層には例えばTiを用いる。上記下部電極層6の第一面側に、圧電薄膜2が形成されていない下部電極層6の外周部全域が露出する下部電極露出部3が設けられている。圧電薄膜2は、下部電極層6の外周部全域に露出される下部電極露出部3の最小幅Wが、基板の外径Dmmに対して、0.005×Dmm以上0.05×Dmm以下の範囲に入るように、該範囲を残して下部電極層6の第一面側に成膜されている。ここで下部電極露出部3の最小幅の最小とは、下部電極露出部の幅は出来るだけ小さい方が有利となることから付けた名前であり、対応する最大幅があるわけではない。   As the substrate, for example, a (001) plane Si substrate with a thermal oxide film is used. For example, Pt is used for the lower electrode, and Ti is used for the adhesion layer interposed between the lower electrode layer 6 and the piezoelectric thin film 2, for example. On the first surface side of the lower electrode layer 6, there is provided a lower electrode exposed portion 3 where the entire outer peripheral portion of the lower electrode layer 6 where the piezoelectric thin film 2 is not formed is exposed. In the piezoelectric thin film 2, the minimum width W of the lower electrode exposed portion 3 exposed in the entire outer peripheral portion of the lower electrode layer 6 is 0.005 × Dmm or more and 0.05 × Dmm or less with respect to the outer diameter Dmm of the substrate. The film is formed on the first surface side of the lower electrode layer 6 so as to enter the range, leaving the range. Here, the minimum of the minimum width of the lower electrode exposed portion 3 is a name given because it is advantageous that the width of the lower electrode exposed portion is as small as possible, and does not have a corresponding maximum width.

この下部電極露出部3は、その後の素子化の際の素子取得面積を考えた場合、出来るだけ小さい方が有利となる。幅Wの上限0.05×Dmm以下とすると、基板全面積に対して、素子が取得できない下部電極露出部3の面積は10%以下となり、この値は許容される範囲となる。   The lower electrode exposed portion 3 is advantageously as small as possible in view of the element acquisition area in the subsequent element formation. If the upper limit of the width W is 0.05 × Dmm or less, the area of the lower electrode exposed portion 3 where the element cannot be obtained is 10% or less with respect to the total area of the substrate, and this value is within an allowable range.

また、圧電体薄膜付き基板1は、絶縁特性や誘電率特性、圧電特性などを測定したい圧電薄膜2の第一面の任意の点に、所定の幅の上部電極4を1箇所以上形成した構造となっている。上部電極の最小幅は0.1mm以上5.0mm以下であることが好ましい。ここで上部電極4の幅とは、上部電極4の輪郭幅を意味する。また、上部電極4の最小幅も下部電極露出部の最小幅と同じ意味であり、上部電極の幅は出来るだけ小さい方が有利となることから付けた名前であり、対応する最大幅があるわけではない。上部電極4の最小幅は、例えば、上部電極4の形状が正方形であれば一辺の長さを、円形であれば直径を意味する。この最小幅の範囲は、その後の素子化の際の素子取得面積を考えた場合、出来るだけ小さい方が有利となる。しかし、電極に電圧を印加する際に、先端の尖った端子などを接触させる必要があるので、上部電極があまりに小さい最小幅を持つと、専用の極細端子や高倍率の顕微鏡など特別な設備が必要となる。更に上部電極4は、圧電特性を測定する際に、上部からレーザー光を当て、その反射を測定することで、膜の変位(変形)を測定する場合がある。   The substrate 1 with a piezoelectric thin film has a structure in which one or more upper electrodes 4 having a predetermined width are formed at arbitrary points on the first surface of the piezoelectric thin film 2 for which insulation characteristics, dielectric constant characteristics, piezoelectric characteristics and the like are to be measured. It has become. The minimum width of the upper electrode is preferably from 0.1 mm to 5.0 mm. Here, the width of the upper electrode 4 means the contour width of the upper electrode 4. Also, the minimum width of the upper electrode 4 has the same meaning as the minimum width of the exposed portion of the lower electrode, and the upper electrode 4 is named because it is advantageous to make the width as small as possible, and there is a corresponding maximum width. is not. The minimum width of the upper electrode 4 means, for example, the length of one side if the shape of the upper electrode 4 is square, and the diameter if the shape is circular. It is advantageous that the minimum width range is as small as possible in view of the element acquisition area in the subsequent elementization. However, when applying a voltage to the electrode, it is necessary to contact a terminal with a sharp tip, etc.If the upper electrode has a minimum width that is too small, special equipment such as a dedicated extra-fine terminal or a high-power microscope is required. Necessary. Furthermore, the upper electrode 4 sometimes measures the displacement (deformation) of the film by irradiating laser light from the upper part and measuring the reflection when measuring the piezoelectric characteristics.

このように上部電極4は、電圧を印加する領域のほかに、レーザー光を当てる領域も必要となるため、上部電極最小幅が上述した0.5mm以上5.0mm以下の範囲が両者を満足する範囲となる。そして、ここで使用されるレーザー光は、波長700nm程度の赤
色レーザーが使われることが多いため、用いる電極材料としては、波長700nmでの反射率が60%以上の材料であるAg、Al、Au、Cu、Ni、Pt、Rh、または、それらを含む多層膜、または、それらを含む合金を用いる。
Thus, the upper electrode 4 requires a region to which the laser beam is applied in addition to the region to which the voltage is applied. Therefore, the above-described range in which the minimum width of the upper electrode is 0.5 mm to 5.0 mm satisfies both. It becomes a range. Since the laser beam used here is often a red laser having a wavelength of about 700 nm, the electrode material used is Ag, Al, Au, which is a material having a reflectance of 60% or more at a wavelength of 700 nm. Cu, Ni, Pt, Rh, or a multilayer film containing them, or an alloy containing them.

[圧電薄膜付き基板の製造方法]
次に、本実施の形態に係る圧電体薄膜付き基板の製造方法を説明する。
[Method of manufacturing substrate with piezoelectric thin film]
Next, a method for manufacturing a substrate with a piezoelectric thin film according to the present embodiment will be described.

圧電薄膜付き基板の製造方法は、基板の第一面側に下部電極層を形成し、前記下部電極層の第一面側の一部を遮蔽治具により覆う。前記遮蔽治具に覆われていない前記下部電極層の他部にペロブスカイト構造の圧電薄膜を形成するとともに、該圧電薄膜の形成中、前記下部電極層の一部に圧電薄膜が形成されない下部電極露出部を形成する。前記圧電薄膜の形成後、前記遮蔽治具を除去することで、前記下部電極層の一部に形成されている下部電極露出部を露出させる。   In the method for manufacturing a substrate with a piezoelectric thin film, a lower electrode layer is formed on the first surface side of the substrate, and a part of the lower electrode layer on the first surface side is covered with a shielding jig. A piezoelectric thin film having a perovskite structure is formed on the other part of the lower electrode layer that is not covered by the shielding jig, and the lower electrode is exposed while the piezoelectric thin film is not formed on a part of the lower electrode layer during the formation of the piezoelectric thin film. Forming part. After the formation of the piezoelectric thin film, the shielding jig is removed to expose a lower electrode exposed portion formed in a part of the lower electrode layer.

下部電極層は、例えばスパッタリングまたは蒸着により形成される。下部電極露出部を形成するには、圧電薄膜を形成する際に、下部電極層の外周部全域または一部の領域を遮蔽治具によって保護し、圧電薄膜が成膜されない下部電極層の面を形成する工程を含むようにする。これにより、絶縁特性や誘電率特性、圧電特性を測るときに必要な下部電極露出部を、圧電薄膜の成膜後に圧電薄膜を除去することなく形成することができる。   The lower electrode layer is formed by sputtering or vapor deposition, for example. To form the exposed portion of the lower electrode, when forming the piezoelectric thin film, the entire outer peripheral portion or a part of the lower electrode layer is protected by a shielding jig, and the surface of the lower electrode layer on which the piezoelectric thin film is not formed is protected. A step of forming is included. As a result, it is possible to form the exposed portion of the lower electrode necessary for measuring the insulation characteristic, dielectric constant characteristic, and piezoelectric characteristic without removing the piezoelectric thin film after forming the piezoelectric thin film.

これによれば、圧電薄膜の形成中に、遮蔽治具を用いて下部電極層の一部を遮蔽することにより、特性評価に必要な下部電極露出部を形成するようにしたので、圧電薄膜形成後に下部電極を露出させる工程がなくなる。したがって、圧電薄膜付き基板を非破壊で簡易的な工程で特性を評価できる。評価した圧電膜付き基板が良品であればこれを売ることができる。   According to this, since a part of the lower electrode layer is shielded by using a shielding jig during formation of the piezoelectric thin film, the exposed portion of the lower electrode necessary for characteristic evaluation is formed. The process of exposing the lower electrode later is eliminated. Therefore, the characteristics of the substrate with the piezoelectric thin film can be evaluated by a non-destructive and simple process. If the evaluated substrate with a piezoelectric film is a non-defective product, it can be sold.

次に、前記下部電極層の一部が前記下部電極層の外周部全域である場合の圧電薄膜付き基板の製造方法を図面を用いて具体的に説明する。   Next, a method for manufacturing a substrate with a piezoelectric thin film in the case where a part of the lower electrode layer is the entire outer peripheral portion of the lower electrode layer will be specifically described with reference to the drawings.

図2は、本実施の形態に係る圧電体薄膜付き基板の製造工程の概略を示す工程フロー図である。   FIG. 2 is a process flow diagram showing an outline of the manufacturing process of the substrate with the piezoelectric thin film according to the present embodiment.

熱酸化膜付(001)面Si基板に、蒸着またはスパッタリングで、下部電極層6を成膜した基板5を作製する(図2(a))。作製後、リング状の遮蔽治具7で下部電極付きの基板5を保持する。リング状遮蔽治具7は、中央に円形の開口部9を有するリング状プレートで形成されている。リング状プレートの開口部9は、その上端部が段差面10を介して広口に形成されている。下部電極面を下にして遮蔽治具7の段差面10で電極付き基板5の外周部を保持する(図2(b))。開口部9により露出した下部電極層6の中央部にスパッタリング法でKNN薄膜2を形成し、段差面10で覆われた下部電極層6の周辺部には圧電薄膜が形成されない下部電極露出部3が形成されるようにする(図2(c))。こうすることで、圧電特性等を測るときに必要な下部電極露出部3を、圧電薄膜の成膜後に圧電薄膜を除去することなく、成膜中に形成することが可能となる。   A substrate 5 in which a lower electrode layer 6 is formed on a (001) Si substrate with a thermal oxide film by vapor deposition or sputtering is produced (FIG. 2A). After the production, the substrate 5 with the lower electrode is held by the ring-shaped shielding jig 7. The ring-shaped shielding jig 7 is formed of a ring-shaped plate having a circular opening 9 at the center. The opening 9 of the ring-shaped plate has a wide opening at the upper end through the step surface 10. The outer peripheral portion of the electrode-attached substrate 5 is held by the stepped surface 10 of the shielding jig 7 with the lower electrode surface facing downward (FIG. 2B). The KNN thin film 2 is formed by the sputtering method at the center of the lower electrode layer 6 exposed through the opening 9, and the lower electrode exposed portion 3 in which no piezoelectric thin film is formed at the periphery of the lower electrode layer 6 covered with the stepped surface 10. Is formed (FIG. 2C). By doing so, it is possible to form the lower electrode exposed portion 3 necessary for measuring piezoelectric characteristics and the like during film formation without removing the piezoelectric thin film after the piezoelectric thin film is formed.

上記の圧電薄膜面を上にして、この圧電薄膜2の表面に所定の上部電極の最小幅と同じ寸法の開口8aを形成したメタルマスク8を被せる(図2(d))。メタルマスク8に形成する開口8aは、圧電薄膜2の評価したい任意の点に形成する。メタルマスク8によって形成される所定の上部電極4の最小幅は0.5mm以上5.0mm以下となるようにするのがよい。また、メタルマスク8によって形成される上部電極4は、圧電薄膜2の中央部に形成される第1上部電極と、第1上部電極から等間隔の距離に形成される複数の第2上部電極とからなるのがより好ましい。   With the piezoelectric thin film surface facing upward, a metal mask 8 having an opening 8a having the same dimension as the minimum width of a predetermined upper electrode is placed on the surface of the piezoelectric thin film 2 (FIG. 2D). The opening 8a formed in the metal mask 8 is formed at an arbitrary point where the piezoelectric thin film 2 is desired to be evaluated. The minimum width of the predetermined upper electrode 4 formed by the metal mask 8 is preferably 0.5 mm or more and 5.0 mm or less. The upper electrode 4 formed by the metal mask 8 includes a first upper electrode formed at the center of the piezoelectric thin film 2 and a plurality of second upper electrodes formed at equal distances from the first upper electrode. More preferably, it consists of

圧電薄膜2の表面にメタルマスク8を被せた後、蒸着またはスパッタリングで上部電極4を圧電薄膜上に形成して本実施の形態の圧電薄膜付き基板が製造される(図2(e))。こうして上部電極4を形成することで、圧電薄膜の圧電特性を測る際に、レーザー光を照射して膜の変位を測定出来る。また、メタルマスク8を用いて評価したい任意の点に上部電極4を形成することが可能となる。   After the metal mask 8 is put on the surface of the piezoelectric thin film 2, the upper electrode 4 is formed on the piezoelectric thin film by vapor deposition or sputtering, and the substrate with the piezoelectric thin film of the present embodiment is manufactured (FIG. 2E). By forming the upper electrode 4 in this way, when measuring the piezoelectric characteristics of the piezoelectric thin film, it is possible to measure the displacement of the film by irradiating laser light. Further, the upper electrode 4 can be formed at an arbitrary point to be evaluated using the metal mask 8.

ところで、上述した製造工程の内、圧電体薄膜を成膜する際に用いる所定の開口を持つリング状遮蔽治具7は、前述のように下部電極露出部の最小幅が0.005×Dmm以上で且つ、0.05×Dmm以下になるような場合は、圧電薄膜を成膜する際の成膜温度(例えば20〜800℃)における遮蔽治具の線膨張係数αと、基板の線膨張係数αとが、1≦α/α≦4となるように材質を選ぶ必要がある。これはα/αが1以下になる場合は、高温成膜時に基板の方が治具よりも伸びて、基板が破損する恐れがあり、またα/αが4以上になると、高温成膜時に遮蔽する治具の開口径(内径)が基板の外径よりも大きくなってしまい、下部電極露出部が出来なくなってしまうためである。 By the way, in the manufacturing process described above, the ring-shaped shielding jig 7 having a predetermined opening used when the piezoelectric thin film is formed has a minimum width of the lower electrode exposed portion of 0.005 × D mm or more as described above. in and 0.05 if × Dmm such that below, and the linear expansion coefficient alpha w shielding jig in the film forming temperature for forming the piezoelectric thin film (e.g., 20 to 800 ° C.), the linear expansion of the substrate It is necessary to select a material so that the coefficient α b satisfies 1 ≦ α w / α b ≦ 4. This is because when α w / α b is 1 or less, the substrate may be stretched more than the jig during high-temperature film formation, and the substrate may be damaged, and when α w / α b is 4 or more, This is because the opening diameter (inner diameter) of the jig that shields during high temperature film formation becomes larger than the outer diameter of the substrate, and the exposed portion of the lower electrode cannot be formed.

本実施の形態の製造方法によれば、圧電体薄膜付き基板の外周全域、若しくは一部に、下部電極層よりも狭い面積の圧電薄膜が成膜されるように、圧電膜の成膜中に下部電極上の成膜面を遮蔽して、基板の外径Dに対して、最小幅が0.005×Dmm以上0.05×Dmm以下となる下部電極露出部を有する圧電薄膜付き基板を作製する。これにより、圧電薄膜付き基板を作製後に、圧電膜の評価の際に必要だったフォトリソグラフィーやエッチング処理などの圧電薄膜除去工程を省略することが可能となる。これにより、圧電膜の評価に必要なプロセス工程を大幅に簡略化できる。これに加え、それらプロセス工程で発生する不良による歩留り低下も回避することができ、また、フォトリソグラフィーやエッチング処理には大掛かりな設備が必要であるが、それらも不要になるため、圧電体薄膜付き基板及びその基板を用いた圧電体素子の製造コストを大幅に下げることが可能となる。   According to the manufacturing method of the present embodiment, during the formation of the piezoelectric film, the piezoelectric thin film having a smaller area than the lower electrode layer is formed on the entire outer periphery or a part of the substrate with the piezoelectric thin film. A substrate with a piezoelectric thin film having a lower electrode exposed portion having a minimum width of 0.005 × Dmm or more and 0.05 × Dmm or less with respect to the outer diameter D of the substrate is shielded from the film formation surface on the lower electrode. To do. This makes it possible to omit the piezoelectric thin film removal step such as photolithography and etching necessary for the evaluation of the piezoelectric film after the production of the substrate with the piezoelectric thin film. Thereby, the process steps required for evaluating the piezoelectric film can be greatly simplified. In addition to this, it is possible to avoid a decrease in yield due to defects occurring in these process steps, and large equipment is required for photolithography and etching processing, but these are also unnecessary, so a piezoelectric thin film is attached. The manufacturing cost of the substrate and the piezoelectric element using the substrate can be greatly reduced.

そして、上記のような、下部電極が露出した構造を持ち、圧電体薄膜付き基板の圧電膜上の評価が必要な箇所に、最小幅が0.5mm以上5.0mm以下の上部電極を有する構造にすることで、基板内の任意の場所の圧電膜の評価が、非破壊で実現できるようになる。   And the structure which has the structure where the lower electrode was exposed as mentioned above, and has an upper electrode with a minimum width of 0.5 mm or more and 5.0 mm or less at a place where evaluation on the piezoelectric film of the substrate with the piezoelectric thin film is necessary By doing so, the evaluation of the piezoelectric film at an arbitrary location in the substrate can be realized non-destructively.

また、上述した工程を経て得られた圧電薄膜付き基板は、その後加工処理することなく、そのままの状態で評価に必要な下部電極露出部と上部電極とを有するので、本実施の圧電薄膜付き基板の製造方法に、下部電極露出部と上部電極との間に電圧を印加することで、圧電薄膜の特性を検査する工程を含ませることが可能となる。製造工程中に圧電薄膜の特性を検査する工程を組み込めるので、特性ばらつきを抑えるような成膜条件になるようフィードバックが可能となる。   Moreover, since the board | substrate with a piezoelectric thin film obtained through the process mentioned above has the lower electrode exposure part and upper electrode which are required for evaluation as it is, without processing after that, the board | substrate with a piezoelectric thin film of this embodiment By applying a voltage between the exposed portion of the lower electrode and the upper electrode, it is possible to include a step of inspecting the characteristics of the piezoelectric thin film. Since a process for inspecting the characteristics of the piezoelectric thin film can be incorporated during the manufacturing process, feedback can be made so that the film forming conditions can suppress the characteristic variation.

したがって、装置構造や成膜条件、装置や原料の経時的な変化によって、同一基板の面内や成膜の各ロット間、多数枚同時成膜の場合でもロット内の基板間で、膜の特性を均一化できる。特に、圧電薄膜の中央部に第1上部電極、前記第1上部電極から等間隔の距離に複数の第2上部電極を形成すると、圧電薄膜付き基板の圧電薄膜上の面内特性評価が必要な箇所をカバーできる。そのため、基板が大口径化したときでも面内分布や基板間の特性のばらつきを抑えることが可能となり、素子化したときの基板1枚からの素子取得率が増加し、歩留りを向上でき、低コスト化が図れる。その結果、安定して特性ばらつきの少ない高品質な圧電体薄膜付き基板及びその基板を用いた圧電体素子を供給することが可能となる。   Therefore, depending on the structure of the equipment, film formation conditions, equipment and raw materials over time, film characteristics within the same substrate surface, between lots of film formation, and between substrates in a lot even when multiple sheets are formed simultaneously. Can be made uniform. In particular, when the first upper electrode is formed in the center of the piezoelectric thin film and a plurality of second upper electrodes are formed at equal distances from the first upper electrode, in-plane characteristic evaluation on the piezoelectric thin film of the substrate with the piezoelectric thin film is required. Can cover places. Therefore, even when the substrate is increased in diameter, it is possible to suppress in-plane distribution and variation in characteristics between the substrates, increase the element acquisition rate from one substrate when it is formed into an element, and improve the yield. Cost can be reduced. As a result, it is possible to supply a high-quality substrate with a piezoelectric thin film with little characteristic variation and a piezoelectric element using the substrate.

[他の実施の形態]
本発明の実施の形態では、下部電極にPtを用いたが、Ptを含む合金、Au、Ru、Ir、又は、SuRuO、LaNiO、などの金属酸化物電極を用いた場合も同様の効果が期待できる。また密着層にTiを用いたが、Taを密着層に用いたり、密着層なしであったりする場合でも同様の効果が期待できる。基板についても、熱酸化膜付き(001)面Si基板を用いたが、異なる面方位のSi基板や、熱酸化膜無しのSi基板、SOI基板でも同様の効果が得られる。また、Si基板以外に、石英ガラス基板、GaAs基板、サファイヤ基板、ステンレスなどの金属基板、MgO基板、SrTiO基板、又はKNN基板などの圧電性基板などを用いてもよい。KNN膜は特に他の元素を添加していないが、5%原子数以下のLi、Ta、Sb、Ca、Cu、Ba、Ti、等をKNN膜に添加した場合でも同様の効果が得られる。
[Other embodiments]
In the embodiment of the present invention, Pt is used for the lower electrode, but the same effect can be obtained when an alloy containing Pt, a metal oxide electrode such as Au, Ru, Ir, or SuRuO 3 , LaNiO 3 is used. Can be expected. Although Ti is used for the adhesion layer, the same effect can be expected even when Ta is used for the adhesion layer or when there is no adhesion layer. As the substrate, a (001) plane Si substrate with a thermal oxide film was used, but the same effect can be obtained with a Si substrate having a different plane orientation, a Si substrate without a thermal oxide film, or an SOI substrate. In addition to the Si substrate, a quartz glass substrate, a GaAs substrate, a sapphire substrate, a metal substrate such as stainless steel, a piezoelectric substrate such as an MgO substrate, an SrTiO 3 substrate, or a KNN substrate may be used. The KNN film is not particularly added with other elements, but the same effect can be obtained even when Li, Ta, Sb, Ca, Cu, Ba, Ti, etc. having 5% or less atomic number are added to the KNN film.

また、実施の形態では、上部電極形成の際にメタルマスクを使用したが、コストをかけることを前提とすれば、フォトリソグラフィーの工程を使って、更に小さい上部電極にすることは可能である。   In the embodiment, the metal mask is used when forming the upper electrode. However, if it is assumed that the cost is increased, it is possible to make the upper electrode smaller by using a photolithography process.

以下に実施例1〜6および比較例1〜5のSi基板上に形成した膜厚3μmのKNN薄膜を作製し圧電特性を評価した例を説明する。   Hereinafter, an example will be described in which a 3 μm-thick KNN thin film formed on the Si substrates of Examples 1 to 6 and Comparative Examples 1 to 5 was manufactured and piezoelectric characteristics were evaluated.

[KNN薄膜の成膜]
前記した本実施の形態に係る製造方法により、圧電体薄膜付き基板を作製した。基板には円形状の両面ミラーの熱酸化膜付きSi基板((001)面方位、厚さ0.525mm、熱酸化膜厚さ200nm、直径100mm)を用いた。まず、基板上にRFマグネトロンスパッタリング法で、Ti密着層(膜厚2nm)、Pt下部電極((111)面優先配向、膜厚200nm)を形成した。Ti密着層とPt下部電極は、基板温度100〜350℃、放電パワー200W、導入ガスAr雰囲気、圧力2.5Pa、成膜時間1〜3分の条件で成膜した。
[Deposition of KNN thin film]
A substrate with a piezoelectric thin film was produced by the manufacturing method according to the present embodiment described above. As the substrate, a circular double-sided mirror Si substrate with a thermal oxide film ((001) plane orientation, thickness 0.525 mm, thermal oxide film thickness 200 nm, diameter 100 mm) was used. First, a Ti adhesion layer (film thickness 2 nm) and a Pt lower electrode ((111) plane preferred orientation, film thickness 200 nm) were formed on a substrate by RF magnetron sputtering. The Ti adhesion layer and the Pt lower electrode were formed under conditions of a substrate temperature of 100 to 350 ° C., a discharge power of 200 W, an introduced gas Ar atmosphere, a pressure of 2.5 Pa, and a film formation time of 1 to 3 minutes.

[実施例1〜6]
その上に、下部電極露出部最小幅が1mm、0.5mm、5mmになるように、RFマグネトロンスパッタリング法で、KNN薄膜を3μm形成した。KNN圧電薄膜は、Na/(K+Na)=0.50のKNN焼結体をターゲットに用い、基板温度700℃、放電パワー800W、導入ガスAr雰囲気、圧力1.3Paの条件で、成膜面を鉛直方向下向きに成膜した。KNN薄膜のスパッタ成膜時間は膜厚がほぼ3μmになるように調整して行った。このときの成膜中に用いる下部電極露出部を遮蔽する遮蔽治具は、下部電極露出部最小幅が0.5mmのものは、インコネル625(α/α=3.41)とカーボン(α/α=1.14)、1mm、5mmのものはインコネル625をそれぞれ使用した。
[Examples 1 to 6]
A 3 μm thick KNN thin film was formed thereon by RF magnetron sputtering so that the minimum width of the exposed portion of the lower electrode was 1 mm, 0.5 mm, and 5 mm. The KNN piezoelectric thin film uses a KNN sintered body of Na / (K + Na) = 0.50 as a target, and has a film formation surface under conditions of a substrate temperature of 700 ° C., a discharge power of 800 W, an introduced gas Ar atmosphere, and a pressure of 1.3 Pa. The film was formed vertically downward. The sputter deposition time of the KNN thin film was adjusted so that the film thickness was about 3 μm. The shielding jig that shields the exposed portion of the lower electrode used during film formation at this time has a minimum width of the exposed portion of the lower electrode of 0.5 mm. Inconel 625 (α w / α b = 3.41) and carbon ( α w / α b = 1.14) Inconel 625 was used for 1 mm and 5 mm.

その後、形成したKNN薄膜の上の、図3に示すような位置に、径0.5mm、1mm、5mmの円形の上部電極が形成されるようなメタルマスクを乗せた。上部電極は、面内任意の5点、例えば、第1上部電極が圧電薄膜の中央部(座標(0,0))に、複数の第2上部電極が第1上部電極から所定距離離れた、例えば40mm離れた圧電薄膜の周辺部(座標(0,40)、(40,0)、(0,−40)、座標(−40,0)に等間隔に形成される。このようなメタルマスクを乗せ、例えばPt上部電極(膜厚20nm)をRFマグネトロンスパッタリング法で形成した。これら、下部電極露出部の最小幅が異なるもの、治具の材質が異なるもの、上部電極の径が異なるものの組合せで、実施例1〜6の圧電薄膜付き基板を作製した。   Thereafter, a metal mask on which a circular upper electrode having a diameter of 0.5 mm, 1 mm, and 5 mm was formed was placed on the formed KNN thin film at a position as shown in FIG. The upper electrode has any five points in the plane, for example, the first upper electrode is at the center of the piezoelectric thin film (coordinates (0, 0)), and the plurality of second upper electrodes are separated from the first upper electrode by a predetermined distance. For example, the metal thin film is formed at equal intervals in the periphery (coordinates (0, 40), (40, 0), (0, −40), coordinates (−40, 0)) of the piezoelectric thin film separated by 40 mm. For example, a Pt upper electrode (thickness 20 nm) was formed by RF magnetron sputtering, a combination of those having different minimum width of the lower electrode exposed portion, different jig materials, and different upper electrode diameters. Thus, substrates with piezoelectric thin films of Examples 1 to 6 were produced.

[比較例1〜5]
一方、比較例として、下部電極露出部最小幅が0.5mm、1mm、6mmで成膜中に用いる下部電極露出部を遮蔽する治具の材質がインコネル625(α/α=3.41)であるものと、下部電極露出部最小幅が0.5mmで、成膜中に用いる下部電極露出部を遮蔽する治具の材質が、SUS304(α/α=4.56)、石英(α/α=0.11)のものを使用した。
[Comparative Examples 1-5]
On the other hand, as a comparative example, the lower electrode exposed portion minimum width is 0.5 mm, 1 mm, and 6 mm, and the material of the jig for shielding the lower electrode exposed portion used during film formation is Inconel 625 (α w / α b = 3.41). ), The minimum width of the lower electrode exposed portion is 0.5 mm, and the material of the jig for shielding the lower electrode exposed portion used during the film formation is SUS304 (α w / α b = 4.56), quartz (Α w / α b = 0.11) was used.

その後、形成したKNN薄膜の上に、図3に示すような位置に、上部電極の径が1mm、0.2mm、6mmとなるようなメタルマスクを乗せ、Pt上部電極(膜厚20nm)をRFマグネトロンスパッタリング法で形成した。下部電極露出部最小幅が異なるもの、治具の材質が異なるもの、上部電極の最小幅が異なるものの組合せで、比較例1〜5の圧電薄膜付き基板を作製した。   Thereafter, a metal mask with the upper electrode diameters of 1 mm, 0.2 mm, and 6 mm is placed on the formed KNN thin film at the position shown in FIG. It formed by the magnetron sputtering method. Substrates with piezoelectric thin films of Comparative Examples 1 to 5 were prepared by combinations of different lower electrode exposed portion minimum widths, different jig materials, and different upper electrode minimum widths.

[圧電特性評価]
その後、作製したKNN薄膜付き基板を、ダブルレーザービーム干渉計を用いて、電圧の印可と同方向(縦方向)の歪みを測定し、圧電定数d33をその歪み量から求めた。このダブルレーザービーム干渉計は、通常、基板表面のみにレーザービームを当てて、歪みを測定すると、基板のたわみ変形の分も一緒に測定されてしまうものを、裏面からもレーザービームを当てて、この基板のたわみ分を相殺できる。このダブルビームレーザー干渉計を用いた圧電定数d33の算出方法及び、装置の構成、測定方法は下記文献1及び文献2に記載されている方法で行った。また、圧電定数d33の算出する際に用いるKNN薄膜のヤング率は104GPaを用いた。
[Piezoelectric evaluation]
Thereafter, the produced substrate with a KNN thin film was measured for distortion in the same direction (longitudinal direction) as voltage application using a double laser beam interferometer, and the piezoelectric constant d 33 was determined from the amount of distortion. This double laser beam interferometer usually applies a laser beam only to the substrate surface, and when the distortion is measured, the amount of deflection deformation of the substrate is also measured. This deflection of the substrate can be offset. The calculation method of the piezoelectric constant d 33 using this double beam laser interferometer, the configuration of the apparatus, and the measurement method were performed by the methods described in Document 1 and Document 2 below. The Young's modulus of the KNN thin film used in calculating the piezoelectric constant d 33 was used 104GPa.

文献1:眞岩 宏司、一ノ瀬 昇、応用物理 第71巻 第10号(2002)1227−1232
文献2:H.Maiwa、J.A.Christman、S−H.Kim、J−P.Maria、B.Chen、S.K.Streiffer and A.I.Kingon:Jpn.J.Appl.Phys.38、5402(1999)
Reference 1: Koji Kajiiwa, Noboru Ichinose, Applied Physics Vol. 71, No. 10 (2002) 1227-1232.
Reference 2: H.C. Maiwa, J .; A. Christman, SH. Kim, JP. Maria, B.M. Chen, S.M. K. Striffer and A.M. I. Kingon: Jpn. J. et al. Appl. Phys. 38, 5402 (1999)

このようにして測定した実施例1〜6は、表1に示すように、圧電体薄膜付き基板の面内任意の5点の圧電特性が、いずれも良好(○)であった。したがって、非破壊でフォトリソグラフィーやエッチングなどの大掛かりな設備を必要としない簡易的な評価方法で測定が可能である。   In Examples 1 to 6 thus measured, as shown in Table 1, the piezoelectric properties at any five points in the plane of the substrate with the piezoelectric thin film were all good (◯). Therefore, measurement is possible with a simple evaluation method that is non-destructive and does not require large-scale facilities such as photolithography and etching.

Figure 2012054317
Figure 2012054317

一方、比較例1〜5は、表2に示すように、いずれも評価結果が悪かった(×)。α/αが4以上となるSUS304を用いた比較例1では、表2に示すように、成膜中の加熱で、治具の開口径が基板径よりも大きくなってしまい本実施例の基板成膜面を下にした製造方法では、基板が落下してしまい測定が出来なかった。 On the other hand, as shown in Table 2, Comparative Examples 1 to 5 all had poor evaluation results (x). In Comparative Example 1 using SUS304 in which α w / α b is 4 or more, as shown in Table 2, the opening diameter of the jig becomes larger than the substrate diameter due to heating during film formation. In the manufacturing method in which the substrate film-forming surface was down, the substrate dropped and measurement could not be performed.

Figure 2012054317
Figure 2012054317

また、α/αが1以下となる石英を用いた比較例2では、成膜中の加熱で、治具の基板保持部が基板径よりも小さくなってしまい基板が割れてしまい測定が出来なかった。 Further, in Comparative Example 2 using quartz in which α w / α b is 1 or less, the substrate holding portion of the jig becomes smaller than the substrate diameter due to heating during film formation, and the substrate is cracked. I could not do it.

更に、上部電極径を0.2mmとした比較例3では、メタルマスクによるスパッタリング法では、所望のサイズの電極が形成できず測定不可となった。   Furthermore, in Comparative Example 3 in which the upper electrode diameter was 0.2 mm, an electrode having a desired size could not be formed by the sputtering method using a metal mask, making measurement impossible.

また、下部電極露出部を0.05×Dmm以上(本実施例では、基板径=100mmな
ので6mmは0.05×Dmm以上)にした比較例4では、実施例1〜6と同様に基板面内の任意の点について圧電特性の測定が可能である。しかし図4に示すように基板表面の有効使用率と下部電極露出部最小幅の関係を見ると、基板径100mmの場合、下部電極露出部最小幅が5mm以上(0.05×Dmm以上)になると有効使用率が90%以下になってしまう。有効使用率が90%以下になると実際の素子の取得効率が大きく減少するので、90%以上が望まれる。よって比較例4は測定可能であるが、適用不可となる。
Further, in Comparative Example 4 in which the exposed portion of the lower electrode is 0.05 × Dmm or more (in this example, the substrate diameter = 100 mm, 6 mm is 0.05 × Dmm or more), the substrate surface is the same as in Examples 1-6. Piezoelectric characteristics can be measured at any point. However, as shown in FIG. 4, when the relationship between the effective usage rate of the substrate surface and the minimum width of the exposed portion of the lower electrode is seen, the minimum width of the exposed portion of the lower electrode is 5 mm or more (0.05 × Dmm or more) when the substrate diameter is 100 mm. Then, the effective usage rate becomes 90% or less. When the effective usage rate is 90% or less, the actual element acquisition efficiency is greatly reduced, so 90% or more is desired. Therefore, although Comparative Example 4 can be measured, it is not applicable.

また、同様に上部電極径を6mm(5mm以上)にした比較例5では、今回の面内5点の場合は、有効使用率が90%以上である。しかし、図5に示すように基板表面の有効使用率と上部電極露出部最小幅の関係を見ると、測定点を9点以上にすると90%を下回る。よって前述、下部電極露出部の場合と同様に、適用不可となる。   Similarly, in Comparative Example 5 in which the diameter of the upper electrode is 6 mm (5 mm or more), the effective usage rate is 90% or more in the case of 5 points in this plane. However, as shown in FIG. 5, the relationship between the effective usage rate of the substrate surface and the minimum width of the exposed portion of the upper electrode is less than 90% when the number of measurement points is 9 or more. Therefore, as in the case of the lower electrode exposed portion, it cannot be applied.

[実施例7]
更に、実施例1〜6では、図6(a)に示すように成膜方式にフェイスダウン方式を採用して成膜面を鉛直方向下向きKNN膜を成膜しているが、図6(b)に示すように、フェイスアップ方式を採用して成膜面を鉛直方向上向きにして、下部電極露出部3を遮蔽する治具7を基板5上に乗せて成膜する製造方法を用いてもよい。フェイスダウン方式は、リング状遮蔽治具上に基板を支持できるため基板保持用金具を必要としない。これに対して、実施例7で採用したフェイスアップ方式は、遮蔽治具では基板を支持できないため、基板保持用部材としての基板保持用金具(図示略)を必要とするが、実施例1〜6と同様の非破壊評価が行える効果がある。
[Example 7]
Further, in Examples 1 to 6, as shown in FIG. 6A, the face-down method is adopted as the film formation method to form the KNN film with the film formation surface facing vertically downward. As shown in FIG. 4B, a manufacturing method may be used in which a film is formed by placing the jig 7 that shields the lower electrode exposed portion 3 on the substrate 5 with the face-up method and with the film formation surface facing vertically upward. Good. The face-down method can support the substrate on the ring-shaped shielding jig, and does not require a substrate holding fixture. In contrast, the face-up method employed in Example 7 cannot support a substrate with a shielding jig, and thus requires a substrate holding bracket (not shown) as a substrate holding member. There is an effect that non-destructive evaluation similar to 6 can be performed.

[実施例8]
また、実施例1〜6では、基板外周全域に下部電極露出部があるが、実施例8の下部電極露出部を遮蔽する治具の形状を図7に示すように、下部電極露出部3aが外周部の一部分のみにある場合でもよい。実施例8によれば、実施例1〜7と比べて圧電薄膜付き基板の有効使用率がさらに向上する。
[変形例]
上記実施例では、円形のシリコン基板を用いて圧電薄膜付き基板を形成したが、円形状の基板に限定されることなく、多角形状を用いても良い。多角形状の基板を用いる場合には、もっとも長い対角線をD’として、下部電極露出部の幅を0.005D’以上0.05D’以下となるよう決定すればよい。また、上記実施例では、4インチ円形状基板を用いて説明したが、4インチサイズ以上の基板、例えば、6インチサイズや12インチサイズであっても、本発明の適用は可能である。
[Example 8]
Moreover, in Examples 1-6, although there exists a lower electrode exposure part in the board | substrate outer periphery whole region, as shown in FIG. 7 in the shape of the jig | tool which shields the lower electrode exposure part of Example 8, lower electrode exposure part 3a It may be in a part of the outer periphery. According to Example 8, the effective usage rate of the substrate with piezoelectric thin film is further improved as compared with Examples 1-7.
[Modification]
In the said Example, although the board | substrate with a piezoelectric thin film was formed using the circular silicon substrate, it is not limited to a circular-shaped board | substrate, You may use polygonal shape. When a polygonal substrate is used, the longest diagonal line may be D ′ and the width of the lower electrode exposed portion may be determined to be 0.005D ′ or more and 0.05D ′ or less. In the above embodiment, a 4-inch circular substrate has been described. However, the present invention can be applied to a 4-inch or larger substrate, for example, a 6-inch size or a 12-inch size.

1 圧電体薄膜付き基板
2 圧電薄膜部
3 下部電極露出部
4 上部電極
5 基板
6 下部電極
7 下部電極露出部を遮蔽する治具
8 所定の上部電極幅の開口を持つメタルマスク
DESCRIPTION OF SYMBOLS 1 Substrate with piezoelectric thin film 2 Piezoelectric thin film portion 3 Lower electrode exposed portion 4 Upper electrode 5 Substrate 6 Lower electrode 7 Jig 8 for shielding lower electrode exposed portion Metal mask having opening of predetermined upper electrode width

Claims (10)

基板上に下部電極層が形成され、該下部電極層上にペロブスカイト構造の圧電薄膜が形成された圧電薄膜付き基板において、
前記下部電極層上に形成される前記圧電薄膜が前記下部電極層よりも狭い面積で形成されることにより、前記下部電極層の一部が該圧電薄膜から露出している下部電極露出部が前記下部電極層に設けられている圧電薄膜付き基板。
In a substrate with a piezoelectric thin film in which a lower electrode layer is formed on a substrate, and a piezoelectric thin film having a perovskite structure is formed on the lower electrode layer,
The piezoelectric thin film formed on the lower electrode layer is formed with a smaller area than the lower electrode layer, so that the lower electrode exposed portion where a part of the lower electrode layer is exposed from the piezoelectric thin film A substrate with a piezoelectric thin film provided on the lower electrode layer.
請求項1に記載の前記圧電薄膜付き基板において、前記下部電極層の外周部が露出するよう前記下部電極露出部が設けられる圧電薄膜付き基板。   2. The substrate with a piezoelectric thin film according to claim 1, wherein the lower electrode exposed portion is provided so that an outer peripheral portion of the lower electrode layer is exposed. 請求項2に記載の前記圧電薄膜付き基板において、前記外周部に形成される前記下部電極露出部の幅が、前記基板の外径Dに対して、0.005×D以上0.05×D以下である圧電薄膜付き基板。   3. The substrate with a piezoelectric thin film according to claim 2, wherein a width of the exposed portion of the lower electrode formed on the outer peripheral portion is 0.005 × D or more and 0.05 × D with respect to an outer diameter D of the substrate. A substrate with a piezoelectric thin film as follows. 請求項1〜3のいずれかに記載の前記圧電薄膜付き基板において、前記ペロブスカイト構造の圧電薄膜が、一般式(K1−xNa)NbO(0<x<1)で表されるニオブ酸カリウムナトリウムである圧電薄膜付き基板。 Niobium in the piezoelectric thin film-attached substrate according to any one of claims 1 to 3, the piezoelectric thin film of the perovskite structure, represented by the general formula (K 1-x Na x) NbO 3 (0 <x <1) A substrate with a piezoelectric thin film that is potassium sodium oxide. 基板上に下部電極層を形成し、
前記下部電極層の一部を遮蔽治具により覆うとともに、
前記遮蔽治具に覆われていない前記下部電極層の他部にペロブスカイト構造の圧電薄膜を形成することで、前記下部電極層の一部に圧電薄膜が形成されない下部電極露出部を形成し、
前記圧電薄膜の形成後、前記遮蔽治具を除去することで、前記下部電極層の一部に形成されている下部電極露出部を露出させる圧電薄膜付き基板の製造方法。
Forming a lower electrode layer on the substrate;
Covering a part of the lower electrode layer with a shielding jig,
By forming a piezoelectric thin film having a perovskite structure on the other part of the lower electrode layer that is not covered by the shielding jig, a lower electrode exposed portion where no piezoelectric thin film is formed on a part of the lower electrode layer is formed,
A method of manufacturing a substrate with a piezoelectric thin film in which the lower electrode exposed portion formed in a part of the lower electrode layer is exposed by removing the shielding jig after the formation of the piezoelectric thin film.
請求項5に記載の前記圧電薄膜付き基板の製造方法において、前記下部電極層の一部が前記下部電極層の外周部であり、該外周部に形成される前記下部電極露出部の幅が、前記基板の外径Dに対して、0.005×D以上0.05×D以下である圧電薄膜付き基板の製造方法。   6. The method for manufacturing a substrate with a piezoelectric thin film according to claim 5, wherein a part of the lower electrode layer is an outer peripheral part of the lower electrode layer, and a width of the lower electrode exposed part formed on the outer peripheral part is The manufacturing method of the board | substrate with a piezoelectric thin film which is 0.005 * D or more and 0.05 * D or less with respect to the outer diameter D of the said board | substrate. 請求項6に記載の前記圧電薄膜付き基板の製造方法において、
前記圧電薄膜の形成温度の範囲における前記遮蔽治具の線膨張係数αと前記基板の線膨張係数αが、1≦α/α≦4である圧電薄膜付き基板の製造方法。
In the manufacturing method of the substrate with a piezoelectric thin film according to claim 6,
The manufacturing method of the board | substrate with a piezoelectric thin film whose linear expansion coefficient (alpha) w of the said shielding jig and the linear expansion coefficient (alpha) b of the said board | substrate in the range of the formation temperature of the said piezoelectric thin film are 1 <= (alpha) w / (alpha) b <= 4.
請求項5ないし7のいずれかに記載の前記圧電薄膜付き基板の製造方法であって、
前記圧電薄膜上に幅が0.5mm以上5.0mm以下の上部電極を形成し、下部電極露出部と前記上部電極との間に電圧を印加することで、前記圧電薄膜の特性を検査する工程を含む圧電薄膜付き基板の製造方法。
A method for manufacturing the substrate with a piezoelectric thin film according to any one of claims 5 to 7,
Forming an upper electrode having a width of 0.5 mm or more and 5.0 mm or less on the piezoelectric thin film, and applying a voltage between the exposed portion of the lower electrode and the upper electrode, thereby inspecting the characteristics of the piezoelectric thin film A method for manufacturing a substrate with a piezoelectric thin film comprising:
請求項5ないし8のいずれかに記載の前記圧電薄膜付き基板の製造方法において、前記上部電極は、前記圧電薄膜の中央部に形成される第1上部電極と、前記第1上部電極から等間隔の距離に形成される複数の第2上部電極とからなる圧電薄膜付き基板の製造方法。   9. The method for manufacturing a substrate with a piezoelectric thin film according to claim 5, wherein the upper electrode is equidistant from a first upper electrode formed at a central portion of the piezoelectric thin film and the first upper electrode. The manufacturing method of the board | substrate with a piezoelectric thin film which consists of several 2nd upper electrodes formed in this distance. 請求項5ないし9のいずれかに記載の前記圧電薄膜付き基板の製造方法において、前記ペロブスカイト構造の圧電薄膜が、一般式(K1−xNa)NbO(0<x<1)で表されるニオブ酸カリウムナトリウムである圧電薄膜付き基板の製造方法。 Table In the method for manufacturing the piezoelectric thin film-attached substrate according to any one of claims 5 to 9, the piezoelectric thin film of the perovskite structure, with the general formula (K 1-x Na x) NbO 3 (0 <x <1) Of manufacturing a substrate with a piezoelectric thin film, which is potassium sodium niobate.
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