JP2012028565A - Bipolar semiconductor device manufacturing method and bipolar semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bipolar semiconductor device manufacturing method, which allows the prevention of increase in forward voltage even under conditions including a high temperature and a high current density, and to provide a bipolar semiconductor device.SOLUTION: The bipolar semiconductor device manufacturing method includes a manufacturing process of a SiC pin diode 20. The manufacturing process includes forming, on C plane of an n type 4HSiC substrate 21, a buffer layer 22, which is an n type SiC growth layer, a drift layer 23, a p type junction layer 24 and a p+ type contact layer 25, and thereafter removing the whole n type 4HSiC substrate 21 by chemical mechanical polishing (CMP). Thus, it becomes possible to avoid the phenomenon that minority carriers having reached the substrate escalate a basal plane dislocation included in the substrate into a stacking fault when passing a forward current through the device.

Description

  The present invention relates to a method for manufacturing a bipolar semiconductor device and a bipolar semiconductor device capable of reducing defects that become the core of stacking faults, which are factors that cause forward voltage to increase with current application.

  Wide-gap semiconductor materials such as silicon carbide (SiC) have excellent characteristics such as about 10 times higher dielectric breakdown field strength than silicon (Si), and high breakdown voltage bipolar with high reverse voltage resistance. It attracts attention as a suitable material for power semiconductor elements.

  Bipolar semiconductor elements such as pin diodes, bipolar transistors, GTO (gate turn-off transistor), and GCT (gate commutation type turn-off transistors) have a higher built-in voltage than unipolar semiconductor elements such as Schottky diodes and MOSFETs. The on-resistance is significantly reduced by the conductivity modulation of the drift layer by the implantation of.

  Accordingly, bipolar semiconductor elements are used in high voltage and large current regions such as power applications in order to reduce loss. When these bipolar semiconductor elements are made of SiC, it is possible to achieve performance that is significantly superior to that of Si elements.

  For example, in the case of a 10 kV high voltage pin diode element composed of SiC, the forward voltage is about 1/3 that of a Si pin diode, and the reverse recovery time corresponding to the off-time speed is as fast as about 1/20 or less. It is. In addition, power loss can be reduced to about 1/5 or less of Si pin diodes, which can greatly contribute to energy saving. In addition to SiC pin diodes, SiC npn transistors, SiC SIAFETs, SiC SIJFETs, and the like have been developed and similar power loss reduction effects have been reported (for example, Non-Patent Document 1). In addition, SiC GTO using a p-type semiconductor layer of opposite polarity as a drift layer has been developed (for example, Non-Patent Document 2).

  By the way, in the SiC bipolar semiconductor element, there is a phenomenon called “forward voltage drift” in which the forward voltage increases when a current flows in the forward direction. This forward voltage drift is generated by stacking faults expanding into the drift layer. Defects that become seeds of this stacking fault include basal plane dislocations (basal plane dislocations) and surface defects (half loops). Among these, many basal plane dislocations exist in the substrate. When minority carriers reach this substrate, stacking faults expand from the substrate into the drift layer.

Therefore, in Patent Document 1 (US Pat. No. 6,889,874), a buffer layer having an impurity concentration similar to that of the substrate is formed between the drift layer and the substrate, and minority carriers reach the substrate from the drift layer. Technology to prevent this is shown. A semiconductor multilayer structure of an SiC bipolar semiconductor device according to this technique is schematically shown on the left side of FIG. 5, and an electron density distribution K1 and a hole density distribution K2 corresponding to each semiconductor layer of the semiconductor multilayer structure are schematically shown on the right side of FIG. Indicate. The right side of FIG. 5 shows an electron density distribution K1 and a hole density distribution K2 when a current of about 100 A / cm ² is passed at room temperature.

In the SiC bipolar semiconductor device having this buffer layer, as shown on the right side of FIG. 5, when a current having a current density of about 100 A / cm ² flows at room temperature, holes as minority carriers do not reach the substrate. No expansion of stacking faults from the substrate was observed.

However, when a current exceeding 200 ° C. or a current density of 200 A / cm ² or more is applied, holes as minority carriers have reached the substrate as indicated by the symbol M on the right side of FIG. An increase in stacking faults from the substrate occurred. That is, the buffer layer alone could not prevent holes (minority carriers) from reaching the substrate, the stacking faults expanded from the substrate, and forward voltage drift occurred.

US Pat. No. 6,849,874

Edited by Hiroyuki Matsunami, “Semiconductor SiC Technology and Applications”, pages 218-221, published by Nikkan Kogyo Shimbun A. K. Agarwal et. al, Materials Science Forum Volume 389-393, 2000, pp. 1349-1352.

  Accordingly, an object of the present invention is to provide a bipolar semiconductor device manufacturing method and a bipolar semiconductor device that can prevent an increase in forward voltage even under conditions of high temperature and high current density.

In order to solve the above problems, a method for manufacturing a bipolar semiconductor device according to the present invention includes forming a buffer layer of a first conductivity type with a silicon carbide semiconductor on a substrate made of a silicon carbide semiconductor,
Forming a drift layer of a first conductivity type with a silicon carbide semiconductor on the buffer layer;
A method for manufacturing a bipolar semiconductor element, wherein a second conductivity type semiconductor layer is formed of a silicon carbide semiconductor on the drift layer,
Of the first conductivity type buffer layer, the first conductivity type drift layer, and the second conductivity type semiconductor layer, at least the first conductivity type buffer layer and the first conductivity type drift layer are disposed on the substrate. After the formation, the substrate made of the silicon carbide semiconductor is removed.

  According to the method for manufacturing a bipolar semiconductor device of the present invention, since the substrate made of the silicon carbide semiconductor is removed, the basal plane dislocations included in the substrate are stacked when minority carriers reach the substrate during forward energization. The phenomenon of expanding into defects can be eliminated. Therefore, according to the present invention, it is possible to manufacture a bipolar semiconductor element that can prevent an increase in forward voltage even under conditions of high temperature and high current density.

  In one embodiment of the method for manufacturing a bipolar semiconductor device, the buffer layer, the drift layer, and the second conductivity type semiconductor layer are formed on the substrate, and then the substrate is removed.

  According to the method for manufacturing a bipolar semiconductor element of this embodiment, an element structure including the buffer layer, the drift layer, and the second conductivity type semiconductor layer can be easily formed.

In the bipolar semiconductor device of the present invention, a buffer layer of the first conductivity type made of a silicon carbide semiconductor,
A drift layer of a first conductivity type formed on the buffer layer and made of a silicon carbide semiconductor;
A second conductivity type semiconductor layer formed on the drift layer and made of a silicon carbide semiconductor;
Of the first conductivity type buffer layer, the first conductivity type drift layer, and the second conductivity type semiconductor layer, at least the first conductivity type buffer layer and the drift layer are made of a silicon carbide semiconductor. Then, the substrate was removed.

  According to the bipolar semiconductor device of the present invention, since the substrate is removed, the phenomenon that the basal plane dislocation contained in the substrate expands to stacking faults when minority carriers reach the substrate during forward energization is eliminated. be able to. Therefore, according to the bipolar semiconductor device of the present invention, an increase in the forward voltage can be prevented even under conditions of high temperature and high current density.

  In one embodiment of the method of manufacturing a bipolar semiconductor device, the buffer layer, the drift layer, and the second conductivity type semiconductor layer are formed on the substrate, and then the substrate is removed.

  According to the bipolar semiconductor device of this embodiment, the device structure including the buffer layer, the drift layer, and the second conductivity type semiconductor layer can be easily formed.

  In the bipolar semiconductor device of one embodiment, the buffer layer has a thickness of 2.5 μm or less.

  According to the bipolar semiconductor device of this embodiment, the crystal growth time can be suppressed and the resistance of the buffer layer can be suppressed to suppress an increase in the loss of the device.

  In consideration of the formation of an electrode under the buffer layer and the conditions for crystal growth, the lower limit of the thickness of the buffer layer is 0.5 μm as an example.

  In the bipolar semiconductor device of one embodiment, the buffer layer is a cathode, and the second conductivity type semiconductor layer formed on the drift layer is an anode.

  According to this embodiment, since the substrate is removed, a phenomenon in which stacking faults expand from the substrate even under conditions of high temperature and high current density is eliminated, and a diode that can prevent an increase in forward voltage can be realized.

In one embodiment, the first conductivity type buffer layer is a collector layer, and the second conductivity type semiconductor layer formed on the drift layer is a base layer.
Further, the transistor has a first conductivity type emitter layer formed on the base layer and made of a silicon carbide semiconductor.

  According to this embodiment, since the substrate is removed, there is no phenomenon in which minority carriers reach the substrate even under conditions of high temperature and high current density, and there is no phenomenon in which stacking faults expand from the substrate. It is possible to realize a transistor that can prevent an increase in the above.

In one embodiment of the bipolar semiconductor device, the buffer layer is a collector layer,
The IGBT is formed on the second conductivity type semiconductor layer and has an emitter layer made of the first conductivity type silicon carbide semiconductor.

  According to this embodiment, since the substrate is removed, there is no phenomenon in which minority carriers reach the substrate even under conditions of high temperature and high current density, and there is no phenomenon in which stacking faults expand from the substrate, and stable characteristics. Can be obtained for a long period of time.

  According to the method for manufacturing a bipolar semiconductor element of the present invention, since the substrate made of the silicon carbide semiconductor is removed, basal plane dislocations included in the substrate are expanded to stacking faults when minority carriers reach the substrate. This phenomenon can be eliminated. This makes it possible to manufacture a bipolar semiconductor element that can prevent an increase in forward voltage even under conditions of high temperature and high current density.

It is sectional drawing which shows the cross section of the SiC pin diode as 1st Embodiment of the bipolar semiconductor element of this invention. It is sectional drawing which shows the cross section of the npn bipolar transistor as 2nd Embodiment of the bipolar semiconductor element of this invention. It is sectional drawing which shows the cross section of IGBT as 3rd Embodiment of the bipolar semiconductor element of this invention. It is a figure which shows typically the carrier density distribution corresponding to the semiconductor laminated structure of the SiC bipolar semiconductor element of the said 1st Embodiment. It is a figure which shows typically the carrier laminated distribution (room temperature, low current density) corresponding to the semiconductor laminated structure of the conventional SiC bipolar semiconductor element. It is a figure which shows typically the carrier density distribution (high temperature, high current density) corresponding to the semiconductor laminated structure of the conventional SiC bipolar semiconductor element.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

(First embodiment)
FIG. 1 is a cross-sectional view of a pn junction diode (pin diode) 20 as a first embodiment of a bipolar semiconductor device of the present invention. In the manufacturing process of the first embodiment, a semiconductor layer described below is formed on a substrate 21 made of n-type 4H SiC as the first conductivity type. The 4H type “H” represents a hexagonal crystal, and the 4H type “4” represents a crystal structure in which the atomic stacking has a four-layer period.

  In the manufacturing process of the first embodiment, n-type 4H—SiC and p-type (second conductivity type) 4H—SiC are sequentially epitaxially grown on the n-type 4H type SiC substrate 21 as described later. Next, the epitaxial pin diode 20 is fabricated.

The n-type 4H SiC substrate 21 shown in FIG. 1 was prepared by slicing an ingot grown by the modified Rayleigh method with an off angle θ of 8 degrees and mirror-polishing. The carrier density of the SiC substrate 21 determined by the Hall effect measurement method is 8 × 10 ¹⁸ cm ⁻³ and the thickness is 400 μm.

A nitrogen-doped n-type SiC layer (n-type growth layer) and an aluminum-doped p-type SiC layer (p-type growth layer) are sequentially formed on the C-plane (carbon surface) of the substrate 21 by CVD. The n-type growth layer, which is the nitrogen-doped n-type SiC layer, becomes the n-type buffer layer 22 and the n-type drift layer 23 shown in FIG. The buffer layer 22 serving as the cathode has a donor density of 7 × 10 ¹⁷ cm ⁻³ and a film thickness of 10 μm. The drift layer 23 has a donor density of about 5 × 10 ¹⁵ cm ⁻³ and a film thickness of 300 μm.

On the other hand, the p-type growth layer, which is the aluminum-doped p-type SiC layer, becomes the p-type junction layer 24 and the p + -type contact layer 25 that become the anode. The p-type bonding layer 24 has an acceptor density of 5 × 10 ¹⁷ cm ⁻³ and a film thickness of 1.5 μm. The p + type contact layer 25 has an acceptor density of about 1 × 10 ¹⁸ cm ⁻³ and a film thickness of 0.5 μm.

  In the manufacturing process of the pin diode 20 of this embodiment, an n-type buffer layer 22, an n-type drift layer 23, a p-type junction layer 24, and a p + type contact layer 25 are sequentially formed on the SiC substrate 21. However, the processing conditions during the production will be described in more detail below.

First, in the manufacturing process of the pin diode 20 of this embodiment, silane (SiH ₄ ) and propane (C ₃ H ₈ ) are used as material gases. Nitrogen (N ₂ ) and trimethylaluminum (Al (CH ₃ ) ₃ ) are used as dopant gases. Further, hydrogen (H ₂ ) is used as a carrier gas. The flow rate of each gas is represented by sccm (standard cc per minute) or slm (standard liter minute). The pressure is expressed in kPa (kilo pascal). Moreover, in the following description, the numerical value in the parenthesis attached after the name of each gas represents a flow rate. The temperature of the SiC substrate 21 is kept at 1550 ° C., and the pressure in the processing chamber is kept at 5.6 kPa.

  In the step of forming the buffer layer 22 as an n-type SiC growth layer on the C-plane of the n-type 4HS SiC substrate 21, silane (30 sccm) as a silicon source gas, propane (12 sccm), nitrogen (30 sccm) as a carbon source gas, and Hydrogen (10 slm) is supplied as a carrier gas. The processing time for this step is 40 minutes.

  In the step of forming the drift layer 23 which is an n-type SiC growth layer, silane (30 sccm), propane (12 sccm), nitrogen (0.2 sccm) and hydrogen (10 slm) are supplied. The processing time for this step is 1200 minutes. In the step of forming the P-type bonding layer 24, silane (30 sccm), propane (12 sccm), trimethylaluminum (15 sccm), and hydrogen (10 slm) are supplied. The processing time for this step is 6 minutes. In the step of forming the p + -type contact layer 25, silane (30 sccm), propane (12 sccm), trimethylaluminum (30 sccm) and hydrogen (10 slm) are supplied. The processing time for this step is 2 minutes.

  Next, after the epitaxial growth as described above, all portions of the n-type 4HSiC substrate 21 were removed by CMP (chemical mechanical polishing). In addition, after the step of forming the drift layer 23 and before the step of forming the P-type bonding layer 24, all portions of the n-type 4HS SiC substrate 21 are removed by CMP (chemical mechanical polishing). Also good.

  The SiC epitaxial wafer for the pin diode of the first embodiment can be manufactured by the processing of each of the above forming steps.

  Next, by subjecting the SiC epitaxial wafer according to the first embodiment to processing described below, the pin diode 20 of this embodiment shown in FIG. 1 can be manufactured.

First, both ends of the SiC epitaxial wafer are removed by reactive ion etching (RIE) and processed into a mesa structure. As an etching gas in this RIE, CF ₄ (carbon tetrafluoride) and O ₂ were used, and etching was performed to a depth of about 2.5 μm by a plasma processing apparatus under conditions of a pressure of 5 Pa and a high frequency power of 260 W. Further, as a mask material at this time, a SiO ₂ film (thickness 10 μm) deposited by CVD was used.

Next, in order to alleviate electric field concentration at the bottom of the mesa formed by etching, a p-type JTE (junction termination extension) 26 having a width of 250 μm and a depth of 0.7 μm was provided on the mesa bottom. The p-type JTE 26 was formed by Al ion implantation. The energy of the Al ion implantation is changed in six steps between 30 to 450 keV, and the total dose is 1.2 × 10 ¹³ cm ⁻² . In addition, when the p-type JTE 26 was formed, the JTE 26 injection layer was designed to have a box profile. Ion implantation was all performed at room temperature, and graphite (thickness 5 μm) was used as a mask for ion implantation. Heat treatment for activating the implanted ions was performed in an argon gas atmosphere at 1700 ° C. for 3 minutes. After the annealing, a thermal oxide film 27 as a protective film was formed by wet oxidation at a temperature of 1200 ° C. for 3 hours. In FIG. 1, reference numeral 30 denotes an insulating protective film (or oxide film).

  Next, Ni (thickness 350 nm) is formed on the lower surface of the n-type SiC buffer layer 22 to be the cathode to form the cathode electrode 28. A film of Ti (titanium: thickness 350 nm) and Al (aluminum: thickness 100 nm) is deposited on the P + type contact layer 25 to form an anode electrode 29. The anode electrode 29 is composed of a Ti layer 29a and an Al layer 29b. Finally, heat treatment is performed at 1000 ° C. for 20 minutes to make the cathode electrode 28 and the anode electrode 29 ohmic electrodes, respectively. The size of the pn junction is 2.6 mmφ and is almost circular. In this embodiment, the p-type JTE 26 is formed by aluminum ion implantation. However, the same effect can be obtained even when boron (B) ion implantation is used.

The pin diode 20 of the first embodiment has a withstand voltage of 20 kV and an on-voltage of 5.0V. The pin diode 20 was energized in the forward direction at a current density of 200 A / cm ² for 1 hour, and the current-voltage characteristics at room temperature immediately after starting energization and after energization for 1 hour were measured with a curve tracer. As a result of this measurement, the forward voltage difference ΔVf between the forward current voltage characteristic immediately after the start of energization at a forward current density of 200 A / cm ² and the forward current voltage characteristic after 1 hour energization is 0.1 V or less. There was almost no difference. Therefore, the pin diode 20 of the first embodiment hardly deteriorated even after the energization for 1 hour described above.

  On the other hand, after the epitaxial growth described above, the comparison pin diode in which the substrate 21 was left without removing the substrate 21 and the cathode electrode 28 was formed on the lower surface of the substrate 21 was performed on the first embodiment. The current-voltage characteristics at room temperature immediately after the start of energization and after energization for 1 hour were measured with a curve tracer. As a result of this measurement, the forward voltage difference ΔVf was 20 V or less, and an increase in the forward voltage was observed.

  Next, referring to FIG. 4, the effect of preventing the increase of the forward voltage by removing all the parts of the n-type SiC substrate 21 will be qualitatively described. The left side of FIG. 4 schematically shows the stacked structure of the pin diode 20 of the first embodiment, and the right side of FIG. 4 schematically shows the carrier density distribution corresponding to the stacked structure. In FIG. 4, a curve K1 represents an electron density distribution, and a curve K2 represents a hole density distribution. As described above, since the n-type SiC substrate 21 is removed, the phenomenon that basal plane dislocations contained in the substrate expand to stacking faults when minority carriers (holes) reach the substrate during forward energization is eliminated. Can do. That is, since the n-type SiC substrate 21 has been removed, holes (minority carriers) reach the n-type SiC substrate 21 even under conditions of high temperature and high current density, as indicated by symbol G on the right side of FIG. There is no phenomenon, and there is no phenomenon in which stacking faults expand from the n-type SiC substrate 21, and the pin diode 20 that can prevent an increase in the forward voltage can be realized.

  As described above, according to the SiC pin diode 20 of the first embodiment, after the epitaxial growth as described above, all parts of the n-type 4HS SiC substrate 21 are removed by CMP (chemical mechanical polishing). The phenomenon that the basal plane dislocations contained in the substrate expand into stacking faults can be eliminated by the minority carriers reaching the substrate during forward energization. As a result, almost no forward voltage deterioration occurs, so that it can be used for a long time and the life is extended. In the first embodiment, since there is no increase in on-resistance due to forward voltage degradation, an internal loss does not increase, and a highly reliable pin diode that can maintain stable characteristics for a long time can be obtained.

  In the first embodiment, the thickness of the n-type SiC buffer layer 22 is 10 μm. However, the thickness of the buffer layer 22 may be 10 μm or less. For example, the thickness of the buffer layer 22 can be set to a minority carrier diffusion distance of 2.5 μm or less, thereby suppressing the crystal growth time and suppressing the resistance of the buffer layer to suppress an increase in device loss. Can do.

  In consideration of the formation of the cathode electrode 28 under the buffer layer 22 and the crystal growth conditions, the lower limit value of the thickness of the buffer layer is set to 0.5 μm as an example.

(Second embodiment)
Next, FIG. 2 shows a second embodiment of the bipolar semiconductor device of the present invention. FIG. 2 is a cross-sectional view of an npn bipolar transistor 50 as the second embodiment. Also in the manufacturing process of the second embodiment, an n-type 4H SiC substrate is employed. On this n-type 4H-type SiC substrate, n-type 4H-SiC, p-type 4H-SiC, and n-type 4H-SiC were successively epitaxially grown in this order to produce an npn bipolar transistor 50.

  In the npn bipolar transistor of the second embodiment, in the manufacturing process, n-type 4H—SiC, p-type 4H—SiC, on the (000-1) carbon surface of the substrate using n-type 4H-type SiC, An npn bipolar transistor 50 was fabricated by epitaxial growth in the order of n-type 4H—SiC.

The n-type 4H-type SiC substrate 51 was prepared by slicing an ingot grown by the modified Rayleigh method so that the off angle θ was 8 degrees, and mirror polishing. The substrate 51 is n-type, has a carrier density of 8 × 10 ¹⁸ cm ⁻³ and a thickness of 400 μm as measured by the Hall effect measurement method. A buffer layer 52 and a drift layer 53 of a nitrogen-doped n-type SiC layer are formed on the C surface of the substrate 51 by a CVD method.

  On this drift layer 53, an aluminum-doped p-type SiC p-type growth layer 54 and a nitrogen-doped n-type SiC layer n-type growth layer 55 were sequentially formed by an epitaxial growth method. The buffer layer 52 and the drift layer 53 become an n-type collector layer.

The buffer layer 52 has a donor density of 7 × 10 ¹⁷ cm ⁻³ and a film thickness of 10 μm. The drift layer 53 has a donor density of about 5 × 10 ¹⁵ cm ⁻³ and a film thickness of 15 μm. The p-type growth layer 54 to be the p-type base layer has an acceptor density of 2 × 10 ¹⁷ cm ⁻³ and a film thickness of 1 μm. The n-type growth layer 55 has a donor density of about 7 × 10 ¹⁷ cm ⁻³ and a film thickness of 0.75 μm.

Next, processing conditions for manufacturing the npn bipolar transistor 50 of this embodiment will be described. Silane (SiH ₄ ) and propane (C ₃ H ₈ ) are used as material gases. Nitrogen (N ₂ ) and trimethylaluminum {Al (CH ₃ ) ₃ } are used as dopant gases. Further, hydrogen (H ₂ ) is used as a carrier gas. The temperature of the substrate is kept at 1550 ° C., and the pressure in the processing chamber is kept at 5.6 kPa. The flow rate of each gas is represented by sccm (standard cc per minute) or slm (standard liter minute). The pressure is expressed in kPa (kilo pascal). In the following description, the numerical value in parentheses after the name of each gas represents the flow rate.

  In the step of forming the buffer layer 52 on the C-plane of the n-type 4HSiC substrate 51, silane (30 sccm), propane (12 sccm), nitrogen (30 sccm) and hydrogen (10 slm) are supplied. The processing time for this step is 40 minutes. In the step of forming the drift layer 53, silane (30 sccm), propane (12 sccm), nitrogen (0.2 sccm), and hydrogen (10 slm) are supplied. The processing time for this step is 60 minutes.

  In the step of forming the P-type growth layer 54, silane (30 sccm), propane (12 sccm), trimethylaluminum (6 sccm) and hydrogen (10 slm) are supplied. The processing time for this step is 4 minutes. In the step of forming the n-type growth layer 55, silane (30 sccm), propane (12 sccm), nitrogen (30 sccm), and hydrogen (10 slm) are supplied. The processing time for this step is 3 minutes.

  Next, after the epitaxial growth as described above, all portions of the n-type 4HSiC substrate 51 were removed by CMP (chemical mechanical polishing). Note that after the step of forming the drift layer 53 and before the step of forming the P-type growth layer 54, all portions of the n-type 4HS SiC substrate 51 are removed by CMP (chemical mechanical polishing). Also good.

  The SiC epitaxial wafer for the npn bipolar transistor of the second embodiment can be manufactured by the processing of each of the above steps.

  Then, the npn bipolar transistor 50 of the second embodiment shown in FIG. 2 can be manufactured by performing the processing described below on the SiC epitaxial wafer for the second embodiment.

First, the n-type growth layer 55 is etched by reactive ion etching (RIE) with a width of 10 μm, a depth of 0.75 μm, and a pitch of 23 μm, leaving an n-type growth layer 55 that becomes an emitter. As the etching gas for RIE, CF ₄ and O ₂ were used, and the etching was performed under the conditions of a pressure of 0.05 Torr and a high frequency power of 260 W. Further, as a mask material at this time, a SiO ₂ film (thickness 10 μm) deposited by CVD was used.

Next, in order to perform element isolation in the base region, a mesa structure is formed by reactive ion etching (RIE). CF ₄ and O ₂ were used as the etching gas for this RIE, and the etching was performed to a depth of about 1 μm under the conditions of a pressure of 0.05 Torr and a high frequency power of 260 W. As a mask material at this time, a SiO ₂ film (thickness 10 μm) deposited by CVD was used.

  In the second embodiment, the guard ring 56 for relaxing the electric field concentration at the base end and the base contact region 57 are formed by Al (aluminum) ion implantation in the same process. The base contact region 57 has a width of 3 μm, a distance from the emitter of 5 μm, and the p-type guard ring 56 has a width of 150 μm. Both the contact region 57 and the p-type guard ring 56 have a depth of 0.5 μm.

The energy of Al ion implantation when forming the p-type guard ring 56 and the base contact region 57 is 40 to 560 keV, and the total dose is 1.0 × 10 ¹³ cm ⁻² . As a mask for this ion implantation, a SiO ₂ film (thickness 5 μm) formed by CVD was used. All ion implantations were performed at room temperature, and the heat treatment for activating the implanted ions was performed under conditions of a temperature of 1600 ° C. in an argon gas atmosphere for 5 minutes.

Next, after annealing, a thermal oxide film was formed by wet oxidation at a temperature of 1150 ° C. for 2 hours, and a SiO ₂ film was further deposited by CVD to form an oxide film 58 having a total thickness of 2 μm.

  Next, a collector electrode 59C is formed on the lower surface of the n-type SiC buffer layer 22 that becomes the collector. A base electrode 59B is formed in the base contact region 57. Further, Ni is deposited on the emitter region 55 to form an emitter electrode 69. Next, heat treatment was performed at 1000 ° C. for 20 minutes to form ohmic junctions.

  Finally, the base electrode 59B and the emitter electrode 69 were covered with a Ti / Au electrode 70 to form each electrode terminal. The size of the joint is 3.2 mm × 3.2 mm. In the second embodiment, the guard ring 56 is formed by Al ion implantation, but the same effect can be obtained even when B (boron) ion implantation is used.

  In addition, in the npn bipolar transistor 50 and its manufacturing process, the junction surfaces (surfaces extending in the horizontal direction in the drawing) of the substrate 51, the buffer layer 52, the drift layer 53, the p-type growth layer 54, and the n-type growth layer 55 are as follows. All are parallel to the surface 2 a having an off angle of 8 degrees from the (000-1) carbon surface 2.

The npn bipolar transistor 50 thus fabricated has a withstand voltage of 1400V. The on-resistance was 8.0 mΩcm ² and the maximum current amplification factor was about 12. The npn bipolar transistor 50 was energized with a base current of 0.6 A and a collector current of 14 A (collector current density of 200 A / cm ² ) for 1 hour, and the collector characteristics at room temperature before and after the energization were measured with a curve tracer. In the npn bipolar transistor 50 of this embodiment, the on-resistance was 8.0 mΩ / cm ² immediately after the start of energization and after 1 hour of energization, and there was almost no change in the forward voltage.

On the other hand, even after the above-described epitaxial growth, a base current of 0.6 A and a collector current are also obtained for the npn bipolar transistor of the comparative example in which the substrate 51 is left without being removed and the collector electrode 59C is formed on the lower surface of the substrate 51. The test was conducted by energizing at a density of 200 A / cm ² . The on-resistance at room temperature of this comparative npn bipolar transistor was 8.0 mΩ / cm ² immediately after the start of energization, but became very large at 15.0 mΩ / cm ² after energization for 1 hour. Further, the maximum current amplification factor at room temperature of the npn bipolar transistor of this comparative example was about 12 at the beginning of energization, but decreased to about 6 after energization for 1 hour.

  On the other hand, the maximum current amplification factor of the npn bipolar transistor 50 of the second embodiment was about 12 with almost no change immediately after energization and after energization for 1 hour. As described above, in the npn bipolar transistor 50 of the second embodiment, almost no forward voltage deterioration occurred even after a 1-hour energization test.

  As described above, according to the SiC npn bipolar transistor 50 of the second embodiment, after the epitaxial growth as described above, all portions of the n-type 4HS SiC substrate 51 are removed by CMP (chemical mechanical polishing). Therefore, it is possible to eliminate the phenomenon that the basal plane dislocations included in the substrate expand to stacking faults when the minority carriers reach the substrate during forward energization.

  As a result, almost no forward voltage deterioration occurs, so that it can be used for a long time and the life is extended. In the second embodiment, since there is almost no increase in on-resistance due to forward voltage degradation, an internal loss is not increased, and a highly reliable npn bipolar transistor capable of maintaining stable characteristics for a long time is obtained. It is done.

  In the second embodiment, the thickness of the n-type SiC buffer layer 52 is 10 μm. However, the thickness of the buffer layer 52 may be 10 μm or less. For example, the thickness of the buffer layer 52 can be set to a minority carrier diffusion distance of 2.5 μm or less, thereby suppressing the crystal growth time and suppressing the resistance of the buffer layer to suppress an increase in device loss. Can do.

  In consideration of the formation of the collector electrode 59C under the buffer layer 52 and the crystal growth conditions, the lower limit value of the thickness of the buffer layer is, for example, 0.5 μm.

(Third embodiment)
Next, FIG. 3 shows a cross section of an IGBT (insulated gate bipolar transistor) 80 as a third embodiment of the bipolar semiconductor device of the present invention.

  In the manufacturing process, the IGBT 80 has a p-type 6H-SiC layer and an n-type 6H-SiC layer on the substrate 71 made of n-type 6H-type SiC at a rate of increase in film thickness per time (h) of 15 μm / h. Three layers were epitaxially grown in the order of the p-type 6H—SiC layer, and an IGBT 80 was fabricated as described in detail below. In this IGBT 80, the main joint surface of the p layer and the n layer (the surface extending in the direction perpendicular to the paper surface in the figure) is the {0001} plane.

  Next, a method for manufacturing the IGBT 80 will be described. That is, a p-type film is formed on a substrate using n-type 6H-type SiC having a surface orientation of an off angle θ of 3.5 degrees from the (000-1) carbon surface at a film formation rate of 15 μm / h. A 6H—SiC layer, an n-type 6H—SiC layer, and a p-type 6H—SiC layer are sequentially formed.

The SiC substrate 71 was prepared by slicing an ingot grown by the modified Rayleigh method at a surface inclined by 3.5 degrees from the (000-1) carbon surface and mirror polishing. The SiC substrate 71 is n-type, the thickness is 400 μm, and the carrier density obtained by the Hall effect measurement method is 5 × 10 ¹⁸ cm ⁻³ .

Three layers of an aluminum-doped p-type SiC layer, a nitrogen-doped n-type SiC layer, and an aluminum-doped p-type SiC layer were continuously epitaxially grown on this SiC substrate 71 by the CVD method. This p-type SiC layer becomes the buffer layer 72 and the drift layer 73 of FIG. The buffer layer 72 has an acceptor density of 1 × 10 ¹⁷ cm ⁻³ and a film thickness of 3 μm. The drift layer 73 has an acceptor density of about 5 × 10 ¹⁵ cm ⁻³ and a film thickness of 15 μm. The n-type growth layer 74 formed on the drift layer 73 has a donor density of 2 × 10 ¹⁷ cm ⁻³ and a film thickness of 2 μm. The p-type growth layer 75 formed on the n-type growth layer 74 has an acceptor density of about 1 × 10 ¹⁸ cm ⁻³ and a film thickness of 0.75 μm.

  Next, processing conditions when manufacturing this IGBT 80 will be described.

First, silane (SiH ₄ ) and propane (C ₃ H ₈ ) are used as material gases. Further, nitrogen (N ₂ ) and trimethylaluminum {Al (CH ₃ ) ₃ } are used as dopant gases. Further, hydrogen (H ₂ ) is used as a carrier gas. Here, the flow rate of each gas is represented by sccm (standard cc per minute) or slm (standard liter minute). The pressure is expressed in kPa (kilo pascal). Moreover, in the following description, the numerical value in the parenthesis attached after the name of each gas represents a flow rate.

  The temperature of the n-type SiC substrate 71 is kept at 1550 ° C., and the pressure in the processing chamber is kept at 5.6 kPa. In the step of forming the p-type SiC buffer layer 72 on the C-plane of the n-type SiC substrate 71, silane (30 sccm), propane (12 sccm), trimethylaluminum (3 sccm) and hydrogen (10 slm) are supplied. The processing time for this step is 12 minutes.

  Next, in the step of forming the p-type SiC drift layer 73, silane (30 sccm), propane (12 sccm), trimethylaluminum (0.15 sccm) and hydrogen (10 slm) are supplied. The processing time is 60 minutes.

  Next, in the step of forming the n-type growth layer 74, silane (30 sccm), propane (12 sccm), nitrogen (9 sccm) and hydrogen (10 slm) are supplied. The processing time for this step is 8 minutes. In the step of forming the p-type growth layer 75, silane (30 sccm), propane (12 sccm), trimethylaluminum (30 sccm) and hydrogen (10 slm) are supplied. The processing time for this step is 3 minutes.

  Next, after the epitaxial growth as described above, all portions of the n-type SiC substrate 71 were removed by CMP (chemical mechanical polishing). Note that all parts of the n-type SiC substrate 71 are removed by CMP (Chemical Mechanical Polishing) after the formation process of the drift layer 73 and before the formation process of the n-type growth layer 74. Also good.

  The SiC epitaxial wafer for IGBT 80 can be obtained by the processing in each of the above steps.

  And the IGBT80 shown in FIG. 3 can be produced by performing the process demonstrated below to the SiC epitaxial wafer for said 3rd Embodiment.

First, by using photolithography, the central portion of the p + growth layer 75 is etched by RIE to form a hole 76a, and nitrogen is ion-implanted to form a contact region 76 to be an emitter. Next, in order to form a gate region, the p + growth layer 75 and the n + growth layer 74 are etched by RIE to form holes 78a (two in FIG. 3). Next, an SiO ₂ film is deposited by CVD to form an insulating film 77 in order to form a MOS structure on the wall surface of the hole 78a. Next, Ni is deposited on the collector region of the n-type SiC buffer layer 72 to form the collector terminal 79C. Further, an emitter electrode 79 is deposited on the contact region 76. Next, heat treatment is performed to form ohmic junctions. Further, a Mo electrode is formed on the insulating film 77 to form a gate electrode 78.

The IGBT 80 according to the present embodiment thus completed has a withstand voltage of 900 V, an on-resistance of 11 mΩcm ² , and a collector-emitter voltage of −14 V. Further, a gate voltage of −40 V was applied to the IGBT 80, a collector current of 1.4 A was applied for 1 hour, and the collector characteristics at room temperature at the start of energization and after the energization for 1 hour were measured with a curve tracer. In this IGBT 80, it was found that the collector-emitter voltage immediately after energization and after energization for 1 hour was -14 V, almost no change and therefore almost no deterioration.

On the other hand, in the IGBT of the comparative example in which the substrate 71 is left without removing the substrate 71 and the collector terminal 79C is formed on the lower surface of the substrate 71 after the epitaxial growth described above, the withstand voltage is 900 V and the on-resistance is 11 mΩcm ^2. The collector-emitter voltage is -14V. Further, a gate voltage of −40 V was applied to the IGBT of this comparative example, a collector current of 1.4 A was applied for 1 hour, and the collector characteristics at room temperature at the start of energization and after the energization for 1 hour were measured with a curve tracer. In the IGBT of this comparative example, the collector-emitter voltage immediately after energization was −14 V, whereas the collector-emitter voltage after 1 hour energization was as large as −29 V.

  On the other hand, according to the IGBT 80 of the present embodiment, after the epitaxial growth as described above, all the portions of the n-type SiC substrate 71 are removed by CMP (chemical mechanical polishing). The phenomenon that the basal plane dislocation contained in the substrate expands to stacking faults by the carrier reaching the substrate can be eliminated.

  As a result, almost no forward voltage deterioration occurs, so that it can be used for a long time and the life is extended. Further, in this third embodiment, since there is almost no increase in on-resistance due to forward voltage degradation, an internal loss is not increased, and a highly reliable IGBT that can maintain stable characteristics for a long time can be obtained.

  In the third embodiment, the thickness of the p-type SiC buffer layer 72 is 3 μm. However, the thickness of the buffer layer 72 may be 3 μm or less. For example, the thickness of the buffer layer 72 can be set to 2.5 μm or less. In this case, the crystal growth time can be suppressed, and the resistance of the buffer layer can be suppressed to suppress an increase in device loss. In consideration of the formation of the collector terminal 79C under the buffer layer 72 and the crystal growth conditions, the lower limit value of the thickness of the buffer layer is set to 0.5 μm as an example.

  In the above, the SiC pin diode, the npn bipolar transistor, and the IGBT have been described as the embodiments of the SiC bipolar semiconductor device of the present invention. However, the present invention is not limited to the above embodiment, and the SIAFET, SIJFET are not limited thereto. Applicable to various 4H-SiC bipolar semiconductor devices such as thyristors, GTO, MCT (Mos Controlled Thyristor), SiCGT (SiC Commutated Gate Thyristor), EST (Emitter Switched Thyristor), BRT (Base Resistance Controlled Thyristor) It is. Of course, the present invention can be applied to various 4H-SiC bipolar elements such as elements having opposite polarities (for example, pnp transistors for npn transistors), and can be applied to SiC bipolar elements using various crystal structures such as 6H-SiC. Is.

  Since the SiC bipolar semiconductor element of the present invention has a high withstand voltage and a low on-voltage, it can suppress current loss and can be used with a large current. As an example, a vehicle such as a home appliance field, an industrial field, or an electric vehicle When applied to a power control device incorporated in a power control device such as an inverter in the field, power system field such as power transmission, etc., switching loss can be reduced, and it can be used with a large current and is reliable. Can be improved.

20 pin diode 21 n-type SiC substrate 22 n-type SiC buffer layer 23 n-type SiC drift layer 24 p-type junction layer 25 p + type contact layer 26 p-type JTE
27 Thermal oxide film 28 Cathode electrode 29 Anode electrode 30 Insulating protective film 50 npn bipolar transistor 51 n-type SiC substrate 52 n-type SiC buffer layer (collector layer)
53 n-type SiC drift layer (collector layer)
54 p-type growth layer (base layer)
55 n-type growth layer (emitter layer)
56 p-type guard ring 57 contact region 58 oxide film 59B base electrode 69 emitter electrode 71 6H-type SiC substrate 72 p-type SiC buffer layer 73 p-type SiC drift layer 74 n-type growth layer 75 p-type growth layer 76 contact region 77 insulating film 78 Gate electrode 79 Emitter electrode 80 IGBT

Claims (8)

Forming a buffer layer of a first conductivity type with a silicon carbide semiconductor on a substrate made of a silicon carbide semiconductor;
Forming a drift layer of a first conductivity type with a silicon carbide semiconductor on the buffer layer;
A method for manufacturing a bipolar semiconductor element, wherein a second conductivity type semiconductor layer is formed of a silicon carbide semiconductor on the drift layer,
Of the first conductivity type buffer layer, the first conductivity type drift layer, and the second conductivity type semiconductor layer, at least the first conductivity type buffer layer and the first conductivity type drift layer are disposed on the substrate. A method for manufacturing a bipolar semiconductor device, comprising: forming a substrate on the substrate and then removing the substrate made of the silicon carbide semiconductor. In the manufacturing method of the bipolar semiconductor device according to claim 1,
A method of manufacturing a bipolar semiconductor device, comprising: forming the buffer layer, the drift layer, and the second conductivity type semiconductor layer on the substrate; and removing the substrate. A first conductivity type buffer layer made of a silicon carbide semiconductor;
A drift layer of a first conductivity type formed on the buffer layer and made of a silicon carbide semiconductor;
A second conductivity type semiconductor layer formed on the drift layer and made of a silicon carbide semiconductor;
Of the first conductivity type buffer layer, the first conductivity type drift layer, and the second conductivity type semiconductor layer, at least the first conductivity type buffer layer and the drift layer are made of a silicon carbide semiconductor. A bipolar semiconductor device, wherein the substrate is removed after being formed on the substrate. The bipolar semiconductor device according to claim 3, wherein
A bipolar semiconductor device, wherein the substrate is removed after forming the buffer layer, the drift layer, and the semiconductor layer of the second conductivity type on the substrate. The bipolar semiconductor device according to claim 3 or 4,
A bipolar semiconductor device, wherein the buffer layer has a thickness of 2.5 μm or less. In the bipolar semiconductor device according to any one of claims 3 to 5,
A bipolar semiconductor device, wherein the buffer layer is a cathode and the second conductivity type semiconductor layer formed on the drift layer is an anode. In the bipolar semiconductor device according to any one of claims 3 to 5,
The buffer layer is a collector layer and the second conductivity type semiconductor layer formed on the drift layer is a base layer,
A bipolar semiconductor device comprising a transistor having a first conductivity type emitter layer formed on the base layer and made of a silicon carbide semiconductor. In the bipolar semiconductor device according to any one of claims 3 to 5,
The buffer layer is a collector layer,
A bipolar semiconductor device, characterized in that it is an IGBT formed on the second conductivity type semiconductor layer and having an emitter layer made of a first conductivity type silicon carbide semiconductor.

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