JP2012022569A - Arithmetic control apparatus, control method of the same and control program for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To confirm whether or not values of a plurality of registers are matched during register read of a CPU.SOLUTION: A comparative determination section 40 performs a comparison about whether or not all test data held in registers 21-2n are matched and outputs a comparison result as a full comparison result I. The comparative determination section 40 performs a comparison about whether or not a value of any one of the registers 21-2n selected by a data selection section 30 is matched with each of the values of the registers 21-2n and outputs a comparison result as individual comparison results J to M. Selected read data and the full comparison result I are concatenated by a bit concatenation section 50 and outputted as a read data+full comparison result F.

Description

  The present invention relates to an arithmetic and control unit, and in particular, compares the values of a plurality of registers, determines whether all the register values match, and compares each register value with respect to a reference register value. The present invention relates to an arithmetic control device that performs individual comparison determination as to whether or not the values of the two match.

  LSI (Large Scale Integration) has various functions such as arithmetic functions and memory functions mounted on a single chip as functional blocks, and more functions have been developed in recent years due to advances in manufacturing technology. High integration is advancing with blocks.

  Until now, since the scale of the LSI has not been so large, the number of function blocks that implement the above-mentioned predetermined functions is small, and the value held in the register for controlling each function block is changed to the CPU ( Central processing unit) did not occupy much processing time for confirmation processing when reading.

  However, the number of function blocks to be mounted increases as the LSI size increases, and as a result, the number of registers that control the function blocks increases, so the time to check the register values when reading the registers increases. Increased. For this reason, there has been a problem that the processing time of the CPU increases and the throughput indicating the processing capability of the computer is reduced.

  On the other hand, there are Patent Documents 1 to 2 as the contents of the above-mentioned technical fields that have been specifically known conventionally.

  The technique disclosed in Patent Document 1 compares whether or not the values of a plurality of registers match with each other by a comparison circuit, and connects the comparison result with the value of a register read by the CPU. When the CPU reads as a read data, the CPU determines whether or not the values of the other registers match when reading the value of any register, and does not check the value of each register individually. It is a technology that can confirm the value of.

In addition, the technique disclosed in Patent Document 2 stores the same test data in all areas of a RAM (Random Access Memory) and each of the comparison registers, and sequentially stores the stored contents from the top area of the RAM. This is a technique that can detect a defective bit in the RAM by reading, comparing the read value with the value of the comparison register by a comparison circuit, and determining whether or not they match.

JP2009-289071 JP 2003-297100 A

  However, since the techniques disclosed in Patent Documents 1 and 2 hold only two types of determination results in which register values or RAM values all match or do not match, registers that do not specifically match values. Alternatively, it is difficult to immediately specify the RAM area.

(Object of invention)
The present invention improves the above-mentioned disadvantages of the related art, and when the CPU reads the register values, it can simultaneously read all the comparison results as to whether or not all the values of the plurality of registers match. It is an object of the present invention to provide an arithmetic and control unit that can read the individual comparison result of each register when the comparison results are inconsistent.

  In order to achieve the above object, an arithmetic and control unit according to the present invention includes a plurality of functional blocks that realize various functions, a CPU that individually transmits command information related to operation control to the functional blocks, and the functions In an arithmetic and control unit comprising a plurality of registers corresponding to blocks and temporarily holding the command information, the CPU has the same data holding command function for holding the same data as test data for each register; And a holding state check function for checking the holding state of the test data held in each register based on an output of a read data comparison circuit provided in common with the register, and the read data comparison circuit includes: The test data held in each register is compared to determine whether or not they match each other, and the comparison determination result is confirmed as the holding state confirmation. All comparisons sent to the CPU for functions and the individual comparison functions are compared to determine whether all the results of the individual comparison functions match, and the comparison results are sent to the CPU for the holding status confirmation function. And having a function.

  The arithmetic control device control method according to the present invention includes a plurality of functional blocks that realize various functions, a CPU that individually transmits command information related to operation control to the functional blocks, and the functional blocks. And a plurality of registers corresponding to and temporarily holding the command information, wherein the CPU holds the same data as test data for each register, and is specified by the CPU A data selection unit in a read data comparison circuit provided in common with each register from any one of the registers selects the test data as read data, and the test of the read data and each register The comparison determination unit in the read data comparison circuit determines whether or not the data match each other, and makes an individual comparison determination, and the individual comparison result The comparison / determination unit determines whether or not all match, and the bit connection unit in the read data comparison circuit connects the read data and the entire comparison result, and the plurality of individual comparison results are connected to the read data. The individual comparison result register in the comparison circuit holds, the CPU confirms the data connected by the bit connection unit, and the CPU holds the individual comparison result register when all the comparison results do not match. It is characterized in that the contents are confirmed.

  Furthermore, the arithmetic control device control program according to the present invention includes a plurality of functional blocks that realize various functions, a CPU that individually transmits command information related to operation control to the functional blocks, and the functional blocks. And a plurality of registers that temporarily hold the command information, the same data holding command function for holding the same data as test data for each register, by the CPU A data selection function for selecting the test data as read data from any one of the specified registers, and whether or not the read data and the test data of each register match each other Individual comparison function, all comparison functions for judging whether all the individual comparison results match, Bit connection function for linking all the comparison results with each other, individual comparison result holding function for holding the plurality of individual comparison results, and checking the data linked by the bit linking unit, and the all comparison results are inconsistent In this case, the computer can realize a holding state checking function for checking the contents held in the individual comparison result register.

  Since the present invention is configured as described above, according to this, the values held in the respective registers are compared, and all comparison results obtained by comparing whether or not all the registers match each other are linked to the read data. As a result, the CPU can check whether or not it matches the value of the register to be read without reading the values of all the registers individually when reading data. Furthermore, by holding the individual comparison results obtained by individually comparing the values of the respective registers in the individual comparison result register, if the values of the register to be read and the values of all the other registers do not match, a mismatch occurs. An excellent arithmetic control device, arithmetic control device control method, and arithmetic control device control program capable of specifying a certain register and shortening the processing time required when the CPU individually reads the value of the register Can be provided.

1 is a block diagram showing a first embodiment of an arithmetic control device according to the present invention. FIG. 2 is a timing diagram illustrating an operation in the block diagram disclosed in FIG. 1. It is a flowchart which shows operation | movement of CPU70 in the block diagram disclosed in FIG. It is a block diagram which shows the structure of the comparison determination part 40 in the block diagram disclosed in FIG. It is a block diagram which shows other embodiment of the arithmetic control apparatus which concerns on this invention.

Embodiment
Hereinafter, an embodiment of an arithmetic control device according to the present invention will be described with reference to FIGS. 1 and 3 to 4.

  First, the arithmetic and control unit according to the embodiment shown in FIG. 1 individually transmits a plurality of function blocks 81 to 8n (n ≧ 3) that realize various functions, and command information related to operation control to the function blocks. And a plurality of registers 21 to 2n corresponding to the functional blocks described above and temporarily holding the command information described above.

  Here, the CPU 70 described above confirms the same data holding command function for holding the same data as the test data in the registers 21 to 2n and the holding state of the test data held in the registers 21 to 2n. It has a function.

  An individual comparison function that compares and determines whether or not the test data held in the registers 21 to 2n match each other, and transmits the comparison determination result to the CPU 70 for the aforementioned holding state confirmation function, and this individual comparison function The registers 21 to 2n share a read data comparison circuit 90 that has a comparison function for comparing whether or not all the results match and transmits the comparison determination result to the CPU 70 for use in the holding state confirmation function. It is attached to.

  The registers 21 to 2n hold test data as initial values by a reset signal transmitted from the CPU 70 via a reset signal line connected in a form not shown.

  Further, the arithmetic and control unit described above includes a data selection unit 30 that selects the test data as read data N from any one of the registers 21 to 2n specified by the CPU 70, and the read data N and Whether or not the test data held in the registers 21 to 2n match is individually compared and determined, the comparison determination results are output as individual comparison results J to M, respectively, and the individual comparison results J to M all match. The comparison determination unit 40 that compares and determines whether or not and outputs the comparison determination result as the total comparison determination result I, and the read data N and the total comparison result I are connected to the CPU 70 for the holding state confirmation function. A bit concatenation unit 50 for transmitting, and an individual comparison result register 60 for holding the individual comparison results J to M for the above-described holding state confirmation function; It is provided.

  The data selection unit 30, the comparison determination unit 40, the bit connection unit 50, and the individual comparison result register 60 can realize the individual comparison function and the full comparison function of the read data comparison circuit 90 described above.

  The comparison determination unit 40 includes a selection circuit 42 that selects the test data held in any one of the registers 21 to 2n designated by the address path B as the comparison data H, and the comparison data H And comparison circuits 41A to 41n that individually compare and determine whether or not the test data of the registers 21 to 2n match and output the determination results as individual comparison results J to M, respectively, and the individual comparison results J to M And a logical product circuit 43 that performs a logical product operation and outputs the result of the operation as a total comparison result I.

  Here, it is assumed that the address path B is allocated corresponding to the registers 21 to 2n. In the present embodiment, the register 21 is registered when the address path B is 00, and the register is registered when the address path B is 01. 22. If the address path is n, it indicates that the register 2n + 1.

  Further, the logical product circuit 43 is used to calculate the above-described total comparison result I. However, the present invention is not limited to this as long as the test data held in the registers 21 to 2n are all compared. Suppose not.

  As a result, the selection circuit 42 reads the test data held in the register indicated by the address path B output from the CPU 70, and the read test data and the test data held in the registers 21 to 2n are compared with the comparators 41A to 41n. Are compared and output as individual comparison results J to M, the logical product circuit 43 performs an AND operation on the individual comparison results J to M, and the operation result can be output as the entire comparison result I.

  The CPU 70 described above writes a write signal A that is a control signal for writing data, an address path B that specifies a data write destination and a read destination, a read signal C that is a control signal for reading data, and a write signal. Write data D that is the contents of the data is output.

  Further, a register selection unit 10 is provided that outputs a chip select signal G that changes any one of the registers 21 to 2n to a writable state based on the write signal A and the address path B described above.

  Thus, data can be written to the registers 21 to 2n by the write data D output from the CPU 70 and the chip select signal G output from the register selection unit 10. The registers 21 to 2n are connected to the functional blocks 81 to 8n by a control signal or the like, and read a register value designated by the address path B by a read signal C and output it as read data N.

  Further, when the CPU 70 reads the data of the register designated by the address path B, the data selection unit 30 outputs the value of the register selected by the address path B as the read data N, and this read data N and the comparison determination unit 40 All the comparison results I output from are connected by the bit linking unit 50 and output as read data + all comparison results F, and the CPU 70 can read this read data + all comparison results F.

  Further, when the CPU 70 reads the test data held by the register, the read data + all comparison result F is read, so that it can be confirmed whether or not the read register and all other registers match. In the case of a mismatch, the CPU 70 can identify the register that does not match by reading the individual comparison result E from the individual comparison result register 60.

[Overall operation]
Next, the overall operation of the arithmetic and control unit will be described with reference to FIGS.
Here, the value of n shown in FIG. 1 is set to 4, the registers 21 to 24 are reset to 4 bits, the write data D and the read data N are both 5 bits, and the registers 21 to 24 are reset to the registers 21 to 24 as a reset signal in a not-shown form. An example in which the signals 21A to 24A are connected will be described.

  The reset signals 21A to 24A described above are reset signals that are valid at the Low level, and start from the reset state. Further, the write signal A and the read signal C are also effective signals at the low level, and can be written or read when at the low level.

  Here, in this embodiment, the registers 21 to 24 are reset by the reset signals 21A to 24A described above, and an initial value 1 is held as test data in each register. However, the CPU 70 registers 21 to 24. When the same specific data is written (the same data holding command process), the same operation is performed by changing the value held in the registers 21 to 24 from the initial value 1 to the specific value described above. .

  In FIG. 2, first, the low level reset signals 21A to 24A are respectively input to the registers 21 to 24 to be in a reset state, and the initial value 1 is held as test data, respectively.

  Next, at time T1, the CPU 70 changes the above-described reset signals 21A to 24A to High level, and releases the reset state for the registers 21 to 24. Subsequently, at time T2, the CPU 70 changes the address path B to 00 and changes the read signal C to the low level.

  In response to the change in the contents of the address path B and the read signal C by the CPU 70 described above, the data selection unit 30 reads the test data held in the register 21 which is a register corresponding to the address path 00 (data Selection step).

Here, the operation of the comparison determination unit 40 will be described with reference to FIG.
The data of the registers 21 to 2n is input to the comparison / determination unit 40, and the register specified by the address path B of the CPU 70 is selected and read by the selection circuit 42 to generate the comparison data H. The comparison data H and the values of the registers 21 to 2n are compared by the comparison circuits 41A to 41n. When they match, 1 is used as a signal, and when they do not match, 0 is used as a signal of the individual comparison results J to M. Output. Further, the entire comparison result I is output through a circuit (for example, a logical product circuit) that becomes 1 when the individual comparison results J to M all match.

  The operation of the above-described comparison / determination unit 40 will be specifically described as follows. Since the value of the address path B connected in a form not shown is 00, the selection circuit 42 of the comparison / determination unit 40 selects the test data input from the register 21 that is a register corresponding to this address path, and The selected data is output to the comparison circuits 41A to 41D as selection data H (value is 1).

  The comparator 41A compares and determines whether or not 1 which is the value of the comparison data H described above and 1 which is the value of the test data held in the register 21 and output from the register 21 match. 1 shown is output as an individual comparison result J (individual comparison process). Similarly, the comparison circuit 41B compares whether or not 1 as the comparison data H and 1 as the test data of the register 22 match, and outputs 1 indicating the match as an individual comparison result K. The comparison circuit 41C and the comparison circuit 41D also compare whether or not the comparison data H matches the test data held in the registers 23 to 24, and outputs 1 as both comparison results L and M.

The above-mentioned individual comparison result J is the least significant bit, the individual comparison result K is the most significant bit from the least significant bit, the individual comparison result L is the most significant two bits from the least significant bit, and the individual comparison result M is the least significant three bits. When arranged in the upper bits, the individual comparison results J to M are 1111b (FH (F) ₁₆ = (1111) ₂ ).

  On the other hand, the AND circuit 43 performs an AND operation (1AND1AND1AND1) on the individual comparison results J to M (value is 1111) output from the comparison circuits 41A to 41D, and the result 1 of the logical product operation is It is calculated and 1 is output as the total comparison result I (all comparison process).

  Subsequently, the bit concatenation unit 50 arranges 1 which is the value of the test data held in the register 21 selected by the data selection unit 30 as the least significant bit, and the logical product of the comparison determination unit 40 described above. 1 which is the value of all the comparison results I output from the circuit 43 is arranged in the most significant bit from the least significant bit, and these two bits are concatenated (bit concatenation step). Is output.

  For this reason, the CPU 70 reads 11 which is the value of the read data + all comparison results F and refers to 1 which is the value of the most significant bit (all comparison results), so that the registers 21 to 24 are all set to 1. I can confirm that I am doing it. This eliminates the need for the CPU 70 to individually read the registers 21 to 24 and determine whether the read data N and the registers 21 to 24 match.

  Subsequently, the above-described 111b is latched in the individual comparison result register 60 as the individual comparison results J to M for the address path 00 at time T3 (individual comparison result holding step). When the CPU 70 changes the address path B to 01, the write signal A to the low level, the read signal C to the high level, the write data D to Fh, and writes Fh as the write data D to the address 01, the write signal Fh, which is write data D, is written to the register 22 at the rising edge of the clock signal in the low period A, and the data held in the register 22 is changed from 1 which is test data to Fh.

At time T4, the CPU 70 sets the address path B to 00 and the read signal C to the low level, and reads the register 21. The comparison determination unit 40 compares and determines the value of the register 21 that is the address path 00 and the values of the registers 21 to 24. At this time, since the value in the register 21 becomes Fh at the above-described time T3, the comparison circuit 41B compares Fh that is the value of the register 22 with 1 that is the value of the comparison data H, and does not match. 0 indicating that they do not match is output as the individual comparison result K.

  On the other hand, in the comparison circuit 41A, since the comparison circuits 41C and 41D keep the values of the register 21 and the registers 23 to 24 and the comparison data H is 1, the individual comparison result J, the individual comparison results L and M Both output 1.

  For this reason, the individual comparison result J is 1, the individual comparison result L is 0, the individual comparison result M is 1, and the individual comparison result N is 1. Therefore, when the logical product operation is performed on the individual comparison results J to M, all the operations are performed. 0 is output as the comparison result I

  The bit connection unit 50 bit-links 0 which is the value of all comparison results I and 1 which is selection data of the address path 00 (register 21), and the CPU 70 reads 01 as read data + all comparison results F. Since the value of the most significant bit (all comparison results) is 0, it can be confirmed that the value of all comparison result register 21 and the value other than register 21 do not match.

  At time T5, the individual comparison results J to M are latched in the individual comparison result register 60, and the value held in the individual comparison result register 60 is 1101. Here, the CPU 70 reads the individual comparison result from the individual comparison result register 60 by setting the address path B to XX (arbitrary address) and setting the read signal C to the low level in order to confirm the mismatch address. Since the data in the register 22 is rewritten to Fh at time T3, the data 0Dh obtained by comparing the values of the register 21 and the registers 21 to 24 can be read. Since the comparison bit of the register 21 is “1”, only the register 22 can be identified as a mismatch. At time T6, the address path is set to 01, the read signal C is set to the low level, the register 22 is read, and the details are read. Check.

  Thereafter, when writing is performed with the address path B set to 01 and the write data D set to 01 at time T7, the register 22 becomes 1, and all the registers become 1.

  At time T8, when the address path B is set to 03, the read signal C is set to the low level, and the register 24 is read, the CPU 70 reads 11 as read data + total comparison result F. Here, since all comparison results that are the most significant bits of the read data + all comparison results F are 1, the CPU 70 determines that all of the registers 21 to 24 are 1, and needs to read the registers 21 to 24 individually. Disappears.

  Next, the operation of the CPU 70 will be described with reference to FIG.

  First, when the CPU 70 confirms the register processing performed by the functional blocks 81 to 84 on the registers 21 to 24 corresponding to the functional blocks 81 to 84, the CPU 70 reads the data stored at the head address of the register. (FIG. 3: Step S101).

  Subsequently, the CPU 70 determines whether or not the expected value for checking the test data calculated by the CPU 70 matches the data read from the register (FIG. 3: step S102), and all the data read at the same time. With reference to the comparison bits (all comparison results), it is determined whether or not all comparison bits are 1 (match) (FIG. 3: step S103). If the result of this determination is 1, all the test data held in the registers 21 to 24, which are the register group, match the above-mentioned expected value for confirmation. None (OK) is processed (FIG. 3: step S104), and the process ends normally (FIG. 3: step S105).

  On the other hand, if the read data matches with the expected value for confirmation (FIG. 3: step S102), the comparison bits read at the same time are referred to (FIG. 3: step S103). If all the comparison bits are 0 (mismatch), all of the register groups do not match the expected value for confirmation, so the individual comparison result is read from the individual comparison result register 60 (FIG. 3: step S106), A register that does not match is specified (FIG. 3: step S107), and the process proceeds to the abnormal termination system (FIG. 3: step S108).

  If the result of the determination that the read data is not the expected value for confirmation (FIG. 3: step S102) is a mismatch, all the comparison bits read at the same time are referenced (FIG. 3: step S109). If all the comparison bits are 1 (match), all the register groups do not match the expected value for confirmation, so it is determined as NG (FIG. 3: step S110) and the process proceeds to the abnormal termination system (FIG. 3: step S108). ).

  Further, if the result of determination of the above-described read data with the expected value for confirmation (FIG. 3: step S102) is a mismatch, all the comparison bits read at the same time are referred to (FIG. 3: step S109). When the bit is 0 (mismatch), the individual comparison result is read from the individual comparison register 60 (FIG. 3: step S111), and the individual comparison bit becomes 1 (matches with the comparison results of the comparators 41A to 41D). The registered register is an NG register (FIG. 3: step S114). Also, the registers whose individual comparison bits indicating that they do not match in the comparison results of the comparators 41A to 41D are 0, read the corresponding registers by that number (FIG. 3: step S116), It is determined whether or not the test data matches the expected value for confirmation (FIG. 3: step S117). If they match, it is determined as an OK register (FIG. 3: step S112). If they do not match, NG is determined. The register is determined (FIG. 3: step S113), and the process shifts to the abnormal termination system (FIG. 3: step S108).

  By doing so, the comparison processing of the CPU 70 can be reduced when a large number of functional blocks are mounted. For example, when 100 functional blocks having a certain function are mounted (n = 100), 100 registers from 21 to 2100 control the functional block. When initial values are confirmed for these registers, or when the same data is written to the registers 21 to 2100 and the data of the written registers is read back, confirmation is performed for each of the 100 registers so far. It was necessary to check whether it was consistent with the initial value of or the specific value written. However, in this embodiment, one of the 100 registers is read, and all the comparison results of the registers are referred to. If they match completely, they match the initial values or the written specific values. All you need to do is check. Further, if not all coincidence, the value of the read register is compared with the values of all other registers, so that the mismatched register can be identified from the individual comparison result register 60, and the CPU 70 However, it is possible to reduce the processing time of the CPU 70 because the processing for reading and comparing all the registers normally performed is reduced.

  Here, in the operation in the first embodiment described above, each execution content executed in the above steps may be programmed, and this may be configured to function on a computer.

(Effect of embodiment)
As described above, in the present embodiment, whether the register value corresponding to the address path B designated by the CPU 70 matches each register other than this register is compared with the comparison circuits 41A to 41A in the comparison determination unit 40. 41n compares each, and outputs each comparison result as individual comparison results J to M. The AND operation circuit 43 performs an AND operation on the individual comparison results J to M and outputs the operation result as an all comparison result I. Data from the all comparison result I and the register corresponding to the address path B described above is output. The bit connection unit 50 connects the register values input by the selection unit 30, and the CPU 70 reads as read data + all comparison results F. For this reason, all the comparison results I can be obtained when reading the register values, and it is possible to compare whether or not the read data and the register values other than the read data match. Further, when all the comparison results I and the read data do not match, by reading the individual comparison results J to M from the individual comparison register 60, it is possible to specify a register that does not match the read data. For this reason, it is not necessary for the CPU 70 to compare whether or not each register matches the read data, and even if there is a mismatch, the CPU 70 refers to the individual comparison register 60 and does not match the read data. A certain register can be specified, and the processing time of the CPU 70 can be reduced.

[Other Embodiments]
As described above, in one embodiment, when the CPU 70 reads test data held in any one of the registers 21 to 2n as shown in FIG. 1, the test held in the register to be read is stored. The case where the CPU 70 calculates the expected value of the data for confirmation and compares the calculated expected value for confirmation with the actual test data held in the register to be read is exemplified. On the other hand, as shown in FIG. 5, the CPU 70 is provided with an expected value register 90 by address mapping, and the expected value register 90 holds the expected value for checking the test data held by the register to be read. Then, the comparison / determination unit 40 individually compares and determines whether or not the registers 21 to 2n and the expected value for confirmation match, and outputs the comparison determination results as individual comparison results J to M, respectively. Whether the individual comparison results J to M are all coincident or not is determined and the comparison determination result is output as the entire comparison result I. When the CPU 70 reads the expected value register, the registers 21 to 2n are for confirmation. Whether or not it matches the expected value can be confirmed by referring to the entire comparison result I, and further, which register is confirmed by referring to the individual comparison holding register 60 It is possible to confirm whether or not consistent with the expected value, it is possible to CPU70 itself omit a process of comparing the test data expected value register 21 to 2n.
Even in this case, it is possible to obtain an error status display system having the same effects as those of the above-described embodiment.

About the embodiment mentioned above, if the summary of the novel technical content is put together, it will become as the following additional remarks.
In addition, although one part or all part of the said embodiment is put together as follows as a novel technique, this invention is not necessarily limited to this.

(Supplementary Note 1) A plurality of functional blocks that realize various functions, a CPU that individually transmits command information related to operation control to the functional blocks, and the command information that corresponds to the functional blocks and that temporarily stores the command information In an arithmetic and control unit comprising a plurality of registers held in
The CPU has the same data holding command function for holding the same data as the test data for each register, and the read data comparison commonly provided for the register with the holding state of the test data held in each register. It has a holding state confirmation function to confirm based on the output of the circuit,
The read data comparison circuit compares and determines whether or not the test data held in the registers match each other, and transmits the comparison determination result to the CPU for the holding state check function; and An arithmetic control apparatus comprising: an all-comparison function that compares and determines whether or not all the results of the individual comparison functions match and transmits the comparison determination result to the CPU for the holding state confirmation function.

(Appendix 2) In the arithmetic and control unit according to appendix 1,
A data selection unit that selects the test data as read data from any one of the registers specified by the CPU;
A comparison determination unit that determines whether or not the read data and the test data of each register match each other and determines whether or not all the individual comparison results match; and
A bit concatenation unit that concatenates the read data and all the comparison results and outputs the result to the CPU for the holding state confirmation function;
An arithmetic control device comprising: an individual comparison result register for holding the plurality of individual comparison results for the holding state confirmation function.

(Supplementary note 3) In the arithmetic and control unit according to supplementary note 2,
The comparison determination unit includes a selection circuit that selects the read data as comparison data, a comparison circuit that determines whether or not the comparison data and the test data of each register match each other, and the plurality of individual determinations An arithmetic control device comprising: a logical product circuit that performs a logical product operation on the comparison result.

(Supplementary note 4) In the arithmetic and control unit according to supplementary notes 2 to 3,
The CPU has a function of calculating and outputting an expected value for checking the test data held by the register when any one of the registers is specified, and
An expected value register holding the expected value for confirmation is provided in common with each of the registers,
The comparison determination unit individually compares and determines whether the expected value for confirmation held in the expected value register and the test data of each register match each other, and the comparison determination result is stored in the individual comparison result register. An arithmetic and control unit characterized by transmitting each of the individual comparison results and comparing whether or not the individual comparison results all match and transmitting the comparison determination result to the bit concatenation unit.

(Supplementary Note 5) A plurality of functional blocks that realize various functions, a CPU that individually transmits command information related to operation control to the functional blocks, and the command information that corresponds to the functional blocks and that temporarily stores the command information And a plurality of registers held in the arithmetic and control unit,
The CPU holds the same data as test data for each register,
A data selection unit in a read data comparison circuit provided in common with each register from any one of the registers specified by the CPU selects the test data as read data,
Whether or not the read data and the test data of each register coincide with each other, a comparison determination unit in the read data comparison circuit makes an individual comparison determination,
Whether or not the individual comparison results all match, the comparison determination unit determines all comparisons,
A bit connection unit in the read data comparison circuit connects the read data and the entire comparison result,
The individual comparison results in the read data comparison circuit hold the plurality of individual comparison results,
The CPU confirms the data concatenated by the bit concatenation unit,
A method of controlling an arithmetic and control unit, characterized in that the CPU confirms the content held in the individual comparison result register when all the comparison results do not match.

(Supplementary Note 6) A plurality of functional blocks that realize various functions, a CPU that individually transmits command information related to operation control to the functional blocks, and the command information corresponding to the functional blocks and temporarily And a plurality of registers held in the arithmetic and control unit,
Same data holding command function for holding the same data as test data for each register,
A data selection function for selecting the test data as read data from any one of the registers specified by the CPU;
An individual comparison function for individually comparing whether or not the read data and the test data of each register match each other;
An all comparison function for determining whether all the individual comparison results match or not
A bit connection function for connecting the read data and all the comparison results;
An individual comparison result holding function for holding the plurality of individual comparison results;
A holding state confirmation function for confirming the data concatenated by the bit concatenation unit and confirming the content held in the individual comparison result register when all the comparison results are inconsistent;
A program for controlling an arithmetic and control unit, characterized in that a computer is realized.

  In the present invention, when the CPU reads the value of the register, the comparison unit compares the CPU read data with the value of each register other than that read by the CPU, and outputs each comparison result as an individual comparison result. Further, the comparison determination unit compares whether all registers other than those read by the CPU match, and outputs the comparison results as all comparison results. When all the comparison results and the CPU read data are bit-connected and the CPU reads, it is possible for the CPU to check whether the value of the read target register matches the register other than the read target at the time of data reading. . Furthermore, even if all the comparison results do not match, the CPU can check the mismatched registers by referring to the individual comparison results. This eliminates the need for the CPU to check whether or not the individual registers match the read data, thereby reducing the CPU processing time.

2n registers (n = 1, 2, 3,...)
30 data selection unit 40 comparison determination unit 41n comparison circuit (n = A, B, C...)
42 selection circuit 43 AND circuit 50 bit concatenation unit 60 individual comparison register 70 CPU
8n function blocks (n = 1, 2, 3 ...)

Claims (6)

A plurality of functional blocks that realize various functions, a CPU that individually transmits command information related to operation control to the functional blocks, and a plurality that correspond to each functional block and temporarily hold the command information In the arithmetic and control unit comprising the register,
The CPU has the same data holding command function for holding the same data as the test data for each register, and the read data comparison commonly provided for the register with the holding state of the test data held in each register. It has a holding state confirmation function to confirm based on the output of the circuit,
The read data comparison circuit compares and determines whether or not the test data held in the registers match each other, and transmits the comparison determination result to the CPU for the holding state check function; and An arithmetic control apparatus comprising: an all-comparison function that compares and determines whether or not all the results of the individual comparison functions match and transmits the comparison determination result to the CPU for the holding state confirmation function. The arithmetic and control unit according to claim 1,
A data selection unit that selects the test data as read data from any one of the registers specified by the CPU;
A comparison determination unit that determines whether or not the read data and the test data of each register match each other and determines whether or not all the individual comparison results match; and
A bit concatenation unit that concatenates the read data and all the comparison results and outputs the result to the CPU for the holding state confirmation function;
An arithmetic control device comprising: an individual comparison result register for holding the plurality of individual comparison results for the holding state confirmation function. In the arithmetic and control unit according to claim 2,
The comparison determination unit includes a selection circuit that selects the read data as comparison data, a comparison circuit that determines whether or not the comparison data and the test data of each register match each other, and the plurality of individual determinations An arithmetic control device comprising: a logical product circuit that performs a logical product operation on the comparison result. The arithmetic and control unit according to claim 2,
The CPU has a function of calculating and outputting an expected value for checking the test data held by the register when any one of the registers is specified, and
An expected value register holding the expected value for confirmation is provided in common with each of the registers,
The comparison determination unit individually compares and determines whether the expected value for confirmation held in the expected value register and the test data of each register match each other, and the comparison determination result is stored in the individual comparison result register. An arithmetic and control unit characterized by transmitting each of the individual comparison results and comparing whether or not the individual comparison results all match and transmitting the comparison determination result to the bit concatenation unit. A plurality of functional blocks that realize various functions, a CPU that individually transmits command information related to operation control to the functional blocks, and a plurality that correspond to each functional block and temporarily hold the command information And an arithmetic and control unit having a register of
The CPU holds the same data as test data for each register,
A data selection unit in a read data comparison circuit provided in common with each register from any one of the registers specified by the CPU selects the test data as read data,
Whether or not the read data and the test data of each register coincide with each other, a comparison determination unit in the read data comparison circuit makes an individual comparison determination,
Whether or not the individual comparison results all match, the comparison determination unit determines all comparisons,
A bit connection unit in the read data comparison circuit connects the read data and the entire comparison result,
The individual comparison results in the read data comparison circuit hold the plurality of individual comparison results,
The CPU confirms the data concatenated by the bit concatenation unit,
A method of controlling an arithmetic and control unit, characterized in that the CPU confirms the content held in the individual comparison result register when all the comparison results do not match. A plurality of functional blocks that realize various functions, a CPU that individually transmits command information related to operation control to the functional blocks, and a plurality that correspond to each functional block and temporarily hold the command information And an arithmetic and control unit having a register of
Same data holding command function for holding the same data as test data for each register,
A data selection function for selecting the test data as read data from any one of the registers specified by the CPU;
An individual comparison function for individually comparing whether or not the read data and the test data of each register match each other;
An all comparison function for determining whether all the individual comparison results match or not
A bit connection function for connecting the read data and all the comparison results;
An individual comparison result holding function for holding the plurality of individual comparison results;
A holding state confirmation function for confirming the data concatenated by the bit concatenation unit and confirming the content held in the individual comparison result register when all the comparison results are inconsistent;
A program for controlling an arithmetic and control unit, characterized in that a computer is realized.

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