JP2011523745A - Shader complex having distributed level 1 cache system and centralized level 2 cache - Google Patents

Abstract

[Solution]
The shader pipe texture filter uses the level 1 cache system as the primary method of storage, but has the ability to cause the level 1 cache system to read and write to the level 2 cache system as needed. The level 1 cache system communicates with the level 2 cache system via a wide channel memory bus. Also, the level 1 cache system may be configured to support dual shader pipe texture filters while maintaining access to the level 2 cache system. A method is also presented that has the ability to use a level 1 cache system as the primary method of storage and to allow the level 1 cache system to read and write to the level 2 cache system as needed. Furthermore, the level 1 cache system can allocate a memory area defined to be sharable among other resources.
[Selection] Figure 3

Description

  The present invention relates generally to computational processing performed within a computer system, and more particularly to graphics processing tasks performed within a computer system.

  A graphics processing unit (GPU) is a complex integrated circuit specifically designed to perform graphics processing tasks. The GPU may perform graphics processing tasks required by end user applications such as video game applications, for example. In such an example, there are a number of software hierarchies between the end user application and the GPU.

  The end user application communicates with an application programming interface (API). The API allows end-user applications to output graphics data and instructions in a standardized format rather than in a GPU dependent format. A number of APIs are commercially available, including DirectX (registered trademark) developed by Microsoft Corp. and OpenGL (registered trademark) developed by Silicon Graphics, Inc. is there. The API communicates with the driver. The driver converts the standard code received from the API into instructions in a unique format understood by the GPU. Drivers are typically written by the GPU manufacturer. The GPU then executes instructions from the driver.

  The GPU generates pixels that produce an image from a higher hierarchical description of its components in a process known as rendering. GPUs typically make use of the concept of continuous drawing through the use of pipelines that process pixel, texture, and geometric data. These pipelines are often a collection of fixed function special purpose pipelines such as rasterizers, setup engines, color blenders, hierarchical depth, texture mapping And a set of programmable stages achievable in a shader pipe or shader pipeline, a “shader” is a computer graphic that refers to a set of software instructions used by a graphic resource before producing a rendering effect. Is the term. The GPU can also employ a multiplexed programmable pipeline in parallel processing design to obtain higher throughput. Multiplexing shader pipelines is sometimes referred to as shader pipe arrays.

  The GPU also supports a concept known as texture mapping. Texture mapping is a process used to determine the texture color for texture mapped pixels through the use of the color of neighboring pixels or texels of the texture. This process is also called texture smoothing or texture interpolation. However, high image quality texture mapping requires a high degree of computational complexity.

  In addition, GPUs with integrated shaders also support many types of shader processing from pixels, vertices, primitives, and surfaces at the same time, so general-purpose computers demand higher performance general-purpose memory access capabilities. Is increasing.

  Texture filters rely on fast access to local cache memory for pixel data. However, the use of dedicated local cache memory for texture filters typically hinders the use of more general purpose shared memory. While general purpose shared memory is more flexible, it typically has a slower response time and therefore less performant.

  In view of the increasing complexity of new software applications, there is also a growing demand to provide efficient and high quality rendering, texture filtering and error correction in the GPU.

  Accordingly, there is a need for a system and / or method that alleviates the aforementioned drawbacks. In particular, there is a need for a distributed level 1 cache system for each texture filter combined with a centralized sharable level 2 cache system.

  This section is intended to outline some aspects of the present invention and is intended to provide a brief introduction to some preferred embodiments. Simplifications or omissions may be made to avoid obscuring the purpose of this field. Such simplifications or omissions are not intended to limit the scope of the invention. In accordance with the principles of the present invention as embodied and broadly described herein, the present invention includes a method and apparatus whereby a shader pipe texture filter uses a level 1 cache system as the primary method of storage, but a level 2 cache system. The level 1 cache system has the ability to read from and write to as needed. Each level 1 cache system has a specific shader pipe texture filter, but level 2 cache memory does not have such a relationship and is therefore available to all level 1 cache systems. In addition, the level 1 cache system can allocate a memory area defined to be sharable among other resources.

  In an embodiment of the present invention, the level 1 cache system is configured with dual access so that the two shader pipe texture filters have access to a single level 1 cache system.

  In other embodiments, more than one level 2 cache system is configured to be accessible by each level 1 cache system.

  In other embodiments, communication between the Level 1 and Level 2 cache systems utilizes more than one memory channel, which results in greater data throughput.

  In other embodiments, one or more level 1 cache systems may allocate an area of memory that is defined to be shared among other resources, including other level 1 cache systems. In a particular example, this approach will allow for faster fetch times for texel data if the requested data has already been moved from the level 2 cache system to the level 1 cache system. .

  Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with reference to the accompanying drawings. It should be noted that the present invention is not limited to the specific embodiments described herein. This embodiment is presented here for illustrative purposes only. Additional embodiments will be apparent to those skilled in the art, including the relevant fields, based on the teachings contained herein.

  The accompanying drawings, which are incorporated herein and form part of the application documents, illustrate embodiments of the present invention, and together with the general description above and the detailed description of the embodiments presented below, illustrate the principles of the invention. Help explain.

FIG. 1 is a system diagram illustrating an implementation or implementation of a single level 1 cache system with a single level 2 cache system.

FIG. 2 is a system diagram illustrating the implementation or implementation of multiple level 1 and level 2 cache systems.

FIG. 3 is a system diagram illustrating the implementation or implementation of a dual port level 1 and multiple level 2 cache system.

FIG. 4 is a flowchart illustrating an implementation of a method for a shader filter cache system.

  The features and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is indicated by one or more digits in the leftmost digit of the corresponding reference number.

  The invention will be better understood from the following description of various "embodiments" of the invention. Thus, the various specific “embodiments” are various aspects of the invention, but each of the aspects is not an entire invention. In one aspect, the present invention relates to a distributed level 1 cache system with a centralized level 2 cache system. Each shader pipe texture filter has a dedicated level 1 cache system that provides read and write access to the texel data contained within that range. There are also one or more level 2 cache systems, which are not dedicated to shader pipe texture filters and are therefore accessible by all level 1 cache systems.

  Although specific configurations, arrangements, and steps are discussed, it should be understood that this is for exemplary purposes only. Those skilled in the art, including the relevant fields, will recognize that other configurations, arrangements, and steps may be used without departing from the spirit and scope of the invention. It will be apparent to those skilled in the art including the relevant fields that the present invention may be employed in various other applications.

  It should be noted that references in the specification to “one embodiment”, “embodiment”, “exemplary embodiment”, etc. may include specific features, structures, or characteristics of the described embodiment, All embodiments need not include the particular features, structures, or characteristics. Moreover, such phrases are not necessarily referring to the same embodiment. Further, where a particular feature, structure, or characteristic is described in connection with an embodiment, whether or not it is explicitly described, the particular feature, structure, Alternatively, it can be said that the realization of characteristics is within the knowledge of those skilled in the art.

  While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those skilled in the art will be able to use the teachings provided herein to recognize additional modifications, applications, and embodiments within the scope and in additional areas where the present invention would be significantly useful. Will do.

  FIG. 1 is a diagram of a single level 1 cache system and a single level 2 cache system 100 according to an embodiment of the present invention. The system 100 includes a single shader pipe texture filter 110 and the associated level 1 cache system 120 is configured to communicate with the level 2 cache system 130 using a wide channel memory bus 125.

  In the embodiment shown in FIG. 1, shader pipe texture filter 110 employs the concept of bilinear filtering to determine the color of a particular pixel. During bilinear filtering, shader pipe texture filter 110 analyzes texel data for the four pixels closest to the pixel in question. The texel data for the four texels is then combined by a weighted average according to the distance to calculate the desired result. The texel data in question is retrieved and retrieved from the level 1 cache system 120 associated with the active shader pipe texture filter 110.

  However, if the desired texel data is not in the level 1 cache system 120 at the desired time, the level 1 cache system 120 issues a read request for the desired texel data to the level 2 cache system 130. In this case, the requested data is then copied from the level 2 cache system 130 to the level 1 cache system 120 for analysis and processing by the shader pipe texture filter 110.

  FIG. 2 is a diagram of a multiplexed shader pike texture filter with a level 1 cache and a level 2 cache system in accordance with an embodiment of the present invention. The system 200 includes one or more shader pipe texture filters, which are denoted herein as shader pipe texture filters 1 through N represented by 110-1 through 110-N, and are “N”. Represents a positive integer greater than 1. The system 200 also includes a level 1 cache system associated with each shader pipe texture filter, which are denoted herein as L1-1 cache systems through L1-N cache systems, denoted 120-1 through 120N. , “N” represents a positive integer greater than 1. Also included is a wide channel memory bus 125 that links the level 1 cache systems 120-1 through 120N to a series of level 2 cache systems. In this embodiment, the level 2 cache system includes one or more level 2 cache systems, which are denoted here as L2-1 to L2-M cache systems, denoted as 130-1 through 130-M. “M” is an integer greater than 1, but not necessarily the same as the number N of level 1 cache systems.

  In the embodiment of FIG. 2, each of the shader pipe texture filters 110-1 to 110N employs the concept of bilinear filtering that determines the color of a particular pixel. As described above, each shader pipe texture filter 110-1 to 110N needs to analyze the texel data for the four pixels closest to the pixel in question. Thus, the texel data in question for each shader pipe texture filter is retrieved and retrieved from the associated level 1 cache system. Therefore, the shader pipe texture filter 110-1 issues a request for texel data to the L1-1 cache system 120-1. The remaining shader pipe texture filters will similarly issue texel data requests.

  However, if the desired texel data for any particular shader pipe texture filter does not exist in the associated level 1 cache system 120, the level 1 cache system will issue a read request for the desired texel data to the level 2 cache system 130. Can be issued. Since there is a multiplexed level 2 cache system in the embodiment of FIG. 2, one or more of them can respond to level 1 cache system requests for texel data. However, in other embodiments, there may be a single level 2 cache system while having a multiplexed shader pipe texture filter and associated level 1 cache system.

  In other embodiments with respect to FIG. 2, one or more level 1 cache systems may allocate a region of memory defined to be shared among other resources including other level 1 cache systems. In a particular example, this approach allows a faster fetch time for texel data if the requested data has already been moved from the level 2 cache system to the level 1 cache system.

  FIG. 3 is a diagram of a multiplexed shader pike texture filter with a dual port level 1 cache and multiplexed level 2 cache system in accordance with an embodiment of the present invention. The system 300 includes one or more dual-port level 1 cache systems, each supporting up to two shader pipe texture filters, and a level 2 cache system. In this embodiment, the level 1 cache system supports up to two shader pipe texture filters for their texel data requests. In this embodiment, there are one or more level 1 cache systems L1-1 to L1-N represented by reference numerals 320-1 to 320-N, where N represents a positive integer. Here, each level 1 cache supports two shader pipe texture filters, shown as shader pipe texture filters A and 310 and shader pipe texture filters B and 312. Level 1 caches 320-1 through 320-N also have access through the wide channel memory bus 125 to the level 2 cache system represented by L2-1 through L2-M, where M is a positive It is an integer.

  In other embodiments with respect to FIG. 3, one or more level 1 cache systems may allocate a region of memory defined to be shared among other resources including other level 1 cache systems. In a particular example, this approach allows a faster fetch time for texel data if the requested data is already moving from the level 2 cache system to the level 1 cache system.

  FIG. 4 is a flow chart illustrating a method 400 whereby the shader pipe texture filter utilizes the level 1 cache system as the primary storage method with the ability to access the level 2 cache as needed. Method 400 begins at step 402. In step 404, each level 1 cache system can allocate a memory area defined to be sharable among other resources. In step 406, the shader pipe texture filter issues a read or write instruction to the associated level 1 cache system. In step 408, the level 1 cache system retrieves, collects, or writes texel data as necessary. In step 410, each level 1 cache system can issue read and write requests to the level 2 cache system. Method 400 ends at step 412.

  The functions, processes, systems and methods outlined in FIGS. 1, 2, 3 and 4 may be implemented or implemented in software, firmware or hardware, or combinations thereof. If programmable logic is used, the logic can be executed on a commercially available processing platform or special purpose device.

  As will be apparent to those skilled in the art including the relevant fields, based on the description herein, embodiments of the present invention should be designed in software using a hardware description language (HDL) such as Verilog or VHDL. Can do. An HDL design can model the behavior of an electronic system, where the design is synthesized and eventually fabricated into a hardware device. The HDL design may also be stored in a computer product and captured in a computer system prior to hardware manufacture.

  It should be understood that the detailed description, rather than the summary and abstract, is intended to be used for interpreting the scope of the claims. The summary and summary section may illustrate one or more, but not all, exemplary embodiments of the present invention contemplated by the inventor, and thus is intended to limit the present invention and the appended claims. Never done.

  The present invention has been described above using functional building blocks that indicate the implementation of specific functions and their relationships. The boundaries of these functional blocks have been arbitrarily defined here for convenience of explanation. Alternative boundaries may be defined as long as certain functions and their relationships are properly performed.

  The foregoing description of specific embodiments does not require undue experimentation by others applying knowledge within the skill of the art and without departing from the general concept of the invention. To the extent that the particular embodiments can be readily modified and / or adapted to various applications, the general nature of the invention will be fully clarified. Accordingly, such adaptations and modifications are intended to be within the meaning and scope of the equivalents of the disclosed embodiments, based on the teachings and guidance presented herein. It should be understood that the expressions and terms herein are for illustrative purposes and are not intended to be limiting, and the expressions and terms herein are interpreted by one of ordinary skill in the art in view of the teachings and guidelines. It should be.

  While various embodiments of the invention have been described above, it should be understood that they have been presented for purposes of illustration only and are not intended to be limiting. It will be apparent to those skilled in the art, including the relevant fields, that various changes in form and detail may be made herein without departing from the spirit and scope of the invention. Accordingly, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims (19)

A distributed level 1 cache system configured to communicate with a shader pipe texture filter;
A shader filter cache system comprising a level 2 cache system,
The level 1 cache system and the level 2 cache system are configured and arranged such that they can communicate with each other using a memory channel. The level 1 cache system comprises one or more level 1 cache blocks each with a shader pipe texture filter;
The system of claim 1, wherein the shader pipe texture filter is configured to read data from and write data to the level 1 cache block. The level 2 cache system comprises one or more level 2 cache blocks;
The system of claim 1, wherein the level 1 cache system is configured to read data from a level 2 cache block and write to a level 2 cache block.   The system of claim 1, wherein the level 1 cache system is configured to communicate with the level 2 cache system using one or more memory channels.   The system of claim 1, wherein the level 1 cache system is configurable to be shared between one or more shader pipe texture filters. A method for caching shader filter data, comprising:
Receiving read and write instructions from the shader pipe filter for access to the level 1 cache system;
Executing the instruction from the shader pipe filter;
Allocating a memory area in the level 1 cache system defined to be shared among other resources;
Managing read and write requests from the level 1 cache system to the level 2 cache system.   The method of claim 6, wherein the receiving comprises receiving from a plurality of shader pipe filters. Receiving comprises receiving from a plurality of level 1 cache systems;
The method of claim 6, wherein allocating the defined area comprises allocating a defined area of a plurality of level 1 cache systems.   Managing read and write requests from the level 1 cache system to the level 2 cache system comprises managing read and write requests from the level 1 cache system to a plurality of level 2 cache systems. The method according to claim 6.   The method of claim 6, wherein the method is performed by combining hardware description language instructions. A system for caching shader filter data,
A processor;
A memory in communication with the processor,
The memory is
Receiving read and write instructions from the shader pipe filter for access to the level 1 cache system;
Executing the instruction from the shader pipe filter;
Allocating a memory area in the level 1 cache system defined to be shared among other resources;
A system for storing a plurality of processing instructions for instructing the processor to manage read and write requests from the level 1 cache system to the level 2 cache system.   The system of claim 11, further comprising instructions that cause the processor to manage instructions from a plurality of shader pipe filters.   The system of claim 11, further comprising instructions that cause the processor to manage a plurality of level 1 cache systems.   The system of claim 11, further comprising instructions that cause the processor to manage a plurality of level 2 cache systems. A system for caching shader filter data,
Means for receiving read and write instructions from the shader pipe filter for access to the level 1 cache system;
Means for executing the instructions from the shader pipe filter;
Means for allocating a memory region in the level 1 cache system defined to be shared among other resources;
Means for managing read and write requests from the level 1 cache system to the level 2 cache system.   The system of claim 15, further comprising means for managing instructions from the plurality of shader pipe filters.   The system of claim 15 further comprising means for managing a plurality of level 1 cache systems.   The system of claim 15 further comprising means for managing a plurality of level 2 cache systems. A computer readable medium that conveys one or more sequences of one or more instructions that cause the computer system to perform a method of caching shader filter data when executed by one or more processor-based computer systems, the computer readable medium comprising: The method is
Receiving read and write instructions from the shader pipe filter for access to the level 1 cache system;
Executing the instruction from the shader pipe filter;
Allocating a memory area in the level 1 cache system defined to be shared among other resources;
Managing read and write requests from the level 1 cache system to the level 2 cache system.

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