JP2011258229A - Memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory system that accelerates a read/write performance.SOLUTION: A memory system includes: first memories 13-1, ..., 13-n each of which is composed of a flash type EEPROM with the arrangement of a plurality of memory cells to electrically erase and write data; a second memory 14 which is constituted by one of a ferroelectric memory, a magnetoresistive memory, and a phase change memory, and has a smaller capacity and a higher writing speed compared with the first memories; a control circuit 15 for controlling the first and the second memories 13 and 14; and an interface circuit for communicating with an external part. The first memories 13 store data. The second memory 14 stores at least one information among route information, directory information, a data file name, a data file size, file allocation table information for storing a storage part of the data, and a data writing termination time, so as to store the data.

Description

  In the embodiment of the present invention, a file storage represented by a NAND flash memory (NAND-Flash Memory) having a large capacity but a long read time, programming time, and erase time is required. A memory system is constructed by skillfully combining a flash EEPROM type non-volatile memory, a FeRAM capable of high-speed read / write, and a controller for controlling it. Effective data read / write speed improvement for small data, file allocation table (FAT: File Allocation Table), directory information, etc., read / write speedup, and allocation table write required for instantaneous power failure countermeasures (Data) read / write performance prevention, frequent read / write Speed of over data relates to a memory system that allowed to facilitate the specification change of the controller.

  Today, semiconductor memories are used everywhere from the main memory of large computers to personal computers, home appliances, mobile phones, and the like. The market is growing significantly in the flash EEPROM type nonvolatile memory represented by NAND flash memory, and various memory cards (SD card, MMC card, MS card, CF card) are used for images, movies, sounds, and games. As a medium for storing information such as a digital camera, a digital video, a music device such as MP3, a storage medium such as a mobile PC, a storage medium such as a digital TV It is used as. USB compatible cards are also widely used as PC storage media.

  Flash EEPROM type non-volatile memories are mainly classified into NOR type and NAND type. The NOR type as shown in FIG. 23B is capable of high-speed reading, has a read count of about 10 13, and stores an instruction code of a portable device. It is used for However, the effective write bandwidth is small and is not suitable for file recording.

  On the other hand, the NAND type can be highly integrated compared with the NOR type, and although the access time is as low as 25 μs, burst read is possible, the effective bandwidth is high, and the write time is also programmed. Although it has a slow erase time of about 200 μs and about 1 ms, it has a large effective bandwidth because it has a large number of bits that can be programmed and erased at one time, fetches write data in bursts, and can program many bits at once. Taking advantage of such advantages, it is used in the memory card, the USB memory, and the memory of a mobile phone recently.

  FIG. 19 shows a memory cell structure of a NAND flash EEPROM, where (a) shows a planar layout (Layout) of the cell block, (b) shows a sectional view, and (c) shows an equivalent circuit. Since one memory cell is arranged at the intersection of the word line and the bit line, it is suitable for high integration. For this reason, as shown in (c), a plurality of floating gate type transistors are connected in series, and selection transistors are arranged at both ends of the bit line BL and the source line SL.

  The configuration of the memory cell array is shown in FIG. One erase unit is the memory cell block unit of FIG. 19 when viewed in the bit line direction. When viewed in the word line direction, one mat is formed, and the capacity is about 256 KB. This erase unit is divided into a plurality of units, and this is called a block. The program unit is one word line in the erase block and every other bit line (even bit line EvenBL or odd bit line OddBL). When the number of series cells is 32, 256 KB / 32/2 = 4KB. This program unit is called a page. In this example, the block / page ratio is 64. In reading, either the odd bit line OddBL or the even bit line EvenBL is read. For example, when reading the even bit line EvenBL, the odd bit line OddBL is set to Vss in order to reduce the noise of interference between the bit lines BL.

  FIG. 21 shows an example of read / program / erase operation of the NAND flash. In the read operation, the word line of the cell to be read is set to 0 V, the others are set to High, and the threshold voltage Vt of the cell transistor is Vt> 0, the potential of the bit line BL is lowered, and if Vt <0, the bit line BL is It remains high and the cell data is read.

  In the erase operation, the well potential of the entire cell block is set to 20 V, and the others are set to 0 V, whereby electrons of the floating gate are extracted to the well side by a tunnel current, and the threshold voltage Vt is set lower than 0 V. Therefore, erase is a large unit of 256 KB.

  The programming is performed by setting the word line of the selected cell to 20V and setting the bit line to 0V to increase the threshold voltage by electron injection into the floating gate by tunnel current.

  At this time, non-selected cells in the same block suppress the writing by setting the word line to about 7 V and reducing the voltage application to the non-selected transistors. For a bit not to be written in the selected word, the bit line is set to 7V, and then the unselected word line is raised to 7V to boot the source and drain voltages of the cell transistor, thereby suppressing writing. In this example, a binary method for storing 1-bit information in one cell is used, but in recent years, a 4-value method for storing 2-bit information in one cell has come to be used.

  FIG. 22 is a schematic diagram showing a case where the threshold voltage of one cell (cell transistor) is given four values. By writing 1 or 0 in the lower bit in the first program and writing the upper bit in the second program, the cell threshold voltage has four distributions as a result. Although this quaternary method is suitable for high density, it is necessary to suppress the distribution of the threshold voltage Vt of the cell transistor within a narrow range, and the program time and erase time are slower than the binary value. In addition, the lead also takes a long time since it needs to be judged at least twice.

  FIG. 23 shows a configuration example of another flash EEPROM. FIG. 23A is called an AND type, which is also excellent in high-speed writing, and is used as a file storage memory. (C) is called the DINOR type, and is similar to the AND type of (a). However, like NOR, it is excellent in high-speed reading, and is mainly used for storing instruction codes in mobile phones and the like.

  By the way, in a memory system such as a memory card using the NAND flash or the like, one to several NAND flashes and a controller for controlling the NAND flash or the like are mounted on the card. This controller has the following four functions.

  First, it has an interface circuit on the host side, and performs read / write from the host to the NAND.

  Second, it has a NAND interface circuit, and reads / writes from the NAND to the host.

Third, address management / bad block management and the like when writing data to the NAND are performed.

  Fourthly, write control is performed on blocks corresponding to FAT, directories, etc., in a relatively small unit of less than a block unit.

  However, in the memory system using the NAND flash, it takes time to read / program / erase even if data is held, but it takes much more time at the card level and OS level. In particular, the worst case is when reading / writing a small file.

  One solution that can deal with this problem is that it can be read / written as fast as a DRAM as a storage medium, and a ferroelectric memory (here, FeRAM) as a non-volatile memory that stores information even when the power is turned off. Is called). In addition to high-speed read / write, the number of rewrites is 10 to the 13th to the 16th power, and the read / write time is about DRAM, so it is called the ultimate memory. If these are used, the problem of slow read / write of the NAND flash can be solved.

  However, at present, the FeRAM is not as highly integrated as the NAND flash and has a high cost.

  Next, FeRAM will be briefly described. FIG. 16A shows a memory cell of a conventional ferroelectric memory having a configuration of one transistor (transistor) +1 capacitor (Capacitor). The memory cell configuration of a conventional ferroelectric memory is a configuration in which a transistor and a capacitor are connected in series. The cell array has a configuration in which bit lines BL for reading data, word lines WL0 and WL1 for selecting memory cell transistors, and plate lines PL0 and PL1 for driving one end of a ferroelectric capacitor are arranged.

  However, in the conventional ferroelectric memory, in order to prevent destruction of polarization information of the ferroelectric capacitor of the non-selected cell, the plate line needs to be divided for each word line and driven individually. However, there is a problem that the chip size is very large, 20% to 30%, and the driving time of the plate line is slow.

  In order to solve the above problem, the inventors of the prior application (Patent Document 1, Patent Document 2 and Patent Document 3) are (1) a small memory cell, (2) a non-volatile ferroelectric memory. Has proposed a new ferroelectric memory that is compatible with three points: a planar transistor that can be easily fabricated, and (3) a versatile high-speed random access function. FIG. 16B shows the configuration of the ferroelectric memory of this prior application. In the prior application, one memory cell is constituted by parallel connection of a cell transistor and a ferroelectric capacitor, and one memory cell block is formed by connecting a plurality of parallel-connected memory cells in series, and one end is a block selection. The other end is connected to the bit line BL via the transistor, and the other end is connected to the plate line PL. As for the operation, at the time of standby, as shown in FIG. 17A, all word lines WL0 to WL3 are set to high, the memory cell transistors are turned on, and the block selection signal BS is set to low. (Low) and the block selection transistor is turned off. By doing so, both ends of the ferroelectric capacitor are electrically short-circuited by the cell transistor that is turned on, so that a potential difference between both ends does not occur, and the storage polarization is stably maintained.

  In the active state, as shown in FIG. 17B, only the memory cell transistor connected in parallel to the ferroelectric capacitor to be read is turned off, and the block selection transistor is turned on. Thereafter, the plate line (PL) is set high and the block selection signal BS is set high, so that the potential difference between the plate line PL and the bit line BL is applied to both ends of the ferroelectric capacitor C1 connected in parallel to the turned-off memory cell transistor. The polarization information of the ferroelectric capacitor is read out to the bit line BL. Therefore, even if cells are connected in series, by selecting an arbitrary word line, cell information of an arbitrary ferroelectric capacitor can be read, and complete random access can be realized. In addition, since the plate line can be shared by a plurality of memory cells, the area of the plate line drive circuit (PL Driver) can be increased while reducing the chip size, thereby realizing high-speed operation.

  Further, in Patent Document 4, the present inventors have proposed a ferroelectric memory capable of ultra-high speed operation. In this ferroelectric memory, as shown in FIG. 16C, a ferroelectric capacitor and a cell transistor are connected in series, a plurality of these cells are connected in parallel, and a reset transistor is connected in parallel to this parallel connection. This is connected to the bit line via the block selection transistor, and the speed can be further increased by the effect of the parallel connection of the series connection of the cells while exhibiting the effect of the prior application. Unlike the conventional ferroelectric memory, all the ferroelectric caps (Cap) can be short-circuited via the reset transistor by turning on all the cell transistors during standby, and the plate drive line This is because it can be shared.

  Further, as shown in FIG. 18, an MRAM has been proposed as a nonvolatile memory capable of high-speed reading / writing. This is because a thin film of Al2O3 or the like is sandwiched between magnetic layers (FixeLayer, FreeLayer), and if the spin direction of the upper and lower magnetic layers coincides, the current of the thin film increases, and if the spin is reversed, the current decreases. A memory having a binary value as a difference.

  However, high-speed read / write is possible like FeRAM, but the chip is larger and the cost is higher than NAND flash. In addition, a phase change memory (also referred to as phase change memory or PRAM) having a relatively short write time has been proposed, but this is also expensive.

  As described above, a memory system using a flash type EEPROM memory or the like is slow to read and takes time for program / erase. In addition, extra system information needs to be written at the card level and OS level, which further takes time. In particular, the worst case is when reading / writing a small file.

  One solution that can deal with this problem is a memory system that uses a non-volatile memory capable of high-speed reading / writing, such as FeRAM / MRAM / PRAM, but has a problem of high cost.

JP 10-255483 A Japanese Patent Laid-Open No. 11-177036 JP 2000-22010 A JP 2004-263383 A

  The problem to be solved by the invention is to provide a memory system capable of increasing the read / write speed.

  The memory system of the embodiment includes a first memory composed of a flash type EEPROM in which a plurality of electrically erasable and writable memory cells are arranged, a ferroelectric memory, a magnetoresistive memory, and a phase change A second memory having a smaller capacity and a faster writing speed than the first memory, a control circuit for controlling the first and second memories, and an interface circuit for communicating with the outside The first memory stores data, and the second memory stores route information, directory information, a file name of the data, or the data for storing the data. File size, file allocation table information for storing the data storage location, or when the data has been written In response to writing from the outside of the memory system, a write end flag to the second memory is written to the second memory, and then a write end flag to the first memory is set to the second memory. It writes to the memory.

  Prior to the description of the embodiments, problems of the conventional memory system considered by the present inventors will be described with reference to FIGS. 24 and 25, and then various embodiments of the memory system capable of solving the problems will be described. .

  FIG. 24 is a schematic diagram showing an operation when a write command is issued from the host side to an SD card or the like. Before the controller writes data to the flash (NAND flash memory, etc. will be referred to as “flash”), the system block assignment table (Assign Table) in the flash A flag (Flag) indicating that data writing is started is written in a bit corresponding to a block in which data is written (in the case of writing 0). Then, after writing data on each page in the block corresponding to the actual data, the logical-physical conversion address is finally written.

  The logical-physical conversion address is address data indicating where the written data corresponds to the original logical address. After that, to indicate that the data has been completely written, a flag indicating that the data writing has been completed is written in the bit corresponding to the block in which the data has been written in another assignment table of the system block in the flash. Case 0). This means that when data is being suddenly extracted or when an instantaneous power failure occurs, the extent to which the data has been written is determined when the power is turned on again, and the data is restored from the middle. In the system block, information on a bad block (Bad Block) indicating a block that cannot be used, system parameters, and the like are stored. In this conventional memory system, the assignment table, the logical-physical conversion address, etc. are read from the flash to the volatile memory such as SRAM on the controller side when the power is turned on, and the writing occurs. Then, the volatile memory is updated and the logical-physical conversion address of the flash system block or data writing block is written. The conventional memory card having such a configuration has the following problems.

  First, in the flash program, tunnel injection is performed in units of one page (4 KB), and 200 μs is required. Therefore, it takes 200 μs to write the 512B assignment table. Therefore, it takes 400 μs to write to the assignment table at the beginning and end of data writing in order to prevent data destruction, card removal, instantaneous power failure, etc. It takes 200 μs to write 4 KB data. It takes 600 μs to complete, and the effective write bandwidth is reduced to 1/3.

  Secondly, since the logical-physical address is also written to the flash, it is necessary to read the logical-physical address written at the same time as the data of all blocks of the flash to the controller side at power-on. Considering the required time of 25 μs, it takes about 1 second to read all the logical-physical addresses distributed in the flash. This is because without this address, it is not possible to know where data is stored even if a read / write command is received. Therefore, the conventional memory system cannot read / write data immediately upon power-on, and cannot cope with the rapid shooting of a digital camera or the like. There is also a method of collecting logical-physical addresses in one place, but this leads to a concentration of reads / programs in one place, which causes a problem in flash with write restrictions.

  Third, when operating on an operating system (OS) such as Windows (registered trademark), the performance of the execution write bandwidth is further deteriorated. For example, if you write one 4KB data, but write data to media such as a hard disk device, memory card, DVD, CD, etc., root information, directory information, file size It is necessary to write as much as 20 KB of system data such as the address where the file is stored, the write end time, etc., and the number of times of writing becomes very large. When these pieces of information are written in a memory system using a flash or the like, they are programmed in different locations. Furthermore, for example, to write an address (FAT) or the like where a file is stored in a memory system such as a flash, it is necessary to write an assignment table for measures against instantaneous power failure twice. , It takes 10 times the original writing time.

  As described above, a memory system using a flash EEPROM memory or the like is slow to read and takes time for programming / erasing. Furthermore, it is necessary to write extra system information at the card level and OS level, which takes more time. In particular, the worst case is when reading / writing small files.

  One solution that can cope with this problem is a memory system using a non-volatile memory capable of high-speed reading / writing, such as FeRAM, MRAM, and PRAM. However, there is a problem of high cost.

  Based on the above considerations, the present invention makes it possible to make a large-capacity memory system by skillfully combining a flash EEPROM memory or the like and a nonvolatile memory capable of high-speed read / write such as FeRAM, MRAM, or PRAM. The high-speed read / write is realized while configuring.

  Next, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram showing a memory system according to the first embodiment of the present invention. This memory system stores wiring 12 connected to a host device (Host) 11, NAND flash EEPROM memories 13-1,..., 13-n that store large amounts of data, system information, data, and the like. A ferroelectric memory 14 is built in, and is composed of a controller 15 that controls communication with the host device 11 and the NAND flash EEPROM memories 13-1,..., 13-n.

  The ferroelectric memory 14 not only stores system information and data but also writes data to the ferroelectric memory 14 when a write command is received from the host device 11. At this time, after writing the write start flag, the write address, and the write end flag to the ferroelectric memory 14, the data is written to the flash EEPROM memories 13-1, ..., 13-n. I do. At this time, the data write start flag, the write address, and the write end flag are also written in the ferroelectric memory 14 in the flash EEPROM memories 13-1,.

  As a result, in response to a write command from the outside of the memory system, the memory system once writes data to the ferroelectric memory 14 and has a write end flag so that the memory system can be written from the outside. finish. After that, even if an instantaneous power failure or card removal occurs while data is being written to the flash type EEPROM memories 13-1,. It is only necessary to re-execute data movement and copying from the body memory 14 to the flash-type EEPROM memories 13-1,.

  As the ferroelectric memory 14 used here, all the ferroelectric memories described in the prior art can be used. Further, MRAM, PRAM or the like can be used in place of the ferroelectric memory 14, and all the methods shown in the description of the prior art can be applied to the flash type EEPROM memories 13-1,.

[Second Embodiment]
FIG. 2 is a block diagram showing a memory system according to the second embodiment of the present invention. This memory system includes NAND flash EEPROM memories (NAND flash memory) 13-1,..., 13-n, a ferroelectric memory (FeRAM) 14, and a controller (NAND flash memory controller) 15. Inside the controller 15, there are an interface circuit (Host-Interface) 21 with the host device 11, an interface circuit (Flash Memory-Interface) 22 with the NAND flash EEPROM memories 13-1,. Interface circuit (FeRAM-Interface) 23 with the body memory 14, the entire controller 15, the NAND flash EEPROM memories 13-1 to 13 -n and the MCU (Micro Control Unit) 24 for controlling the ferroelectric memory 14, It has a micro code memory 25 for storing an instruction code (micro code) of the MCU 24, a multiplexer / demultiplexer (MUX / DMUX) 26, and a page buffer 27. ing.

  The multiplexer / demultiplexer 26 switches the data destination to the NAND flash EEPROM memory 13-1,..., 13-n side and stores the data when it is a data area according to an address from the external host device 11. Route information, directory information, file name of the data, file size of the data, file allocation table (FAT) information for storing the data storage location, or writing of the data If it is end time information or the like, the data destination is switched to the ferroelectric memory 14 side.

  With such a configuration, the flash type EEPROM memories 13-1,..., 13-, which have a large capacity as a data storage memory requiring a large memory area, but require a read cue time, a program time, and an erase time. n, which requires only a small memory area, but with data writing, it requires a small capacity but a large number of places to be written. Ferroelectric memory capable of high-speed read / write with a small capacity for storing the file name of the data, the file size of the data, the file allocation table information for storing the data storage location, or the write end time of the data To store system information in effect. Time can be greatly reduced, the overall OS system, the performance of the entire memory system can be greatly improved. In particular, when the size of the data file to be read / written is small, the storage amount of the system information becomes relatively large, so the effect of the present invention is improved.

  Further, when the data is actually stored in the flash EEPROM memories 13-1,..., 13-n under the control of the MCU 24, the data is temporarily written in the ferroelectric memory 14, and the write start flag Bin and the write end flag Be are set. If the data is written in the ferroelectric memory 14, the writing is completed when viewed from the outside of the memory system, and the apparent writing performance is improved. Thereafter, if write information is stored in the flash type EEPROM memories 13-1,..., 13-n in parallel operation, an instantaneous power failure countermeasure can be taken as in FIG.

  Further, under the control of the MCU 24, a logical-physical conversion address indicating the relationship between the physical address of the block position and page position when actually stored in the flash type EEPROM memory 13-1,..., 13-n and the actual logical address. If the system information such as the above and the write start / end information to the flash type EEPROM memories 13-1,..., 13-n are also written to the ferroelectric memory 14, the system information can be written at high speed, and the data is actually written. The time is large and the effective write performance is improved.

  Further, if the bad block information of the flash type EEPROM memories 13-1,..., 13-n and the system parameters are also written in the ferroelectric memory 14, the flash type EEPROM memories 13-1,. Access is reduced and speeded up. If logical-physical conversion address information and bad block information are stored in the ferroelectric memory 14, the flash EEPROM memories 13-1,..., 13- corresponding to the logical addresses immediately after the memory system is turned on. Since n physical addresses are known, high-speed power-on is possible.

[Third Embodiment]
FIG. 3 is a block diagram showing a memory system according to the third embodiment of the present invention. The structure and effect are almost the same as in FIG. 2, and the difference is that the page buffer 27 'is made into a ferroelectric memory and the microcode memory 25' is made into a ferroelectric memory.

  If the page buffer 27 'is formed of a ferroelectric memory, the data can be held even if the power is turned off at the moment the data is stored in the buffer 27', so that higher speed writing can be realized. Further, if the microcode memory 25 'is formed of a ferroelectric memory, the microcode can be easily changed, and the time for redesign and remanufacturing can be saved.

[Fourth Embodiment]
FIG. 4 is a block diagram showing a memory system according to the fourth embodiment of the present invention. The structure and effects are almost the same as those in FIG. 2, and the difference is that all the ferroelectric memories 14 (14-1, 14-2) are mounted on the controller 15 side.

  The ferroelectric memories 14-1 and 14-2 are easy to be mixed because only a ferroelectric cap (Cap) portion is added to a normal CMOS process. Therefore, in the case of a small-capacity ferroelectric memory, the cost can be reduced when the memory is embedded. As described above, not only in the various embodiments of the present invention but also in the configuration of the memory system, various blocks can be integrated into one chip, and can be arbitrarily combined.

[Fifth Embodiment]
FIG. 5 is a block diagram showing a memory system according to the fifth embodiment of the present invention. The structure and effect are almost the same as those in FIG. 2, and the difference is that an SRAM 28 for temporarily storing system information is mounted on the controller 15 side.

  When the memory system is operated at high speed, the operation speed of the ferroelectric memory (FeRAM) is slightly inferior to that of the SRAM. Therefore, when power is turned on, the system information of the ferroelectric memory 14 is read into the SRAM 28 and the contents are changed. This part can be written back to the ferroelectric memory 14.

[Sixth Embodiment]
FIG. 6 shows an algorithm of the write operation in the memory system according to the sixth embodiment of the present invention. This algorithm can be applied to all the circuits shown in FIGS. 1 to 5, and can be applied to other configurations.

  When the buffer is composed of a ferroelectric memory, when a write command is sent to the memory system, if the write end flag for the buffer is stored in the ferroelectric memory, the writing ends there and an instantaneous power failure occurs. Measures can be taken, and apparent writing performance is improved.

  Further, in the case of SRAM, data may be directly written in the ferroelectric memory without passing through the buffer. In this case, if the write flag is set, even if the power is turned off during writing to the flash EEPROM memory, the continuation can be executed by turning on the power again. Further, if the write flag for the flash EEPROM memory is stored in the ferroelectric memory, the performance is improved.

[Seventh Embodiment]
FIG. 7 is a block diagram showing a memory system according to the seventh embodiment of the present invention. The configuration is similar to that of FIG. 4 and exhibits the same effect as FIG. As a configuration, it is composed of a NAND flash EEPROM memory 13-1,..., 13-n and a controller 15 equipped with a ferroelectric memory. Inside the controller 15, an interface circuit 21 with the host device 11, a NAND flash Stores the interface circuit 22 with the EEPROM memories 13-1,..., 13-n, the entire controller 15, the MCU 24 for controlling the NAND flash EEPROM memories 13-1,. The microcode memory 25, the ferroelectric memory 14 for storing various data and system information, and the data stored in the ferroelectric memory 14 in the flash type EEPROM memories 13-1,. From buffer 27 to flash EEPROM Mori 13-1, ..., and a 13-n used when writing to the ferroelectric write-back buffer, which is formed by a memory (Write-Back Buffer) 29 Prefecture.

Regarding the role and effect of ferroelectric memory,
First, when the data is actually stored in the flash type EEPROM memories 13-1,..., 13-n under the control of the MCU 24, the ferroelectric memory 14 is once written, the write start flag Bin, and the write If the end flag Be is written in the ferroelectric memory 14, the writing is ended when viewed from outside the memory system, and the apparent writing performance is improved. After that, or in parallel operation, if write information is stored in the flash EEPROM memories 13-1,..., 13-n, an instantaneous power failure countermeasure can be taken as in the circuit shown in FIG.

  Second, under the control of the MCU 24, a logical-physical relationship indicating the relationship between the physical address of the block position and page position and the actual logical address when actually stored in the flash type EEPROM memories 13-1,..., 13-n. If system information such as a conversion address and writing start / end information to the flash type EEPROM memories 13-1,..., 13-n are also written to the ferroelectric memory 14, these system information can be written at high speed. Most of the time for writing is increased, and the effective writing performance is improved.

  Third, if the bad block information of the flash type EEPROM memories 13-1,..., 13-n and the system parameters are also written in the ferroelectric memory 14 (14-2), the flash type EEPROM memory 13-1 which operates slowly. ,..., 13-n access is reduced and speeded up. Further, if logical-physical conversion address information and bad block information are stored in the ferroelectric memory 14 (14-2), the flash EEPROM memory 13-1 corresponding to the logical address immediately upon power-on of the memory system. ,..., 13-n are known, so that high-speed power-on is possible.

  Fourth, the ferroelectric memory 14 can be handled like a nonvolatile cache. A certain amount of data area is secured in the ferroelectric memory 14, and data is copied (COPY) from the flash type EEPROM memories 13-1,... Read out of the system.

  Since the information of the logical address once read is already in the ferroelectric memory 14, it is read at high speed after the second time. At this time, the ferroelectric memory 14 stores the addresses of the flash EEPROM memories 13-1,..., 13-n as tag information, and the ferroelectric memory 14 has a memory space. The used page (Used Page) indicating whether or not is used is stored.

  When the information of the address once read is written from outside the memory system, it is apparently terminated only by writing to the ferroelectric memory 14. However, in this case, since the data value of the ferroelectric memory 14 is different from the data value of the flash EEPROM memories 13-1,..., 13-n, a dirty page flag is set. When the usage rate of the area of the ferroelectric memory 14 is increased, data is written back from the ferroelectric memory 14 to the flash EEPROM memories 13-1,..., 13-n via the write-back buffer 29.

  In this case, if the write back buffer 29 exists, the transfer from the ferroelectric memory 14 to the write back buffer 29 is fast, so the write back buffer 29 slowly writes back to the flash EEPROM memories 13-1,..., 13-n. In the meantime, reading / writing to the ferroelectric memory 14 area can be performed, and the speed can be increased. The write-back from the ferroelectric memory 14 to the flash-type EEPROM memories 13-1,. For this reason, the ferroelectric memory 14 is also equipped with a counter memory for storing the number of accesses.

  By installing this cache function, route information for storing data that is expected to be accessed frequently, directory information, the file name of the data, the file size of the data, or the storage location of the data The system information such as the file allocation table (FAT) information to be stored or the data writing end time information is always present on the ferroelectric memory side, so that substantially the same effect as in FIG. 4 can be exhibited.

  Further, in combination with FIG. 4, system information and frequently accessed data can be held on the ferroelectric memory side. Looking at the memory system as a whole, if read / write to the memory system is repeated, frequently accessed data is retained on the ferroelectric memory side, and the flash EEPROM memory is not accessed, greatly improving performance. To do. In particular, the performance improvement is remarkable when the OS frequently accesses the memory with a small file such as a PC.

[Eighth Embodiment]
FIG. 8 is a block diagram showing a memory system according to the eighth embodiment of the present invention. The configuration is almost the same as in FIG. 7, and the effect is the same as in FIG. The difference is that the data area of the cache having a relatively large capacity is configured by the external ferroelectric memory 30. When a large cache is required, the cost is lower than the case where only the ferroelectric memory 14 is mounted. In order to maintain the same performance as in FIG. 7, it is necessary to connect the controller 15 and the external ferroelectric memory 30 with a relatively high bandwidth bus (BUS) 31. A ferroelectric memory has a low read / write energy per bit, and can read / write many bits at a time, so there is no problem.

[Ninth Embodiment]
FIG. 9 is a block diagram showing a memory system according to the ninth embodiment of the present invention. The configuration is almost the same as in FIG. 7, and the effect is the same as in FIG. The difference is that a memory 14 composed of all ferroelectric memories is externally attached to the outside of the controller 15. Further, the page buffer is constituted by the SRAM 32.

[Tenth embodiment]
FIG. 10 shows an algorithm of the write operation in the memory system according to the tenth embodiment of the present invention. This algorithm can be applied to all the circuits shown in FIGS. 7 to 9, and can be applied to other configurations.

  When the buffer is composed of a ferroelectric memory, when a write command is sent to the memory system, if the write end flag for the buffer is stored in the ferroelectric memory, the writing ends there and an instantaneous power failure occurs. Measures can be taken, and apparent writing performance is improved.

  Further, in the case of SRAM, or without passing through the buffer, the next transfer may be performed. If the data to be stored already exists on the ferroelectric memory side, write it to the cache of the ferroelectric memory, and if not, write it to the free space of the ferroelectric memory. The low data may be temporarily copied to a write buffer and then slowly written to the flash EEPROM memory. The difference from the normal cache is that, at the time of writing to the buffer, at the time of writing to the cache of the ferroelectric memory, at the time of writing to the write buffer, at the time of writing to the flash type EEPROM memory, at least the write end flag is set to the ferroelectric memory It is a point to write in the management area.

  Of course, there may also be a write start flag (Start Flag). As a result, the power may be turned off at any time. The point is to move data between each memory. After copying the source data to the destination, set the destination end flag and cancel the source start flag to end the move. . If this is repeated between the host-memory system, the buffer in the memory system, the ferroelectric memory, and the flash EEPROM memory, the power may be turned off at any time. Although it is a problem if the power is turned off while the flag is turned on / off, the write cycle time of the ferroelectric memory is about 20 ns to 100 ns, so a stabilization cap (Cap) is provided to keep the power during this time. Just do it.

  Data may be written directly to the ferroelectric memory. In this case, if the write flag is set, even if the power is turned off during the writing to the flash EEPROM memory, it can be continued by turning on the power again. Further, if the write flag for the flash EEPROM memory is stored in the ferroelectric memory, the performance is improved.

[Eleventh embodiment]
FIG. 11 is a block diagram showing a memory system according to the eleventh embodiment of the present invention. The configuration is almost the same as in FIGS. 1 to 10, and the effect is also almost the same. The difference is that in the configuration of the memory system, in addition to the controller 15 ', the ferroelectric memory 14, and the flash EEPROM 13, a hard disk device (Hard-Disk) 33 and an interface circuit (Hard-Disk Interface) between the hard disk device 22 34 is a point.

  The hard disk device 33 is a device that magnetically reads / writes data by bringing a head (head) close to a magnetic rotating disk, but seek time for moving the head to a desired position is several to several tens of ms. In addition, since it takes time for the rotating disk to make one rotation, an average half-turn waiting time is required, which takes several ms.

  For this reason, the head of read / write is long and it is inferior to reading / writing a small file. Therefore, by combining the hard disk device 33 and the ferroelectric memory 14, it is desirable to store the system area in the ferroelectric memory 14 and the data area in the hard disk device 33. It is also desirable to copy to the ferroelectric memory. In short, read / write is delayed in the order of the ferroelectric memory 14, the flash EEPROM 13, and the hard disk device 33. Compared with the flash EEPROM 13 and the hard disk device 33, the cost per bit of the hard disk device 33 is overwhelmingly low. Therefore, system information is stored in the ferroelectric memory 14, OS is stored in the flash EEPROM 13, and data is stored in the hard disk device 33. Preservation is desirable. By optimally dividing these into regions, it is possible to realize a large capacity and high speed of a PC etc., thereby realizing a high speed PC start-up.

  Further, the effects described so far can be exhibited only by the ferroelectric memory 14 and the hard disk device 33.

[Twelfth embodiment]
FIG. 12 shows an algorithm of the write operation in the memory system according to the twelfth embodiment of the present invention. This algorithm can be applied to the circuit shown in FIG. 12, and can also be applied to other configurations.

[Thirteenth embodiment]
FIG. 13 is a block diagram showing a memory system according to the thirteenth embodiment of the present invention. The ferroelectric memory 14 has three types of memory, that is, a flash EEPROM memory 13 and a hard disk device 33. Further, the ferroelectric memory 14 has a cache function added thereto. The effect is the same as in FIG. 7 and the like, and the hard disk device 33 is further added, so that it can be more finely and optimally divided into system information, system data, user data, etc. FIG. 3 shows an algorithm of a write operation in the memory system according to FIG. This algorithm can be applied to the circuit shown in FIG. 12, and can also be applied to other configurations.

[Fifteenth embodiment]
FIG. 15 shows a specific example showing the effect of the present invention. The horizontal axis represents the file size unit when performing read / write, and the vertical axis represents the effective read / write bandwidth.

  In the case of a single hard disk (HD in the figure), when the file size is large, the read / write bandwidth is large, but when the file size is small, seek time and rotation waiting time are effective and the performance is greatly degraded.

  Similarly, the flash EEPROM (NAND in the figure) increases the effective write bandwidth when the program page unit is increased, and the effective bandwidth of the read increases when the IO bandwidth is increased. However, especially when the write bandwidth is small, it takes time to write system information such as FAT information, and the performance is greatly degraded.

  In contrast, when the system information is provided in the ferroelectric memory and the data is provided in the flash type EEPROM memory (NAND + FeRAM FAT in the figure) as shown in the present invention, the writing performance is maintained even when the file size is small. it can. Furthermore, when the non-volatile cache of the flag information pair is composed of a ferroelectric memory and combined with a flash type EEPROM memory (NAND + FeRAM Cache), the writing performance is greatly improved. Thus, the presence of a cache improves read performance.

  On the other hand, the OS (XP) file number distribution indicates the file size distribution of the OS portion of Windows XP (registered trademark). Looking at the performance at the peak point (Peak Point) of the file size, it can be seen that the performance of the present invention can be improved several times to several tens of times as compared with the conventional flash EEPROM memory system and hard disk system. This shows that the OS operation of the portable device can be dramatically improved.

  Therefore, according to the first to fifteenth embodiments described above, it is possible to obtain a memory system capable of increasing the read / write speed while suppressing an increase in cost.

(Function)
According to one aspect of the present invention, a flash EEPROM memory having a large capacity as a data storage memory requiring a large memory area but requiring a read cue time, a program time, and an erase time is required. Root information or directory (Directory) for storing the above data that needs to be stored and needs only a small memory area, but needs to be written in many places with a small capacity as data is written Information, file name of the data, file size of the data, file allocation table information for storing the data storage location, storage of the write end time of the data, and actual data (Block) stored in the above flash EEPROM memory System information such as the assignment table (Assign Table) that shows the relationship between the physical address (Address) at the location and page (Page) and the actual logical address (Address), but with a small capacity, high-speed read (Read) / write ( By storing the data in a ferroelectric memory that can perform (Write), the time for writing system information can be substantially reduced, and the performance of the entire OS system and the entire memory system can be greatly improved. In particular, when the size of the data file to be read / written is small, the storage amount of the system information becomes relatively large, so the effect of the present invention is improved.

  Further, by storing in the control circuit or the ferroelectric memory information defining the area stored in the flash type EEPROM memory and the area stored in the ferroelectric memory in the logical address space, The system area can be set freely, and a file (File) frequently read / written in the data area can be accelerated, and the read / write performance of the entire system can be improved.

  Further, data is stored in the flash type EEPROM memory, and flag information indicating that recording of the data to the flash type EEPROM memory is actually started or data in the ferroelectric memory is performed. By storing flag information indicating that recording into the flash EEPROM memory is actually completed, the performance as a memory system is improved.

  Further, data is stored in the flash type EEPROM memory, and each page of the flash type EEPROM memory, a flag indicating whether or not each block is used, and a flag indicating whether or not use is possible are stored in the ferroelectric memory. As a result, the storage speed can be increased, and the performance of the entire system is improved.

  In addition, a ferroelectric memory in which a plurality of memory cells each including a ferroelectric capacitor and a cell transistor are provided, and a plurality of memory cells having a floating gate and electrically erasing and writing data are provided. A flash type EEPROM memory, a ferroelectric memory, a control circuit for controlling the flash type EEPROM memory, and an interface circuit for communicating with the outside, and the ferroelectric memory for external writing After writing the write start flag, write data, write address, and write end flag to the ferroelectric memory, data is written to the flash EEPROM memory and data is written to the flash EEPROM memory. Write start flag and Data, a write address, and a write end flag are written in the ferroelectric memory, so that the memory system once writes data to the ferroelectric memory in response to a write command from the outside of the memory system, By having the flag for the end of writing, writing when the memory system is viewed from the outside is completed. After that, even if an instantaneous power failure or card removal occurs while data is being written to the flash EEPROM memory, if the power is turned on again, the ferroelectric memory can be transferred to the flash EEPROM memory. Re-execute data movement and copying.

  Furthermore, the flash EEPROM memory and the ferroelectric memory are allowed to store data of the same logical address, and the first flag indicating that storage is permitted, and the content of the data at the same logical address are Second flag information indicating whether the flash EEPROM memory and the ferroelectric memory are the same or different, the logical address information, and a physical address stored in the flash EEPROM memory are stored in the ferroelectric memory. As a result, reading / writing of data with high read frequency is only access to the ferroelectric memory, access to the flash type EEPROM memory is reduced, and effective read / write bandwidth is improved.

  Furthermore, the memory system is composed of a hard disk, a flash EEPROM memory, and a ferroelectric memory, the system information is stored in the ferroelectric memory, and the data is stored in the hard disk and the flash EEPROM memory. High-speed operation is possible while being a memory system.

  As described above in detail, according to each embodiment of the present invention, high-speed read / write of file system information such as an OS and system information such as card accompanying data writing can be realized, and the capacity is low and the capacity is high. A memory system capable of reading / writing data at high speed can be constructed.

(Modification)
Although the present invention has been described using various embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention at the stage of implementation. It is. Each of the above embodiments includes inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in each embodiment, at least one of the problems described in the column of problems to be solved by the invention can be solved, and is described in the column of effects of the invention. When at least one of the effects is obtained, a configuration in which this configuration requirement is deleted can be extracted as an invention.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

1 is a block diagram showing a memory system according to a first embodiment of the present invention. The block diagram which shows the memory system which concerns on the 2nd Embodiment of this invention. The block diagram which shows the memory system which concerns on the 3rd Embodiment of this invention. The block diagram which shows the memory system which concerns on the 4th Embodiment of this invention. The block diagram which shows the memory system which concerns on the 5th Embodiment of this invention. FIG. 10 is an algorithm diagram showing a write operation of a memory system according to a sixth embodiment of the present invention. The block diagram which shows the memory system which concerns on the 7th Embodiment of this invention. The block diagram which shows the memory system which concerns on the 8th Embodiment of this invention. The block diagram which shows the memory system which concerns on the 9th Embodiment of this invention. The algorithm diagram which shows write-in operation | movement of the memory system based on the 10th Embodiment of this invention. The block diagram which shows the memory system which concerns on the 11th Embodiment of this invention. The algorithm diagram which shows write-in operation | movement of the memory system based on the 12th Embodiment of this invention. A block diagram showing a memory system concerning a 13th embodiment of the present invention. The algorithm diagram which shows write-in operation | movement of the memory system based on the 14th Embodiment of this invention. The characteristic view which shows the relationship between the file size unit of the memory system to which the 1st thru | or 14th embodiment of this invention is applied, and a bandwidth. The circuit diagram which shows the conventional ferroelectric memory and the ferroelectric memory of a prior application. The circuit diagram and characteristic diagram for demonstrating the operation example of the ferroelectric memory of a prior application. The circuit diagram and the cross-sectional block diagram which show the memory using the conventional magnetoresistive effect. FIG. 3 is a circuit diagram showing a memory cell block of a conventional NAND flash EEPROM. A circuit diagram and a block diagram for explaining a memory cell array of a conventional NAND flash EEPROM. The circuit diagram for demonstrating the operation example of the conventional NAND type flash EEPROM, and the distribution map of the threshold voltage of a cell transistor. The schematic diagram for demonstrating the multi-value operation | movement of the conventional NAND type flash EEPROM. FIG. 6 is an equivalent circuit diagram of a conventional AND-type, NOR-type, DINOR-type flash EEPROM memory cell. The schematic diagram which shows the operation example of a memory card for demonstrating the problem of the conventional memory system which the present inventors considered. FIG. 7 is a schematic diagram illustrating a file writing sequence in a conventional OS operation for explaining problems of the conventional memory system considered by the present inventors.

  DESCRIPTION OF SYMBOLS 11 ... Host apparatus, 12 ... Wiring, 13-1, ..., 13-n ... NAND type flash EEPROM memory, 14, 14-1, 14-2 ... Ferroelectric memory, 15 ... Controller (control circuit), 21, 22, 23, 34 ... interface circuit, 24 ... MCU, 25, 25 '... microcode memory, 26 ... multiplexer / demultiplexer, 27, 27' ... page buffer, 28 ... SRAM, 29 ... write-back buffer, 30 ... cache Data area, 31 ... bus, 32 ... SRAM, 33 ... hard disk device, Bin / Be ... write start / end information to buffer memory (SRAM, FeRAM, etc.), FAT ... file allocation table, R ... read, W ... write, / BL, BL, BLi ... bit line, PL, PLi ... play Electrode, WL ... word line, WLi ... sub-word lines, BS, BSi ... block select line, SL ... source line, SSL, GSL ... block selection lines, AT ... allocation table.

Claims (14)

A first memory composed of a flash type EEPROM in which a plurality of electrically erasable and writable memory cells are arranged, a ferroelectric memory, a magnetoresistive memory, and a phase change memory; A second memory having a smaller capacity and a faster writing speed than the first memory, a control circuit for controlling the first and second memories, and an interface circuit for communicating with the outside,
Storing data in the first memory;
In the second memory, route information for storing the data, directory information, file name of the data, file size of the data, or file allocation table information for storing the data storage location Alternatively, the data writing end time is stored,
For a write from outside the memory system, a write end flag to the second memory is written to the second memory, and then a write end flag to the first memory is written to the second memory. A memory system characterized by that. A first memory composed of a flash type EEPROM in which a plurality of electrically erasable and writable memory cells are arranged, a ferroelectric memory, a magnetoresistive memory, and a phase change memory; A second memory having a smaller capacity and a faster writing speed than the first memory, a control circuit for controlling the first and second memories, and an interface circuit for communicating with the outside,
Storing data in the first memory;
The second memory stores a logical-physical conversion address indicating a relationship between a block position where the data is actually stored in the first memory, a physical address of a page position, and an actual logical address;
For a write from outside the memory system, a write end flag to the second memory is written to the second memory, and then a write end flag to the first memory is written to the second memory. A memory system characterized by that. A first memory composed of a flash type EEPROM in which a plurality of electrically erasable and writable memory cells are arranged, a ferroelectric memory, a magnetoresistive memory, and a phase change memory; A second memory having a smaller capacity and a faster writing speed than the first memory, a control circuit for controlling the first and second memories, and an interface circuit for communicating with the outside,
In the logical address space, information defining an area to be stored in the first memory and an area to be stored in the second memory is stored in the control circuit or the second memory,
For a write from outside the memory system, a write end flag to the second memory is written to the second memory, and then a write end flag to the first memory is written to the second memory. A memory system characterized by that. A first memory composed of a flash type EEPROM in which a plurality of electrically erasable and writable memory cells are arranged, a ferroelectric memory, a magnetoresistive memory, and a phase change memory; A second memory having a smaller capacity and a faster writing speed than the first memory, a control circuit for controlling the first and second memories, and an interface circuit for communicating with the outside,
Storing data in the first memory;
The second memory indicates flag information indicating that recording of the data has actually started in the first memory or indicates that recording of the data has actually ended in the first memory. Memorize flag information,
For a write from outside the memory system, a write end flag to the second memory is written to the second memory, and then a write end flag to the first memory is written to the second memory. A memory system characterized by that. A first memory composed of a flash type EEPROM in which a plurality of electrically erasable and writable memory cells are arranged, a ferroelectric memory, a magnetoresistive memory, and a phase change memory; A second memory having a smaller capacity and a faster writing speed than the first memory, a control circuit for controlling the first and second memories, and an interface circuit for communicating with the outside,
Storing data in the first memory;
In the second memory, each page of the first memory, a flag indicating whether or not each block is used, and a flag indicating whether or not the block can be used are stored.
For a write from outside the memory system, a write end flag to the second memory is written to the second memory, and then a write end flag to the first memory is written to the second memory. A memory system characterized by that. A first memory composed of a flash type EEPROM in which a plurality of electrically erasable and writable memory cells are arranged, a ferroelectric memory, a magnetoresistive memory, and a phase change memory; A second memory having a smaller capacity and a faster writing speed than the first memory, a control circuit for controlling the first and second memories, and an interface circuit for communicating with the outside,
In response to external writing, the write start flag, write data, write address, and write end flag to the second memory are written to the second memory, and then the data is transferred to the first memory. In the memory system, a write start flag, write data, a write address, and a write end flag in writing and data writing to the first memory are written to the second memory. A first memory composed of a flash type EEPROM in which a plurality of electrically erasable and writable memory cells are arranged, a ferroelectric memory, a magnetoresistive memory, and a phase change memory; A second memory having a smaller capacity and a faster writing speed than the first memory, a control circuit for controlling the first and second memories, and an interface circuit for communicating with the outside,
For writing from the outside, a write end flag to the second memory is written to the second memory, and then a write end flag to the first memory is written to the second memory. And memory system. A first memory composed of a flash type EEPROM in which a plurality of electrically erasable and writable memory cells are arranged, a ferroelectric memory, a magnetoresistive memory, and a phase change memory; A second memory having a smaller capacity and a faster writing speed than the first memory, a control circuit for controlling the first and second memories, and an interface circuit for communicating with the outside,
Storing data in the first memory;
The memory system, wherein the second memory stores an end time for writing the data. Semiconductor memory comprising any one of a ferroelectric memory, a magnetoresistive memory, and a phase change memory, a hard disk device that stores data by magnetism, a control circuit that controls the semiconductor memory and the hard disk device, and communication with the outside An interface circuit for performing
Data is stored in the hard disk device, and route information, directory information, a file name of the data, a file size of the data, or storage of the data is stored in the semiconductor memory. A memory system characterized by storing file allocation table information for storing a location or a data write end time. A semiconductor memory including any one of a ferroelectric memory, a magnetoresistive memory, and a phase change memory, a hard disk device that stores data by magnetism, a control circuit that controls the semiconductor memory and the hard disk device, and communication with the outside Interface circuit to perform,
Data is stored in the hard disk device, and the semiconductor memory has a logical-physical relationship indicating the relationship between the physical address of the sector position and track position where the data is actually stored in the memory of the hard disk device, and the actual logical address. A memory system for storing a translation address. Semiconductor memory comprising any one of a ferroelectric memory, a magnetoresistive memory, and a phase change memory, a hard disk device that stores data by magnetism, a control circuit that controls the semiconductor memory and the hard disk device, and communication with the outside An interface circuit for performing
A memory system characterized in that, in a logical address space, information defining an area to be stored in the hard disk device and an area to be stored in the semiconductor memory is stored in the control circuit or the semiconductor memory. Semiconductor memory comprising any one of a ferroelectric memory, a magnetoresistive memory, and a phase change memory, a hard disk device that stores data by magnetism, a control circuit that controls the semiconductor memory and the hard disk device, and communication with the outside An interface circuit for performing
The hard disk device stores data, and the semiconductor memory has flag information indicating that the data has actually started to be recorded on the hard disk device or the data has actually been recorded on the hard disk device. A memory system for storing flag information indicating that the operation has been performed. Semiconductor memory comprising any one of a ferroelectric memory, a magnetoresistive memory, and a phase change memory, a hard disk device that stores data by magnetism, a control circuit that controls the semiconductor memory and the hard disk device, and communication with the outside An interface circuit for performing
A memory system, wherein data is stored in the hard disk device, and each track of the hard disk device, a flag indicating whether or not sector information is used, and a flag indicating whether or not use is possible are stored in the semiconductor memory. Semiconductor memory comprising any one of a ferroelectric memory, a magnetoresistive memory, and a phase change memory, a hard disk device that stores data by magnetism, a control circuit that controls the semiconductor memory and the hard disk device, and communication with the outside An interface circuit for performing
In response to external writing, a write end flag to the semiconductor memory is written to the semiconductor memory, and then a write end flag to the hard disk device is written to the semiconductor memory.

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