JP2011244178A - Image processor and control method of image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processor capable of efficiently performing an image data processing such as compression and decompression with respect to first image data and second image data stored in a storage part.SOLUTION: An image processor 1 according to the present invention comprises an image data lossless compression core 22 and an image data lossy compression core 21, and further comprises a DRAM for storing the first image data and the second image data, and a CPU 12 for separating the first image data stored in the DRAM into a first region part and a second region part according to characteristics, wherein the image data lossy compression core 21 performs compression of the second region part and the second image data while the image data lossless compression core 22 performs compression of the first region part.

Description

  The present invention relates to an image processing apparatus that performs compression processing of image data or expansion processing of compressed image data. In particular, the present invention relates to an image processing apparatus including a compression processing unit that uses different compression processing methods for a compression processing unit that performs reversible compression of image data and a compression processing unit that performs irreversible compression.

  Digital multi-function peripherals having many functions including a scanner function, a copy function, a printer function, and a FAX function have been developed. The digital multi-function peripheral can process in parallel jobs that have been instructed by the user and jobs that have been submitted from remote devices via a communication network or telephone line network. For this reason, the processing performed in the digital multi-function peripheral becomes very complicated.

  Furthermore, in recent years, not only the above-described functions but also various functions have been added, and the multifunctional functions of digital multifunction peripherals have been further advanced. For example, new functions implemented in digital multifunction devices include various network-related services or processing of data provided from recording media such as USB memory or SD card, creation of PDF documents, creation of various forms, etc. Application functions to realize it are listed.

  Digital MFPs can achieve the functions described above without sacrificing user convenience, and are required to properly process all jobs even when multiple functions are required at the same time. It is done.

  Also, one of the main functions of the digital multifunction peripheral is to output a still image digital image. For this reason, improvement of the image quality of the digital image output from the digital multifunction peripheral is an indispensable problem. In general, in order to achieve an improvement in image quality in a digital image, the gradation of pixels is increased, an appropriate image process is performed on the digital image, or a compression method with small image quality degradation is employed. However, if only the purpose of improving the image quality of a digital image is achieved, other processing capabilities (for example, the processing speed required for image output processing) of the entire digital multi-function peripheral will be reduced, and the convenience of the user will be impaired. Therefore, it is desirable to determine an image processing method in consideration of both image quality and processing capability.

  For example, compression methods used for digital image storage / transmission include compression formats called lossless compression and lossy compression. Lossless compression is a compression format that can restore an original image completely by compressing the image and performing decompression processing later. Typical methods for lossless compression include MR (modified READ), MMR (modified modified READ), JBIG, and the like used in FAX and the like.

  On the other hand, irreversible compression includes a method of compressing an image by deleting some information when compressing the image. Therefore, it is impossible to restore the original image after decompression. Examples of lossy compression methods include JPEG, JPEG2000, JPEG-XR, and the like. In general, irreversible compression has the advantage that the compression rate can be increased and the compression rate can be adjusted compared to the lossless compression. On the other hand, since the original image cannot be restored after decompression, the image quality will be lower than that of lossless compression.

  If the compression rate is thus reduced, the data size of the compressed image data is increased. For this reason, in a storage device such as a hard disk drive, a sufficient storage area for image data cannot be secured, or the transfer time of image data to the storage area becomes long. As a result, the performance of the entire digital multi-function peripheral is degraded.

  Conversely, when emphasis is placed on improving the processing capability of the digital multi-function peripheral and irreversible compression is selected as the compression method, if the compression rate is increased too much, the image quality will deteriorate and the image quality that satisfies the user cannot be obtained.

  Therefore, Patent Document 1 proposes an image processing apparatus that uses the characteristics of both lossless compression and lossy compression. The image processing apparatus disclosed in Patent Document 1 analyzes a still image, determines a characteristic area (characteristic area) such as a photographic area or a character area, and divides it into layers. Then, compression is performed according to the characteristics of the obtained layer. For example, for an image having a large density change such as a photographic area, even if irreversible compression is performed, the influence of image quality deterioration is small. For this reason, irreversible compression that can increase the compression rate is performed in a photographic region or the like. On the other hand, image quality degradation is conspicuous for character areas due to block noise or the like in lossy compression. For this reason, the character area is subjected to lossless compression in consideration of image quality.

JP 2010-10819 A (published on January 14, 2010)

  However, the conventional technique as described above has a problem that the data amount reduction processing cannot be efficiently performed on the image data.

  More specifically, in the case of a configuration in which compression processing is performed separately for each layer of a photo area and a character area as in the image processing device disclosed in Patent Document 1, compression processing of lossless compression or lossy compression is performed. Each time it is done, it is necessary to access the main memory and read the image data. For this reason, the number of accesses to the main memory storing the image data increases, and the image data cannot be efficiently compressed.

  Therefore, in order to reduce the number of accesses to the main memory, it is possible to assume a configuration in which image data is read in units of a predetermined number of pixels and both irreversible compression processing and reversible compression processing are performed on the image data. That is, it can be considered that the access to the main memory that is performed when performing lossless compression and lossy compression is made common.

  However, in the case of a configuration in which access to the main memory is shared as described above, the following problems occur. That is, when there is a difference in processing performance (processing speed) between a compressor that performs lossless compression processing and a compressor that performs lossy compression processing, a compressor with high processing performance is processed by a compressor with low processing performance. The problem arises that there is a need to wait until is completed.

  Thus, even with a configuration in which access to the main memory is shared, efficient compression processing cannot be realized. This problem occurs not only in the compression process but also in the decompression process of the compressed image data. That is, image data processing such as compression processing and decompression (decompression) processing cannot be performed efficiently.

  The present invention has been made in view of the above problems, and an object thereof is to realize an image processing apparatus and an image processing apparatus control method capable of efficiently performing image data processing on image data. There is.

  In order to solve the above-described problem, the image processing apparatus according to the present invention performs a first data processing unit that performs image data processing including at least one of compression of image data and expansion of the compressed image data. And an image processing apparatus having a second data processing unit having a different processing method of image data processing from the first data processing unit and a processing time for the image data processing being shorter than that of the first data processing unit. In addition, as image data to be subjected to the image data processing, a storage unit that stores first image data including regions having different characteristics and second image data different from the first image data, and storage in the storage unit The first image data that has been subjected to image data processing by the first data processing unit in accordance with the characteristics of the regions constituting the first image data, A separation unit that separates the second data processing unit into a second region part that is a region where image data processing is performed by the second data processing unit, and the first data processing unit performs image data processing of the first region part. In addition, the second data processing unit reads the second region portion and the second image data from the storage unit and performs image data processing.

  Since the image processing apparatus according to the present invention includes the first data processing unit and the second data processing unit that have different image data processing methods, the image data of the image data is obtained by an appropriate method according to the characteristics of the image data. Processing can be performed.

  Note that the characteristics of the image data include whether or not the image data is greatly affected by the deterioration of the image quality accompanying the image data processing.

  According to the above configuration, since the separation unit is further provided, the first image data can be separated into the first region portion and the second region portion according to the characteristics of the regions constituting the image data. The separated first region portion and second region portion can be subjected to image data processing in parallel by the first data processing unit and the second data processing unit, respectively. For example, as the image data is compressed, the first image data is separated depending on whether the image data is greatly affected by the deterioration in image quality, and the first data processing unit and the second data are separated according to the respective characteristics. Processing can be performed in parallel with the processing unit.

  The second data processing unit also reads out the second image data from the storage unit in addition to the second region portion while the first data processing unit performs image data processing of the first region portion. Image data processing can be performed.

  For this reason, the image processing apparatus according to the present invention has an effect that the image data processing can be efficiently executed on the image data stored in the storage unit.

  In the image processing apparatus according to the present invention, in the configuration described above, a priority for performing the image data processing is set in the first area portion and the second image data. A transfer unit configured to read each of the two image data from the storage unit and transfer the read image data to the second data processing unit; and the transfer unit converts the second area portion or the second image data into the second data processing according to the priority. It may be configured to forward to a part.

  According to the configuration described above, since the transfer unit is provided, the second region portion or the second image data can be transmitted to the second data processing unit in accordance with a preset priority.

  Therefore, even when image data processing execution has priority, processing can be performed according to the priority.

  In the image processing apparatus according to the present invention, in the configuration described above, when the transfer unit transfers image data of either the second region portion or the second image data to the second data processing unit, A transmission data instruction signal indicating whether the image data to be transferred is the second area portion or the second image data is output, and the second data processing unit is transferred based on the transmission data instruction signal It may be configured to determine whether the data is the second region portion or the second image data, and to execute image data processing according to the transferred data.

  In the image processing apparatus according to the present invention, in the configuration described above, the second data processing unit includes first data processing information that is information for executing image data processing of the second region portion, and the first data processing unit. Second data processing information that is information for executing image data processing of two image data, and based on the transmission data instruction signal, either the first data processing information or the second data processing information is stored. It may be configured to select the image data and execute image data processing according to the transferred data.

  According to the above configuration, the second data processing unit holds the first data processing information and the second data processing information, and the image is based on the first data processing information or the second data processing information according to the transmission data instruction signal. Data processing can be performed. Therefore, the second data processing unit can perform processing according to each processing content even when the processing content of the transferred image data processing is different.

  In order to solve the above-described problem, a control method for an image processing apparatus according to the present invention performs image data processing including at least one of compression of image data and expansion of the compressed image data. The one data processing unit and the first data processing unit have a processing method for image data processing and a second data processing unit having a processing time required for the image data processing smaller than that of the first data processing unit. A control method for an image processing device, wherein the image processing device includes first image data including regions having different characteristics and second image data different from the first image data as image data to be subjected to the image data processing. And storing the first image data stored in the storage unit in accordance with the characteristics of the area constituting the first image data. A separation step of separating a first region portion, which is a region where image data processing is performed by the unit, and a second region portion, which is a region where image data processing is performed by the second data processing unit, and the first data processing unit While performing the image data processing of the first region portion, the second data processing unit reads the second region portion and the second image data from the storage unit and performs image data processing. And a step.

  Since the control method of the image processing apparatus according to the present invention includes the first data processing unit and the second data processing unit that are different in the processing method of the image data processing, the image data is processed by an appropriate method according to the characteristics of the image data. Image data processing can be performed.

  Note that the characteristics of the image data include whether or not the image data is greatly affected by the deterioration of the image quality accompanying the image data processing.

  Since the method further includes a separation step, the first image data can be separated into the first region portion and the second region portion according to the characteristics of the regions constituting the image data. The separated first region portion and second region portion can be subjected to image data processing in parallel by the first data processing unit and the second data processing unit, respectively. For example, as the image data is compressed, the first image data is separated depending on whether the image data is greatly affected by the deterioration in image quality, and the first data processing unit and the second data are separated according to the respective characteristics. Processing can be performed in parallel with the processing unit.

  In addition, since the image data processing step is included, the second data processing unit includes the second data portion in addition to the second region portion while the first data processing unit performs image data processing of the first region portion. Image data can also be read from the storage unit and subjected to image data processing.

  For this reason, the control method of the image processing apparatus according to the present invention has an effect that the image data processing can be efficiently executed on the image data stored in the storage unit.

  As described above, the image processing apparatus according to the present invention is at least one of compression of image data and expansion of the compressed image data in order to solve the above-described problem. The first data processing unit that performs image data processing including two processes differs from the first data processing unit in the processing method of image data processing, and the processing time required for the image data processing is greater than that of the first data processing unit. An image processing apparatus having a smaller second data processing unit, wherein the image data to be subjected to the image data processing is a first image data including regions having different characteristics and a second image different from the first image data. A storage unit for storing data and the first image data stored in the storage unit by the first data processing unit according to the characteristics of the area constituting the first image data. A separation unit that separates a first region part that performs data processing into a second region part that performs image data processing by the second data processing unit, and the first data processing unit includes: While performing the image data processing of the first region portion, the second data processing unit reads the second region portion and the second image data from the storage unit, and performs image data processing. And

  For this reason, the image processing apparatus according to the present invention has an effect that the image data processing can be efficiently executed on the image data stored in the storage unit.

  As described above, the control method of the image processing apparatus according to the present invention includes a first data processing unit that performs image data processing including at least one of compression of image data and expansion of the compressed image data. And a second data processing unit having a processing method for image data processing different from that of the first data processing unit and a processing time required for the image data processing is shorter than that of the first data processing unit. In the control method, the image processing apparatus stores, as image data to be subjected to the image data processing, first image data including regions having different characteristics and second image data different from the first image data. A storage unit, wherein the first image data stored in the storage unit is converted into an image by the first data processing unit according to the characteristics of the area constituting the first image data. A separation step for separating a first area portion that is an area for performing data processing and a second area portion that is an area for performing image data processing by the second data processing section; While performing the image data processing of the region portion, the second data processing unit reads the second region portion and the second image data from the storage unit, and performs an image data processing step of performing image data processing; It is characterized by including.

  For this reason, the control method of the image processing apparatus according to the present invention has an effect that the image data processing can be efficiently executed on the image data stored in the storage unit.

1, showing an embodiment of the present invention, is a block diagram illustrating a configuration of main parts related to compression processing in an image processing apparatus. FIG. 1, showing an embodiment of the present invention, is a block diagram illustrating a main configuration of a compression module. FIG. 4 is a flowchart illustrating a processing flow of compression processing in the compression module according to the embodiment of this invention. FIG. 4 is a diagram illustrating an example of reading data from a DRAM to an SRAM according to an embodiment of the present invention. It is a figure which shows embodiment of this invention and shows the replacement process performed by the data replacement part. It is a figure which shows embodiment of this invention and shows the replacement process performed by the data replacement part. FIG. 5 is a diagram illustrating an embodiment of the present invention and a time chart of arbitration processing by an arbiter. FIG. 4 shows an embodiment of the present invention, and shows a comparison of processing times when the compression processing of the first image data set is performed in each of the instruction data lossless compression core, the image data lossless compression core, and the image data lossy compression core. FIG. 4 is a flowchart illustrating a processing flow of compression processing in the compression module according to the embodiment of this invention. FIG. 5 is a diagram illustrating a signal waveform when the image data lossy compression core receives image data according to the embodiment of the present invention. FIG. 5 is a diagram illustrating an example of a processing state when two types of image data are compressed in a time-sharing manner according to the embodiment of this invention. 1, showing an embodiment of the present invention, is a block diagram showing a main configuration of an image data lossy compression core. FIG.

  An embodiment of the present invention will be described below with reference to FIGS. That is, the image processing apparatus 1 according to the present embodiment determines a feature region (characteristic region) such as a photograph region or a character region from image data, and reversible compression or lossy compression (image data processing) according to the feature region. Is to do. The image processing apparatus 1 can be realized by, for example, a copying machine, a printer, a scanner, a facsimile, or a digital multifunction machine that integrates these.

  First, a configuration relating to compression processing in the image processing apparatus 1 will be described with reference to FIG. FIG. 1 shows an embodiment of the present invention and is a block diagram showing a main configuration relating to compression processing in an image processing apparatus 1.

(Configuration related to compression processing of image processing apparatus)
As shown in FIG. 1, the image processing apparatus 1 according to the present embodiment includes an interrupt control unit 11, a CPU 12, a memory controller 14, an HDD controller 15, an image processing unit 16, and an instruction data generation unit as a configuration related to compression processing. 17 and an image quality improvement image processing unit 18. These units can transmit and receive data through the system bus 2.

  When receiving an event signal from each unit included in the image processing apparatus 1, the interrupt control unit 11 notifies the CPU 12 that an event has occurred. Examples of this event signal include a notification of DMA transfer completion and a notification indicating cancellation of DMA transfer due to a communication error with a slave module (memory controller 14 or the like in the present embodiment). That is, the event signal is a notification signal output from each DMA unit to the interrupt control unit 11. These notification signals notified from each DMA unit are configured to be held in a register (not shown) included in the interrupt control unit 11. Then, the CPU 12 can determine what event has occurred by reading the notification signal from the corresponding register. The CPU 12 determines the content to be operated next depending on the determined event type.

  The CPU 12 performs various controls of each unit included in the image processing apparatus 1. Specifically, the CPU 12 reads program data from a DRAM (main memory) 3 to be described later via the memory controller 14, and operates by interpreting the read command. The CPU 12 can control each unit of the entire image processing apparatus 1 by reading out these commands in order. Examples of this command include a start and end command for the DMA unit, or an interrupt processing command.

  The memory controller 14 is connected to the DRAM 3 and is a module that controls reading and writing of data with respect to the DRAM 3 in accordance with an instruction from the CPU 12 or each DMA unit. In other words, the memory controller 14 operates as a slave module, and reads or writes data of the instructed data size from the address of the DRAM 3 instructed by the CPU 12 that is the master module or each DMA unit. Then, the memory controller 14 transfers the data read from the DRAM 3 in response to the read request to the master module (CPU 12 or each DMA unit) that has made the read request. Alternatively, the memory controller 14 acquires data to be written from the master module in response to a write request, and writes the data to the DRAM 3. The memory controller 14 also performs refresh control and the like so as not to erase data stored in the DRAM 3.

  The HDD controller 15 has a DMA unit, and is a module that reads or writes data from or to a hard disk (HDD) in accordance with an activation command from the CPU 12 to the DMA unit. When all data transfer is completed, the HDD controller 15 notifies the interrupt control unit 11 of completion. Then, this notification is notified to the CPU 12 via the interrupt control unit 11. The data handled by the HDD controller 15 includes all data stored in the HDD such as image data, instruction data, compressed data, and program data.

  The image quality improvement image processing unit 18 has a DMA unit, and is a module that realizes processing related to image quality improvement such as high image quality processing and resolution conversion processing. The image quality improved image processing unit 18 acquires image data from the DRAM 3 in response to a start command from the CPU 12 to the DMA unit. And according to the instruction | indication from CPU12, an image quality improvement process, a resolution conversion process, etc. are implemented with respect to the acquired image data.

  The image processing unit 16 has a DMA unit and is a module that realizes an image processing function. The image processing unit 16 acquires image data from the DRAM 3 in response to a start command from the CPU 12 to the DMA unit, and stores it in the SRAM 25 that is a data buffer. Then, the image processing unit 16 reads the image data stored in the SRAM 25, performs image processing in accordance with an instruction from the CPU 12, and writes the image data in the SRAM 25 that is an output buffer. When the image processing is completed in this way, in the image processing unit 16, the DMA unit writes to the DRAM 3. When this series of processing is repeated and image processing for all image data is completed, the image processing unit 16 sends a completion notification to the interrupt control unit 11. This completion notification is notified to the CPU 12 via the image processing unit 16. Examples of the image processing executed in the image processing unit 16 include processing such as image quality enhancement processing, resolution conversion processing, encryption processing, compression processing, and decompression processing of image data. The compression process and the expansion process correspond to the image data process of the present invention.

  In addition, the image processing unit 16 includes a compression module 13 as a member that executes a compression process. Details of the compression module 13 will be described later.

  The instruction data generation unit 17 has a DMA unit and is a module that generates compression method instruction data (referred to as instruction data). This instruction data is data for specifying the compression format of the image data. The instruction data generation process will be described below.

  The image processing apparatus 1 according to the present embodiment generates instruction data for image data in the following flow. That is, the instruction data generation 17 reads data from the DRAM 3 in accordance with a start command from the CPU 12 and performs image analysis inside the instruction data generation 17. The instruction data generation unit 17 generates 4-bit instruction data (referred to as instruction data) for each pixel (in this embodiment, a total of 24 bits for each RGB is 24 bits as one pixel) from the image analysis result. That is, 4 bits of instruction data are generated for each pixel of 24 bits of image data. For example, when 100 MB of image data is compressed, the instruction data for the 100 MB of image data has a size of 16.7 MB. In this way, the instruction data generation unit 17 generates instruction data under the control instruction from the CPU 12.

  The generated instruction data is written into the DRAM 3 by the DMA included in the instruction data generation unit 17 in accordance with an instruction from the CPU 12 via the memory controller 14. When the instruction data for all the pixels is written in the DRAM 3, the completion of the instruction data generation process is notified to the interrupt control unit 11. This completion notification is sent to the CPU 12 via the interrupt control unit 11.

  Examples of the image analysis performed on the image data include processing such as region determination. That is, in the area determination process, an image having a large color change and density change and a large amount of high-frequency components is determined to be a photographic area, and instruction data for performing irreversible compression on the area is generated. Note that the specific processing content of the image analysis is a known technique, and therefore details thereof are omitted here.

  The compression module 13 has a compression module DMA 24 composed of a plurality of DMA units, and performs data compression processing in accordance with instructions from the CPU 12. As shown in FIG. 1, the compression module 13 includes three compression core modules (an image data lossy compression core 21, an image data lossless compression core 22, and an instruction data lossless compression core 23). In the present specification, when it is not necessary to distinguish between the image data lossy compression core 21, the image data lossless compression core 22, and the instruction data lossless compression core 23, these are collectively referred to as a compression core module. I will call it.

  When the compression module 13 reads image data and instruction data from the DRAM 3, the compression module 13 distributes the data to the three compression core modules, and performs lossless compression and lossy compression. More specifically, the image data irreversible compression core 21 performs irreversible compression on a predetermined area (photo area) including a photograph or the like in the image data. On the other hand, the image data lossless compression core 22 performs lossless compression on an area (character area) in which characters and the like exist in the same image data. The instruction data lossless compression core 23 performs lossless compression of instruction data corresponding to the image data. Below, with reference to FIG. 2, the more detailed structure of the compression module 13 which concerns on this Embodiment is demonstrated. FIG. 2 shows an embodiment of the present invention, and is a block diagram for explaining a main configuration of the compression module 13.

  In FIG. 2, it is described that the compression module 13 reads the first image data, the compression method instruction data, and the second image data from the DRAM 3 for ease of explanation. However, actually, the various image data described above are read from the DRAM 3 through the system bus 2 and the memory controller 14.

(Configuration of compression module)
As shown in FIG. 2, the compression module 13 according to the present embodiment includes a compression module DMA24 (DMA unit 24a to DMA unit 24g), SRAM 25 (SRAM 25a to 25g), arbiter 26, SRAM read controllers 27a to 27c, data replacement. Sections 28a to 28b, a compression core module (image data lossy compression core 21, image data lossless compression core 22, instruction data lossless compression core 23), and SRAM light controllers 29a to 29c.

  The compression module DMA24 (particularly the DMA units 24a to 24c), the SRAM 25 (particularly the SRAMs 25a to 25c), the arbiter 26, and the SRAM read controllers 27a to 27c implement the transfer unit of the present invention.

  The number of DMA units 24a to 24g, SRAMs 25a to 25g, SRAM read controllers 27a to 27c, data replacement units 28a to 28b, compression core modules, and SRAM write controllers 29a to 29c included in the compression module 13 are limited to the numbers described above. Is not to be done. It can be provided as appropriate according to the type of data to be compressed.

  The SRAM 25 stores instruction data read from the DRAM 3, image data (first image data, second image data), and four compressed data (compressed data 24d to 24g) obtained as a result of compressing these various data. It is memory.

  The first image data is, for example, an image acquired from a scanner, and the second image data is, for example, various image formats such as a FAX image.

  The arbiter 26 determines a module that accesses the SRAM 25 in order to read data. More specifically, the arbiter 26 issues an access permission for the SRAM 25 of the SRAM read controllers 27a to 27c. For this reason, only the SRAM read controller to which permission is issued by the arbiter 26 can access the SRAM 25 and read data.

  The data replacement units 28a to 28b perform replacement processing on the image data read from the SRAM 25 by the SRAM read controllers 27b and 27c according to the contents of the instruction data. Then, the data replacement units 28a to 28c output the result of the replacement process to the compression core module. Details of the replacement process will be described later.

  The SRAM write controllers 29a to 29c write data (first to fourth compressed data) compressed by the respective compression core modules to the SRAM 25 (SRAMs 25d to 25g), respectively. Each of the data written in the SRAM 25 is written into the DRAM 3 by the DMAs 24 d to 24 g via the memory controller 14.

  The compression module 13 having the above-described configuration can compress two types of image data (first image data set and second image data) in parallel. The processing flow of the compression processing in the compression module 13 will be described with reference to FIG. 2 and FIGS. FIG. 3 shows an embodiment of the present invention and is a flowchart showing a processing flow of compression processing in the compression module 13.

(Processing flow of compression processing)
First, as a premise, as two types of image data to be compressed in parallel, data including first image data and its instruction data (first image data set) and image data different from the first image data are used. It is assumed that certain second image data is stored in the DRAM 3 as shown in FIG. A part of the first image data is irreversibly compressed, and the other part is reversibly compressed. The instruction data is reversibly compressed. It is assumed that the second image data is only subjected to lossy compression.

  The DMA transfer of instruction data to the SRAM 25 is performed by the DMA unit 24a, and the DMA transfer of the first image data to the SRAM 25 is performed by the DMA unit 24b. The DMA transfer of the second image data to the SRAM 25 is performed by the DMA unit 24c. On the other hand, the DMA transfer of the lossless instruction data to the DRAM 3 is performed by the DMA unit 24d, and the DMA transfer of the losslessly compressed first image data to the DRAM 3 is performed by the DMA unit 24e by the lossy compressed first image. DMA transfer of data to the DRAM 3 is performed by the DMA unit 24f. It is assumed that the DMA unit 24g performs the DMA transfer of the lossy-compressed second image data to the DRAM 3.

  Note that the image compression processing of each of the two types of image data can be activated and terminated independently. Therefore, for convenience of explanation, each case will be described individually in the following flowchart.

(Compression processing of the first image data set)
First, compression processing of the first image data set will be described.

  As shown in FIG. 3, the CPU 12 performs source operation setting of the DMA unit (DMA units 24a and 24b) (step S11, hereinafter referred to as S11). The DMA source operation setting is to set a position (address) in the DRAM 3 in which data acquired by each of the DMA units 24a and 24b is stored, a data size corresponding to the image size, and the like. This setting is configured so that the CPU 12 automatically performs the setting based on the data size of the document stored in the DRAM 3 and the usage status of the DRAM 3.

  In step S11, the CPU 12 also sets data handled by each of the DMA unit 24a and the DMA unit 24b. Specifically, the CPU 12 performs this setting by designating an address indicating a storage position of data read by each of the DMA units 24a and 24b. For example, when the instruction data and the first image data are stored in the DRAM 3 as shown in FIG. 2, the CPU 12 sets the storage address of the instruction data to the address 0x0000_0000 for the DMA unit 24a and the DMA unit 24b. The storage address of the first image data is set as an address 0x1000_0000.

  Next, the CPU 12 performs destination operation setting of the DMA unit (DMA unit 24d to DMA unit 24f) (S12).

  The destination operation setting is to designate in which position (address) of the DRAM 3 the data after compression processing should be stored.

  More specifically, the CPU 12 sets the DMA unit 24d to store the instruction data after the lossless compression (first compressed data) at the start address 0x3000_0000. The DMA unit 24e is set to store the image data after the lossless compression (second compressed data) at the start address 0x4000_0000. The DMA unit 24e is set to store the image data after the lossy compression (third compressed data) at the start address 0x5000_0000.

  When the source operation setting and the destination operation setting are completed as described above, the CPU 12 activates the compression module DMA24 (S13). When the CPU 12 instructs the compression module DMA 24 to start, each DMA unit (in this embodiment, the DMA units 24 a and 24 b) requests data from the DRAM 3.

  First, the DMA unit 24b reads the first image data from the DRAM 3 by the data size of the SRAM. Then, the read data is stored in the SRAM 25 (S14).

  Specifically, as shown in FIG. 4, data read from the DRAM 3 is read to the SRAM 25. FIG. 4 illustrates an embodiment of the present invention, and is a diagram illustrating an example of reading data from the DRAM 3 to the SRAM 25.

  That is, the image data stored in the DRAM 3 has 100 pixels in the main scanning direction (left-right direction in the figure), and the data is continuously stored as shown in FIG. In the present embodiment, the irreversible compression process is performed in units of 8 × 8 pixels. On the other hand, since the SRAM 25 has a capacity of three 8 × 8 pixels, rectangular area data (192 pixels) for 24 lines in the main scanning direction and 8 lines in the sub-scanning direction (vertical direction in the figure) are transferred to the DMA. The unit 24b reads from the DRAM 3 and stores it in the SRAM 25. As a result, pixel data is stored in the SRAM 25 as shown in FIG.

  Next, the DMA unit 24a reads the instruction data from the DRAM 3 by the data size of the SRAM. Then, the read data is stored in the SRAM 25 (S15).

  Specifically, similarly to the first image data described above, the data read from the DRAM 3 is read to the SRAM 25 as shown in FIG.

  That is, it is assumed that the instruction data is continuously stored from the set start address, similarly to the first image data. In addition, the area | region part for which instruction | indication data is required is a rectangular area part corresponding to the image area | region which performs irreversible compression in 1st image data. For this reason, the DMA unit 24a acquires data for 24 pixels in the main scanning direction and 8 pixels in the sub-scanning direction of the corresponding area and stores them in the SRAM 25.

  When the acquisition of the instruction data and the first image data is completed as described above, the compression module DMA 24 notifies the SRAM read controllers 27a to 27c of the completion of data acquisition. When this notification is received, the SRAM read controllers 27a to 27c start reading processing of the image data and the instruction data according to the arbitration result of the arbiter 26 for the image data and the instruction data. The data replacement units 28a and 28b perform replacement processing on the image data read from the SRAM 25 by the SRAM read controllers 27b and 27c in accordance with the contents of the instruction data. When the replacement process is performed, the SRAM read controllers 27a to 27c transfer the compressed core module (S16).

  Here, the replacement process executed by the data replacement units 28a and 28b will be described with reference to FIG. FIG. 5 shows an embodiment of the present invention, and is a diagram showing a replacement process executed by the data replacement units 28a and 28b.

  First, the case where the result after the replacement process is output to the image data lossy compression core 21 will be described.

  The data replacement units 28 a and 28 b obtain the pixel “001” of the image data and the corresponding instruction data “1” from the respective SRAMs 25. Here, the instruction data is indicated by a binary value of “0” or “1”, “0” means a pixel to be subjected to lossless compression processing, and “1” performs lossy compression processing. It means that the pixel is a power pixel.

  Thus, the value “1” of the instruction data means that the irreversible compression process is performed on the pixel “001” of the corresponding first image data. Therefore, the pixel “001” of the first image data is output to the image data lossy compression core 21.

  Next, the value of the instruction data corresponding to the pixel “002” of the first image data is also “1”. Therefore, the pixel “002” is also output to the image data lossy compression core 21. In this way, the output to the image data lossy compression core 21 is repeated sequentially.

  In FIG. 5, when the pixel “007” of the first image data is processed, the value of the instruction data is “0”. Here, since the value “0” of the instruction data means that lossless compression is performed, the pixel “007” of the image data is replaced with “0x00” and output to the image data lossy compression core 21.

  As described above, when the replacement process is repeated for a total of 64 pixels corresponding to 8 pixels in the main scanning direction and 8 lines in the sub-scanning direction, that is, 64 times, the data after the replacement process as shown on the right side of FIG. Forwarded to

  In this embodiment, the replacement process is simply replaced with “0x00” in order to simplify the process. However, various methods are conceivable for improving the image quality.

  Next, a case where the result after the replacement process is output to the image data lossless compression core 22 will be described with reference to FIG. FIG. 6 shows an embodiment of the present invention, and is a diagram showing replacement processing executed by the data replacement units 28a and 28b.

  The processing procedure of the replacement process here is the same as that in FIG. That is, a rectangular area of 8 pixels in the main scanning direction and 8 pixels in the sub scanning direction is processed line by line. Specifically, processing is performed in ascending order of pixel numbers of the first image data.

  However, the result after the replacement processing is different from the case where the result is output to the image data lossy compression core 21 in the following points. That is, the replacement process for the value of the instruction data is reversed. More specifically, the value “1” of the instruction data means that irreversible compression processing is performed. Therefore, the pixel of the first image data corresponding to the value of the instruction data “1” is replaced with “0x00” and output to the image data lossless compression core 22. On the other hand, since the pixel of the first image data corresponding to the value of the instruction data “0” means that lossless compression is performed, it is output to the lossless compression core as it is.

  By the way, each of the SRAM read controllers 27a to 27c accesses the SRAM 25a storing the same instruction data and the SRAM 25b storing the first image data. Therefore, the arbiter 26 arbitrates access control for the SRAMs 25a and 25b.

  Hereinafter, the arbitration process by the arbiter 26 will be described with reference to FIG. FIG. 7 shows an embodiment of the present invention and is a diagram showing a time chart of arbitration processing by the arbiter 26.

  As described above, when the SRAM read controllers 27a to 27c according to the present embodiment receive the data acquisition completion notification from the respective DMA units 24a and 24b, the SRAM read controllers 27a to 27c request the SRAM 25 for data by request signals (“req1”, “Req2” and “req3”) are all made high active. The arbiter 26 selects one of the SRAM read controllers 27a to 27c issuing the request and activates the address valid signal (“avalid1”, “avalid2”, or “avalid3”).

  In the embodiment illustrated in FIG. 7, it is assumed that the image data lossless compression core 22 is selected as the output destination of the image data after the replacement processing, and “avalid 1” is active. As described above, the SRAM read controller 27a having “avalid 1” becomes active (High) and obtains the right to access the SRAM 25 corresponds to the address (“address”) output at the next clock (“clock”). Data (“data”) can be acquired.

  On the other hand, the SRAM I / F that provides an interface between the SRAM read controllers 27 a to 27 c and the SRAMs 25 a and 25 b receives the SRAM read control selection signal from the arbiter 26. In response to the SRAM read control selection signal, a request signal input from each of the SRAM read controllers 27a to 27c is output as an SRAM chip select signal (“CS”). The SRAM I / F outputs an address signal from each SRAM read controller to the SRAM 25 in response to the SRAM read control selection signal.

  As described above, in the present embodiment, time-sharing access to the same SRAM 25 from a plurality of modules (SRAM read controllers 27a to 27c) can be realized by the arbitration process by the arbiter 26. However, such a time-sharing control can be omitted if the SRAM has a configuration having three read ports.

  When the image data and the instruction data are transferred to the compression core module, compression processing (lossless compression processing or lossy compression) is performed in the compression core module (S17).

  The compressed image data and instruction data are stored in the SRAM 25 (SRAMs 25d to 25g) by the SRAM write controllers 29a to 29c (S18).

  In the image processing apparatus 1 according to the present embodiment, when the compression processing is completed, each of the three compression core modules sends a completion notification indicating the completion to the compression module DMA 24 (DMA units 24d to 24g). It is configured as follows. More specifically, the instruction data lossless compression core 23 notifies the DMA unit 24d of completion every time the instruction data lossless compression processing is completed. The image data lossless compression core 22 notifies the DMA unit 24e of completion every time the image data lossless compression processing is completed. Further, the image data lossy compression core 21 notifies the DMA unit 24f of completion every time the lossy compression of image data is completed.

  In step S12, the compression module DMA24 (DMA units 24d to 24g) sets the compressed data (first compressed data to third compressed data) stored in the SRAM 25 (SRAMs 25d to 25f) in order from the one that received the completion notification. The data is written to the DRAM 3 based on the destination operation setting (S19).

  Until the compression process is completed for all the instruction data and the first image data stored in the DRAM 3 (until “YES” is determined in step S20), the processes from step S14 to step S19 are repeated.

  If “YES” is determined in step S20, the compression module DMA24 (DMA units 24d to 24f) notifies the CPU 12 of the end of the compression process.

  As described above, the image processing apparatus 1 according to the present embodiment executes the “compression processing of the first image data set”.

  By the way, the access to the SRAM 25 of the SRAM read controllers 27a to 27c is time-division controlled by the arbiter 26. In practice, processing proceeds in parallel.

  Moreover, since the compression method differs between the lossless compression and the lossy compression, the time required for the compression processing differs. For this reason, the process executed by the image data lossy compression core 21 and the process executed by the image data lossless compression core 22 and the instruction data lossless compression core 23 have different end timings.

  For example, assuming that the processing capacity of each of the image data lossless compression core 22 and the instruction data lossless compression core 23 is 75 MB / s and the processing capacity of the image data lossy compression core 21 is 200 MB / s, the relationship between the time required for compression processing is as follows: It is expressed as in FIG. In FIG. 8, one filled block indicates the compression processing time for the image data and the instruction data for the SRAM size. In the example shown in FIG. 8, the image data lossy compression core 21 has completed the compression process in less than half the time of the image data lossless compression core 22 or the instruction data lossless compression core 23. FIG. 8 illustrates an embodiment of the present invention, in which the first image data set is compressed by the instruction data lossless compression core 23, the image data lossless compression core 22, and the image data lossy compression core 21, respectively. It is a figure which shows the comparison of the processing time in.

  As described above, the access timing for the SRAM 25 of each of the SRAM read controllers 27a to 27c is adjusted by the arbiter 26. However, the time lag of the access timing to the SRAM 25 of each of the SRAM read controllers 27a to 27c is very small. Therefore, the compression processing executed by the image data lossy compression core 21, the image data lossless compression core 22, and the instruction data lossless compression core 23 can be regarded as being executed in parallel at substantially the same timing. . For this reason, in FIG. 8, the start of compression processing for instruction data and image data corresponding to the SRAM size is shown to be almost simultaneous.

  As can be seen from FIG. 8, when the processing speed of the compression processing is different, the next SRAM has the higher processing speed of the compression processing without waiting for the processing of the lower processing speed of the compression processing to be completed. It is impossible to execute compression processing for instruction data and image data corresponding to the size. That is, there is a waiting time until the image data lossy compression core 21 starts the next compression process.

  By the way, as described above, the image processing apparatus 1 according to the present embodiment has data (first image data) including first image data and instruction data thereof as two types of image data to be subjected to compression processing in parallel. In addition to the set), the second image data is stored in the DRAM 3.

  Therefore, the image processing apparatus 1 according to the present embodiment is configured to perform compression processing of the second image data by using the above-described waiting time generated in the image data lossy compression core 21. Yes.

  In the following, the processing flow of the compression processing of the second image data will be described first with reference to FIG. The compression processing of the first image data and the second image data executed in the image data lossy compression core 21 will be described.

(Second image data compression process)
Referring to FIG. 9, the compression process of the second image data is as follows. FIG. 9 shows an embodiment of the present invention and is a flowchart showing a processing flow of compression processing in the compression module 13.

  First, as a premise, it is assumed that only the irreversible compression is performed on the second image data.

  As shown in FIG. 9, the CPU 12 performs source operation setting of the DMA unit (DMA unit 24c) (S31). In step S31, specifically, the CPU 12 instructs an address indicating a storage position of data read by the DMA unit 24c. For example, the CPU 12 sets the storage address of the second image data as the address 0x2000_0000 for the DMA unit 24c.

  Next, the CPU 12 performs destination operation setting of the DMA unit 24g (S32). More specifically, the CPU 12 sets the DMA unit 24g to store the image data after the lossy compression (fourth compressed data) at the start address 0x6000_0000.

  When the source operation setting and the destination operation setting are completed as described above, the CPU 12 activates the compression module DMA24 (S33). When the activation instruction is given to the compression module DMA 24 by the CPU 12, the DMA unit (the DMA unit 24 c in this embodiment) requests data from the DRAM 3.

  First, the DMA unit 24c reads the second image data from the DRAM 3 by the data size of the SRAM. Then, the read data is stored in the SRAM 25 (S34).

  Specifically, the data read from the DRAM 3 is read to the SRAM 25 in the same manner as in FIG.

  When the acquisition of the second image data from the DRAM 3 is completed, that is, when the reading of the second image data for the SRAM data size is completed, the compression module DMA24 notifies the SRAM read controller 27c of the completion of data acquisition.

  Upon receiving this notification, the SRAM read controller 27c starts the second image data reading process. Then, the SRAM read controller 27 c omits the replacement process by the data replacement units 28 a and 28 b in accordance with an instruction from the CPU 12, and compresses the read second image data according to the arbitration result of the arbiter 26 (image data non-data). Transfer to the lossless compression core 21) (S35).

  When the second image data is transferred to the compression core module (image data lossy compression core 21), compression processing (irreversible compression) is performed in the compression core module (S36).

  The compressed second image data is stored in the SRAM 25g by the SRAM write controller 29c (S37).

  Further, the image data lossy compression core 21 notifies the DMA unit 24f of completion every time the lossy compression of image data is completed.

  When receiving the completion notification, the compression module DMA24 (DMA unit 24g) writes the compressed data (fourth compressed data) stored in the SRAM 25g to the DRAM 3 based on the destination operation setting set in step S12 ( S38).

  Until the compression process is completed for all the second image data stored in the DRAM 3 (until “YES” is determined in step S39), the processes from step S34 to step S38 are repeated.

  If “YES” is determined in the step S39, the compression module DMA24 (DMA unit 24g) notifies the CPU 12 of the end of the compression process.

  As described above, in the image processing apparatus 1 according to the present embodiment, the “compression processing of the second image data set” is executed.

  As described above, the “second image data compression process” does not include the step of reading the instruction data from the DRAM 3 (S15) as compared to the “first image data set compression process” shown in FIG. Except for this point, the same processing is performed.

  In the present embodiment, for convenience of explanation, the “compression processing of the first image data set” and the “compression processing of the second image data set” have been described separately. However, in the image processing apparatus 1, both processes are performed in parallel. Is going. In particular, as described above, the image processing apparatus 1 according to the present embodiment uses the waiting time after the compression processing of the first image data that occurs in the image data lossy compression core 21 to generate the second image data. The compression process is performed. For this reason, the use of the image data lossy compression core 21 requires hardware ingenuity.

  Hereinafter, parallel processing in the image data irreversible compression core 21 of the first image data set and the second image data will be described.

(Parallel processing in image data lossy compression core)
In the image processing apparatus 1 according to the present embodiment, as a premise, it is assumed that the compression processing for the first image data set is prioritized over the second image data.

  First, the SRAM read controller 27c is configured to receive data read completion notifications from the DMA units 24a and 24b that perform data transfer of the first image data set and the DMA unit 24c that performs data transfer of the second image data, respectively. Has been.

  Here, since it is necessary to preferentially compress the first image data set, when the data read completion notification is received from each of the DMA units 24a to 24c, the SRAM read controller 27c performs the first image data set. Give priority to data transfer.

  When the data read completion notification is received from only the DMA unit 24c, it is determined that the first image data set is not completely stored in the SRAM 25. Therefore, in this case, the SRAM read controller 27c Data transfer of the second image data having a low priority is performed.

  Further, immediately after the transfer of the instruction data and the first image data stored in the SRAMs 25a and 25b to the compression core module is completed, the second image data to be processed exists in the SRAM 25c, and from the DMA unit 24c. When the read completion notification is received, the SRAM read controller 27c transfers the second image data.

  Except when these two conditions are satisfied, the SRAM read controller 27c preferentially transfers the first image data set even when the reading completion notification is received from the DMA unit 24c.

  As described above, since the first image data set is preferentially transferred except when the above two conditions are satisfied, the image processing apparatus 1 according to the present embodiment has a desired performance. Can be protected.

  That is, the SRAM read controller 27c can transmit the first image data set or the second image data to the image data lossy compression core 21 according to a preset priority.

  For this reason, when there is a time constraint on the process for the first image data set, the process for the first image data set can be prioritized. Note that the time-constrained process is, for example, a copy job in which the first image data set must comply with the catalog specifications presented in the image processing apparatus 1.

  In the above description, the first image data set is prioritized over the second image data for the compression process. However, when compression processing is performed with priority given to the second image data over the first image data set, the same processing can be performed only by switching the priority. That is, when the second image data is set to be preferentially processed, the SRAM read controller 27c interprets the read completion notification from the DMA units 24a and 24b and the DMA unit 24c by reversing the priority relationship. Become.

  The image data lossy compression core 21 receives different types of image data of the first image data set and the second image data. For this reason, when supplying image data to the image data lossy compression core 21, the SRAM read controller 27 c needs to indicate which image data is being transferred. As shown in FIG. 10, the SRAM read controller 27 c includes the image number signal (transmission data instruction signal) in the signal output to the image data lossy compression core 21, which image data is being transferred. Can indicate.

  More specifically, when image data is transferred to the image data irreversible compression core 21, the image data irreversible compression core 21 receives a signal shown in FIG. 10 including an image number signal. FIG. 10 is a diagram showing signal waveforms when the image data lossy compression core 21 receives image data.

  As shown in FIG. 10, when the image valid signal is “High”, the image data is supplied to the image data lossy compression core 21 as valid image data. At this time, by simultaneously displaying the image number signal to the image data lossy compression core 21, it is possible to distinguish whether the supplied image data is the first image data or the second image data. In the example shown in FIG. 10, when the image number signal is “High”, the first image data is supplied. When the image number signal is “Low”, the second image data is supplied. The core 21 recognizes.

  Further, since the image data lossy compression core 21 receives two types of image data indicated by the image number signal at random as shown in FIG. 11, the compression processing corresponding to each image data is time-divisionally performed. Must be realized. The image data lossy compression core 21 needs to have two register setting sets in order to compress two types of image data in a time division manner. FIG. 11 illustrates an embodiment of the present invention, and is a diagram illustrating an example of a processing state when two types of image data are compressed in a time division manner.

  Therefore, as shown in FIG. 12, the image data lossy compression core 21 according to the present embodiment has a compression core 31 and a register having two types of register sets (a first register set 33a and a second register set 33b). 32. FIG. 12 shows an embodiment of the present invention, and is a block diagram showing a main configuration of the image data lossy compression core 21.

  In the first register set (first data processing information) 33a and the second register set (second data processing information) 33b, register settings for executing compression processing corresponding to the first image data and the second image data are provided. A set is recorded. For example, when the lossy compression method is JPEG, examples of the register setting set include pixel sampling setting, quantization table setting, and Huffman table setting.

  The first register set 33a and the second register set 33b in the register 32 are set by the CPU 12 via the register I / F 34.

  The compression core 31 is a core part of the image data irreversible compression core 21 and performs arithmetic processing for irreversibly compressing the image data. The compression core 31 selects either the first register set 33a or the second register set 33b in the register 32 according to the image number signal. Then, the register setting of the selected first register set 33a or second register set 33b is received from the register 32, and irreversible compression processing of the first image data or the second image data is executed.

  The compression core 31 passes the compressed data (third compressed data or fourth compressed data) after the irreversible compression processing to the SRAM write controller 29c and stores it in the SRAM 25f or the SRAM 25g.

  Also in the transfer of the compressed data, the image data lossy compression core 21 determines whether the compressed data is the compressed data of the first image data (third compressed data) or the compressed second image data with respect to the SRAM write controller 29c. It is necessary to indicate whether it is data (fourth compressed data). Therefore, when outputting the compressed data, the compression core 31 outputs a signal including the image number signal to the SRAM write controller 29c, which is the same as when receiving the first image data or the second image data from the SRAM read controller 27c. .

  The SRAM write controller 29c determines whether the compressed data to be transferred is the third compressed data or the fourth compressed data according to the image number signal. When the SRAM write controller 29c determines that the compressed data to be compressed is the third compressed data, the SRAM write controller 29c stores it in the SRAM 25f.

  The third compressed data stored in the SRAM 25f is stored at a predetermined position in the DRAM 3 by the DMA unit 24f. The fourth compressed data stored in the SRAM 25g is stored at a predetermined position in the DRAM 3 by the DMA unit 24g.

  With the above configuration, compression processing for two types of image data can be performed in parallel in the image data lossy compression core 21. As a result, the image data irreversible compression core 21 can perform the compression process of the second image data during the waiting time shown in FIG. 8, so that the efficiency of the compression process for the image data can be improved.

  In the above description, the compression process for compressing image data has been described as an example. However, the present invention is not limited to this, and can be similarly realized by a decompression process for compressed image data. That is, in the decompression processing of the compressed image data, there is a difference in processing capability between the case of decompressing the lossless compressed image data and the case of decompressing the lossy compressed image data. For this reason, even in the case of decompression processing of compressed image data, processing efficiency is improved by performing different types of image data decompression processing during the decompression processing waiting time, as in the above-described compression processing. be able to.

  Further, the case where there is a difference in processing capability between the image data lossless compression core 22 and the image data lossy compression core 21 has been described above. However, for example, even when the same lossless compression or lossy compression is used, if there is a difference in the processing capability of the compression module, similarly, compression processing of different types of image data in the waiting time that occurs in the higher processing capability It is possible to improve the processing efficiency.

  As described above, in the image processing apparatus 1 according to the present embodiment, the image data lossless compression core 22 that compresses image data and the image data lossless compression core 22 have different image data compression methods and compression processing. The image data lossy compression core 21 is provided with a small time. Furthermore, the image processing apparatus 1 includes a first region portion that compresses the first image data set by the image data lossless compression core 22 according to the characteristics of the regions that constitute the first image data, and image data lossy compression. A CPU 12 is also provided that is separated into a second region portion to be compressed by the core 21. The image processing apparatus 1 is configured to compress the second area portion and the second image data different from the first image data while the first area portion is compressed by the image data lossless compression core 22. Has been.

  For this reason, the image processing apparatus 1 according to the present embodiment can efficiently perform compression processing on the first image data set and the second image data stored in the DRAM 3.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately modified within the scope of the claims are also included in the technical scope of the present invention.

  The image processing apparatus 1 according to the present embodiment performs compression processing on a plurality of types of image data with another compression core module having a high processing speed while performing compression processing with the compression core module having a low processing speed. Can do. Therefore, the present invention can be widely applied to apparatuses including two or more compression core modules having different processing performance (processing speed).

1 Image processing device 3 DRAM (storage unit)
12 CPU (separator)
13 Compression module 17 Instruction data generation unit 21 Image data lossy compression core (second data processing unit)
22 Image data lossless compression core (first data processing unit)
23 Instruction data lossless compression core 24 Compression module DMA (transfer unit)
24a to 24c DMA unit (transfer unit)
25 SRAM (transfer unit)
25a-25c SRAM (transfer unit)
26 Arbiter (transfer section)
27a to 27c SRAM read controller (transfer unit)
32 register 33a first register set (first data processing information)
33b Second register set (second data processing information)

Claims (5)

The first data processing unit that performs image data processing including at least one of compression of image data and decompression of compressed image data differs from the first data processing unit in the processing method of image data processing. And an image processing apparatus having a second data processing unit having a processing time required for the image data processing smaller than that of the first data processing unit,
As image data for performing the image data processing, a storage unit for storing first image data including regions having different characteristics and second image data different from the first image data;
The first image data stored in the storage unit is divided into a first region portion that is a region where image data processing is performed by the first data processing unit according to the characteristics of the region constituting the first image data, and A separation unit that separates the second data processing unit into a second region that is a region where image data processing is performed by the second data processing unit
While the first data processing unit is performing image data processing of the first region portion, the second data processing unit reads the second region portion and the second image data from the storage unit, and An image processing apparatus that performs data processing. Priorities for performing the image data processing are set in the first area portion and the second image data,
A transfer unit that reads each of the second region portion and the second image data from the storage unit and transfers the read data to the second data processing unit;
The image processing apparatus according to claim 1, wherein the transfer unit transfers the second region portion or the second image data to the second data processing unit according to the priority. When transferring the image data of either the second region portion or the second image data to the second data processing unit, the transfer unit transfers either the second region portion or the second image data. A transmission data instruction signal indicating whether or not
The second data processing unit determines whether the transferred data is the second area portion or the second image data based on the transmission data instruction signal, and performs image data processing according to the transferred data The image processing apparatus according to claim 2, wherein: The second data processing unit is first data processing information that is information for executing image data processing of the second region portion, and information that is information for executing image data processing of the second image data. 2 data processing information,
4. The image data processing corresponding to the transferred data is executed by selecting either the first data processing information or the second data processing information based on the transmission data instruction signal. An image processing apparatus according to 1. The first data processing unit that performs image data processing including at least one of compression of image data and decompression of compressed image data differs from the first data processing unit in the processing method of image data processing. And a control method for an image processing apparatus having a second data processing unit having a processing time required for the image data processing smaller than that of the first data processing unit,
The image processing apparatus further includes a storage unit that stores first image data including regions having different characteristics and second image data different from the first image data as image data to be subjected to the image data processing. And
The first image data stored in the storage unit is divided into a first region portion that is a region where image data processing is performed by the first data processing unit according to the characteristics of the region constituting the first image data, and A separation step of separating into a second region portion that is a region where image data processing is performed by the second data processing unit;
While the first data processing unit is performing image data processing of the first region portion, the second data processing unit reads the second region portion and the second image data from the storage unit, and A control method for an image processing apparatus, comprising: an image data processing step for performing data processing.

Images