JP2011239226A - Synchronous circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a synchronous circuit capable of achieving broadband characteristics and low phase noise characteristics with a small area.SOLUTION: A phase detector 11 detects a phase difference between a reference signal and a feedback signal. Voltage generators 12 and 13 generate voltages based on an output signal of the phase detector 11. A pulse generator 16 generates a pulse signal based on the reference signal. A voltage control oscillator 14 generates an oscillation signal in synchronization with the pulse signal. A frequency divider 15 divides the signal from the voltage control oscillator and generates the feedback signal. The voltage control oscillator 14 comprises: a level shift circuit 14c to shift a voltage level supplied by a voltage generation circuit and a ring oscillator consisting of a plurality of inverter circuits 14a and 14b driven by the voltage supplied by the voltage generation circuit as well as the voltage with the voltage level shifted by the level shift circuit. The pulse signal is supplied to one of the inverter circuits.

Description

  The present invention relates to a synchronous circuit using an injection locked ring voltage controlled oscillator (VCO) applied to, for example, a semiconductor integrated circuit.

  In order to prevent an increase in cost of a wireless communication circuit due to miniaturization of a semiconductor integrated circuit, it is expected to realize a scalable analog circuit capable of reducing a circuit area. For example, as a VCO used for a phase locked loop (PLL) applied to a wireless communication circuit, a circuit using the resonance characteristics of an inductor (L) and a capacitor (C) is often used. By setting the Q value of the LC circuit high, performance with high frequency accuracy and low phase noise characteristics can be realized. For this reason, in recent years, a VCO using an LC resonance circuit on an integrated circuit is often used.

  However, with the miniaturization of the semiconductor integrated circuit, the transistor circuit portion is reduced in area, whereas the LC resonant circuit portion cannot be reduced because the circuit constant is determined. Therefore, the chip cost is limited. In addition, when a process of less than 0.1 μm is applied to the LC resonance type circuit, it has become difficult to satisfy the phase noise specification of the system.

  For this reason, a ring oscillation circuit has attracted attention as a circuit technique that replaces an oscillation circuit using an LC resonance circuit. However, the current ring oscillator circuit has essentially a large phase noise. For this reason, research and development of a high-performance PLL circuit using a ring oscillation circuit has been vigorously advanced. For example, research results such as Non-Patent Documents 1 and 2 have been reported.

Non-Patent Document 1 proposes a configuration method of a PLL synthesizer circuit having a ring oscillation circuit as an element circuit in order to improve the phase noise characteristics of the ring oscillation circuit. The technique disclosed in this document 1 uses a phase noise preamplification technique to suppress phase noise by feeding back noise in the loop band. In the technique of this document 1, the phase noise at a frequency detuned by 0.6 MHz from the oscillation frequency is -124 dBc / Hz, and a phase noise characteristic similar to a VCO using an LC resonance circuit is achieved in a small area of 0.07 mm ^2. is doing.

Similarly to Reference 1, Non-Patent Document 2 also optimizes the loop band of the PLL synthesizer and improves phase noise characteristics. In the technique of Reference 2, the phase noise at a frequency detuned by 10 kHz from the oscillation frequency in the frequency range of 110 MHz to 180 MHz is −90 dBc / Hz, and this is achieved with a small area of 0.64 mm ² .

Cao, et al. “A 04 ps-RMS-Jitter 1-3GHz Ring-Oscillator PLL Using Phase Noise Preamplification”, IEEE Journal of Solid-State Circuits, vol. 43, No. 9, pp.2079-2089, Sep. , 2008. T. Morie, et al. “A -90dBc @ 10kHz Phase Noise Fractional-N Frequency synthesizer with Accurate Loop Bandwidth Control Circuit”, IEEE Symposium on VLSI Circuits Digest of Technical Papers, pp.52-55, 2005.

  However, Documents 1 and 2 described above provide feedback and suppression of noise within the loop band, or optimize the loop band of the PLL synthesizer to improve the phase noise characteristics.

  On the other hand, in order to reduce the phase noise by the configuration of the entire PLL circuit including the oscillation circuit, it is necessary to set a wide loop band. However, when the loop band is set wide, it becomes difficult to apply feedback, and stable phase synchronization operation becomes difficult. For this reason, it has been difficult to stably realize a wide loop band and improve the phase noise characteristics by a trade-off with the stability of the phase synchronization operation.

  An object of the present invention is to provide a synchronous circuit capable of obtaining a broadband characteristic and a low phase noise characteristic with a small area.

  According to the first aspect of the present invention, the first aspect of the synchronization circuit includes a phase detector that detects a phase difference between a reference signal and a feedback signal, a voltage generator that generates a voltage based on an output signal of the phase detector, and the reference A pulse generator that generates a pulse signal based on a signal; a voltage-controlled oscillator that oscillates an oscillation signal based on a voltage supplied from the voltage generator in synchronization with the pulse signal supplied from the pulse generator; A frequency divider that divides the oscillation signal supplied from the voltage controlled oscillator and generates the feedback signal, and the voltage controlled oscillator shifts the level of the voltage supplied from the voltage generation circuit. A plurality of inverter circuits having a level shift circuit, and a load circuit driven by a voltage supplied from the voltage generation circuit and a level shifted voltage supplied from the level shift circuit And Ranaru ring oscillator is constituted by, in one of the plurality of inverter circuits, the pulse signal supplied from the pulse generator is characterized in that it is supplied.

  According to the second aspect of the present invention, the second aspect of the synchronous circuit includes a first delay detector that delay-detects a reference signal, a second delay detector that delay-detects a signal, and an output signal of the first delay detector. Supplied from the first voltage generating circuit, the second voltage generating circuit generating the voltage from the output signal of the second delay detector, and the first and second voltage generating circuits. A differential amplifier that outputs a voltage difference voltage; a pulse generator that generates a pulse signal based on the reference signal; and a pulse generator that is supplied from the differential amplifier in synchronization with the pulse signal supplied from the pulse generator A voltage-controlled oscillator that oscillates an oscillation signal based on a voltage; and a frequency divider that divides the oscillation signal supplied from the voltage-controlled oscillator and generates the feedback signal. Voltage supplied from the differential amplifier A level shift circuit for shifting the level, a ring oscillator including a plurality of inverter circuits driven by a voltage supplied from the differential amplifier and a level shifted voltage supplied from the level shift circuit The pulse signal supplied from the pulse generator is supplied to one of the plurality of inverter circuits.

  The present invention can provide a synchronous circuit capable of obtaining a broadband characteristic and a low phase noise characteristic with a small area.

1 is a configuration diagram showing a phase synchronization circuit according to a first embodiment of the present invention. The block diagram which shows an example of the ring VCO shown in FIG. FIG. 3 is a circuit diagram showing an example of a differential inverter circuit constituting the ring VCO shown in FIG. 2. FIG. 4 is a circuit diagram illustrating an example of an inverter circuit illustrated in FIG. 3. 5A is a diagram showing the operation of the level shifter shown in FIG. 2, and FIG. 5B is a diagram showing the resistance value of the P-channel MOS transistor shown in FIG. FIG. 3 is a circuit diagram illustrating an example of a level shifter illustrated in FIG. 2. 7A is a photomicrograph showing a semiconductor integrated circuit including a synchronous circuit according to the first embodiment, FIG. 7B is a diagram showing oscillation characteristics of the ring VCO, and FIG. FIG. 7D is a diagram showing the spurious level and phase noise characteristics of the VCO, and FIG. 7D is a diagram showing the phase noise characteristics of the ring VCO according to the first embodiment in comparison with other phase noise characteristics. The figure which shows the frequency and phase locked loop circuit concerning the 2nd Embodiment of this invention. The circuit diagram which shows the modification of a ring VCO.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows a phase locked loop (PLL circuit) according to a first embodiment of the present invention. In the first embodiment, a phase-locked operation and an injection-locked operation using an injection-locked ring VCO are simultaneously performed, so that a low-phase noise synchronization signal can be generated.

  In FIG. 1, a reference signal ref is supplied to one input terminal of a phase detector (phase comparator) 11, and a feedback signal output from the frequency divider 15 is supplied to the other input terminal. The reference signal is, for example, a rectangular wave with a duty ratio of 50%. However, it is not limited to a rectangular wave, and may be a sine wave. The phase detector 11 detects the phase difference between the reference signal ref and the feedback signal. The output signal of the phase detector 11 is supplied to a charge pump circuit (CP) 12.

  The charge pump circuit 12 includes, for example, a P-channel MOS transistor (hereinafter referred to as a PMOS transistor) P1 and an N-channel MOS transistor (hereinafter referred to as an NMOS transistor) N1 connected in series between a node to which a power supply VDD is supplied and the ground. It is comprised by. The charge pump circuit 12 generates a pulse signal according to the output signal of the phase detector 11, and outputs this pulse signal from the connection node between the PMOS transistor P1 and the NMOS transistor N1. A low-pass filter (LPF) 13 is connected to this connection node.

  The LPF 13 includes, for example, a resistor R1 and a capacitor C1 connected in series between the connection node and the ground, and a capacitor C2 connected between the connection node and the ground. The LPF 13 integrates the pulse signal supplied from the charge pump circuit 12 and generates a DC control voltage bias. This control voltage bias is supplied to the ring VCO 14. This ring VCO 14 is an injection locking type ring VCO, and has an injection locking terminal into which a pulse signal is injected.

  On the other hand, the reference signal ref is supplied to the pulse generator 16. The pulse generator 16 generates, from the reference signal ref, a pulse signal having the same frequency as the reference signal ref and a duty ratio of, for example, 10 to 20%. The pulse signal output from the pulse generator 16 that rises and falls quickly is supplied to the injection locking terminal of the ring VCO 14 via the delay circuit 17.

  The delay circuit 17 adjusts the injection timing of the pulse signal to the ring VCO 14. That is, the delay circuit 17 delays the pulse signal inj output from the pulse generator 16 by a time (ΔT) from when the reference signal ref is supplied to the phase detector 11 to when bias is supplied to the ring VCO 14. . In this configuration, the synchronization operation by the PLL and the synchronization operation by the signal injection to the VCO are made to compete. In order to improve the phase noise characteristics with only the PLL, it is necessary to increase the loop band (gain) of the PLL, but the operation becomes unstable and difficult to realize. Therefore, in this configuration, a low phase noise characteristic can be realized by narrowing the PLL loop band, causing the PLL to perform rough phase synchronization, and injecting the reference signal directly into the VCO. The delay circuit 17 is for effectively performing injection locking by matching the phase of the injection signal with the phase of the VCO in the rough phase locking state of the PLL. This avoids competition between the PLL operation and the pulse signal injection locking operation, and enables a stable low phase noise operation.

  The ring VCO 14 oscillates in synchronization with the pulse signal inj supplied from the delay circuit 17, and the oscillation frequency is controlled by the control voltage bias supplied from the LPF 13. The oscillation signal output from the ring VCO 14 is output via the buffer amplifier 18 and supplied to the frequency divider 15. The frequency divider 15 divides the oscillation signal by 1 / N to generate a feedback signal. This feedback signal is supplied to the other input terminal of the phase detector 11.

  FIG. 2 shows an example of the ring VCO 14. As described above, the ring VCO 14 is an injection-locked ring VCO, and in order to enable I / Q output and to reduce phase noise in the power supply voltage range, two differential inverter circuits 14a, 14b is used. Further, a bias level shifter 14c for controlling the load resistance of the inverter circuits constituting the differential inverter circuits 14a and 14b is provided in order to realize the ring VCO 14 having a broadband characteristic in the power supply voltage range.

  The differential inverter circuits 14a and 14b are connected in series, and the output terminals out3 and out4 of the differential inverter circuit 14b are connected to the inverting input terminal and the non-inverting input terminal of the differential inverter circuit 14a, respectively, so that positive feedback is applied. Has been.

  The differential inverter circuit 14a has an injection locking terminal 14a-1, and the pulse signal inj output from the delay circuit 17 is supplied to the injection locking terminal 14a-1. The differential inverter circuit 14a oscillates in synchronization with the injection of the pulse signal inj.

  The bias level shifter 14c is a circuit for controlling the oscillation frequency of the VCO. The bias level shifter 14c passes through the control voltage bias supplied from the LPF 13 and generates a control voltage biasn level-shifted from the control voltage bias. These biases, biasn Are supplied to the differential inverter circuits 14a and 14b, respectively. The ring VCO 14 has an oscillation frequency variable based on the control voltages bias and biasn.

  FIG. 3 shows an example of the differential inverter circuit 14a as a delay cell of the ring VCO shown in FIG. The differential inverter circuit 14a includes, for example, four inverter circuits I1, I2, I3, and I4 and an NMOS transistor N11. A signal out4 is supplied to the input terminal of the inverter circuit I1, and a signal out3 is supplied to the input terminal of the inverter circuit I2.

  A latch circuit LT composed of inverter circuits I3 and I4 is connected between the output terminals of the inverter circuits I1 and I2.

  Further, the current path of the NMOS transistor N11 is connected between the output terminals of the inverter circuits I1 and I2. The gate of the NMOS transistor N11 is connected to the injection locking terminal 14a-1, and the pulse signal inj is supplied to the injection locking terminal 14a-1. The NMOS transistor N11 is turned on when the pulse signal inj is injected, and the output terminals of the inverter circuits I1 and I2 are short-circuited for a moment. For this reason, the differential inverter circuit 14a as a delay cell is reset in synchronization with the pulse signal inj and starts an oscillation operation.

  For example, the differential inverter circuit 14b employs a similar configuration in which the NMOS transistor N11 is omitted from the differential inverter circuit 14a.

  FIG. 4 shows an example of the inverter circuit I3 constituting the differential inverter circuits 14a and 14b. The inverter circuit I4 has the same configuration as the inverter circuit I3. The inverter circuits I1 and I2 are, for example, normal CMOS inverter circuits.

  The inverter circuit I3 includes a PMOS transistor P21 and an NMOS transistor N21 that form a CMOS inverter, and PMOS transistors P22 and P23 that form a load circuit. The PMOS transistors P22 and P23 are connected in parallel between the node to which the power supply voltage VDD is supplied and the current path of the PMOS transistor P21. Control voltages bias and biasn output from the bias level shifter 14c are supplied to the gates of the PMOS transistors P22 and P23, respectively.

  FIG. 5A shows the relationship between the control voltages bias and biasn. The voltage bais is a voltage that monotonously increases from 0 V, like the power supply voltage. On the other hand, the voltage baisn is a voltage that increases from the time when the voltage bais exceeds the threshold voltage Vthp of the PMOS transistor, for example.

  FIG. 5B shows the relationship between the control voltages bias and biasn and the resistance values (resistance) between the sources and drains of the PMOS transistors P22 and P23. The resistance value of the PMOS transistor P22 increases as the control voltage bias is increased. When bias becomes larger than the threshold voltage Vthp of the PMOS transistor, the PMOS transistor P22 is turned off and the resistance value becomes constant. For this reason, when the PMOS transistor is controlled only by the control voltage bias, even if bias becomes larger than the threshold voltage Vthp of the PMOS transistor, an increase in the oscillation frequency of the ring VCO 14 cannot be expected.

  However, the resistance value between the source and the drain of the PMOS transistor P23 does not change when the control voltage bias is equal to or lower than the threshold voltage Vthp of the PMOS transistor, and increases with the control voltage biasn when the bias becomes larger than the threshold voltage Vthp of the PMOS transistor. Begin to. That is, the oscillation frequency of the ring VCO 14 increases according to the control voltage biasn when the control voltage bias exceeds the threshold voltage Vthp. That is, the total resistance value total of the PMOS transistors P22 and P23 increases according to the resistance value of the PMOS transistor P22 when the control voltage bias is from 0 V to the threshold voltage Vthp of the PMOS transistor, and the control voltage bias is the threshold voltage Vthp of the PMOS transistor. Exceeds the value, it increases according to the resistance value of the PMOS transistor P23. For this reason, the value of the load resistance of the CMOS inverter increases almost monotonically when the control voltage bais is between 0V and a power supply voltage, for example, 1.8V. Therefore, the ring VCO 14 can change the oscillation frequency in a wide band with respect to a change in the power supply voltage 1.8 V from 0 V of the DC control voltage bias supplied from the LPF 13.

  Further, the oscillation signal can be controlled with full amplitude from the ground potential to the power supply voltage (Rail to Rail control) using the inverter circuit. For this reason, it is possible to increase the frequency change of the oscillation signal, and a wider band operation is possible. Further, since the oscillation signal also uses an inverter circuit, a full amplitude output from the ground potential to the power supply voltage is obtained. Since the phase noise becomes smaller as the amplitude becomes larger, it is effective for lowering the phase noise. That is, according to the injection locking type ring VCO according to the first embodiment, the broadband characteristic is good and low phase noise can be realized.

  FIG. 6 shows an example of the bias level shifter 14c. The bias level shifter 14c is a circuit that generates a control voltage biasn that is shifted from the control voltage bias, and includes NMOS transistors N31 to N38, a constant current source I31, and a resistor R31.

  That is, one end of the current path of the NMOS transistor N31 is connected to a node to which the power supply voltage VDD is supplied, and the other end of the current path is grounded via the NMOS transistors N32 and N33. The control voltage bias output from the LPF 13 is supplied to the gate of the NMOS transistor N31.

  The connection node of the NMOS transistors N31 and N32 is connected to the gate of the NMOS transistor N34. One end of the current path of the NMOS transistor N34 is connected to a node to which the power supply voltage VDD is supplied, and the other end of the current path is grounded via NMOS transistors N35 and N36. Biasn is output from the connection node of the NMOS transistors N34 and N35.

  The constant current source I31, the resistor R31, and the NMOS transistors N37 and N38 constitute a bias circuit. The power supply voltage VDD is supplied to the gate of the NMOS transistor N38, and the voltage of the connection node between the resistor R31 and the NMOS transistor N37 is supplied to the gate of the NMOS transistor N37.

  The NMOS transistors N32, N33, and N35, N36 each constitute a cascode-connected constant current source circuit. The power supply voltage VDD is supplied to the gates of the NMOS transistors N33 and N36, and the voltage at the connection node of the resistor R31 and the NMOS transistor N37 is supplied to the gates of the NMOS transistors N32 and N35.

  In the configuration described above, the source voltage of N31 is controlled in the NMOS transistor N31 according to the control voltage bias supplied to the gate, and the NMOS transistor N34 has a potential at the connection node between the NMOS transistors N31 and N32 equal to or higher than the threshold voltage of the PMOS transistor. In this case, the bias potential is set to be generated. For this reason, the voltage characteristic shown to Fig.5 (a) can be acquired.

  The bias level shifter 14c is not limited to the circuit shown in FIG.

  In the above configuration, the reference signal ref shown in FIG. 1 is supplied to the phase detector 11 and compared with the feedback signal supplied from the frequency divider 15. The phase detector 11 detects the phase difference between the reference signal ref and the feedback signal and outputs a detection signal. The charge pump circuit 12 generates a voltage based on the detection signal supplied from the phase detector 11. The LPF 13 smoothes the voltage supplied from the charge pump circuit 12 and outputs a DC control voltage bias. The ring VCO 14 starts oscillating in synchronization with the injection locking pulse signal inj supplied from the delay circuit 17 and outputs a signal having a frequency corresponding to the control voltage bias. That is, when the control voltage bias is equal to or lower than the threshold voltage Vthp of the PMOS transistors P22 and P23 as loads of the inverter circuits I3 and I4 constituting the differential inverter circuits 14a and 14b, the resistance value between the source and drain of the PMOS transistor P22 Changes and oscillates, and when the control voltage bias exceeds the threshold voltage Vthp of the PMOS transistors P22 and P23, the resistance value between the source and drain of the PMOS transistor P23 changes and oscillates. The output signal of the ring VCO 14 is frequency-divided by the frequency divider 15 and supplied to the phase detector 11 as a feedback signal, and oscillation is continued.

  According to the first embodiment, the ring VCO 14 constituting the phase synchronization circuit is constituted by the differential inverter circuits 14a and 14b and the bias level shifter 14c. For this reason, since the phase synchronization circuit does not include an inductor as in the prior art, an increase in the chip area can be prevented.

FIG. 7A shows an example of a chip including the phase synchronization circuit shown in the first embodiment. This chip includes a phase detector 11, a charge pump circuit 12, an LPF 13, a ring VCO 14, and a frequency divider 15 in a range indicated by a broken line A in FIG. Since this chip does not include an inductor, a phase locked loop is realized with a small area of, for example, 0.1 mm ² .

  In addition, since the phase locked loop according to the first embodiment does not include an inductor, the design can be easily changed even when the integrated circuit is further miniaturized. That is, in the case of a circuit including an inductor, when the minimum dimension of the integrated circuit is reduced, it is necessary to redesign the circuit in order to satisfy the specifications for the inductor. However, the phase locked loop according to the first embodiment that does not include an inductor does not require a basic circuit design change even when the minimum size of the integrated circuit is reduced.

  Further, the ring VCO 14 includes differential inverter circuits 14a and 14b and a bias level shifter 14c. Of the inverter circuits I1 to I4 constituting the differential inverter circuits 14a and 14b, the ring VCO 14 includes PMOS transistors of the inverter circuits I3 and I4. The load circuit thus controlled is controlled by a control voltage bais supplied from the bias level shifter 14c and a control voltage biasn having a voltage change range shifted from bais. Therefore, an oscillation operation is possible in a wide change range of bias output from the LPF 14.

  FIG. 7B shows the characteristics of the prototype ring VCO 14 shown in FIG. The prototyped chip is manufactured by a 0.18 μm CMOS process. For this reason, the power supply voltage VDD is, for example, 1.8V. As apparent from FIG. 7B, the control range of the oscillation operation is in the range where the control voltage bias is 0 V to the power supply voltage 1.8 V, and it can be seen that the oscillation operation is possible in the entire range of the power supply voltage.

  The range of the oscillation frequency is, for example, 1.65 GHz to 0.65 GHz, and it can be seen that oscillation in a wide frequency band is possible.

Further, as apparent from FIG. 7B, by controlling the resistance value between the source and drain of the PMOS transistors P22 and P23 of the inverter circuits I3 and I4 by the bias level shifter 14c, the control voltage bias is changed from 0V to 1. In the range where the voltage changes to 8V, the change of the oscillation frequency can be made almost constant. Specifically, the value obtained by differentiating the change in the frequency of the ring VCO 14, that is, the value of K _VCO as the conversion gain (VCO gain) of the ring VCO 14 can be within a relatively narrow range of −380 to −640. .

When configuring the PLL, ideally, the value of K _VCO is preferably constant. According to the circuit shown in the first embodiment, since the value of K _VCO is within a relatively narrow range of −380 to −640, stable oscillation operation is possible in the range of power supply voltage 0 V to 1.8 V. is there.

  FIG. 7C shows the relationship between the harmonic (spurious) signal with respect to the frequency (90 to 50 MHz) of the reference signal ref and the phase noise characteristic. As can be seen from FIG. 7C, the harmonic signal is in the range of −30 dBc to −40 dBc in the range of the reference frequency 91 MHz to 50 MHz (control voltage monitor range 0.25 V to 1.55 V), and phase noise. Is substantially constant at −110 dBc in the reference frequency range of 91 MHz to 50 MHz (control voltage monitor range of 0.25 V to 1.55 V). Specifically, it can be seen that, for example, characteristics of harmonic signal −30 dBc and phase noise −105 dBc are obtained at an oscillation frequency of 1.44 GHz and a reference signal frequency of 90 MHz (N = 16 division).

  Thus, it can be seen that the phase noise and the harmonic signal component are kept constant within the loop band.

  Further, the ring VCO 14 can improve the phase noise by the injection locking operation as compared with the case of only the PLL operation as in the first embodiment.

  That is, FIG. 7D shows a phase noise characteristic (free-running) of a single VCO with respect to a detuning (offset) frequency, a phase noise characteristic (PLL) of a PLL circuit using a ring VCO that does not perform injection locking, and injection locking. 2 shows the phase noise characteristic (PLL + inj) of the PLL circuit using the ring VCO subjected to the above and the phase noise characteristic (ref. (90 MHz)) of the reference signal. As is apparent from FIG. 7D, the phase noise of the PLL circuit using the ring VCO subjected to injection locking according to the first embodiment is −122 dBc/Hz@0.2 MHz at an offset frequency of 0.2 MHz. The phase noise of a PLL circuit using a ring VCO that does not perform injection locking is improved by about −14 dBc with respect to −108 dBc/Hz@0.2 MHz. As shown in FIG. 7D, at an offset frequency of 0.2 MHz or higher, the value of phase noise −122 dBc is a value suitable for an electronic device such as a mobile phone.

(Second Embodiment)
FIG. 8 shows a second embodiment. The same parts as those in FIG. 1 are denoted by the same reference numerals, and only different parts will be described.

  In the first embodiment, the case where the present invention is applied to the phase synchronization circuit has been described. On the other hand, the second embodiment shows a case where the present invention is applied to a frequency synchronization circuit.

  In FIG. 8, the reference signal ref is, for example, a rectangular wave, and this reference signal ref is supplied to the delay detection circuit 21. The delay detection circuit 21 is configured by, for example, a delay circuit and an exclusive OR circuit, and is an exclusive OR circuit of a reference signal ref and a signal refd obtained by delaying the reference signal ref. The output signal of the delay detection circuit 21 is supplied to the LPF 23. The LPF 23 integrates, for example, the output signal of the delay detection circuit 21 to generate a DC voltage.

  The feedback signal output from the frequency divider 15 is supplied to the delay detection circuit 22. This delay detection circuit has the same configuration as the delay detection circuit 21, and is a circuit that obtains an exclusive OR of the feedback signal and the delayed feedback signal. The output signal of the delay detection circuit 22 is supplied to the LPF 24, and a DC voltage is generated.

  Output voltages of the LPFs 23 and 24 are supplied to the differential amplifier 25. The differential amplifier 25 detects a difference voltage between the DC voltages supplied from the LPFs 23 and 24. The output voltage of the differential amplifier 25 is supplied to the ring VCO 14 via the LPF 26. The ring VCO 14 oscillates in synchronization with the frequency using the output voltage of the LPF 26 as a control voltage bias. At this time, the oscillation operation of the ring VCO 14 is synchronized with the pulse signal inj injected from the delay circuit 17. That is, the ring VCO 14 oscillates in synchronization with the phase of the reference signal ref. For this reason, the ring VCO 14 oscillates in synchronization with the frequency and phase.

  According to the second embodiment, the injection locked ring VCO 14 is provided as the VCO constituting the frequency locked circuit. For this reason, this frequency synchronization circuit is also synchronized with the phase of the reference signal ref, and can realize low phase noise characteristics.

  Further, since the frequency synchronization circuit of the second embodiment is configured by a CMOS circuit without using an inductor, the occupied area of the chip can be reduced.

  In addition, the ring VCO is constituted by a differential inverter circuit, and the two PMOS transistors constituting the load circuit of the inverter circuit constituting the differential inverter circuit are controlled by the control voltage bias and biasn shifted from bais. ing. Therefore, an oscillation operation can be performed in a wide range of the power supply voltage VDD, and a wide frequency band can be obtained.

(Modification)
FIG. 9 shows a modification of the ring VCO. In the first and second embodiments, the ring VCO 14 is configured by a differential inverter circuit. However, the present invention is not limited to the differential inverter circuit, and can be configured by a single ring VCO.

  FIG. 9 shows a single ring VCO 31 according to a modification. The ring VCO 31 includes an odd number, for example, three inverter circuits I21, I22, I23 connected in series, and an NMOS transistor N41. The output terminal of the inverter circuit I23 is connected to the input terminal of the inverter circuit I21 to form a positive feedback loop. The current path of the NMOS transistor N41 is connected between the connection node of the inverter circuits I21 and I22 and, for example, the ground. A pulse signal inj is supplied to the gate of the NMOS transistor N41.

  In this ring VCO 31, when the pulse signal inj is injected into the gate of the NMOS transistor N41, the NMOS transistor N41 is turned on and the input terminal of the inverter circuit I22 is momentarily grounded. In this way, oscillation is started in synchronization with the reference signal ref.

  The connection position of the NMOS transistor N41 is not limited between the connection node of the inverter circuits I21 and I22 and the ground, but between the connection node of the inverter circuits I21 and I22 and the node to which the power supply voltage VDD is supplied. It is also possible to provide it.

  Also according to the above modification, it is possible to configure a synchronous circuit with low phase noise and a reduced area occupied by the chip.

  Further, by adopting the configuration shown in FIG. 4 for each of the inverter circuits I21, I23, and I23, stable control can be performed over a wide range from the ground potential to the power supply voltage, and broadband oscillation can be realized.

  In addition, the present invention is not limited to the first and second embodiments, and various modifications can be made without departing from the scope of the invention.

  DESCRIPTION OF SYMBOLS 11 ... Phase detector, 12 ... Charge pump circuit, 13 ... LPF, 14 ... Injection locked ring VCO, 15 ... Frequency divider, 16 ... Pulse generator, 17 ... Delay circuit, 14a, 14b ... Differential inverter circuit, 14c ... Bias level shifter, I1-I4 ... Inverter circuit, N11 ... N channel MOS transistor, P22, P23 ... P channel MOS transistor, 21, 22 ... Delay detection circuit, 23, 24 ... LPF, 25 ... Differential amplifier, 31 ... Single ring VCO.

Claims (9)

A phase detector for detecting a phase difference between the reference signal and the feedback signal;
A voltage generator for generating a voltage based on an output signal of the phase detector;
A pulse generator for generating a pulse signal based on the reference signal;
A voltage controlled oscillator that oscillates a signal based on a voltage supplied from the voltage generator in synchronization with a pulse signal supplied from the pulse generator;
A frequency divider that divides the signal supplied from the voltage controlled oscillator and generates the feedback signal;
Comprising
The voltage controlled oscillator is:
A level shift circuit for shifting the level of the voltage supplied from the voltage generation circuit;
A ring oscillator including a plurality of inverter circuits having a load circuit driven by a voltage supplied from the voltage generation circuit and a level shifted voltage supplied from the level shift circuit;
A synchronization circuit, wherein a pulse signal supplied from the pulse generator is supplied to one of the plurality of inverter circuits. A first delay detector for delay-detecting the reference signal;
A second delay detector for delay detecting the signal;
A first voltage generation circuit for generating a voltage from an output signal of the first delay detector;
A second voltage generating circuit for generating a voltage from the output signal of the second delay detector;
A differential amplifier that outputs a voltage difference between the voltages supplied from the first and second voltage generation circuits;
A pulse generator for generating a pulse signal based on the reference signal;
A voltage controlled oscillator that oscillates a signal based on a voltage supplied from the differential amplifier in synchronization with a pulse signal supplied from the pulse generator;
A frequency divider that divides the signal supplied from the voltage controlled oscillator and generates the feedback signal;
Comprising
The voltage controlled oscillator is:
A level shift circuit for shifting the level of the voltage supplied from the differential amplifier;
A ring oscillator comprising a plurality of inverter circuits driven by a voltage supplied from the differential amplifier and a level shifted voltage supplied from the level shift circuit;
Composed of
A synchronization circuit, wherein a pulse signal supplied from the pulse generator is supplied to one of the plurality of inverter circuits. The ring oscillator is composed of a plurality of differential inverter circuits connected in series in which an output signal is positively fed back to an input terminal,
3. The synchronous circuit according to claim 1, wherein the pulse signal is supplied to one of the plurality of differential inverter circuits. The differential inverter circuit is:
A first inverter circuit to which an input signal is supplied;
A second inverter circuit supplied with the inverted input signal;
A latch circuit connected between output terminals of the first and second inverter circuits and configured by third and fourth inverter circuits for latching output signals of the first and second inverter circuits;
A first transistor of a first conductivity type connected between the output terminals of the first and second inverter circuits and having the pulse signal supplied to the gate;
The synchronization circuit according to claim 1, further comprising: Each of the third and fourth inverter circuits is
A second transistor of the second conductivity type;
A third transistor of the first conductivity type having a gate and a current path commonly connected to the gate and the current path of the second transistor;
A fourth transistor of a second conductivity type having a current path connected to a current path of the second transistor and a gate supplied with an output voltage of the voltage generation circuit;
A fifth transistor of a second conductivity type having a current path connected to the current path of the second transistor and having a gate supplied with a level shifted voltage output from the level shift circuit;
The synchronization circuit according to claim 1, further comprising: The level shift circuit includes:
The output voltage of the voltage generator exceeds the threshold voltage of the second and fourth transistors of the second conductivity type, and the level-shifted voltage is output from the power supply voltage to the power supply voltage. The synchronization circuit according to claim 1.   The synchronization circuit according to claim 1, wherein the pulse generator generates a pulse signal having a duty ratio smaller than a duty ratio of the reference signal based on the reference signal.   The synchronization circuit according to claim 1, further comprising a delay circuit that delays a pulse signal output from the pulse generator. The ring oscillator is
A plurality of inverter circuits connected in series in which an output signal is positively fed back to the input terminal;
A sixth transistor of a first conductivity type in which a current path is connected between one output terminal of the plurality of inverter circuits and a first power supply, and the pulse signal is supplied to a gate;
The synchronization circuit according to claim 1, further comprising:

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