JP2011217258A - Apparatus and method for transffering data - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such a problem that securing a data transfer band corresponding to a peak rate may reduce network band utilization efficiency, in a data transfer apparatus which has a plurality of data transfer channels and performs isochronous transfer.SOLUTION: Priorities are set to channels and transfer band allocation is started in order from a highest-priority channel by a flow control part. Improvement of band utilization efficiency and preventing data transfer from being missed for a high-priority channel are achieved by implementing this for each cycle.

Description

  The present invention relates to a data transfer apparatus and a data transfer method for effectively using a data transfer band of a common bus when transferring a plurality of types of data to a common bus by isochronous transfer.

  In a data transfer apparatus that multicasts data transmitted from a plurality of channels to a network by isochronous transfer, it is necessary to ensure smooth transfer of data transmitted from each channel to the network. This can be realized by securing a value obtained by adding the peak value of the transfer band for each data as the use band of the data transfer apparatus. However, since the peak of data transfer of all channels rarely overlaps, using this method of securing the used bandwidth will secure an excess bandwidth and secure the bandwidth of other devices connected to the network. It becomes a factor to inhibit.

  In order to solve such a problem, there is a method of lending unused bandwidth generated when handling variable rate data to another channel. In addition, there is a method in which a channel used for transferring intermittent burst type data such as video data is used for transferring audio data during the blanking period of the data transfer (Patent Documents 1 and 2).

JP 2001-94575 A JP2003-8578

  In a method of lending unused bandwidth generated when handling variable rate data to other channels, arbitration between two channels is assumed. When this method is applied to a data transfer apparatus having a large number of channels, arbitration between a large number of channels may have to be performed, and processing such as arbitration may be complicated.

  In addition, for a channel that performs intermittent burst type data transfer, a method of assigning a transfer band is premised on transfer of fixed-length data. Therefore, it is impossible to appropriately assign a transfer band to a channel that transfers variable length data such as encoded data.

  A data transfer device for transferring a plurality of data to a common bus by isochronous transfer, and when assigning a transfer band for each data prior to data transfer to the common bus and data transfer to the common bus, the priority of the data In descending order, the flow control unit that allocates the transfer band within the range of the allowable band reserved on the common bus, and the transfer band allocated by the flow control unit is subtracted from the use band reserved in advance on the common bus. A bandwidth updating unit that updates the allowable bandwidth.

  According to the present invention, in a data transfer apparatus including a plurality of channels for performing data transfer, it is possible to allocate a transfer band to each channel within the range of the band secured by the data transfer apparatus. As a result, it is not necessary to secure an extra bandwidth, and it is possible to effectively utilize a limited transfer bandwidth of the common bus. Further, even when the allowable bandwidth allocated to one data transfer device is reduced, it is possible to reliably transfer high priority data.

Conventional circuit diagram Circuit configuration diagram according to this embodiment Circuit diagram of data size controller Operation flow of data size controller Time variation of audio data volume Time variation of video data volume Time variation of the amount of encoded data Data volume of audio data, video data, encoded data Packet configuration with conventional circuit Packet configuration by the circuit according to this embodiment

  FIG. 1 shows a general configuration of a data transfer apparatus that multicasts data transmitted from a plurality of channels to a network by isochronous transfer. Data is input to the FIFO memories FA to FD corresponding to the channels ChA to ChD. The FIFO memories FA to FD function as a buffer. The FIFO memories FA to FD notify the packet generation unit PG of the stored data amount. The packet generation unit PG generates a packet after determining the transfer amount according to the notified data amount. Then, the packet generation unit PG extracts data from the FIFO memories FA to FD, generates a packet, and outputs the packet to the transmission unit SP.

  FIG. 2 shows a configuration diagram in the present embodiment. The configuration in this embodiment includes a data size control unit DSC in addition to the configuration shown in FIG. The data size controller DSC receives the amount of data stored in each FIFO memory from the FIFO memories FA to FD. In the data size control unit DSC, various control signals such as a use band reserved for the data transfer apparatus and a maximum transfer amount per cycle of each channel are stored in a register or the like which will be described later. . Then, the data size control unit calculates the transfer amount allocated to each channel based on these control signals and notifies the packet generation unit PG. The packet generation unit PG extracts data from the FIFO memories FA to FD based on the transfer amount assigned to each channel notified by the data size control unit DSC, and outputs the packet to the transmission unit SP.

Next, FIG. 3 shows a circuit diagram of the data size control unit DSC according to the present embodiment. FIG. 3 illustrates data transfer defined by the IEEE 1394 standard.
The data size control unit DSC includes size setting registers CLR (A) to CLR (D) for each of the channels ChA to ChD. The size setting registers CLR (A) to CLR (D) manage Channel_LIMIT (A) to Channel_LIMIT (D). Channel_LIMIT (A) to Channel_LIMIT (D) are values indicating the maximum amount of data that can be sent in one cycle for each channel.

The FIFO usage rate calculator FUA calculates the ratio between the amount of data stored in the FIFO memories FA to FD and the maximum amount of data that can be stored in the FIFO memories FA to FD, that is, the usage rate of each FIFO memory. To do. The FIFO usage rate calculator FUA includes FIFO usage rate calculators FUA (A) to FUA (D) corresponding to the channels ChA to ChD.
Signals FIFO_DATA_SIZE A to FIFO_DATA_SIZE D indicating the amount of data accumulated in each FIFO memory are input to the FIFO usage rate calculators FUA (A) to FUA (D) from the FIFO memory existing outside the data size controller DSC. The FIFO usage rate calculators FUA (A) to FUA (D) calculate the usage rate of each FIFO memory based on the signals FIFO_DATA_SIZE A to FIFO_DATA_SIZE D indicating the amount of data stored in the FIFO memory, and the result is a flow control sequencer. Output to FCS.

  The flow control sequencer FCS starts operation by detecting a CycleStart event defined by the IEEE1394 standard.

  The flow control sequencer FCS receives a signal indicating a processing channel determination rule to be obeyed from a setting register CR that determines the processing channel determination rule. In this embodiment, it is assumed that the following three types of processing channel determination rules are used. The processing channel determination rules can be used in combination.

  The processing channel determination rule 1 compares the usage rates of the FIFO memories FA to FD related to the respective channels ChA to ChD obtained by the FIFO usage rate calculators FUA (A) to FUA (D). As a result of comparison, it is a rule that data is transferred from a channel having the highest FIFO usage rate. By performing data transfer from the channel with the highest FIFO usage rate, it is possible to prevent data transfer from being lost due to overflow of the FIFO memory equally for all channels.

  The processing channel determination rule 2 is a rule for processing channels in order of priority set by the user. The higher the priority set by the user, the lower the possibility that the FIFO memory of that channel will overflow. Therefore, by increasing the priority of a channel that transmits important data, the user can prevent data transfer from being lost due to overflow of data from the FIFO memory for the channel. The priority setting by the user can be performed for only one channel or for all channels. Channels for which priority is not set by the processing channel determination rule 2 may be handled as equivalent priorities, or may be set according to the processing channel determination rule 1 or the processing channel determination rule 3 described later. Good.

  The processing channel determination rule 3 is a rule for performing priority control using a flag in addition to the processing channel determination rule 1. A flag ZERO_FLAG is set for a channel to which no transfer is assigned at the transfer timing. At the next transfer timing, the transfer is preferentially performed from the channel for which the flag ZERO_FLAG is set, thereby ensuring fairness between the channels.

  When the processing channel determination rule 2 is selected as the processing channel determination rule, information about the priority of each channel is held in the setting register CR and input to the flow control sequencer FCS.

  The flow control sequencer FCS receives the usage rate of each FIFO memory from the FIFO usage rate calculators FUA (A) to FUA (D), and selects a channel to be processed based on the usage rate. The flow control sequencer FCS has a register for managing the flag ZERO_FLAG inside, and uses this register when the processing channel determination rule 3 is selected as the processing channel determination rule.

  The flow control sequencer FCS receives FIFO_DATA_SIZE A to FIFO_DATA_SIZE D, which are values indicating the amount of data stored in each FIFO memory, from an external FIFO memory. The flow control sequencer FCS receives from the size setting register CLR the maximum bandwidths Channel_LIMIT (A) to Channel_LIMIT (D) that can be transferred at a single transfer timing determined in each of the channels ChA to ChD. The flow control sequencer FCS determines the data transfer amount of each channel based on the input FIFO_DATA_SIZE A to FIFO_DATA_SIZE D and Channel_LIMIT (A) to (D).

  Further, the flow control sequencer FCS reads a value indicating the used bandwidth reserved for the data transfer apparatus from the BANDWIDTH_AVAILABLE register under the isochronous manager defined by the IEEE1394 standard existing outside. The flow control sequencer FCS writes a value indicating the reserved bandwidth as a remaining transfer amount LIMIT_SIZE in a register LSR that holds the remaining transfer amount. Each time a transfer amount is assigned to each channel, LIMIT_SIZE is subtracted by the assigned amount.

  The flow control sequencer FCS calculates the transfer amount of each channel according to the flow described later as FIG. 4 based on the input signal group, and outputs the calculation result to the transfer amount holding registers TSR (A) to TSR (D). To do. The transfer amount holding registers TSR (A) to TSR (D) hold the input transfer amounts as TRANS_SIZE (A) to (D). The transfer amount holding registers TSR (A) to TSR (D) notify the packet generation unit PG existing outside of the transfer amount assigned to each channel.

FIG. 4 shows a flow in which the data size control unit DSC according to the present embodiment determines the transfer amount of each channel. The CycleStart signal is input to the flow control sequencer FCS, and the data size control unit DSC starts processing upon detection of a CycleStart event (S0). The user determines a use band value LIMIT_SIZE occupied by the data transfer device by setting a register existing outside the device (S2).
In the IEEE 1394 standard, the BANDWIDTH_AVAILABLE register under the isochronous resource manager indicates the amount of data that can be allocated by the common bus, and LIMIT_SIZE is determined within this value range.
The data size controller DSC reads a value from the setting register CR and determines which processing channel decision rule is to be followed (S4). The data size control unit DCS determines a processing channel according to the processing channel determination rule (S6). The user selects one of the processing channel determination rules 1 to 3 in advance.

  The value Channel_LIMIT stored in the size setting register CLR that defines the maximum size that can be transferred at one transfer timing set for each processing channel is compared with the data size FIFO_DATA_SIZE stored in the FIFO memory of the processing channel. (S8).

  If Channel_LIMIT is larger than FIFO_DATA_SIZE (S8: YES), FIFO_DATA_SIZE is stored as TRANS_SIZE in the transfer amount register TSR that holds the amount of data to be transferred at the next transmission timing (S10). Thereby, all data stored in the FIFO memory of the processing channel can be transferred.

  If FIFO_DATA_SIZE is greater than or equal to Channel_LIMIT (S8: No), Channel_LIMIT is stored as TRANS_SIZE in the transfer amount register TSR (S12). As a result, the transfer amount transferred from one channel can be limited to Channel_LIMIT or less, and the use band can be prevented from being monopolized by a specific channel.

A comparison is made between LIMIT_SIZE, which is the maximum transfer amount that can be sent at the next transfer timing, and TRANS_SIZE (S14).
When LIMIT_SIZE is greater than or equal to TRANS_SIZE (S14: Yes), a value obtained by subtracting the value stored in TRANS_SIZE from the value stored in LIMIT_SIZE is stored in LIMIT_SIZE (S16). Further, when the processing channel determination rule is the processing channel determination rule 3, the processing channel flag ZERO_FRAG is cleared (S18). If the processing channel determination rule is not the determination rule 3, the processing (S18) is skipped. Then, it is checked whether or not data remains in the FIFO memories of all channels (S20). If no data remains (S20: NO), the process is terminated (S28). If there is a channel for which TRANS_SIZE assignment has not been completed (S20: YES), the processing channel is determined again according to the processing channel determination rule (S6). At this time, the assigned channel is not selected.

If TRANS_SIZE is not less than LIMIT_SIZE for the processing channel (S14: No), LIMIT_SIZE is substituted for TRANS_SIZE (S22). LIMIT_SIZE indicates the maximum transfer amount of the used band on the network in the initial state (S2). Thereafter, the process proceeds, and every time channel data is allocated, the amount is transferred by TRANS_SIZE indicating the allocated transfer amount (S16). Therefore, at this time, the maximum size of the transfer amount that can still be allocated is shown. This is because, by substituting LIMIT_SIZE for TRANS_SIZE, data transfer beyond LIMIT_SIZE, which indicates the transfer amount that can be transferred in the corresponding channel at the current transfer timing, is impossible.
Then, TRANS_SIZE of a channel that has not been processed is set to zero (S24). Next, when the processing channel determination rule is the determination rule 3, the flag ZERO_FLAG of the channel in which the TRANS_SIZE is set to zero is set (S26). If the processing channel determination rule is not processing channel determination rule 3, the processing (S26) is skipped. Thus, the process ends (S28).
When TRANS_SIZE for all channels is determined as described above, each channel reads data from the FIFO memory according to the allocated transfer amount TRANS_SIZE and generates a packet. Each packet is transmitted to the network via the transmitter SP. The process up to this point is defined as one cycle, and the above flow is repeated each time a CycleStart event is detected.

  A specific example of data size control according to this embodiment will be described with reference to FIGS. First, with respect to three types of typical data transferred by the IEEE 1394 bus, the time change of the transfer amount will be described.

  As shown in FIG. 5, the audio data Audio has a characteristic that data of a fixed length is always transferred without changing with time.

  As shown in FIG. 6, since video data Video captured by a video camera transfers data in units of frames, there is a feature that there is a blanking period between data transfers and data is transferred intermittently. .

  As shown in FIG. 7, when transferring encoded data TS1 encoded by an encoding technique such as DVD or Blu-ray Disc (registered trademark) data, the data transfer amount varies with time.

  Further, FIGS. 5, 6, and 7 show times T1, T2, and T3, respectively. At time T1, the data transfer amount of video data Video and TS1 whose data transfer amount varies depending on the time is the maximum. At time T2, the data transfer amount of TS1, whose data transfer amount fluctuates depending on the time, is reduced compared to T1. At time T3, the data transfer amount of Video whose data transfer amount varies depending on the time is zero.

  FIG. 8 shows the data amount of the encoded data TS2 similar to the audio data Audio, video data Video, encoded data TS1, and encoded data TS1. The audio data Audio has a fixed length. The data amount of the video data Video becomes a maximum value at times T1 and T2, and becomes zero at time T3. The data amount of the encoded data TS1 has a maximum value at time T1.

  A packet configuration at each time when a packet is transmitted at times T1, T2, and T3 is illustrated. FIG. 9 shows transfer packets transferred at times T1, T2, and T3 in a conventional method in which data is transferred as much as it enters the FIFO memory. In the conventional method, it is necessary to secure the transfer bandwidth BW1 that is the sum of the transfer amount at time T1, that is, the peak value of the transfer amount of each channel.

  FIG. 10 illustrates a packet configuration when the data size control unit DSC described in the present embodiment is used. Note that the processing channel determination rule 1 is used as the processing channel determination rule.

At time T1, video data VIDEO and encoded data TS1 having an average high data rate have a large use amount of the FIFO memory, and as a result, the FIFO usage rate increases, so that a bandwidth is preferentially secured. In the case of FIG. 10, no bandwidth is allocated to a part of the encoded data TS2 and the audio data Audio that have a small FIFO memory usage and a low FIFO usage rate.
Even in such a case, if the amount of use of the FIFO memory related to the encoded data TS2 and the audio data Audio increases after the next transfer cycle, the bandwidth can be secured preferentially, and the FIFO overflow is prevented. be able to.

  At time T2, since the data rate of the encoded data TS1 has decreased and the amount of FIFO used for the encoded data TS1 has decreased, the audio data Audio and the encoded data TS2 are transferred.

  At time T3, the video data VIDEO data becomes zero, so the VIDEO bandwidth is not secured. Therefore, encoded data TS1 and TS2 and audio data Audio are transferred during this period.

  When the data size control unit DSC described in the present embodiment is used, the transfer band that needs to be secured for the transfer apparatus is the transfer band BW2 shown in FIG. The transfer band BW2 is smaller than the transfer band BW1 that needs to be secured in the prior art, and the transfer band secured for the transfer apparatus can be reduced.

  In the following, operational effects of the present embodiment will be described. The total bandwidth of the common bus is limited, and in isochronous transfer, a transfer device connected to the bus needs to secure a transfer bandwidth for each transfer device. Conventionally, an apparatus that transmits multiple channels had to secure a maximum bandwidth for the amount of data that fluctuates over time for each channel. Therefore, the maximum value is flattened and no extra bandwidth is required. Therefore, since the bandwidth of the common bus can be released to other devices, the finite common bus bandwidth can be used effectively.

  Also, for example, when streaming video data, if a part of the transfer data is lost, normal video playback cannot be performed. If the transfer becomes temporarily impossible due to initialization of the common bus or the like, such a data loss may occur if the FIFO memory of the transfer device overflows. In the present embodiment, overflow can be suppressed by setting a high priority for bandwidth allocation for data that is defective when transfer data such as video data is lost.

  If a transfer exceeding the reserved bandwidth is performed, the protocol is violated and the communication function of the entire common bus is hindered. Therefore, it is important to suppress data transfer exceeding the reserved bandwidth. In the present embodiment, since the bandwidth can be shared for each channel within the range of the transfer bandwidth secured by the transfer device, data exceeding the secured bandwidth is not transferred. Furthermore, when data stored in any of the FIFO memories is about to overflow, a bandwidth is preferentially allocated to avoid overflow. Also in this case, since the transfer band is allocated within the range of the reserved transfer band, data exceeding the reserved band is not transferred.

  When transferring a plurality of data whose data amount fluctuates with time, the process of monitoring each channel and distributing the increase / decrease in the data amount among the channels is executed, for example, in a cycle as short as 125 μS in the IEEE 1394 standard. It can also cope with sudden fluctuations in data volume.

  In the transfer channel determination rule 1, a channel for performing transfer band allocation processing is determined based on the FIFO usage rate obtained by the FIFO usage rate calculators FUA to FUD. As a result, it is possible to prevent the FIFO memory from overflowing equally for all channels, and to prevent data transfer from being lost.

  In transfer channel determination rule 2, the user sets priorities for an arbitrary number of channels in advance. This allows a user to set a high priority for a channel for transferring important data, so that overflow of the FIFO memory related to the channel can be prevented preferentially. Can be prevented.

  In transfer channel determination rule 3, a flag ZERO_FLAG is set for a channel to which no transfer band is assigned. For a channel for which the flag ZERO_FLAG is set, transfer bandwidth is preferentially assigned at the next cycle start event, thereby ensuring fairness between channels.

  In addition, it cannot be overemphasized that various improvement and deformation | transformation are possible within the range which does not deviate from the meaning of this invention.

  The FIFO memories FA to FD are examples of data holding units. Further, data transfer by IEEE 1394 is an example of isochronous transfer.

  Hereinafter, various aspects of the invention will be summarized as additional notes.

<Appendix 1>
A data transfer device for transferring a plurality of data to a common bus by isochronous transfer,
A data holding unit for holding the data;
A processing data determination unit that determines a processing order related to the data when allocating a transfer bandwidth for each data prior to data transfer to the common bus;
A data transfer apparatus comprising: a flow control unit that allocates the transfer band in an order determined by the processing data unit within a range of an allowable band secured on the common bus.
<Appendix 2>
The data transfer apparatus according to appendix 1, wherein the processing data determination unit allocates a transfer band in descending order of priority among the data.
<Appendix 3>
The data transfer apparatus according to appendix 1 or 2, further comprising: a band update unit that updates the transfer band by subtracting the transfer band from the allowable band when the transfer band is allocated to the data by the flow control unit.
<Appendix 4>
A data holding unit usage rate calculator that calculates a ratio between the data amount held by the data holding unit and the maximum data amount that can be held by the data holding unit as a usage rate of the data holding unit;
A data transfer apparatus according to any one of appendices 1 to 3, further comprising: a processing data determination unit that sets the priority higher as the usage rate is higher.
<Appendix 5>
A priority flag management unit that sets a priority flag for data for which the transfer bandwidth is not allocated;
5. The data transfer apparatus according to any one of appendices 1 to 4, wherein a high priority is set for data for which the priority flag is set.
<Appendix 6>
6. The data transfer apparatus according to any one of appendices 1 to 5, further comprising a priority holding register that holds a setting for the priority.
<Appendix 7>
7. The data transfer apparatus according to any one of appendices 1 to 6, wherein the priority holding register sets and holds the priority related to one or a plurality of data at a predetermined value.
<Appendix 8>
A data transfer method for transferring a plurality of data to a common bus by isochronous transfer,
Holding the data;
Prior to data transfer to the common bus, when allocating the transfer bandwidth for each piece of data, the transfer bandwidth is assigned within the allowable bandwidth reserved in the common bus in descending order of priority among the data. Steps,
And a step of updating the allowable bandwidth by reducing the transfer bandwidth allocated by the step of allocating the transfer bandwidth.

DSC data size control unit FA to FD FIFO memory SP transmission unit PG packet generation unit FUA FIFO usage rate calculator CLR size setting register FCS flow control sequencer CR setting register TSR transfer amount holding register LSR register for holding the remaining transfer amount

Claims (6)

A data transfer device for transferring a plurality of data to a common bus by isochronous transfer,
A data holding unit for holding the data;
A processing data determination unit that determines a processing order related to the data when allocating a transfer bandwidth for each data prior to data transfer to the common bus;
A data transfer apparatus comprising: a flow control unit that allocates the transfer band in an order determined by the processing data unit within a range of an allowable band secured on the common bus. The data transfer apparatus according to claim 1, wherein the processing data determination unit allocates a transfer band in descending order of priority among the data. 3. The data transfer device according to claim 1, further comprising a bandwidth update unit that updates the transfer bandwidth by subtracting the transfer bandwidth from the allowable bandwidth when the transfer bandwidth is allocated to the data by the flow control unit. A data holding unit usage rate calculator that calculates a ratio between the data amount held by the data holding unit and the maximum data amount that can be held by the data holding unit as a usage rate of the data holding unit;
The data transfer apparatus according to claim 1, further comprising: a processing data determination unit that sets the priority higher as the usage rate is higher. A priority flag management unit that sets a priority flag for data for which the transfer bandwidth is not allocated;
5. The data transfer apparatus according to claim 1, wherein the priority is set high for the data for which the priority flag is set. A data transfer method for transferring a plurality of data to a common bus by isochronous transfer,
Holding the data;
Prior to data transfer to the common bus, when allocating the transfer bandwidth for each piece of data, the transfer bandwidth is assigned within the allowable bandwidth reserved in the common bus in descending order of priority among the data. Steps,
And a step of updating the allowable bandwidth by reducing the transfer bandwidth allocated by the step of allocating the transfer bandwidth.

Images