JP2011216894A - Method of manufacturing semiconductor apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor apparatus with high operation performance and reliability.SOLUTION: A semiconductor apparatus has: an active layer surrounded by a silicon oxide film provided on a silicon substrate, a silicon oxide film with a film thickness of 0.05-0.5 μm that is obtained by carrying out thermal oxidation to a single crystal silicon substrate before becoming a single crystal island-shaped silicon layer, which includes part of the single crystal silicon substrate and becomes an active layer of a TFT, and that is provided by bonding to the silicon oxide film at a bonding interface, and a silicon oxide film of the other surface provided by carrying out thermal oxidation to an active layer; and a gate electrode provided on the active layer. The single crystal island-shaped silicon layer is obtained by dividing a single crystal silicon substrate, to which hydrogen is introduced via the oxidation silicon film having a film thickness of 0.05-0.5 μm, at a part where the hydrogen is introduced.

Description

The present invention provides a method for manufacturing a thin film transistor (hereinafter referred to as a TFT) using a single crystal silicon thin film formed over a substrate having an insulating surface, and includes a semiconductor circuit including a semiconductor circuit including a TFT. The present invention relates to a manufacturing method.

Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, such as an electro-optical device typified by a liquid crystal display device, a semiconductor circuit in which TFTs are integrated, and such an electric device. Electronic devices including optical devices and semiconductor circuits as parts are also included in the category.

In recent years, SOI (Silicon) has achieved low power consumption as VLSI technology has made significant progress.
on Insulator) structure is drawing attention. This technique is a technique in which an active region (channel formation region) of an FET that has been conventionally formed of bulk single crystal silicon is a single crystal silicon thin film.

In an SOI substrate, a buried oxide film made of silicon oxide exists on single crystal silicon, and a single crystal silicon thin film is formed thereon. Various methods are known for manufacturing such an SOI substrate. Recently, a bonded SOI substrate has attracted attention. A bonded SOI substrate, as its name suggests, realizes an SOI structure by bonding two silicon substrates. This technology may be able to form a single crystal silicon thin film on a glass substrate or the like in the future.

Among the bonded SOI substrates, a technology called Smart-Cut (registered trademark of SOITEC) is attracting particular attention recently. The Smart-Cut method was developed in 1996 by SOITEC, France, and is a method for manufacturing a bonded SOI substrate using hydrogen embrittlement. Smar
The detailed technology of the t-Cut method is detailed in “Industrial Research Committee, August issue of electronic materials, pp. 83-87, 1997”.

As another method, a technique called ELTRAN (registered trademark of Canon) is known. This technique is a method for manufacturing an SOI substrate using selective etching of a porous silicon layer. For details of the ELTRAN method, see "T.Yonehara, K.Sakaguchi and T.Hamag."
uchi: Appl.Phys.Lett.43 [3], 253 (1983) ".

Either method can be used to form a single crystal silicon thin film having a desired thickness on a substrate. However, both methods have a problem that a high stress is generated and remains in the formed single crystal silicon thin film because high temperature heat treatment is performed in the process of bonding two substrates.

If the stress at this time remains in the active layer of a TFT formed of a single crystal silicon thin film, it may act as a carrier trap level or cause a change in TFT characteristics over time. This problem is a very important problem in using the Smart-Cut method and the ELTRAN method, and a fundamental solution is required.

The present invention provides means for solving the above-mentioned problems, and includes Smart-Cut method and EL
It is an object of the present invention to provide a method for removing levels and defects caused by stress from a single crystal silicon thin film formed by a TRAN method.

And improvement of the operation performance of TFT using such a single crystal silicon thin film, and further TFT
It is an object of the present invention to improve the operation performance and reliability of semiconductor circuits and electro-optical devices using the above. Furthermore, it is an object to improve the operation performance and reliability of an electronic device equipped with such a semiconductor circuit or an electro-optical device.

The structure of the invention disclosed in this specification includes a first step of adding hydrogen from the main surface side to the first single crystal silicon substrate having a silicon oxide film on the main surface to form a hydrogenated layer, First
A second step of bonding a single crystal silicon substrate and a second substrate to be a support through the silicon oxide film; a third step of dividing the first single crystal silicon substrate by a first heat treatment; A fourth step of performing a second heat treatment on the single crystal silicon thin film remaining on the second substrate in a step, a fifth step of flattening a main surface of the single crystal silicon thin film, and the single crystal silicon thin film And a seventh step of performing a thermal oxidation process on the island-like silicon layer.

According to another aspect of the invention, there is provided a first step of adding hydrogen from the main surface side to the first single crystal silicon substrate having a silicon oxide film on the main surface to form a hydrogenated layer, and the first step. A second step of bonding a single crystal silicon substrate and a second substrate to be a support through the silicon oxide film; a third step of dividing the first single crystal silicon substrate by a first heat treatment; A fourth step of flattening a main surface of the single crystal silicon thin film remaining on the second substrate in a step; a fifth step of patterning the single crystal silicon thin film to form an island-like silicon layer; and And a sixth step of performing thermal oxidation treatment on the silicon layer.

According to another aspect of the invention, there is provided a first step of forming a porous silicon layer by anodizing a first single crystal silicon substrate, and a second step of epitaxially growing a single crystal silicon thin film on the porous silicon layer. And a third step of forming a silicon oxide film on the single crystal silicon thin film, and a fourth step of bonding the first single crystal silicon substrate and the second substrate to be a support through the silicon oxide film. A fifth step of performing a first heat treatment on the first single crystal silicon substrate and the second substrate, a sixth step of polishing the first single crystal silicon substrate until the porous silicon layer is exposed, A seventh step of removing the porous silicon layer and exposing the single crystal silicon thin film; an eighth step of patterning the single crystal silicon thin film to form an island-like silicon layer; And having a ninth step of performing thermal oxidation treatment, the relative island silicon layer.

According to another aspect of the invention, there is provided a first step of forming a porous silicon layer by anodizing a first single crystal silicon substrate, and a second step of epitaxially growing a single crystal silicon thin film on the porous silicon layer. And a third step of forming a silicon oxide film on the single crystal silicon thin film, and a fourth step of bonding the first single crystal silicon substrate and the second substrate to be a support through the silicon oxide film. A fifth step of polishing the first single crystal silicon substrate until the porous silicon layer is exposed; a sixth step of removing the porous silicon layer and exposing the single crystal silicon thin film; and the single crystal A seventh step of patterning the silicon thin film to form an island-shaped silicon layer; an eighth step of performing a thermal oxidation treatment on the island-shaped silicon layer;
It is characterized by having.

Note that the thermal oxidation treatment is performed at a temperature of 1050 to 1150 ° C. (typically 1100 ° C.). When the temperature exceeds about 1100 ° C., stress relaxation of the Si—O—Si bond occurs and the bonding interface is stabilized.

In the above structure, the thermal oxidation treatment is preferably performed in an oxidizing atmosphere containing a halogen element. As an oxidizing atmosphere containing a halogen element, oxygen and hydrogen chloride (HCl)
Or a mixed gas of oxygen and nitrogen trifluoride (NF ₃ ) may be used.

Of course, other methods such as dry O ₂ oxidation, wet O ₂ oxidation, steam (steam) oxidation, pyrogenic oxidation (hydrogen combustion oxidation), and oxygen partial pressure oxidation can be used.

Although the present invention having the above-described configuration, the most important gist is the Smart-Cut method or ELTR.
The purpose is to perform a heat treatment step at a high temperature on an island-like silicon layer formed of a single crystal silicon thin film formed by using the AN method. By doing so, the stress in the single crystal silicon layer is relieved, and trap levels and defects due to stress strain can be removed from the active layer of the TFT.

Therefore, the final crystallinity of the active layer can be almost restored to the original single crystal state, and the operation performance and reliability of the TFT can be improved. The operation of all the semiconductor devices that constitute the semiconductor circuit with the TFT. Performance and reliability can be improved.

When a single crystal silicon thin film is formed by a bonded SOI technique typified by the Smart-Cut method or ELTRAN method, the crystallinity inside the formed silicon layer can be restored to a substantially complete single crystal. That is, a single crystal silicon thin film having almost no trap levels or defects can be used as the active layer of the TFT.

Therefore, it is possible to greatly improve the operation performance and reliability of the plurality of TFTs formed on the substrate. Accordingly, it is possible to improve the operation performance and reliability of a semiconductor circuit, an electro-optical device, and an electronic device including the semiconductor circuit or the electro-optical device, each of which includes a plurality of TFTs.

The figure which shows the formation process of an island-like silicon layer. The figure which shows the formation process of an island-like silicon layer. The figure which shows the formation process of an island-like silicon layer. The figure which shows the formation process of an island-like silicon layer. 10A and 10B show a manufacturing process of a TFT. FIG. 9 illustrates a structure of a semiconductor circuit. FIG. 9 illustrates a structure of a semiconductor circuit. FIG. 11 illustrates a structure of an electronic device.

The embodiment of the present invention will be described in detail with the examples described below.

The configuration of the present invention will be described with reference to FIGS. First, the single crystal silicon substrate 10
Prepare 1 Next, thermal oxidation treatment is performed, and a silicon oxide film 1 is formed on the main surface (element formation surface).
02 is formed. The film thickness may be appropriately determined by the practitioner, but may be 0.05 to 0.5 μm. This silicon oxide film 102 later functions as a buried oxide film of the SOI substrate. (Fig. 1 (A
))

Next, hydrogen is added from the main surface side of the single crystal silicon substrate 101 through the silicon oxide film 102. In this case, hydrogen may be added using an ion implantation method in the form of hydrogen ions. Of course, the hydrogen addition step can be performed by other means. Thus, the hydrogenated layer 103 is formed. In this embodiment, hydrogen ions are used in an amount of 1 × 10 ¹⁶ to 1 × 10 ¹⁷ atoms / cm ^2.
Add at a dose of. (Fig. 1 (B))

Note that the depth at which the hydrogenation layer 103 is formed needs to be precisely controlled because it determines the thickness of the single crystal silicon thin film later. In this embodiment, the depth direction of the hydrogenation profile is controlled so that a 50 nm thick single crystal silicon layer remains between the main surface of the single crystal silicon substrate 101 and the hydrogenation layer 103.

Next, the single crystal silicon substrate 101 and a substrate having an insulating surface (second substrate) are attached to each other. As the second substrate, a substrate having a thin silicon oxide film on the surface is typically used. As the substrate, a substrate having high heat resistance such as a silicon substrate, a quartz substrate, a ceramic substrate, or a crystallized glass substrate is used. In this embodiment, a silicon substrate 105 provided with a thin silicon oxide film 104.
Is used. (Figure 1 (C))

At this time, since the bonding interface is made of silicon oxide films having high hydrophilicity, they are bonded by hydrogen bonds by the reaction of moisture contained on both surfaces.

Next, a heat treatment (first heat treatment) at 400 to 600 ° C. (typically 500 ° C.) is performed. By this heat treatment, a volume change of microdepletion occurs in the hydrogenated layer 103, and a fracture surface is generated along the hydrogenated layer 103. Thereby, the first single crystal silicon substrate 101 is divided, and the silicon oxide film 102 and the single crystal silicon thin film 106 are left on the second substrate. (Fig. 2 (A))

Next, a furnace annealing step is performed in a temperature range of 1050 to 1150 ° C. as a second heat treatment step. In this step, stress relaxation of the Si—O—Si bond occurs at the bonding interface, and the bonding interface is stabilized. That is, this is a process for completely bonding the single crystal silicon thin film 106 onto the second substrate 104. In this embodiment, this step is performed at 1100 ° C. for 2 hours.

Thus, the buried oxide film 107 is defined by stabilizing the bonding interface.
In FIG. 2B, a dotted line in the buried oxide film 107 indicates a bonded interface, which means that the interface is firmly bonded.

Next, the surface of the single crystal silicon thin film 106 is planarized by a polishing process. Although any known means can be used for the polishing step, a polishing technique called CMP (Chemical Mechanical Polishing) may be used.

Next, the single crystal silicon thin film 106 is patterned to form an island-like silicon layer 108 that will later become the active layer of the TFT. (Fig. 2 (C))

The process so far is the same as the normal Smart-Cut method. An important configuration of the present invention is a subsequent thermal oxidation step.

Next, thermal oxidation treatment is performed on the plurality of island-shaped silicon layers 108. By this thermal oxidation treatment, trap levels and defects existing in the island-like silicon layer 108 disappear, and the island-like silicon layer 109 whose crystallinity is recovered is formed. Reference numeral 110 denotes a silicon oxide film formed by thermal oxidation. This silicon oxide film 110 may be used as a gate insulating film of a TFT.

This thermal oxidation treatment may be performed in an oxidizing atmosphere, but is preferably performed in an oxidizing atmosphere containing a halogen element. In this embodiment, in an oxygen atmosphere containing nitrogen trifluoride (NF ₃ ), 800 ° C.
Thermal oxidation treatment for 2 hours is performed.

The purpose of this step is to relieve the stress remaining in the island-like silicon layer 108.
This will be described.

When heat treatment is performed at a high temperature in the process of FIG. 2B, a strong stress is applied to the single crystal silicon thin film 106, and as a result, trap levels and defects due to the stress are generated inside the thin film.
These trap levels and defects remain even after patterning to form an active layer. Needless to say, such trap levels cause the movement of carriers (electrons or holes) to be hindered, and the TFT characteristics are remarkably deteriorated.

However, in the configuration of the present invention, the trap level and defects inside the island-like silicon layer disappear by performing the thermal oxidation step of FIG. 2D, so that the TFT characteristics can be greatly improved and the reliability can be improved. Can do.

This example is an example in which the order of the manufacturing steps of Example 1 is changed. Since it is the same as that of Example 1 to the middle, description is abbreviate | omitted.

First, the procedure up to the substrate cutting step in FIG. Next, the second
When the single crystal silicon thin film remaining on the substrate is polished and planarized by means such as CMP, an island-shaped silicon layer is formed by performing a patterning process.

When the island-like silicon layer is formed, thermal oxidation is performed in that state. That is, the feature of this embodiment is that the stabilization of the bonding interface and the reduction of trap levels and defects in the island-like silicon layer are performed at the same time by the same heat treatment (temperature range is 1050 to 1150 ° C.). Become.

As described above, in Example 1, the second heat treatment process for stabilizing the bonding interface and the thermal oxidation process for reducing trap levels and defects are performed separately. Therefore, the number of processes can be reduced by combining both processes.

In Examples 1 and 2, an example in which trap levels and defects are reduced from a single crystal silicon thin film formed by the Smart-Cut method is shown. However, the present invention is a single crystal formed by another bonded SOI technology. It is also effective for silicon thin films.

In this embodiment, an example in which the present invention is applied to a single crystal silicon thin film formed by an ELTRAN method which is one of bonded SOI technologies will be described with reference to FIGS.

First, a single crystal silicon substrate 301 is prepared, and a porous silicon layer 302 is formed by anodizing the main surface. The anodizing step may be performed in a mixed solution of hydrofluoric acid and ethanol. Since the ELTRAN method itself is known, detailed description is omitted here.

Then, a 100 nm thick single crystal silicon thin film 303 is formed on the porous silicon layer 302 by epitaxial growth. (Fig. 3 (A))

After the single crystal silicon thin film 303 is formed, a thermal oxidation process is performed to form 1 on the single crystal silicon thin film.
A silicon oxide film 304 having a thickness of 00 nm is formed. This silicon oxide film 304 functions later as a buried oxide film of the SOI substrate. In addition, the single crystal silicon thin film 3 is formed by this thermal oxidation process.
The film thickness of 05 is 50 nm. (Fig. 3 (B))

Next, a ceramic substrate (second substrate) 307 having a thin silicon oxide film 306 formed on the surface thereof.
And the above-mentioned single crystal silicon substrate 301 are bonded together. (Fig. 3 (C)
)

When the bonding is completed, a heat treatment step is then performed at a temperature of 1050 to 1150 ° C. to stabilize the bonding interface made of silicon oxides. In this embodiment, this heat treatment step is performed at 110.
Perform at 0 ° C. for 2 hours. As described in the first embodiment, a dotted line indicates a bonded interface that is completely bonded. (Fig. 3 (D))

Next, the single crystal silicon substrate 301 is polished from the back side by mechanical polishing such as CMP, and the polishing is finished when the porous silicon layer 302 is exposed. In this way, the state of FIG.

Next, the porous silicon layer 302 is selectively removed by wet etching. The etchant used is preferably a mixed solution of a hydrofluoric acid aqueous solution and a hydrogen peroxide aqueous solution. 49% HF and 30% H
It has been reported that a solution in which ₂ O ₂ is mixed at 1: 5 has a selectivity ratio of 100,000 times or more between the single crystal silicon layer and the porous silicon layer.

Thus, the state of FIG. 4B is obtained. In this state, a buried oxide film 308 (strictly, a laminated film of silicon oxide films 304 and 306) is provided on the ceramic substrate 307, and a single crystal silicon thin film 305 is formed thereon.

Next, the single crystal silicon thin film 305 is patterned to form an island-shaped silicon layer 309. Of course, this island-like silicon layer is basically used as the active layer of the TFT. (Fig. 4 (C))

The numerical conditions described so far are not limited to the present embodiment, but are known ELTRAN.
Legal technology can be used as is.

After the island-like silicon layer 309 is formed, a thermal oxidation process that is a feature of the present invention is performed.
In this embodiment, thermal oxidation is performed at 950 ° C. for 30 minutes in a state where hydrogen chloride gas is mixed in an oxygen atmosphere. Of course, other halogen gases such as nitrogen trifluoride may be mixed in addition to hydrogen chloride. Also, a known thermal oxidation atmosphere such as dry oxygen or wet oxygen may be used. (Fig. 4
(D))

In this manner, the trap states and defects in the island-like silicon layer 309 disappear, and the island-like silicon layer 310 made of a single crystal silicon layer that does not interfere with carrier movement can be formed. Further, the silicon oxide film 311 formed at this time can be used as it is as a gate insulating film of the TFT.

As described above, the operation performance and reliability of the TFT can be greatly improved by forming an island-like silicon layer having no defect and manufacturing a TFT using the layer as an active layer. Accordingly, the operation performance and reliability of a semiconductor circuit using a TFT, an electro-optical device, and an electronic device can be improved.

This example is an example in which the order of the manufacturing steps of Example 3 is changed. Since the process is the same as that in the third embodiment, the description thereof is omitted.

First, the procedure up to the bonding process in FIG.
Next, the process proceeds to the polishing step shown in FIG. 4A without performing the heat treatment step shown in FIG.
Then, the process is finished up to the patterning step of FIG.

When the island-like silicon layer is formed, thermal oxidation is performed in that state. That is, the feature of this embodiment is that the stabilization of the bonding interface and the reduction of trap levels and defects in the island-like silicon layer are performed at the same time by the same heat treatment (temperature range is 1050 to 1150 ° C.). Become.

Thus, in Example 3, the heat treatment process for stabilizing the bonding interface and the thermal oxidation process for reducing trap levels and defects were performed separately, but according to this example, By combining both processes, the number of processes can be reduced.

In this embodiment, the case where a TFT is manufactured using an island-shaped silicon layer formed using the structure of Embodiments 1 to 4 will be described with reference to FIGS.

First, the island-like silicon layer 501 is formed according to the manufacturing steps of any of Embodiments 1 to 4. In this embodiment, a gate insulating film (silicon oxide film) 502 is formed simultaneously with a thermal oxidation process for removing trap levels and defects in the island-like silicon layer 501. Then, a gate electrode 503 made of an n-type polysilicon film is formed on the gate insulating film 502. (Fig. 5 (A)
)

Next, an impurity imparting n-type or p-type is added in a self-aligning manner using the gate electrode 503 as a mask. In this embodiment, an n-type TFT is used as an example, and phosphorus is added as an impurity. Of course, boron may be added to form a p-type TFT. By this step, the impurity region 5
04 is formed. (Fig. 5 (B))

It is also effective to control the threshold voltage of the TFT by adding a reverse conductivity type impurity (for example, boron for an n-type TFT) to the silicon layer directly under the gate electrode.
This impurity may be added from above the gate electrode by through doping, or may be added in advance before forming the gate electrode.

5B is obtained, side walls (side spacers) 505 made of a silicon oxide film are formed next. The sidewall 505 can be formed by using a known anisotropic etching technique.

After the sidewall 505 is formed, a phosphorus addition process is performed again, and the impurity region 50 described above is performed.
An impurity region having a concentration higher than 4 is formed. Through these two impurity addition steps, a source region 506, a drain region 507, an LDD region 508, and a channel formation region 509 are defined. (Fig. 5 (C))

Next, a thermal annealing step is performed to activate the impurities added in the previous step and recover the damage to the silicon layer due to damage during the addition. This thermal annealing step may be performed by any one of furnace annealing, laser annealing, and lamp annealing alone or in combination.

Next, in the state of FIG. 5C, the entire surface is covered with a cobalt film (not shown), and a thermal annealing process is performed to form a cobalt silicide layer 510. In addition to cobalt, a metal film such as titanium or tungsten can also be used. Since this process is a known salicide technique, a detailed description thereof will be omitted.

Next, an interlayer insulating film 511 made of a resin material is formed to a thickness of 1 μm. In addition, as the interlayer insulating film 511, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film may be used, or these insulating films may be stacked.

Next, contact holes are formed in the interlayer insulating film 511 to form source wirings 512 and drain wirings 513 made of a material containing aluminum as a main component. Finally, the furnace is annealed at 350 ° C. for 2 hours in a hydrogen atmosphere to complete the hydrogenation.

In this way, a TFT as shown in FIG. 5D is obtained. Note that the structure described in this embodiment is merely an example, and the TFT structure to which the present invention can be applied is not limited thereto. Therefore, the present invention can be applied to any known top gate TFT.

Further, if a pixel electrode (not shown) electrically connected to the drain wiring 513 in the structure of FIG. 5D is formed by a known means, it is easy to form a pixel switching element of an active matrix display device. is there.

That is, the present invention is a very effective technique as a method for manufacturing an electro-optical device such as a liquid crystal display device or an EL (electroluminescence) display device.

As described above, the present invention can be applied to TFTs having any structure, and various semiconductor circuits can be constructed using the present invention. That is, it can be said that the present invention can be applied to any semiconductor device including a semiconductor circuit formed of TFTs.

In this embodiment, an example of a liquid crystal display device in which a semiconductor circuit is configured with TFTs formed in accordance with the manufacturing process of Embodiment 5 is shown in FIG. Since a known method may be used for a manufacturing method of a pixel TFT (pixel switching element) and a cell assembly process, detailed description thereof is omitted.

In FIG. 6, 11 is a substrate having an insulating surface, 12 is a pixel matrix circuit, 13 is a source driver circuit, 14 is a gate driver circuit, 15 is a counter substrate, 16 is an FPC (flexible printed circuit), and 17 is a signal processing circuit. .

As the signal processing circuit 17, a conventional I / O such as a D / A converter, a γ correction circuit, and a signal dividing circuit is used.
It is possible to form a circuit that performs processing similar to that used in C. Of course, I on the glass substrate
It is also possible to provide a C chip and perform signal processing on the IC chip.

Further, in this embodiment, the liquid crystal display device is described as an example, but the present invention is applied to an EL (electroluminescence) display device and an EC (electrochromic) display device as long as it is an active matrix display device. It goes without saying that it is also possible to do.

Note that when the liquid crystal display device shown in this embodiment is manufactured, any structure of Embodiments 1 to 4 may be adopted.

The present invention can be applied to all conventional IC technologies. That is, it can be applied to all semiconductor circuits currently on the market. For example, the present invention may be applied to a microprocessor such as a RISC processor or an ASIC processor integrated on a single chip, or from a signal processing circuit such as a D / A converter to a portable device (cell phone, PHS, mobile computer). You may apply to a high frequency circuit.

FIG. 7 shows an example of a microprocessor. The microprocessor typically includes a CPU core 21, a RAM 22, a clock controller 23, a cache memory 24, a cache controller 25, a serial interface 26, an I / O port 27, and the like.

Of course, the microprocessor shown in FIG. 7 is a simplified example, and various circuit designs are performed on an actual microprocessor depending on its application.

However, it is an IC (Integrated Circuit) 28 that functions as the center of a microprocessor having any function. The IC 28 is a functional circuit in which an integrated circuit formed on the semiconductor chip 29 is protected with ceramic or the like.

The N-channel TFT 30 and the P-channel TFT 31 having the structure of the present invention constitute an integrated circuit formed on the semiconductor chip 29.
Note that power consumption can be suppressed by configuring a basic circuit with a CMOS circuit as a minimum unit.

The microprocessor shown in this embodiment is mounted on various electronic devices and functions as a central circuit. Typical electronic devices include personal computers, portable information terminal devices, and all other home appliances. Further, a computer for controlling a vehicle (such as an automobile or a train) may be used.

The electro-optical device of the present invention is used as a display of various electronic devices.
Such electronic devices include video cameras, still cameras, projectors, projection TVs, head mounted displays, car navigation systems, personal computers, personal digital assistants (mobile computers, mobile phones, etc.), etc.

FIG. 8A illustrates a mobile phone, which includes a main body 2001, an audio output unit 2002, and an audio input unit 2003.
, A display device 2004, an operation switch 2005, and an antenna 2006. The present invention can be applied to the audio output unit 2002, the audio input unit 2003, the display device 2004, and other signal control circuits.

FIG. 8B illustrates a video camera, which includes a main body 2101, a display device 2102, and an audio input unit 210.
3, an operation switch 2104, a battery 2105, and an image receiving unit 2106. The present invention is applied to a display device 2102, a voice input unit 2103, and other signal systems.

FIG. 8C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, and a display device 2205. The present invention can be applied to the display device 2205 and other signal control circuits.

FIG. 8D illustrates a head mounted display, which includes a main body 2301, a display device 2302, and a band portion 2303. The present invention can be applied to the display device 2302 and other signal control circuits.

FIG. 8E illustrates a rear projector, which includes a main body 2401, a light source 2402, and a display device 24.
03, polarizing beam splitter 2404, reflectors 2405 and 2406, screen 2
407. The present invention can be applied to the display device 2403 and other signal control circuits.

FIG. 8F illustrates a front projector, which includes a main body 2501, a light source 2502, a display device 2503, an optical system 2504, and a screen 2505. The present invention is a display device 250.
3 and other signal control circuits.

As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields.

Claims (9)

A single crystal silicon thin film comprising a part of the single crystal silicon substrate is provided on a first silicon oxide film having a thickness of 0.05 μm to 0.5 μm obtained by thermally oxidizing the single crystal silicon substrate; A method for manufacturing a semiconductor device using the silicon substrate, wherein the first silicon oxide film is bonded to a second silicon oxide film provided on a silicon substrate,
Forming a plurality of island-like silicon layers from the single crystal silicon thin film;
After the thermal oxidation process of the plurality of island-like silicon layers, a gate electrode made of polysilicon is formed on the plurality of island-like silicon layers,
Forming a sidewall on the side surface of the gate electrode;
Forming a source region and a drain region in the plurality of island-shaped silicon layers;
Forming a metal film on the gate electrode, the source region and the drain region, and heating to form a silicide on the gate electrode, the source region and the drain region;
A method for manufacturing a semiconductor device, comprising forming an interlayer insulating film so as to cover the plurality of island-shaped silicon layers. A first silicon oxide film on a support substrate;
A hydrogen-introduced single crystal silicon substrate having a second silicon oxide film with a thickness of 0.05 μm to 0.5 μm formed of a thermal oxide film on the surface is attached to the first silicon oxide film and divided. A method of manufacturing a semiconductor device using the support substrate having a single crystal silicon thin film obtained by:
Forming a plurality of island-like silicon layers from the single crystal silicon thin film;
After the thermal oxidation process of the plurality of island-like silicon layers, a gate electrode made of polysilicon is formed on the plurality of island-like silicon layers,
Forming a sidewall on the side surface of the gate electrode;
Forming a source region and a drain region in the plurality of island-shaped silicon layers;
Forming a metal film on the gate electrode, the source region and the drain region, and heating to form a silicide on the gate electrode, the source region and the drain region;
A method for manufacturing a semiconductor device, comprising forming an interlayer insulating film so as to cover the plurality of island-shaped silicon layers. A silicon substrate having a first silicon oxide film;
A single crystal silicon substrate having a second silicon oxide film having a thickness of 0.05 μm to 0.5 μm made of a thermal oxide film and introduced with hydrogen,
The first silicon oxide film and the second silicon oxide film are bonded together to divide the single crystal silicon substrate to produce a single crystal silicon thin film on the silicon substrate, and the bonding interface is the single crystal A method of manufacturing a semiconductor device using the silicon substrate closer to the silicon substrate than a silicon thin film,
Forming a plurality of island-like silicon layers from the single crystal silicon thin film;
After the thermal oxidation process of the plurality of island-like silicon layers, a gate electrode made of polysilicon is formed on the plurality of island-like silicon layers,
Forming a sidewall on the side surface of the gate electrode;
Forming a source region and a drain region in the plurality of island-shaped silicon layers;
Forming a metal film on the gate electrode, the source region and the drain region, and heating to form a silicide on the gate electrode, the source region and the drain region;
A method for manufacturing a semiconductor device, comprising forming an interlayer insulating film so as to cover the plurality of island-shaped silicon layers.   4. The method for manufacturing a semiconductor device according to claim 1, wherein the metal film is cobalt, titanium, or tungsten.   5. The method for manufacturing a semiconductor device according to claim 1, wherein the interlayer insulating film is formed of a silicon nitride film. A single crystal silicon thin film comprising a part of the single crystal silicon substrate is provided on a first silicon oxide film having a thickness of 0.05 μm to 0.5 μm obtained by thermally oxidizing the single crystal silicon substrate; A method for manufacturing a semiconductor device using the silicon substrate, wherein the first silicon oxide film is bonded to a second silicon oxide film provided on a silicon substrate,
Forming a plurality of island-like silicon layers from the single crystal silicon thin film;
A method for manufacturing a semiconductor device, comprising: forming a gate electrode made of polysilicon on a gate insulating film formed by thermal oxidation after thermal oxidation of the plurality of island-like silicon layers. A first silicon oxide film on a support substrate;
A hydrogen-introduced single crystal silicon substrate having a second silicon oxide film with a thickness of 0.05 μm to 0.5 μm formed of a thermal oxide film on the surface is attached to the first silicon oxide film and divided. A method of manufacturing a semiconductor device using the support substrate having a single crystal silicon thin film obtained by:
Forming a plurality of island-like silicon layers from the single crystal silicon thin film;
A method for manufacturing a semiconductor device, comprising: forming a gate electrode made of polysilicon on a gate insulating film formed by thermal oxidation after thermal oxidation of the plurality of island-like silicon layers. A silicon substrate having a first silicon oxide film;
A single crystal silicon substrate having a second silicon oxide film having a thickness of 0.05 μm to 0.5 μm made of a thermal oxide film and introduced with hydrogen,
The first silicon oxide film and the second silicon oxide film are bonded together to divide the single crystal silicon substrate to produce a single crystal silicon thin film on the silicon substrate, and the bonding interface is the single crystal A method of manufacturing a semiconductor device using the silicon substrate closer to the silicon substrate than a silicon thin film,
Forming a plurality of island-like silicon layers from the single crystal silicon thin film;
A method for manufacturing a semiconductor device, comprising: forming a gate electrode made of polysilicon on a gate insulating film formed by thermal oxidation after thermal oxidation of the plurality of island-like silicon layers.   8. The method for manufacturing a semiconductor device according to claim 2, wherein the supporting substrate is a silicon substrate.

Images