JP2011215124A - Capacitance detecting arrangement and capacitance detecting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a capacitance detecting apparatus and a capacitance detecting method capable of detecting capacitance change stably even in noisy environment.SOLUTION: The capacitance detecting apparatus is equipped with: switches SW1 and SW2 switching over voltage level for charging target detection capacitances Cf and Cs to a plurality of voltage levels with a predetermined period; a plurality of distribution capacitances Cdp and Cdn to which charge charged to the target detection capacitances Cf and Cs is distributed; second switches SW5 and SW6 setting the voltage level for initializing distribution capacitances Cdp and Cdn to a plurality of voltage levels with the predetermined period; other switches SW3 and SW4 switching connection so that charge is distributed from the target detection capacitances Cf and Cs as the electric charge of reverse polarity in a complementary style to the distribution capacity; and a charge amplifier 12 transforming the charge charged in the distribution capacitances Cdp and Cdn to voltage.

Description

  The present invention relates to a capacitance detection device and a capacitance detection method that can detect a minute change in capacitance even in a noisy environment.

  Conventionally, several capacitance detection devices for detecting minute capacitance changes have been proposed. For example, a capacitance detection device that charges an unknown sensor capacitance and monitors the voltage while transferring the charge amount to another fixed capacitance element to detect a change in sensor capacitance has been proposed (for example, Patent Document 1). reference). In addition, a capacitance detection device that detects a change in the capacitance of a sensor by comparing the voltage of the sensor capacitance with a fixed voltage while discharging the amount of charge charged in the fixed capacitance element by the sensor capacitance has been proposed (for example, Patent Documents). 2).

  FIG. 43 shows a schematic configuration of the capacity detection device described in Patent Document 1. Cx shown in the figure is a sensor capacitance including a finger and other parasitic capacitances, and Cs is a fixed capacitance element that actually measures voltage. First, the switches SW1 and SW2 are both turned OFF, and the switch SW3 is turned ON to reset the charge amount of the fixed capacitance element Cs. Next, after all the switches SW are turned off, the switch SW1 is turned on and the other switches SW are turned off to charge the sensor capacitor Cx to the power supply voltage Vdd. Then, after all the switches SW are turned off again, the switch SW2 is turned on and the other switches SW are turned off to transfer the charge amount of the sensor capacitor Cx to the fixed capacitor element Cs. At this time, the amount of charge transferred to the fixed capacitance element Cs is determined under the condition that the voltage is balanced according to the charge amount of the fixed capacitance element Cs before transfer. The charging sequence in which the switches SW1 and SW2 are alternately turned on (including the step of turning off all the switches SW in between) is repeated without resetting the charge of the sensor capacitor Cs. As a result, the inter-terminal potential Vs of the fixed capacitance element Cs rises as shown in FIG.

となる。この場合、指の有無による比較電圧Vrefを超えるのに必要な充電シーケンス回数は、ほぼセンサ容量Cxの大きさに比例し、指の有無で10%の違いがあったとして、比較電圧Vrefを超える充電シーケンスの回数の差も10%と程度となる。 Therefore, the comparison voltage Vref is set as shown in FIG. 45 with respect to the voltage Vs measured in order to determine the difference in the sensor capacitance Cx depending on the presence / absence of a finger (touch / non-touch). Charging when the comparison voltage Vref is exceeded due to the difference in the rise time of Vs between the sensor capacitance Cx (11pF) when there is a finger and the sensor capacitance Cx (10pF) when there is no finger, and the intersection with the comparison voltage Vref This can be determined as a difference in the number of times T of the sequence. The voltage of Vs is expressed by an equation

It becomes. In this case, the number of charge sequences required to exceed the comparison voltage Vref due to the presence or absence of the finger is almost proportional to the size of the sensor capacitance Cx, and exceeds the comparison voltage Vref, assuming that there is a 10% difference between the presence and absence of the finger. The difference in the number of charging sequences is about 10%.

  FIG. 46 shows a schematic configuration of the capacity detection device described in Patent Document 2. In the capacitance detection device described in Patent Document 2, the sensor capacitance Cx and the fixed capacitance elements Ca and Cs are connected as shown in FIG. 46, the switch SW1 is turned ON first, the other switches SW are turned OFF, and the fixed capacitance element Ca is set. Is charged to the power supply voltage Vdd. After that, after all the switches SW are turned off, the switch SW1 is turned off, the switches SW2 and SW3 are turned on, the charges of the fixed capacitor element Cs and the sensor capacitor Cx are reset, and the charges of the fixed capacitor element Ca are discharged. Discharge to ground with resistor R. Thereafter, all the switches SW are turned OFF, and Vx that is the potential between the terminals of the sensor capacitor Cx is measured. The sequence of discharging the fixed capacitance element Ca is repeated while comparing the Vx at that time with the comparison voltage Vref, and the presence / absence of a finger (touch / non-touch) is determined by the difference in the number of discharge sequences in which Vx becomes smaller than the comparison voltage Vref ( FIG. 47). In this case, by appropriately setting the magnitudes of Ca, Cs, and Vref, the total number of discharge sequences can be made shorter than the conventional circuit (FIG. 43) as shown in FIG.

Japanese translation of PCT publication No. 2002-530680 JP 2006-78292 A

  However, the conventional circuit described in Patent Document 1 has the following problems. In other words, in recent years, the use of touch sensors has expanded to mobile phones, flat panel TVs, etc. In such cases, the sensor must be installed in a location close to a shield plate or ground frame that is grounded to the ground. It has been. Under the conditions, the ratio of the fixed grounding capacity (base capacity) to the ground of the sensor capacity becomes very large, and the sensor capacity Cx sometimes has a difference of several percent depending on the presence or absence of a finger. Furthermore, there is a need to cover the upper surface of the sensor electrode with a cover plate or housing resin having a thickness of 5 mm or more due to a demand for design, and the sensor capacitance Cx tends to have a smaller ratio of difference due to the presence or absence of a finger. Therefore, in the conventional example of FIG. 43, it is necessary to increase the fixed capacitance element Cs to increase the charge sequence difference exceeding the comparison voltage Vref due to the presence or absence of the finger. There was a problem of becoming.

Further, the conventional circuit described in Patent Document 2 has the following problems. That is, the difference in the number of discharge sequences due to the influence of the base capacitance of the sensor capacitance Cx and the difference in sensor capacitance Cx due to the presence or absence of a finger cannot be increased, and the detection sensitivity is limited.
In these conventional circuits, the polarity of the charging voltage to the sensor is unipolar, so it is difficult to suppress or cancel external noise and circuit noise. The ratio was not obtained.

  The present invention has been made in view of such a point. In order to detect a minute capacitance, the present invention prevents the influence of the fixed capacitance component of the sensor capacitance and the decrease in the amount of change in the sensor, and also in a noisy environment. An object of the present invention is to provide a capacitance detection device and a capacitance detection method that enable stable detection.

  The capacitance detection device of the present invention includes a switching means for connecting to the detected capacitor, one or more distribution capacitors to which the charge charged in the detected capacitor is distributed, and initializing and charging the distribution capacitor. Voltage level supply means for supplying a plurality of voltage levels for distribution, and a charge amplifier for taking out the charge distributed to the distribution capacitor as a charge amount are provided.

  In the capacitance detection device, a charge may be distributed as a charge amount having a reverse polarity from the detected capacitance to the plurality of distribution capacitors in a complementary manner.

  In the capacitance detection device, the detected capacitance may be a coupling capacitance connected to a pulse supply source.

In the capacitance detection device, the charge amplifier is single-ended or fully differential.
In the capacitance detection device, the plurality of distribution capacitors may be divided into a plurality of groups, and the operation may be performed in parallel with different timings of initialization and charge distribution and charge amount extraction timing between the groups. Also good.

  In the capacity detection device, the distribution capacity may be provided with a mechanism capable of changing the size according to the size of the detected capacity.

  The capacitance detection device may further include a variable capacitor for subtracting invalid charges from the distribution capacitor, and a pulse driving unit for driving the variable capacitor in pulses.

  The capacity detecting device of the present invention switches the voltage level for charging the detected capacity to a plurality of voltage levels at a predetermined cycle and switches the charging operation by disconnecting the supply of the voltage level to the detected capacity. A first switch, a plurality of distribution capacitors to which charges charged in the detected capacitors are distributed, and the plurality of distribution capacitors are initialized at a plurality of voltage levels in accordance with the charging operation of the detected capacitors. The second capacitor and the first capacitor and the second switch together with the first capacitor and the second capacitor so that the charge is distributed as a charge amount having a reverse polarity to the plurality of distributed capacitors in a complementary manner. A third switch for switching the connection between the distribution capacitors and a charge amplifier for converting the charge charged in the distribution capacitors into a voltage are provided.

  According to this configuration, it is possible to improve the external noise resistance due to the complementary driving using a plurality of levels of voltage against the low frequency noise from the input unit by the distribution operation. Further, the time for sampling the charge amount of the detected capacitor can be minimized, and the external noise resistance can be greatly improved because the charge amplifier is not directly connected to the detected capacitor during the operation of converting the charge amount into voltage.

  According to the present invention, in the capacitance detection device, an output of a comparator connected to a subsequent stage of the charge amplifier is a logical output, and the logical output is fed back to the input of the charge amplifier as a charge amount via a feedback capacitor. A delta-sigma modulator is configured and converted to a digital value by a digital filter connected to a subsequent stage of the comparator.

  With this configuration, the AD converter can be efficiently configured by making the charge amplifier a part of the configuration of the AD converter. It can also have the effect of suppressing external noise by digital filters.

  In the capacitance detection device, the distribution capacitance may be variable according to the fixed charge amount that is included in the detected capacitance and is invalid for proximity detection of the detection target.

  In the capacitance detection device, it is desirable that the charge amplifier feedback capacitance and the delta-sigma modulator feedback capacitance be variable according to the magnitude of the difference in detection capacitance due to the proximity of the detection target.

  The capacitance detection device may have a configuration in which the detected capacitance is differentially input, or a configuration having an input unit capable of switching between a differential input and a single-ended input.

  Further, the capacity detection method of the present invention switches the voltage level for charging the detected capacitor to a plurality of voltage levels at a predetermined cycle, and disconnects the supply of the voltage level to the detected capacitor. Switching, a plurality of distribution capacitors to which charges charged in the detected capacitor are distributed, respectively, in accordance with a charging operation of the detected capacitor, respectively, at a plurality of voltage levels, and the detected And a step of distributing charge from the capacitor as a charge amount having a reverse polarity in a complementary manner to the plurality of distribution capacitors, and a step of converting the charge charged in the distribution capacitor into a voltage. .

  The capacity detection method of the present invention includes a step of charging the detected capacitor at a first voltage level, and a charge distributed to the detected capacitor is converted into a first distribution capacitor initialized at a predetermined voltage level. A step of distributing, a step of charging the detected capacitor at a second voltage level, and a charge charged in the detected capacitor being equal in capacity to the first distributed capacitor and different from the first distributed capacitor. Complementarily distributing a charge amount of opposite polarity to the second distribution capacitor initialized at the voltage level, and converting the charge charged in the first distribution capacitor and the second distribution capacitor into a voltage And a step of performing.

  These capacitance detection methods enable stable detection even in a noisy environment.

  According to the present invention, it is possible to prevent the influence of the fixed capacitance component of the sensor capacitance and the decrease in the change amount of the sensor in order to detect a minute capacitance, and to enable stable detection even in a noisy environment. .

It is a block diagram of a capacitive touch sensor module. It is a figure which shows the block configuration of a capacity | capacitance detection apparatus. It is a figure of the noise application model which made all the external noise the noise from a finger | toe. It is a conceptual diagram of three capacity | capacitance detection systems in a touch sensor module. It is a basic block diagram of a bipolar chopping filter. It is a block diagram of the chopping filter made into the pipeline. It is a figure which shows the state which isolate | separated the bipolar chopping filter shown in FIG. 5 into the single pole type chopping filter. It is a figure which shows four charge transfer methods applicable to a chopping filter (1st pole). FIG. 9 is an operation timing diagram and output waveform diagram of the chopping filter of FIG. 8. It is a figure which shows four charge transfer methods applicable to a bipolar chopping filter. FIG. 11 is an operation timing diagram and output waveform diagram of the chopping filter of FIG. 10. It is a figure which shows the structural example and charge transfer method of a bipolar type chopping filter whose distribution capacity initialization voltage is 1 level. FIG. 13 is an operation timing diagram and output waveform diagram of the chopping filter of FIG. 12. It is a figure which shows the structural example of the chopping filter of a mutual capacitance detection system which transfers an electric charge using an external electrode pulse. FIG. 15 is an operation timing diagram and output waveform diagram of the chopping filter of FIG. 14. It is a figure which shows the structural example of the chopping filter of a mutual capacitance detection system which transfers an electric charge using an external electrode pulse and an internal pulse. It is an operation | movement timing and output waveform figure of a chopping filter of Fig.16 (a) (b) (c). It is an operation | movement timing and output waveform figure of the chopping filter of FIG.16 (d) (e) (f). It is a figure which shows the structural example of the chopping filter of the differential type | mold mutual capacitance detection system which transfers an electric charge using an external electrode pulse. FIG. 19 is an operation timing diagram and output waveform diagram of the chopping filter of FIG. 18. It is a figure which shows the structural example of the other chopping filter of the differential type | mold mutual capacitance detection system which transfers an electric charge using an external electrode pulse. FIG. 21 is an operation timing diagram and output waveform diagram of the chopping filter of FIG. 20. It is a figure which shows the structural example of the chopping filter of the differential type | mold mutual capacitance detection system which transfers an electric charge using the transfer pulse which is an external electrode pulse and an internal pulse. It is a figure which shows the other structural example of the chopping filter of a differential type | mold mutual capacitance detection system which transfers an electric charge using the transfer pulse which is an external electrode pulse and an internal pulse. It is an operation | movement timing and output waveform figure of the chopping filter of FIG. 22A and 22B. It is a figure which shows the other structural example of the chopping filter of the differential type | mold mutual capacitance detection system which transfers an electric charge using an external electrode pulse and an internal pulse. It is a figure which shows the other structural example of the chopping filter of the differential type | mold mutual capacitance detection system which transfers an electric charge using an external electrode pulse and an internal pulse. It is an operation | movement timing and output waveform figure of the chopping filter of FIG. 24A and FIG. 24B. It is a figure which shows the structural example of the back | latter stage circuit corresponding to a single end chopping filter. It is a figure which shows the structural example of the back | latter stage circuit corresponding to a fully differential chopping filter. It is a specific circuit block diagram of the capacity | capacitance detection apparatus which concerns on a 1st Example. It is a timing chart of the capacity | capacitance detection apparatus which concerns on a 1st Example. It is a figure which shows the structural example of a variable capacity | capacitance. It is a circuit block diagram of the capacity | capacitance detection apparatus which concerns on a 2nd Example. It is a figure which shows the structural example of a crosspoint switch. It is a timing chart of one integration sequence in the 2nd example. It is the whole sequence of the integration sequence of the multiple times in the 2nd example, and is the figure which matched and showed the output waveform of the fully differential amplifier output. It is a figure which shows noise environment evaluation data. It is a circuit block diagram of the modification of a 2nd Example. It is a circuit block diagram of the capacity | capacitance detection apparatus which concerns on a 3rd Example. It is a timing chart of one integration sequence in the 3rd example. It is the whole sequence of the integration sequence of multiple times in the 3rd example, and is the figure showing correspondingly the output waveform of the fully differential amplifier output. It is a circuit block diagram of the chopping filter part which combined the 2nd and 3rd Example. It is a circuit block diagram of the capacity | capacitance detection circuit of a 4th Example. It is a whole sequence of the capacity | capacitance detection circuit of a 4th Example. It is a figure which shows schematic structure of the capacity | capacitance detection apparatus of patent document 1. It is a figure which shows the time change of Vs which is the electric potential between terminals of the fixed capacitance element Cs. It is a figure which shows the relationship between the voltage Vs and the comparison voltage Vref. It is a figure which shows schematic structure of the capacity | capacitance detection apparatus of patent document 2. FIG. 10 is an output waveform diagram of the capacity detection device described in Patent Document 2. FIG. It is a figure which shows the difference in an output waveform by the difference in the capacitance value in the capacity | capacitance detection apparatus of patent document 2. FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a block diagram of a capacitive touch sensor module. In general, a capacitance sensor module includes a sensor unit 101 formed of a conductor, a capacitance detection circuit 102 that converts a capacitance into an electric signal, and a control unit 103 that transmits the obtained electric signal to the host side. In the sensor unit 101, the capacitance Cf of the adjacent finger is connected in parallel to the parasitic sensor capacitance Cs of the sensor unit 101 and the reference potential (GND), so that the capacitance changes. The capacitance detection circuit 102 converts the electric signal. Note that the capacitance value between the finger (person) and the reference potential (GND) is approximately 100 pF or more, which is negligible when considered as a series capacitance with respect to the finger capacitance Cf (0.01 pF to 3 pF).

  FIG. 2 is a diagram showing an overall configuration of a capacitance detection device applicable to the capacitance detection circuit 102 in the capacitive touch sensor module of FIG. The capacitance detection device shown in FIG. 1 converts a low-frequency external noise into a high frequency and functions to reduce noise amplitude, and a base charge amount that removes an offset from charges transferred from the chopping filter 11. A cancel mechanism 12, an integrator 13 functioning as a delta-sigma modulator, and a digital filter 14 that takes in a comparator output (2-bit bit stream) output from the integrator 13 and converts it into a multi-bit digital signal by filtering processing are provided. . The chopping filter 11 takes in the detected capacitance from the sensor unit 101 by converting it into a charge amount. The base charge amount cancellation mechanism 12 cancels the capacitance that is not originally detected as an offset. The integrator 13 functions as a charge amplifier that amplifies the charge amount corresponding to the detected capacitance while integrating the obtained electrical signal (charge amount), and also serves as a delta sigma modulator to take part of the AD converter function. Operate. The digital filter 14 outputs a digital value corresponding to the detected capacitance from the binary bit stream, and contributes to suppression of external noise by a filter function (LPF).

  In such a capacitance detection device, external noise may be applied from the power source of the capacitance detection device, electromagnetic waves to the sensor electrode, and finger (human body), but may be all replaced with application from the finger as shown in FIG. There is no problem.

  4A, 4B, and 4C are conceptual diagrams of three capacitance detection methods in the touch sensor module. FIG. 4A is a self-capacitance detection method, and FIG. 4B is a mutual capacitance detection method. FIG. 5C shows a differential mutual capacitance detection system. In the self-capacitance detection method shown in FIG. 4A, the self-capacitance (capacitance between the sensor electrode and GND) is a detection target. In the mutual capacitance detection method shown in FIG. 4B, a mutual capacitance formed between two sensor electrodes is a detection target. In the differential mutual capacitance detection method shown in FIG. 4C, a capacitance defined as a difference between mutual capacitances formed between a reference electrode and two sensor electrodes is a detection target.

Next, the basic configuration of the chopping filter 11 will be described.
First, the chopping filter 11 of the self-capacitance detection method (FIG. 4A) will be described.
FIG. 5 shows a bipolar chopping filter configuration.
In the self-capacitance detection method shown in FIG. 4A, a capacitor Cf is formed between the finger and the sensor electrode, and a capacitor Cb is formed between the sensor electrode and the ground (GND). The capacitance Cb between the sensor electrode and the ground (GND) is the sensor capacitance. The sensor electrode is connected to the first fixed voltage Vdd via the switch SW1, and is connected to the second fixed voltage (ground) via the switch SW2. The switches SW1 and SW2 constitute a first switch for charging the detected capacitance including the sensor capacitance Cb and the finger capacitance Cf. The sensor electrodes forming the finger capacitance Cf and the sensor capacitance Cb are connected to the distribution capacitance Cdp1 through the switch SW3, and are connected to the distribution capacitance Cdn1 through the switch SW4. The switches SW3 and SW4 constitute a third switch for transferring the charges of the finger capacitor Cf and the sensor capacitor Cs to the distribution capacitors Cdp and Cdn. Both terminals of the distribution capacitor Cdp1 can be short-circuited by the switch SW5, and the distribution capacitor Cdn1 can be grounded via the switch SW6. The switches SW2, SW5, and SW6 constitute a second switch that initializes the sensor capacitance (Cf, Cb) and the distribution capacitances Cdp1, Cdn1. The switches SW7 and SW8 are switches for transferring the charges of the distribution capacitors Cdp1 and Cdn1 to the subsequent stage as differential charge signals. The switches are connected to a base charge amount cancellation mechanism 12 and an integrator 13 (hereinafter referred to as a post-stage circuit) connected to the subsequent stage via switches SW7 and SW8.

  FIG. 6 shows a pipeline configuration of the bipolar chopping filter shown in FIG. On one pole side, a distribution capacitor Cdp2 is connected via a switch SW3b in parallel with the distribution capacitor Cdp1 connected via a switch SW3a. A reset switch SW5b is connected to the distribution capacitor Cdp2. On the other pole side, the distribution capacitor Cdn2 is connected via the switch SW4b in parallel with the distribution capacitor Cdn1 connected via the switch SW4a. A reset switch SW6b is connected to the distribution capacitor Cdn2. At the timing when the distribution capacitors Cdp1 and Cdn1 are transferred to the subsequent circuit, the switches SW7a and SW8a are closed and connected to the subsequent circuit. At the timing when the distribution capacitors Cdp2 and Cdn2 are transferred to the subsequent circuit, the switches SW7b and SW8b are closed and connected to the subsequent circuit. To do. Details of the timing of the chopping filter having the pipeline configuration will be described later.

Next, a configuration example of the self-capacitance detection type chopping filter shown in FIG.
FIG. 7 shows a state where the bipolar chopping filter shown in FIG. 5 is separated into a single pole chopping filter. FIG. 7B shows a chopping filter configuration on the negative side (first pole), and FIG. 7C shows a chopping filter configuration on the positive side (second pole). The present invention can be used with any single pole chopping filter shown in FIGS.

  FIG. 8 shows four charge transfer methods as charge transfer methods applicable to the chopping filter (first pole). The chopping filter shown in FIG. 8A transfers charges when the switches SW1, 4, 6 are turned on / off. FIG. 9A shows an operation timing chart of the chopping filter (switch method) of FIG. The switches SW1 and SW6 are turned on, the switch SW4 is turned off, the capacitor Cs is charged to the fixed voltage Vcc, and the distribution capacitor Cdn1 is reset. At this time, the output S_N on the first pole side is at the GND potential. After turning off the switches SW1 and 6, turning on the switch SW4 transfers charges from the capacitor Cs to the distribution capacitor Cdn1, and the output S_N rises.

  FIGS. 8B to 8D are configuration examples of a chopping filter having the same function as the chopping filter of FIG. 8A, and charge transfer is performed by applying a transfer pulse DRV to the distribution capacitor Cdn1. 8B to 8D, the transfer pulse DRV is applied to the GND side of the distribution capacitor Cdn1 instead of the switch SW6 for resetting the distribution capacitor Cdn1 in the chopping filter of FIG. 8A. FIG. 9B shows an operation timing chart of the chopping filter (internal pulse method) of FIGS. 8B to 8D. By turning on the switches SW1 and SW4 and raising the transfer pulse DRV, the distribution capacitor Cdn1 is charged and the chopping filter output S_N rises to the fixed voltage Vdd. Thereafter, when SW1 is turned off and the transfer pulse DRV falls, the chopping filter output S_N falls to a predetermined level and stabilizes in synchronization with the fall of the transfer pulse DRV.

  In the subsequent integrator 13, the voltage difference between the chopping filter output S_N and the reference voltage VREF is detected as a charge amount.

FIGS. 10A to 10D show four charge transfer methods applicable to a bipolar chopping filter.
The bipolar chopping filter shown in FIG. 10 (a) has the chopping filter configuration shown in FIG. 5, and the voltage according to the capacity of the distribution capacitor Cdp1 becomes the second pole chopping filter S_P. The corresponding voltage is the first pole chopping filter S_N. In the figure, a fixed voltage Vdd is applied to one electrode of the distribution capacitor Cdp1, and one electrode of the distribution capacitor Cdn1 is held at the ground potential. Can also obtain the same function (the part indicated by a circle in the figure and the same meaning in other drawings).

  The bipolar chopping filter shown in FIG. 10 (b) eliminates the switches SW5 and SW6 for resetting the distribution capacitors Cdp1 and Cdn1, and transfers a transfer pulse to the first pole distribution capacitor Cdn1 instead of a fixed potential. DRV_N is applied, and a transfer pulse DRV_P is applied to the distribution capacitor Cdp1 of the second pole instead of the fixed potential.

  The bipolar chopping filter shown in FIG. 10 (c) eliminates the switches SW5 and SW6 for resetting the distribution capacitors Cdp1 and Cdn1, and transfers a transfer pulse instead of a fixed potential to the first capacitor distribution capacitor Cdn1. DRV_N is applied, and a transfer pulse DRV_P is applied to the distribution capacitor Cdp1 of the second pole instead of the fixed potential. Furthermore, one electrode of the distribution capacitor Cdn1 is connected to the fixed voltage Vdd via the switch SW1, and one electrode of the distribution capacitor Cdp1 is connected to the ground via the switch SW2.

  The bipolar chopping filter shown in FIG. 10D removes the reset switches SW5 and SW6 for the distribution capacitors Cdp1 and Cdn1, and transfers the transfer pulse DRV_N instead of the fixed potential for the first distribution capacitor Cdn1. And the transfer pulse DRV_P is applied to the distribution capacitor Cdp1 of the second pole instead of the fixed potential. Further, a switch SW1 is connected between both ends of the distribution capacitor Cdn1, and a switch SW2 is connected between both ends of the distribution capacitor Cdp1.

  FIG. 11A is a timing chart showing the operation content of the bipolar chopping filter shown in FIG. Only the switches SW1 and SW6 are turned on to charge the sensor capacitance Cs to the fixed voltage Vdd, while resetting the distribution capacitance Cdn1 of the first pole. The switches SW1 and SW6 are turned off and the switch SW4 is turned on. As a result, the sensor capacitor Cs and the distribution capacitor Cdn1 are connected in parallel, and the voltage corresponding to the combined capacitor becomes the first pole-side chopping filter output S_N. As shown in FIG. 11A, the first pole-side chopping filter output S_N rises from the ground potential to a voltage corresponding to the combined capacitance. The switch SW4 is turned off at the timing when the chopping filter output S_N becomes stable. Next, the switches SW2 and SW5 are turned on. Thereby, the sensor capacitance Cs is reset, and the distribution capacitance Cdp1 of the second pole is reset. By turning on the switch SW3 after turning off the switches SW2 and SW5, the distribution capacitor Cdp1 and the sensor capacitor Cs are connected in series between the fixed potential and the ground, and the voltage corresponding to the combined capacitance is chopped on the second pole side. Filter output S_P. As shown in FIG. 11A, the chopping filter output S_P on the second pole side drops from the fixed potential Vdd to a voltage corresponding to the combined capacitance. The potential difference between the chopping filter outputs S_N and S_P is detected by the charge amplifier at the subsequent stage. The potential difference between the outputs S_N and S_P is such that Cs> Cdp1, Cdn1 and Cs increases, the potential difference increases.

  FIG. 11B is a timing chart showing the operation content of the bipolar chopping filter shown in FIGS. 10B to 10D. Only the switches SW1 and SW4 are turned on to set the transfer pulses DRV_N and DRV_P to high level. Thereby, on the first pole side, the chopping filter output S_N becomes the fixed voltage Vdd while the transfer pulse DRV_N is at the high level. After that, the switch SW1 connected to the fixed potential Vdd (or transfer pulse DRV_N) is turned off to connect the sensor capacitor Cs and the distribution capacitor Cdn1 in parallel, and the transfer pulse DRV_N is set to the low level, so that the chopping filter output S_N becomes the sensor capacitor. The voltage drops to a voltage corresponding to the charge amount of Cs and stabilizes. Next, switch SW4 is turned off to disconnect the first pole side, switch SW2 is turned on to reset sensor capacitance Cs, switch SW3 is turned on to connect sensor capacitance Cs and distribution capacitance Cdp1, and to distribute The capacitor Cdp1 is connected to the ground (or the high level of DRV_P). Further, the transfer pulse DRV_P is set to low level. Thereby, on the second pole side, the chopping filter output S_P becomes the ground potential while the transfer pulse DRV_P is at the low level. When the switch SW2 is turned off and the transfer pulse DRV_P is set to the high level, the sensor capacitor Cs and the distribution capacitor Cdp1 are connected in parallel, and the chopping filter output S_P rises to a voltage corresponding to the charge amount of the sensor capacitor Cs and is stable. To do. The potential difference between the outputs S_N and S_P is such that Cs> Cdp1, Cdn1 and Cs increases, the potential difference increases.

  12A, 12B, and 12C show a configuration example of a bipolar chopping filter and a charge transfer method using one reference voltage VREF as an initialization voltage of a distribution capacitor. The chopping filters shown in FIGS. 5A, 5B, and 5C are partially different in configuration, but have the same function and operation (chopping filter output). In the chopping filter shown in FIG. 10, the switch SW2 is provided in order to set the sensor capacitance Cs to the ground potential. However, in the chopping filter shown in FIG. 12A, the initialization voltage is only one level of the reference voltage VREF. So switch SW2 has been deleted.

  In the chopping filter shown in FIG. 12A, the reference voltage VREF is applied to one electrode of the sensor capacitor Cs via the switch SW1, and the distribution capacitors Cdp1, Cdn1 are connected in parallel via the switch SW3,4. . Transfer pulses DRV_P and DRV_N are applied to the distribution capacitors Cdp1 and Cdn1.

  The chopping filter shown in FIG. 12B is connected to the reference voltage VREF via the switch SW1 on the rear side of the switch SW3 that connects the sensor capacitor Cs to the distribution capacitor Cdp1, and similarly connects the sensor capacitor Cs to the distribution capacitor Cdn1. The switch SW4 is connected to the reference voltage VREF via the switch SW2 on the subsequent stage side. Transfer pulses DRV_P and DRV_N are applied to the distribution capacitors Cdp1 and Cdn1.

  In the chopping filter shown in FIG. 12C, the distribution capacitors Cdp1 and Cdn1 are connected in parallel to the sensor capacitor Cs via the switches SW3 and SW4. A switch SW1 is connected between both ends of the distribution capacitor Cdp1, and a switch SW2 is connected between both ends of the distribution capacitor Cdn1. The transfer pulse DRV_P applied to the distribution capacitor Cdp1 has a low level potential of the reference voltage VREF, and the transfer pulse DRV_N applied to the distribution capacitor Cdn1 has a high level potential of the reference voltage VREF.

  FIG. 13A is a timing chart showing the operation contents of the chopping filter shown in FIGS. In the case of the chopping filter shown in FIG. 12A, the switches SW1 and SW4 are turned on to apply the reference voltage VREF to one electrode of the sensor capacitor Cs and the distribution capacitor Cdn1, and to the other electrode of the distribution capacitor Cdn1. Transfer pulse DRV_N is set to high level. As a result, the first pole-side chopping filter output S_N becomes the reference voltage VREF. Thereafter, the switch SW1 is turned off, and then the transfer pulse DRV_N is set to a low level, whereby the chopping filter output S_N is lowered to a potential corresponding to the sensor capacitance Cs and stabilized. Next, the switch SW4 is turned off to disconnect the first pole side, and then the switch SW3 is turned on to connect the second pole side to the sensor capacitor Cs and the switch SW1 is turned on to turn on one of the distribution capacitors Cdp1. A reference voltage VREF is applied to the electrode. At this time, the transfer pulse DRV_P applied to the other electrode of the distribution capacitor Cdp1 is kept at a low level. At this time, the chopping filter output S_P on the second pole side becomes the reference voltage VREF. Thereafter, after the switch SW1 is turned off, the transfer pulse DRV_P is switched to a high level, whereby the chopping filter output S_P rises to a potential corresponding to the sensor capacitance Cs and is stabilized. The potential difference between the outputs S_N and S_P decreases as Cs increases.

  In the chopping filter shown in FIG. 12B, the switches SW2 and SW4 are turned on to apply the reference voltage VREF to one electrode of the sensor capacitor Cs and the distribution capacitor Cdn1, and to the other electrode of the distribution capacitor Cdn1. Transfer pulse DRV_N is set to high level. As a result, the first pole-side chopping filter output S_N becomes the reference voltage VREF. Thereafter, the switch SW2 is turned off, and then the transfer pulse DRV_N is set to the low level, so that the chopping filter output S_N is lowered to the potential corresponding to the sensor capacitance Cs and stabilized. Next, the switch SW4 is turned off to disconnect the first pole side, and then the switch SW3 is turned on to connect the second pole side to the sensor capacitor Cs and the switch SW1 is turned on to turn on one of the distribution capacitors Cdp1. A reference voltage VREF is applied to the electrode. The transfer pulse DRV_P applied to the other electrode of the distribution capacitor Cdp1 is kept at a low level. At this time, the chopping filter output S_P on the second pole side becomes the reference voltage VREF. Thereafter, after the switch SW1 is turned off, the transfer pulse DRV_P is switched to a high level, whereby the chopping filter output S_P rises to a potential corresponding to the sensor capacitance Cs and is stabilized. The potential difference between the outputs S_N and S_P decreases as Cs increases.

  FIG. 13B is a timing chart showing the operation contents of the chopping filter shown in FIG. In the case of the chopping filter shown in FIG. 12C, the switches SW2 and SW4 are turned on to apply the transfer pulse DRV_N to one electrode of the sensor capacitor Cs and the distribution capacitor Cdn1, and to the other electrode of the distribution capacitor Cdn1. Transfer pulse DRV_N is set to high level (VREF). As a result, the first pole-side chopping filter output S_N becomes the reference voltage VREF. Thereafter, the switch SW2 is turned off, and then the transfer pulse DRV_N is set to the low level, so that the chopping filter output S_N is lowered to the potential corresponding to the sensor capacitance Cs and stabilized. Next, the switch SW4 is turned off to disconnect the first pole side, and then the switch SW3 is turned on to connect the second pole side to the sensor capacitor Cs and the switch SW1 is turned on to turn on one of the distribution capacitors Cdp1. A low level (VREF) transfer pulse DRV_P is applied to the electrode. Thereby, the chopping filter output S_P on the second pole side becomes the reference voltage VREF. Thereafter, after the switch SW1 is turned off, the transfer pulse DRV_P is switched to a high level, whereby the chopping filter output S_P rises to a potential corresponding to the sensor capacitance Cs and is stabilized. The potential difference between the outputs S_N and S_P decreases as Cs increases.

  Next, a configuration example of the mutual capacitance detection type chopping filter shown in FIG. 4B will be specifically described with reference to FIGS. The chopping filters shown in FIGS. 14A to 14D transfer charges using external electrode pulses.

  In the chopping filter of FIG. 14A, a capacitor Cf is formed between two sensor electrodes, an external electrode pulse DRV is applied to one sensor electrode, and the other electrode forming the capacitor Cb between the grounds is the switch SW1. To the fixed voltage Vdd via the switch SW2 and to the ground via the switch SW2. Switches SW3 and SW4 are connected in parallel to the other electrode forming the capacitor Cb between the grounds, one terminal of the distribution capacitor Cdp1 is connected to the switch SW3, and a fixed voltage is applied to the other terminal of the distribution capacitor Cdp1. Is applied. The switch SW4 is connected to one terminal of the distribution capacitor Cdn1, and a fixed voltage (ground) is applied to the other terminal of the distribution capacitor Cdn1.

  The chopping filter in FIG. 14B has the same function as the chopping filter in FIG. 14A, and a fixed voltage Vdd is applied to the subsequent stage of the switch SW3 via the switch SW1, and the subsequent stage of the switch SW4. Connected to ground via switch SW2.

  14C and 14D is an example in which the initialization potential of the distribution capacitor is set to one level of the reference potential VREF. The chopping filter in FIG. 14C is configured to apply the reference potential VREF to the sensor capacitance (Cf, Cb) via the switch SW1. Other configurations are the same as those of the chopping filter of FIG. In the chopping filter of FIG. 14D, switches SW3 and SW4 are connected in parallel to the other electrode forming the capacitor Cb between the grounds, and the reference voltage VREF is applied to the switch SW3 via the switch SW1. A reference voltage VREF is applied to the switch SW4 via the switch SW2. Other configurations are the same as those of the chopping filter of FIG.

  FIG. 15A is a timing chart showing the operation content of the chopping filter shown in FIGS. 14A and 14B. By turning on the switches SW2 and SW4 while the external electrode pulse DRV is at a low level, the chopping filter output S_N on the first pole side is set to the ground potential, the switch SW2 is turned off, and the external electrode pulse DRV is applied. Set to high level. Thereby, the chopping filter output S_N rises to a potential corresponding to the sensor capacitance (Cf, Cb) and is stabilized. Thereafter, the switch SW4 is turned off to disconnect the first pole side, and then the switches SW1 and SW3 are turned on. As a result, the chopping filter output S_P of the second pole becomes the fixed voltage Vdd. If the external electrode pulse DRV is set to the low level after the switch SW1 is turned off, the chopping filter output S_P falls to a potential corresponding to the sensor capacitance (Cf, Cb) and is stabilized. The potential difference between the outputs S_N and S_P is detected by a subsequent charge amplifier. The waveform changes according to the size of the capacitors Cf, Cb, Cdp1, and Cdn1.

  FIG. 15B is a timing chart showing the operation contents of the chopping filter shown in FIGS. 14C and 14D. In the case of the chopping filter shown in FIG. 14C, when the switches SW1 and SW4 are turned on, the first pole-side chopping filter output S_N becomes the reference voltage VREF. When the external electrode pulse DRV is set to the high level after the switch SW1 is turned off, the chopping filter output S_N rises to a potential corresponding to the sensor capacitance (Cf, Cb) and is stabilized. Thereafter, the switch SW4 is turned off to disconnect the first pole side, and then the switch SW1 is turned on again and the switch SW3 is turned on, so that the chopping filter output S_P on the second pole side becomes the reference voltage VREF. When the external electrode pulse DRV is set to the low level after the switch SW1 is turned off, the chopping filter output S_P falls to a potential corresponding to the sensor capacitance (Cf, Cb) and is stabilized. The potential difference between the outputs S_N and S_P is detected by a subsequent charge amplifier. The waveform changes according to the size of the capacitors Cf, Cb, Cdp1, and Cdn1.

  Next, a configuration example of the mutual capacitance detection type chopping filter shown in FIG. 4B will be specifically described with reference to FIGS. The chopping filters shown in FIGS. 16A to 16F transfer charges using external electrode pulses and internal pulses.

  The chopping filters shown in FIGS. 16A and 16B are configured to apply transfer pulses DRV_N and DRV_P instead of fixed voltages to the distribution capacitors Cdn1 and Cdp1 of the chopping filters shown in FIGS. 14A and 14B. Has been. Other configurations are the same as those of the chopping filter shown in FIGS.

  In the chopping filter of FIG. 16C, a capacitor Cf is formed between two sensor electrodes, an external electrode pulse DRV is applied to one sensor electrode, and a capacitor Cb is formed between the other electrode and the ground. Switches SW3 and SW4 are connected in parallel to the other electrode forming the capacitor Cs between the grounds. One terminal of the distribution capacitor Cdp1 is connected to the switch SW3. The transfer pulse DRV_P is applied to the other terminal of the distribution capacitor Cdp1, and the switch SW1 is connected between both ends of the distribution capacitor Cdp1. Further, one terminal of the distribution capacitor Cdn1 is connected to the switch SW4. The transfer pulse DRV_N is applied to the other terminal of the distribution capacitor Cdn1, and the switch SW2 is connected between both ends of the distribution capacitor Cdn1.

  In the chopping filters of FIGS. 16D to 16F, the initialization voltage of the distribution capacitor is set to one level of the reference voltage VREF. The chopping filter shown in FIG. 16 (d) corresponds to the chopping filter configuration shown in FIG. 16 (a), enables connection to the reference voltage VREF instead of the fixed voltage via the switch SW1, and eliminates the switch SW2. ing. The chopping filter shown in FIG. 16 (e) corresponds to the chopping filter configuration of FIG. 16 (b), and applies the reference voltage VREF to each of the first pole and the second pole via the switches SW1 and SW2. It has a configuration that can be done. The chopping filter shown in FIG. 16 (f) corresponds to the chopping filter configuration shown in FIG. 16 (c), and the transfer pulse DRV_P applied to the distribution capacitor Cdp1 has the low level as the reference voltage VREF and is applied to the distribution capacitor Cdn1. The high level of the transfer pulse DRV_N becomes the reference voltage VREF.

  FIG. 17A (a) is a timing chart showing the operation content of the chopping filter shown in FIGS. 16 (a) and 16 (b). When the switches SW2 and SW4 are turned on and the transfer pulse DRV_N is set to the high level, the chopping filter output S_N is set to the ground potential by the switch SW2. After the switch SW2 is turned off, the transfer pulse DRV_N is set to low level and the external drive pulse DRV is set to high level. As a result, the chopping filter output S_N rises to a voltage corresponding to the sensor capacitance (Cf, Cs) and is stabilized. Next, the switch SW4 is turned off to disconnect the first pole side, and then the switches SW1 and SW3 are turned on and the transfer pulse DRV_P is set to the low level, so that the chopping filter output S_P becomes the fixed voltage Vdd. After turning off the switch SW1, the external drive pulse DRV is set to low level and the transfer pulse DRV_P is set to high level, so that the chopping filter output S_P drops to a voltage corresponding to the sensor capacitance (Cf, Cs) and is stable. To do. The potential difference between the outputs S_N and S_P is detected by a subsequent charge amplifier. FIG. 17A shows a waveform when Cf> Cdp1, Cdn1, and the waveform changes depending on the sizes of Cf and Cdp1, Cdn1. When Cf <Cdp1, Cdn1, the initialization voltage (Vdd, GND) of Cdp1, Cdn1 is reversed.

  FIG. 17A (b) is a timing chart showing the operation content of the chopping filter shown in FIG. 16 (c). When the switches SW2 and SW4 are turned on and the transfer pulse DRV_N is set to the high level (Vdd), the chopping filter output S_N becomes Vdd. After the switch SW2 is turned off, the transfer pulse DRV_N is set to low level and the external drive pulse DRV is set to high level. Thereby, the chopping filter output S_N falls to a voltage corresponding to the sensor capacitance (Cf, Cs) and is stabilized. Next, after turning off the switch SW4 and disconnecting the first pole side, turning on the switches SW1 and SW3 and setting the transfer pulse DRV_P to low level (GND), the chopping filter output S_P is set to the ground voltage GND. Become. After turning off the switch SW1, the external drive pulse DRV is set to low level and the transfer pulse DRV_P is set to high level, so that the chopping filter output S_P rises to a voltage corresponding to the sensor capacitance (Cf, Cs) and is stable. To do. The potential difference between the outputs S_N and S_P is detected by a subsequent charge amplifier. The waveform changes depending on the size of Cf and Cdp1, Cdn1 (Cf <Cdp1, Cdn1 in this example).

  FIG. 17B (a) is a timing chart showing the operation content of the chopping filter shown in FIGS. 16 (d) and 16 (e). In the case of the chopping filter shown in FIG. 16D, the switches SW1 and SW4 are turned on and the transfer pulse DRV_N is set to the high level, so that the first pole-side chopping filter output S_N becomes the reference voltage VREF. After turning off the switch SW1, when the transfer pulse DRV_N is set to low level and the external electrode pulse DRV is set to high level, the chopping filter output S_N rises to a potential corresponding to the sensor capacitance (Cf, Cb) and is stabilized. . After that, the switch SW4 is turned off to disconnect the first pole side, and then the switch SW1 is turned on again and the switch SW3 is turned on, so that the transfer pulse DRV_P is set to the low level. The output S_P becomes the reference voltage VREF. After turning off the switch SW1, the external electrode pulse DRV is set to low level and the transfer pulse DRV_P is set to high level, so that the chopping filter output S_P is lowered to a potential corresponding to the sensor capacitance (Cf, Cb) and stabilized. . The potential difference between the outputs S_N and S_P is detected by a subsequent charge amplifier. The waveform shown in the figure is a waveform of Cf> Cdp1, Cdn1, but the waveform changes depending on the size of Cf and Cdp1, Cdn1.

  In the case of the chopping filter shown in FIG. 16E, the switches SW2 and SW4 are turned on, and the transfer pulse DRV_N is set to the high level, so that the first pole-side chopping filter output S_N becomes the reference voltage VREF. After turning off the switch SW2, when the transfer pulse DRV_N is set to low level and the external electrode pulse DRV is set to high level, the chopping filter output S_N rises to a potential corresponding to the sensor capacitance (Cf, Cb) and is stabilized. . After that, the switch SW4 is turned off to disconnect the first pole side, and then the switch SW1 is turned on and the switch SW3 is turned on to set the transfer pulse DRV_P to the low level, thereby chopping the second pole side. The filter output S_P becomes the reference voltage VREF. After turning off the switch SW1, the external electrode pulse DRV is set to low level and the transfer pulse DRV_P is set to high level, so that the chopping filter output S_P is lowered to a potential corresponding to the sensor capacitance (Cf, Cb) and stabilized. . The potential difference between the outputs S_N and S_P is detected by a subsequent charge amplifier.

  FIG. 17B (b) is a timing chart showing the operation content of the chopping filter shown in FIG. 16 (f). When the switches SW2 and SW4 are turned on and the transfer pulse DRV_N is set to the high level (VREF), the chopping filter output S_N on the first pole side becomes the reference voltage VREF. After turning off the switch SW2, when the transfer pulse DRV_N is set to low level and the external electrode pulse DRV is set to high level, the chopping filter output S_N rises to a potential corresponding to the sensor capacitance (Cf, Cb) and is stabilized. . After that, the switch SW4 is turned off to disconnect the first pole side, and then the switch SW1 is turned on and the switch SW3 is turned on to set the transfer pulse DRV_P to the low level (VREF). The chopping filter output S_P on the side becomes the reference voltage VREF. After turning off the switch SW1, the external electrode pulse DRV is set to low level and the transfer pulse DRV_P is set to high level, so that the chopping filter output S_P is lowered to a potential corresponding to the sensor capacitance (Cf, Cb) and stabilized. . The potential difference between the outputs S_N and S_P is detected by a subsequent charge amplifier. The waveform shown in the figure is an example, and the waveform changes depending on the sizes of Cf, Cdp1, and Cdn1.

  Next, with reference to FIGS. 18A and 18B, a configuration example of the chopping filter of the differential mutual capacitance detection method shown in FIG. The chopping filters shown in FIGS. 18A and 18B transfer charges using external electrode pulses.

  In the chopping filter of FIG. 18 (a), a fixed voltage Vdd is applied via a switch SW1 to one sensor electrode that forms a capacitor Cf1 between the reference electrode and a capacitor Cb1 between the reference electrode. , Connected to the ground via the switch SW2. In addition, a fixed voltage Vdd is applied via the switch SW3 to the other sensor electrode that forms the capacitor Cf2 between the reference electrode and the capacitor Cb2 between the reference electrode and the ground via the switch SW4. Connected to. A distribution capacitor Cdp1 is connected to the one sensor electrode via a switch SW5, and a distribution capacitor Cdp2 is connected to the one sensor electrode via a switch SW7. A fixed voltage Vdd is applied to the distribution capacitors Cdp1 and Cdp2. The other sensor electrode is connected to a distribution capacitor Cdn1 via a switch SW6 and to a distribution capacitor Cdn2 via a switch SW8. A ground potential is applied as a fixed voltage to the distribution capacitors Cdn1 and Cdn2. Distribution capacitor Cdp1 and distribution capacitor Cdn2 are connected to the output terminal of chopping filter output S_P via switches SW11 and SW12, respectively. Distribution capacitor Cdp2 and distribution capacitor Cdn1 are connected to chopping filter output S_N via switches SW9 and SW10, respectively. Connected to the output terminal.

  The chopping filter of FIG. 18B has the same function as the chopping filter of FIG. 18A, and the connection positions of the switches SW5 to SW8 that connect the sensor electrode to the distribution capacitor are set more than the switches SW1 to SW4. It is on the sensor electrode side. Other configurations are the same as those of the chopping filter of FIG.

  FIG. 19 is a timing chart showing the operation contents of the chopping filter shown in FIGS. The switches SW2 and SW4 are turned on and the switches SW5 and SW6 are turned on to set the first and second poles to the ground potential. Thereafter, the switches SW2 and SW4 are turned off and the external electrode pulse DRV is set to the high level. As a result, the first pole-side potential S_P2 of the previous-stage distribution capacitor Cdn1 and the second pole-side potential S_P1 of the distribution capacitor Cdp1 rise from the ground potential. The switches SW5 and SW6 are turned off after the first pole-side potential S_P2 and the second pole-side potential S_P1 are stabilized. After turning off the switches SW5 and SW6, the switches SW1 and SW3 are turned on and the switches SW7 and SW8 are turned on to turn on the first pole-side potential S_N1 of the distribution capacitor Cdp2 and the second pole-side potential S_N2 of the distribution capacitor Cdn2 Becomes the fixed potential Vdd. Thereafter, when the external electrode pulse DRV is set to the low level, the first pole-side potential S_N1 and the second pole-side potential S_N2 fall from the fixed potential Vdd. When the switches SW7 and SW8 are turned off and then the switches SW9 to SW12 are turned on, the charges transferred to Cdp1 and Cdn2 and Cdp2 and Cdn1 are combined, and S_N and S_P appear as a differential voltage near VREF. The potential difference between the chopping filter outputs S_N and S_P is detected by the charge amplifier at the subsequent stage. FIG. 19 shows a waveform in the case of Cf1 <Cf2. The potential difference increases as the capacitance difference between Cf1 and Cf2 increases.

  Next, with reference to FIGS. 20A and 20B, another configuration example of the differential mutual capacitance detection type chopping filter shown in FIG. 4C will be described in detail. The chopping filter shown in FIGS. 20A and 20B is an example in which charge transfer is performed using an external electrode pulse, but the initialization voltage of the distribution capacitor is only one level of the reference voltage.

  In the chopping filter of FIG. 20A, both sensor electrodes are connected to a reference voltage VREF via switches SW1 and SW2. Other configurations are the same as those of the chopping filter shown in FIG.

  The chopping filter of FIG. 20B has the same function as the chopping filter of FIG. 20A, and the connection positions of the switches SW5 to SW8 that connect the sensor electrode to the distribution capacitor are set more than the switches SW1 to SW4. It is on the sensor electrode side. Other configurations are the same as those of the chopping filter of FIG.

  FIG. 21 is a timing chart showing the operation contents of the chopping filter shown in FIGS. In the case of the chopping filter shown in FIG. 20A, the switches SW1 and SW2 are turned on to apply the reference voltage VREF to both sensor electrodes, and the switches SW5 and SW6 are turned on, whereby the first pole-side potential S_P2 The second pole side potential S_P1 becomes the reference voltage VREF. After turning off the switches SW1 and SW2, the external electrode pulse DRV is set to the high level. As a result, the first pole-side potential S_P2 of the distribution capacitor Cdn1 and the second pole-side potential S_P1 of the distribution capacitor Cdp1 rise from the reference voltage VREF. The switches SW5 and SW6 are turned off after the first pole-side potential S_P2 and the second pole-side potential S_P1 are stabilized. After the switches SW5 and SW6 are turned off, the switches SW1 and SW2 are turned on and the switches SW7 and SW8 are turned on so that the first pole side potential S_N1 of the distribution capacitor Cdp2 and the second pole side potential S_N2 of the distribution capacitor Cdn2 are the reference The voltage is VREF. Thereafter, when the external electrode pulse DRV is set to the low level, the first pole-side potential S_N1 and the second pole-side potential S_N2 fall from the reference voltage VREF. When the switches SW7 and SW8 are turned off and then the switches SW9 to SW12 are turned on, the charges transferred to Cdp1 and Cdn2 and Cdp2 and Cdn1 are combined, and S_N and S_P appear as a differential voltage near VREF. The potential difference between the chopping filter outputs S_N and S_P is detected by the charge amplifier at the subsequent stage. FIG. 21 shows a waveform in the case of Cf1 <Cf2. The potential difference increases as the capacitance difference between Cf1 and Cf2 increases.

  In the case of the chopping filter shown in FIG. 20B, the switches SW2 and SW4 are turned on to apply the reference voltage VREF to both sensor electrodes, and the switches SW5 and SW6 are turned on, whereby the first pole-side potential S_P2 The second pole side potential S_P1 becomes the reference voltage VREF. Further, when the distribution capacitors Cdn2 and Cdp2 are initialized, the switches SW1 and SW3 are turned on, and the switches SW7 and SW8 are turned on, so that the second pole-side potential S_N1 and the first pole-side potential S_N2 become the reference voltage VREF. Become. Subsequent operations are the same as those of the chopping filter shown in FIG.

  Next, with reference to FIGS. 22A (a), 22 (b), and 22B, another configuration example of the differential type mutual capacitance detection type chopping filter shown in FIG. 4 (c) will be described in detail. The chopping filter shown in FIGS. 22A and 22B is an example in which charge transfer is performed using an external electrode pulse and a transfer pulse which is an internal pulse, and the initialization voltage of the distribution capacitor is two levels of a fixed voltage Vdd and a ground potential.

  The chopping filter shown in FIG. 22A (a) applies an internal pulse DRV_N instead of a fixed voltage to the distribution capacitors Cdn1 and Cdp1 in the chopping filter configuration shown in FIG. 18 (a). Further, an internal pulse DRV_P is applied to the distribution capacitors Cdn2 and Cdp2 instead of a fixed voltage. Other configurations are the same as those of the chopping filter shown in FIG.

  In the chopping filter shown in FIG. 22A (b), in the chopping filter configuration shown in FIG. 22A (a), the connection position of the switches SW5 to SW8 for connecting the sensor electrode to the distribution capacitor is located closer to the sensor electrode than the switches SW1 to SW4. ing.

  In the chopping filter shown in FIG. 22B, switches SW4 and SW2 are connected between the ends of distribution capacitors Cdn1 and Cdp1, and switches SW3 and SW1 are connected between the ends of distribution capacitors Cdn2 and Cdp2. Yes.

  FIG. 23A is a timing chart showing the operation contents of the chopping filter shown in FIGS. 22A and 22B. The switches SW2 and SW4 are turned on, the switches SW5 and SW6 are turned on, and the internal pulse DRV_N applied to the distribution capacitors Cdn1 and Cdp1 is set to the high level. As a result, the first pole-side potential S_P2 and the second pole-side potential S_P1 become the ground potential. Next, when the external electrode pulse DRV is set to a high level and the internal pulse DRV_N is set to a low level after the switches SW2 and SW4 are turned off, the first pole side potential S_P2 and the second pole side potential S_P1 are reduced to a predetermined level. To rise. By turning on the switches SW1 and SW3 and turning on the switches SW7 and SW8, the first pole-side potential S_N1 and the second pole-side potential S_N2 by the distribution capacitors Cdn2 and Cdp2 become the fixed voltage Vdd. After turning off the switches SW1 and SW3, the first electrode side potential S_N1 and the second electrode side potential S_N2 are lowered to a predetermined level by setting the external electrode pulse DRV to the low level and the internal pulse DRV_P to the high level. To do. Then, by turning on the switches SW9 to SW12, a second pole-side output S_P corresponding to the second pole-side potential S_P1 and the second pole-side potential S_N2 is obtained, and the first pole-side potential S_P2 and the second pole-side potential S_P2 A first pole-side output S_N corresponding to one pole-side potential S_N1 is obtained. A potential difference between the first pole-side output S_N and the second pole-side output S_P is detected by a subsequent circuit. FIG. 23A shows a waveform in the case of Cf2> Cf1> Cdp1, Cdn1, and the potential difference increases as the difference between Cf1 and Cf2 increases. When Cf1, Cf2 <Cdp1, Cdn1, the initialization voltages (Vdd, GND) of Cdp1, Cdn1 are reversed.

  FIG. 23B is a timing chart showing the operation content of the chopping filter shown in FIG. 22B. The switches SW2 and SW4 are turned on, the switches SW5 and SW6 are turned on, and the internal pulse DRV_N applied to the distribution capacitors Cdn1 and Cdp1 is set to the high level. As a result, the first pole-side potential S_P1 and the second pole-side potential S_P2 become the fixed voltage Vdd. Next, after turning off the switches SW2 and SW4, the external electrode pulse DRV is set to high level and the internal pulse DRV_N is set to low level, whereby the first pole side potential S_P1 and the second pole side potential S_P2 are predetermined. Descent to level. By turning on the switches SW1 and SW3 and turning on the switches SW7 and SW8, the second pole side potential S_N1 and the first pole side potential S_N2 by the distribution capacitors Cdn2 and Cdp2 become the ground potential. After turning off the switches SW1 and SW3, the external electrode pulse DRV is set to low level and the internal pulse DRV_P is set to high level, so that the second pole side potential S_N1 and the first pole side potential S_N2 rise to predetermined levels. To do. Then, by turning on the switches SW9 to SW12, a second pole-side output S_P corresponding to the second pole-side potential S_P2 and the second pole-side potential S_N1 is obtained, and the first pole-side potential S_P21 and the second pole-side potential S_P21 A first pole-side output S_N corresponding to one pole-side potential S_N12 is obtained. A potential difference between the first pole-side output S_N and the second pole-side output S_P is detected by a subsequent circuit. FIG. 23A shows a waveform in the case of Cf2 <Cf1 <Cdp1, Cdn1, and the potential difference increases as the difference between Cf1 and Cf2 increases.

  Next, another configuration example of the mutual capacitance difference detection type chopping filter shown in FIG. 4C will be specifically described with reference to FIGS. The chopping filters shown in FIGS. 24A and 24B are examples in which charge transfer is performed using external electrode pulses and internal pulses, and the initialization voltage of the distribution capacitor is one level of the reference voltage VREF.

  In the chopping filter of FIG. 24A (a), both sensor electrodes are connected to a reference voltage VREF via switches SW1 and SW2. Other configurations are the same as those of the chopping filter shown in FIG.

  The chopping filter in FIG. 24A (b) has the same function as the chopping filter in FIG. 24A (a), and the connection positions of the switches SW5 to SW8 that connect the sensor electrode to the distribution capacitor are set higher than the switches SW1 to SW4. It is on the sensor electrode side. Other configurations are the same as those of the chopping filter of FIG.

  The chopping filter of FIG. 24B uses the upper limit level of the internal pulse DRV_N applied to the distribution capacitors Cdp1 and Cdn1 as the reference voltage VREF and the lower limit level of the internal pulse DRV_P applied to the distribution capacitors Cdp2 and Cdn2 in the chopping filter of FIG. 22B. The voltage is VREF.

  FIG. 25A is a timing chart showing the operation contents of the chopping filter shown in FIGS. 24A and 24B. In the case of the chopping filter shown in FIG. 24A (a), the switches SW1 and SW2 are turned on, the switches SW5 and SW6 are turned on, and the internal pulse DRV_N applied to the distribution capacitors Cdp1 and Cdn1 is set to the high level. Cdn1 is initialized with the reference voltage VREF. After turning off the switches SW1 and SW2, the internal pulse DRV_N is set to the low level and the external electrode pulse DRV is set to the high level, so that the first pole side potential S_P2 corresponding to the distribution capacitor Cdn1 and the distribution capacitor Cdp1 are determined. The second pole side potential S_P1 rises. Next, when the switches SW1 and SW2 are turned on and the switches SW7 and SW8 are turned on, the distribution capacitors Cdp2 and Cdn2 are initialized with the reference voltage VREF. After turning off the switches SW1 and SW2, the internal pulse DRV_P is set to the high level and the external electrode pulse DRV is set to the low level, so that the second pole side potential S_N2 corresponding to the distribution capacitor Cdn2 and the distribution capacitor Cdp2 are determined. The first pole side potential S_N1 falls. Then, by turning on the switches SW9 to SW12, a second pole-side output S_P corresponding to the second pole-side potential S_P1 and the second pole-side potential S_N2 is obtained, and the first pole-side potential S_P2 and the second pole-side potential S_P2 A first pole-side output S_N corresponding to one pole-side potential S_N1 is obtained. A potential difference between the first pole-side output S_N and the second pole-side output S_P is detected by a subsequent circuit. FIG. 25A shows waveforms when Cf2> Cf1> Cdp1, Cdn1, and the potential difference increases as the difference between Cf1 and Cf2 increases.

  In the case of the chopping filter of FIG. 24A (b), by turning on the switches SW2 and SW4 and turning on the switches SW5 and SW6 and setting the internal pulse DRV_N applied to the distribution capacitors Cdp1 and Cdn1 to high level, the distribution capacitor Cdp1 , Cdn1 is initialized with the reference voltage VREF. When initializing the distribution capacitors Cdp2 and Cdn2, the internal pulse DRV_P is set to the high level and the external electrode pulse DRV is set to the low level while the switches SW1 and SW3 are turned on and the switches SW7 and SW8 are turned on. . As a result, the distribution capacitors Cdp2 and Cdn2 are initialized with the reference voltage VREF.

  FIG. 25B is a timing chart showing the operation content of the chopping filter shown in FIG. 24B. The switches SW2 and SW4 are turned on, the switches SW5 and SW6 are turned on, and the internal pulse DRV_N applied to the distribution capacitors Cdn1 and Cdp1 is set to the high level. As a result, the first pole-side potential S_P2 and the second pole-side potential S_P1 become the reference voltage VREF. Next, after the switches SW2 and SW4 are turned off, the external electrode pulse DRV is set to the high level and the internal pulse DRV_N is set to the low level, so that the first pole side potential S_P2 and the second pole side potential S_P1 are obtained. Rise to a predetermined level. Next, after the switches SW5 and SW6 are turned off, the switches SW1 and SW3 are turned on and the switches SW7 and SW8 are turned on. At the same time, the internal pulse DRV_P is changed to the reference voltage VREF. As a result, the second pole-side potential S_N2 and the first pole-side potential S_N1 due to the distribution capacitors Cdn2 and Cdp2 become the reference voltage VREF. After turning off the switches SW1 and SW3, the external electrode pulse DRV is set to low level and the internal pulse DRV_P is set to high level, whereby the second pole side potential S_N2 and the first pole side potential S_N1 are lowered to a predetermined level. To do. Then, by turning on the switches SW9 to SW12, a second pole-side output S_P corresponding to the second pole-side potential S_P1 and the second pole-side potential S_N2 is obtained, and the first pole-side potential S_P2 and the second pole-side potential S_P2 A first pole-side output S_N corresponding to one pole-side potential S_N1 is obtained. A potential difference between the first pole-side output S_N and the second pole-side output S_P is detected by a subsequent circuit.

  Next, the configuration of the charge amplifier connected to the subsequent stage of the chopping filter 11 will be described. Here, a circuit configuration example of the base charge amount cancellation mechanism 12 and the integrator 13 constituting the charge amplifier will be described.

FIG. 26 is a configuration example of the subsequent circuit (12, 13) corresponding to the single-ended chopping filter 11.
In the post-stage circuit (12, 13), the above-described chopping filter outputs S_N, S_P are taken in via the switches SW9, SW10. However, in the case of a differential signal input, single-end is performed using SW7, SW8 shown in FIG. Need to be converted to A chopping filter 11 is connected to one end of the base charge amount cancellation capacitor Cbc via switches SW9 and SW10. An input signal BCR is applied to the other end of the base charge amount cancellation capacitor Cbc. When BCR becomes High, the charge amount obtained by multiplying the base charge amount cancellation capacitor Cbc by the BCR potential difference (High level of BCR signal−Low level of BCR signal) is subtracted from the distribution capacitor stored in the chopping filter 11.

  The integrator 13 includes an operational amplifier 1 that amplifies the input voltage OP_IN corresponding to the distribution capacitance (base charge amount cancellation) accumulated in the chopping filter 11, and a comparator 2 that compares the operational amplifier output OP_OUT with the reference voltage VREF2. . In the operational amplifier 1, the output terminal of the chopping filter 11 is connected to the inverting input terminal, and the voltage VREF1 is applied to the non-inverting input terminal. The inverting input terminal and the non-inverting input terminal of the operational amplifier 1 can be connected by a switch SW11. Further, the operational amplifier 1 has a feedback capacitor (Cb1) in which integral capacitance is accumulated between an inverting input terminal and an output terminal. A reset switch SW12 is connected in parallel to the feedback capacitor (Cb1). The comparator 2 generates a comparator output CMP_OUT that changes from a low level to a high level when the + input OP_OUT exceeds the −input VREF2.

  FIG. 27 is a configuration example of the post-stage circuit (12, 13) corresponding to the differential chopping filter 11. The post-stage circuit (12, 13) is connected to the distribution capacitor Cdp of the second pole of the chopping filter 11 via the switch SW13, and is connected to the distribution capacitor Cdn of the first pole of the chopping filter 11 via the switch SW14. The The switch SW13 is connected to one end of the base charge amount cancellation capacitor Cbc1 of one pole, and the switch SW14 is connected to one end of the base charge amount cancellation capacitor Cbc2 of the other pole. A node S_IP in which the transfer charge on one pole side appears and a node S_IN in which the transfer charge on the other pole side appears are connected to the crosspoint switch 5 in parallel. The voltage VREF can be applied to the nodes S_IN and S_IP via the switches SW15 and SW16.

  In the integrator 13, the plus (+) output and the minus (−) output of the fully differential operational amplifier 1 are input to the comparator 2 via the crosspoint switch 6. A crosspoint switch 7 is provided in the feedback path of the fully-differential operational amplifier 1, and a feedback capacitor Cb11 and a switch SW17 are connected to the feedback path from the minus (−) output terminal to the plus (+) input terminal. A feedback capacitor Cb12 and a switch SW18 are connected to the feedback path from the (+) output terminal to the minus (−) input terminal. In addition, it is possible to generate charges corresponding to the magnitudes of Cbc1, Cbc2, Cb21, and Cb22 based on the input signals BCR and BCF of the base charge amount cancellation capacitor and the feedback signals DSR and DSF of the delta sigma modulator.

(First embodiment)
FIG. 28 is a specific circuit configuration diagram of the capacitance detection apparatus 10 according to the first embodiment. In the figure, the input side (left side in FIG. 28) of the base charge amount cancellation mechanism 12 including Cbc is a chopping filter unit, and the output side (right side in FIG. 28) is an integrator 13. The chopping filter section has a chopping filter configuration shown in FIG.

FIG. 29 is a timing chart of the capacity detection device according to the present embodiment.
As shown in the figure, SW1 is turned on, and SW6, SW11, and SW12 are turned on at the same timing. By turning on SW1, the capacity (Cs, Cf) of the input section is charged to Vdd. By turning on SW6, SW11, and SW12 at the same timing, Cdn is initialized. Similarly, the minus (−) input OP_IN of the operational amplifier 12A is initialized to Vr1, and Cb1 is also initialized. Vr1 is set in consideration of the input / output voltage balance of the operational amplifier. At this time, the switch SW8 is in the ON state and is maintained until the charge is transferred to the integrator 13. The input signal BCR of the base charge amount cancellation capacitor Cbc and the feedback signal (input of Cb2) DSR of the delta sigma modulator are both set to Low, and the charges of Cbc and Cb2 are initialized.

  Next, SW1, SW6, SW11, and SW12 are turned off and SW4 is turned on. Thereby, the charge amounts of the sensor capacitor Cs and the finger capacitor Cf are distributed to the distribution capacitor Cdn.

  Next, in order to separate the distribution capacitor Cdn from the capacitors (Cs, Cf) of the input unit, the switch SW4 is turned OFF, and the half sequence of charge distribution by bipolar drive is completed.

  Subsequently, when the switch SW2 is turned on, the sensor capacitance Cs and the finger capacitance Cf are connected to GND, and after the switch SW5 is turned on and Cdp is initialized, the switches SW2 and SW5 are turned off. Similarly, the switch SW3 is turned ON, and the charge amount of the capacitance (Cs, Cf) of the input unit is distributed to the distribution capacitor Cdp.

  Next, the switch SW3 is turned off to separate the distribution capacitor Cdp from the input capacitances (Cs, Cf), and one charge distribution sequence by bipolar driving is completed.

となる。よって、CdpとCdnを同じ大きさにしておくと、CdpとCdnの両端の電位差は同じになり、その電位差VdはQ=CVより

となる。 At this time, Cdp and Cdn are set to the same magnitude, and when the magnitude is Cd, the amount of charge Qd distributed to each is

It becomes. Therefore, if Cdp and Cdn are made the same size, the potential difference between both ends of Cdp and Cdn will be the same, and the potential difference Vd will be less than Q = CV

It becomes.

  Next, the switch SW8 is turned off and the switch SW7 is turned on, so that both Cdp and Cdn are connected with Vdd as a reference. At this time, the reference potential of Cdp and Cdn need not be limited to Vdd. For example, if the GND reference is used, the connection on the Cdp side may be switched with the switch SW.

  Next, the switches SW7 and SW8 are left as they are, and the switches SW9 and SW10 are turned on to connect to the negative (−) input OP_IN of the operational amplifier 12A. At this time, when the external noise that has entered the sensor unit at the time of distribution has a frequency sufficiently longer than the period of bipolar driving, it is distributed to Cdp and Cdn as charge amounts in opposite directions, and thus is greatly suppressed.

の電荷量が分配容量Cdp、Cdnの電荷量から差し引かれる。オペアンプ１２Ａのマイナス（−）入力OP_INはVr1と定常的には等しくなることから、（３）式が導出できる。（１）式から判るように、指の有無（Cfの有無）で検出される電荷量Qdが異なり、指が有る場合の方がQdが大きくなる。Vdd基準に分配容量が接続されるので指がない場合に比べて指が有る場合はこの段階においてオペアンプ１２Ａのマイナス入力（−）OP_INの電位はよりGNDに近くなる。よって、図２９のタイミングチャートに示すように、オペアンプ１２Ａの出力OP_OUTはオペアンプ１２ＡのフィードバックコンデンサCb1を介してVr1とOP_INが等しくなるように上昇する。このとき、ベース電荷量キャンセル機構がない場合は、センサ容量Csの無駄な電荷量もCb1に取り込むため出力電圧が飽和しやすくなりダイナミックレンジがとれなくなる。 Next, BCR input to Cbc goes high to cancel the base charge amount of the sensor unit.

Is subtracted from the charge amount of the distribution capacitors Cdp and Cdn. Since the negative (−) input OP_IN of the operational amplifier 12A is constantly equal to Vr1, equation (3) can be derived. As can be seen from the equation (1), the amount of charge Qd detected differs depending on the presence / absence of the finger (presence / absence of Cf), and the Qd is greater when the finger is present. Since the distribution capacitor is connected to the Vdd reference, the potential of the negative input (−) OP_IN of the operational amplifier 12A is closer to GND at this stage when the finger is present than when there is no finger. Therefore, as shown in the timing chart of FIG. 29, the output OP_OUT of the operational amplifier 12A rises through the feedback capacitor Cb1 of the operational amplifier 12A so that Vr1 and OP_IN become equal. At this time, if there is no base charge amount canceling mechanism, a wasteful charge amount of the sensor capacitor Cs is also taken into Cb1, so that the output voltage is easily saturated and the dynamic range cannot be obtained.

  After the operational amplifier 12A takes in the distributed charge amount corresponding to the potential difference between the distributed voltages Vd and Vr1 to Cb1, the switches SW9 and SW10 are turned OFF, the integrator side and the chopping filter side are disconnected, and then the switches SW7 and SW8 are switched Returning to the distribution state, one integration sequence is completed.

  By repeating this integration sequence, the output of the operational amplifier 12A can be secured to a required level, but an AD converter function can be further added. Specifically, the output of the operational amplifier 12A is connected to the comparator 12B, the output voltage of the operational amplifier 12A is compared with the reference voltage Vr2, and the output CMP_OUT of the comparator 12B is extracted as a binary bit stream while performing an integration operation.

  As shown in the timing chart of FIG. 29, when the output OP_OUT of the operational amplifier 12A exceeds Vr2 in the second integration sequence, DSR becomes High in the integration sequence, and feedback is performed as the amount of charge via Cb2, thereby delta-sigma modulation. I do. This configuration is the first-order delta-sigma modulation itself, and an AD converter that can be easily converted into a multi-bit digital signal can be realized by subsequently configuring the digital filter 14 with a logic circuit. Basically, the digital filter 14 has a low-pass filter function. However, by optimizing the number of captures (cut-off characteristics), it is possible to further increase the external noise resistance. Normally, it is desirable to take a bit stream with an integration number of 200 or more and output a multi-bit digital output with a digital filter. The waveform of the node OP_OUT during these operations is shown in FIG.

  As the distribution capacitances Cdp and Cdn are larger than the capacitances (Cs and Cf) of the input section, the charge capture efficiency increases. However, as shown in FIG. , C2... Cn can be connected in parallel as necessary, and it is desirable that the capacitance value be variable according to the size of the sensor capacitance Cs. Furthermore, it is efficient to weight these capacitors C1, C2,... Cn twice. In addition, it is desirable to adopt a similar configuration in which Cbc for canceling the base charge amount can be varied according to the sensor capacitance. The size (ratio) of the capacitances of Cb1 and Cb2 determines the input / output gain, and it is desirable to adopt the same configuration.

  Further, at the time of distribution, the fixed nodes of the distribution capacitors Cdp and Cdn are connected to Vdd and GND, but the present invention is not limited to this as long as it is a fixed potential. For example, the fixed node of Cdp can be set to GND. Further, the charge transfer to the integrator side of the distribution capacitor may be sequentially transferred without parallel connection of the distribution capacitors. The detection sequence described above is an example, and the same function may be realized using other sequences.

(Second embodiment)
In the second embodiment, the electric charge driven and distributed in bipolar is processed in the differential form as it is, and the charge transfer sequence from the distribution capacitor to the integrator and the capacitance (Cs, Cf) of the input unit to the distribution capacitor are performed. The charge distribution is performed in parallel to realize the pipeline processing of the two processes.

  FIG. 31 is a circuit diagram of the capacitance detecting apparatus according to the second embodiment. The chopping filter has basically the same configuration as the chopping filter having the pipeline configuration shown in FIG. The base charge amount canceling mechanism 12 and the integrator 13 are the same as those shown in FIG. In the capacity detection device of the second embodiment, the distribution capacity Cdp1 and the distribution capacity Cdp2 are assigned in parallel to one pole, and the distribution capacity Cdn1 and the distribution capacity Cdn2 are assigned in parallel to the other pole. The charge distribution and charge transfer are alternately performed by the distribution capacitor Cdp1 and the distribution capacitor Cdp2 provided in parallel with one pole, and the charge distribution and charge are similarly provided by the distribution capacitor Cdn1 and the distribution capacitor Cdn2 provided in parallel with the other pole. Switches SW3 to SW14 for switching connections are provided so that transfer can be performed alternately. A node S_IP in which the transfer charge on one pole side appears and a node S_IN in which the transfer charge on the other pole side appears are connected to the crosspoint switch 15 in parallel. The voltage Vr can be applied to the nodes S_IN and S_IP via the switches SW15 and SW16. In the integrator 13, the plus (+) output and the minus (−) output of the fully differential operational amplifier 18 are input to the comparator 19 via the crosspoint switch 16. A crosspoint switch 17 is provided in the feedback path of the fully-differential operational amplifier 18, and a feedback capacitor Cb11 and a switch SW17 are connected to the feedback path from the minus (−) output terminal to the plus (+) input terminal, and the plus (−) A feedback capacitor Cb12 and a switch SW18 are connected to the feedback path from the (+) output terminal to the minus (−) input terminal. In addition, it is possible to generate charges corresponding to the magnitudes of Cbc1, Cbc2, Cb21, and Cb22 based on the input signals BCR and BCF of the base charge amount cancellation capacitor and the feedback signals DSR and DSF of the delta sigma modulator.

  FIG. 32 is a diagram illustrating a configuration example of the cross point switches 15, 16, and 17. The cross point switches 15, 16, and 17 switch between parallel connection and cross connection by signals of φ1 and φ2. This is for suppressing the flicker noise of the fully differential operational amplifier 18 and has a chopper stabilization function.

Next, the operation of the second embodiment configured as described above will be described.
FIG. 33 is a timing chart corresponding to one bipolar drive / distribution sequence of the capacitance detection apparatus according to the second embodiment, and FIG. 34 is an entire sequence corresponding to a plurality of integration sequences, which is a fully differential amplifier. The output waveform of the output is shown correspondingly.

  First, by turning on the switch SW1, the sensor capacitance Cs and the finger capacitance Cf are charged to Vdd. By turning on the switches SW8, SW15, SW16, SW17, and SW18 at the same timing, Cdn1 is initialized. Similarly, the nodes S_IP and S_IN are initialized to Vr, and Cb11 and Cb12 are also initialized. Also, the base charge amount cancellation capacitance input signals BCR and BCF and the delta-sigma modulator feedback signals DSR and DSF are set in the same manner as in the first embodiment, and the charges of Cbc1, Cbc2, Cb21, and Cb22 are initialized. Further, the cross point switches 15, 16, and 17 are switched in the same manner as the switches SW11, 12, 13, and 14 for each integration sequence.

  Next, the switch SW1 is turned off and the switch SW4 is turned on, so that the charge amount of the capacitance (Cs, Cf) of the input unit is distributed to the distribution capacitor Cdn1. In addition, since delta sigma modulation is performed by a fully differential operation, DSR and DSF are inverted at this point to initialize the output potential of the fully differential operational amplifier 18 and set as a threshold for delta sigma modulation. This is done only for the first integration sequence. At this time, the potential of the node S_N of the distribution capacitor Cdn1 rises from GND due to the coupling with the sensor capacitor as shown in FIG. If Vr is half the voltage of Vdd (usually Vr is set near the center of the operating range of the detection circuit) and the capacitance value of Cdn1 is smaller than the capacitance of the input section (Cs + Cf), it will exceed Vr Stabilizes as a potential.

  Next, in order to disconnect the distribution capacitor Cdn1 from the capacitors (Cs, Cf) of the input unit, the switch SW4 is turned OFF, and the half sequence of charge distribution by bipolar drive is completed.

  Subsequently, when the switch SW2 is turned ON, the capacitance (Cs + Cf) of the input unit is connected to GND, and the switch SW7 is turned ON to initialize Cdp1. At this time, the switches SW15 and SW16 are turned ON, DSR and DSF are inverted, and the charges of Cb21 and Cb22 are initialized.

  Next, the switch SW3 is turned on as before, and the charge amount of the capacitance (Cs + Cf) of the input unit is distributed to the distribution capacitor Cdp1. At this time, the node S_P of the distribution capacitor Cdp1 drops from Vdd in the GND direction as shown in FIG. 33, contrary to the case of the node S_N.

  Next, the switch SW4 is turned off to separate the distribution capacitor Cdp1 from the capacitors (Cs, Cf) of the input unit, and one charge distribution sequence by bipolar driving is completed. As shown in FIG. 33, the node S_P changes.

  The amount of charge distributed by the above sequence and the potential difference between both ends of the distribution capacitor are the same as in the equations (1) and (2). In the first embodiment, the distribution capacitors are connected in parallel here, but in the present embodiment, the parallel connection is not performed, and the process proceeds to the charge transfer sequence from the distribution capacitors to the integrator 13 as it is.

  Thereafter, the charge transfer sequence from the distribution capacitors Cdp1, Cdn1 to the integrator 13 and the charge distribution from the input capacitances (Cs, Cf) to the distribution capacitors Cdp2, Cdn2 are performed in parallel. The charge distribution from the input capacitance (Cs, Cf) to the distribution capacitors Cdp2 and Cdn2 is the same sequence as the distribution capacitors Cdp1 and Cdn1, so the explanation is omitted, but the chopping filter is selected by selectively turning on / off the switches SW11 to SW14. By switching the connection between this part and the integrator 13, pipeline processing is possible, and the restriction on the operation speed of the fully differential operational amplifier 18 can be relaxed. Also, it is desirable that Cdp1, 2, Cdn1, 2 all have the same capacitance value.

  Subsequently, in the charge transfer sequence from the distribution capacitor to the integrator 13, the switches SW11 and SW12 are turned on, and φ1 in the crosspoint switches 15, 16, and 17 becomes High, so that the crosspoint switches 15, 16, and 17 are turned on. Parallel connection is established, and charges are transferred to Cb11 and Cb12. In the first embodiment, the operational amplifier 12A performs charge transfer based on the potential of Vr1, but in this embodiment, charge transfer is performed from Cdp1 and Cdn1 due to the potential difference between Cdp1 and Cdn1 via nodes S_IP and S_IN. The base charge amount cancellation and delta-sigma modulation feedback at this time are based on the same principle as in the first embodiment, and the description is omitted because only the differential configuration is different. The waveforms of the nodes OP_OUTN and OP_OUTP during these operations are shown in FIG.

  It is desirable that Cbc1 and Cbc2 have the same capacitance value, and it is also desirable that the pairs of Cb11 and Cb12 and Cb21 and Cb22 have the same capacitance value.

  In the present embodiment, similar to the first embodiment, the distributed capacitances Cdp1, Cdp2, Cdn1, and Cdn2 and Cbc1, Cbc2, and Cb11, Cb12, Cb21, and Cb22 that perform base charge amount cancellation are configured to have variable capacitance values. It is desirable.

  Further, at the time of distribution, the fixed nodes of the distribution capacitors Cdp1, Cdp2, Cdn1, and Cdn2 are connected to Vdd and GND, but the present invention is not limited to this as long as it is a fixed potential. For example, the fixed nodes of Cdp1 and Cdp2 can be set to GND.

  The above detection sequence is an example, and the same function may be realized using other sequences.

  Using the capacity detection device according to the present embodiment as described above, signal quality under a noise environment was evaluated. FIG. 35 shows the evaluation results. In the evaluation, 10Vp-p noise was applied to the sensor part via the finger capacitance Cf, and the ratio between the output change component S and the output noise component N due to the presence or absence of a finger was measured by changing the noise frequency. is there. It has been confirmed that it is about 20dB better than the conventional technology.

  In the second embodiment, the charge transfer sequence may not be pipelined. FIG. 36 is a modification of the second embodiment, and is a circuit diagram showing a configuration in which the charge transfer sequence is not pipelined. That is, only the distribution capacitor (Cdp1) is provided on one pole, and only the distribution capacitor (Cdn1) is provided on the other pole. A node S_IP in which the transfer charge on one pole side appears and a node S_IN in which the transfer charge on the other pole side appears are connected to the crosspoint switch 15 in parallel. This configuration can be applied when high-speed operation is not required, and the distribution capacity can be reduced and the circuit scale can be reduced as compared with the second embodiment. The specific operation is the same as that of the second embodiment except for the pipeline processing.

(Third embodiment)
In the first embodiment described above, the touch sensor module is intended for detection of self-capacitance (capacitance between sensor electrode and GND) as shown in FIGS. 4 (a) and 4 (b). As shown, a mutual capacitance defined as a difference in capacitance formed between the reference electrode and the two sensor electrodes may be detected. Since differential detection is used, there are merits such as high resistance to external common mode noise and parasitic capacitance (defined as Cs) between the sensor electrode and GND.

  FIG. 37 is a circuit configuration diagram of the capacitance detecting apparatus according to the third embodiment. The basic configuration is the same as that of the second embodiment. In the third embodiment, capacitors Cf1 and Cf2 are formed between the drive electrode (DRV signal) and the differential input portion of the detection circuit.

  FIG. 38 is a timing chart of one integration sequence of the capacitance detecting device according to the third embodiment, and FIG. 39 is an entire sequence corresponding to a plurality of integration sequences, corresponding to output waveforms of the fully differential amplifier output. Let me show you.

  First, the DRV signal is fixed at a low level and the switches SW1 and SW2 are turned on to set the capacitance (Cs, Cf) of the input section to Vr. By turning on the switches SW11, SW12, SW13, and SW14 at the same timing, the nodes S_IP and S_IN are initialized to Vr, and Cb11 and Cb12 are also initialized. Usually, Vr is set near the center in the operating range of the detection circuit. The base charge amount cancellation capacitance input signals BCR and BCF and the delta-sigma modulator feedback signals DSR and DSF are also set in the same manner as in the second embodiment to initialize the charges of Cbc1, Cbc2, Cb21, and Cb22. Similarly to the second embodiment, the cross-point switches 15, 16, and 17 shown in FIG. 32 are arranged in the input / output and feedback path of the fully differential operational amplifier 18, and are connected in parallel by signals φ1 and φ2. Switch the cross connection.

  Next, the switches SW3 and SW4 are turned on, the distribution capacitors Cdp1 and Cdp2 are connected to the capacitors (Cs and Cf) of the input unit, and are initialized in the same manner as described above.

  Next, the switches SW1 and SW2 are turned OFF, and the DRV signal is raised. At this time, the capacitances Cf1 and Cf2 formed between the DRV electrode and the differential input part of the detection circuit have different capacitance values depending on the proximity of an object such as a finger, so the capacitance values of Cdp1 and Cdp2 are large. If they are the same, as shown in FIG. 38, the potentials of the nodes S_P1 and S_P2 vary while rising. FIG. 38 shows a case where Cf1> Cf2.

  Next, the switches SW3 and SW4 are turned OFF, the switches SW1 and SW2 are turned ON again, the input capacity (Cs, Cf) is initialized, the switches SW5 and SW6 are turned ON, and the Cdn1 and Cdn2 are input capacity ( Cs, Cf) and initialized as described above.

  Next, the switches SW1 and SW2 are turned OFF, the DRV signal falls, and the potentials of the nodes S_N1 and SN_2 are different while falling.

  Next, the switches SW5 and SW6 are turned off, and the switches SW7 to SW10 are turned on. At this time, if it is assumed that there is no connection with the integrator 13 at the subsequent stage, if the distribution capacitors Cdp1, Cdp2, Cdn1, and Cdp2 have the same capacitance value, the potential difference between the nodes S_P1 and S_P2 and the potential difference between the nodes S_N2 and S_N1 are the same. When S_P1 and S_N2 and S_P2 and S_N1 are connected, a potential difference centered on Vr is obtained, and the integrator 13 in the subsequent stage detects this potential difference as a charge amount. The initialization of the threshold setting for delta-sigma modulation up to this point is the same as in the second embodiment. Subsequent integration processing including base charge amount cancellation is the same as in the second embodiment.

  Also in this embodiment, as in the above-described embodiment, Cbc1 and Cbc2 are preferably set to the same capacitance value, and the pairs of Cb11, Cb12 and Cb21, Cb22 are preferably set to the same capacitance value. Further, it is desirable that the distribution capacitors Cdp1, Cdp2, Cdn1, and Cdp2 and Cbc1, Cbc2, and Cb11, Cb12, Cb21, and Cb22 that perform base charge amount cancellation have variable capacitance values.

  Further, at the time of distribution, the fixed nodes of the distribution capacitors Cdp1, Cdp2, Cdn1, and Cdn2 are connected to Vdd and GND, but the present invention is not limited to this as long as it is a fixed potential. For example, the fixed node of Cdp1, 2 can be set to GND. The detection sequence is an example, and the same function may be realized using other sequences.

  Note that the second embodiment and the third embodiment may be combined for the chopping filter unit to constitute a capacitance detection circuit that can handle both self-capacitance detection and mutual capacitance detection as shown in FIG. Switch between differential input and single-ended input by switching the switch. Except for the operation of switching between the differential input and the single-ended input, the operation is the same as in the second and third embodiments.

(Fourth embodiment)
As shown in FIG. 41, it is possible to form a pipeline with the chopping filter configuration of FIG. 10D and use a fully differential charge amplifier (base charge amount cancellation mechanism and integrator) shown in FIG. good. FIG. 42 shows the entire sequence of the capacitance detection circuit shown in FIG.

  The capacitance detection device shown in FIG. 41 converts the capacitance value into a charge amount by the chopping filter 11 connected to the capacitance (Cf, Cb) of the input unit and the base charge amount cancellation mechanism 12 at the subsequent stage, and the amount of charge in the integrator. To voltage. The integrator has a built-in comparator 2 and sequentially sends the obtained voltage to the subsequent digital filter 14 as a binary bit stream. The digital filter 14 converts the binary bit stream into a multi-bit digital signal by filtering. The chopping filter 11 has an action of converting low-frequency external noise into a high frequency and an action of suppressing the noise amplitude, and the base charge amount cancellation mechanism 12 cancels the offset amount of the capacitor Cf that is not originally detected. The integrator 13 integrates the obtained electric signal (charge amount), amplifies the charge amount corresponding to the finger capacitance Cf, and functions as a delta sigma modulator function to take part of the function of the AD converter. The digital filter 14 outputs a digital value corresponding to the detected capacity from the binary bit stream and contributes to suppression of external noise by a filter function (LPF).

  In the chopping filter 11, the switches SW4 and SW8 are turned on, and the chopping filter output S_N becomes the fixed voltage Vdd due to the high level of the transfer pulse DRV_N (see FIG. 11B). After that, the switch SW8 is turned off, the sensor capacitor Cs and the distribution capacitor Cdn1 are connected in parallel, and the transfer pulse DRV_N is set to the low level, so that the chopping filter output S_N decreases to a voltage corresponding to the charge amount of the sensor capacitor Cs. Stabilize. Next, the switch SW4 is turned off to disconnect the first pole side, and then the switches SW3 and SW7 are turned on to connect the sensor capacitor Cs and the distribution capacitor Cdp1. At this time, a high level of DRV_P is applied to the distribution capacitor Cdp1. By setting the transfer pulse DRV_P to the low level, the chopping filter output S_P becomes the ground potential while the transfer pulse DRV_P is at the low level. When the switch SW7 is turned off and the transfer pulse DRV_P is set to the high level, the sensor capacitor Cs and the distribution capacitor Cdp1 are connected in parallel, and the chopping filter output S_P rises to a voltage corresponding to the charge amount of the sensor capacitor Cs and is stable. To do. Then, the switches SW11 and SW13 are turned on to transfer the potential difference between the chopping filter outputs S_N and S_P to the integrator 13 via the base charge amount cancellation mechanism.

  On the other hand, in the base charge amount cancellation mechanism 12 and the integrator 13, the input signals BCR and BCF of the base charge amount cancellation capacitor and the feedback signals DSR and DSF of the delta sigma modulator are set in the same manner as in the first embodiment, and Cbc1 , Cbc2, Cb21, and Cb22 are set. Also, the input signals BCR and BCF of the base charge amount cancellation capacitors Cbc1 and Cbc2 and the feedback signal (input of Cb21 and Cb22) DSR of the delta sigma modulator are set as shown in the timing chart, and the charge of Cbc1, Cbc2 and Cb21, Cb22 Perform initialization. Further, cross-point switches 5, 6, and 7 are arranged on the input / output and feedback path of the fully differential operational amplifier 1, and the parallel connection and the cross connection are switched by signals of φ1 and φ2. This is for suppressing the flicker noise of the fully differential operational amplifier 1 and has a chopper stabilization function. The cross point switches 5, 6, and 7 are switched for each integration sequence. In order to initialize delta-sigma modulation, DSR and DSF are inverted so far and the initial value of the integrator is set. At the same time as the charge of the chopping filter is transferred to the integrator, BCR and BCF are inverted and base charge cancellation is performed. This is the same principle as the initialization of the integrator because the amount of charge corresponding to the amount of offset charge transferred to the integrator is subtracted during each integration operation. When the integration operation for one time is completed, operations other than the initialization of Cb21 and Cb22 are continuously repeated, and the charge transfer to the integrator is repeated. FIG. 42 shows an example in which OP_OUTN becomes smaller than OP_OUTP in the second integration operation. At this time, the output of the comparator 2 becomes Hi, so that the amount of charge transferred from the sensor is the charge set by Cb21 and Cb22. This pulse is sent to the digital filter. Each time the output of the comparator 2 becomes Hi, DSR and DSF are inverted, and the charge amounts corresponding to Cb21 and Cb22 are subtracted in the same manner as when the integrator is initialized. Ultimately, the digital value is determined by how many times the output of the comparator 2 becomes Hi while repeating a predetermined number of integrations, and AD conversion is performed by filtering the bit stream with a digital filter.

  The present invention is applicable to a capacitance detection device that detects a change in capacitance in a touch sensor module or the like.

DESCRIPTION OF SYMBOLS 1,18 Fully differential operational amplifier 2,19 Comparator 11 Chopping filter 12 Base charge amount cancellation mechanism 13 Integrator 12A Operational amplifier 12B Comparator 14 Digital filter 15, 16, 17 Crosspoint switch 101 Sensor part 102 Capacity | capacitance detection circuit 103 Control part

Claims (14)

  Switching means for connecting to the detected capacitor, one or more distribution capacitors to which the charge charged in the detected capacitor is distributed, and a plurality of voltage levels for initializing and distributing the distribution capacitor And a charge amplifier for taking out the charge distributed to the distribution capacitor as a charge amount.   The capacitance detection device according to claim 1, wherein charges are distributed as a charge amount having a reverse polarity in a complementary manner from the detected capacitance to the plurality of distribution capacitors.   3. The capacitance detection device according to claim 1, wherein the detected capacitance is a coupling capacitance connected to a pulse supply source.   4. The capacitance detection device according to claim 1, wherein the charge amplifier is single-ended or fully differential.   2. The pipeline configuration according to claim 1, wherein the plurality of distribution capacitors are divided into a plurality of groups, and the initialization and charge distribution timing and the charge amount extraction timing are different between the groups and operate in parallel. The capacity detection device according to claim 4.   6. The capacity detection device according to claim 1, wherein the distribution capacity can be varied according to the size of the detected capacity.   The variable capacity | capacitance for subtracting a reactive charge from the said distribution capacity | capacitance, and the pulse drive means for carrying out the pulse drive of the said variable capacity | capacitance were comprised, The claim 1 characterized by the above-mentioned. Capacity detection device.   A first switch for switching a charging operation by switching the voltage level for charging the detected capacitor to a plurality of voltage levels at a predetermined cycle and disconnecting the supply of the voltage level to the detected capacitor; A plurality of distribution capacitors to which the charge charged in the detection capacitor is distributed; a second switch for initializing the plurality of distribution capacitors at a plurality of voltage levels in accordance with a charging operation of the detection capacitor; Connection between the detected capacitor and each of the distribution capacitors together with the first and second switches so that the charge is distributed as a charge amount of opposite polarity in a complementary manner from the detection capacitor to the plurality of distribution capacitors. And a charge amplifier for converting the charge charged in the distribution capacitor into a voltage.   The output of the comparator connected to the subsequent stage of the charge amplifier is used as a logic output, and the logic output is fed back to the input of the charge amplifier as a charge amount via a feedback capacitor to form a delta-sigma modulator. 9. The capacitance detection device according to claim 8, wherein the capacitance value is converted into a digital value by a connected digital filter.   9. The capacitance detection according to claim 8, further comprising: a mechanism capable of changing a size of the distribution capacitor according to a fixed charge amount that is included in the detected capacitance and is ineffective for proximity detection of a detection target. apparatus.   11. The capacitor according to claim 9, further comprising a mechanism capable of varying a feedback capacitor of the charge amplifier and a feedback capacitor of the delta sigma modulator according to a magnitude of a difference in detection capacitance due to proximity of a detection target. Detection device.   12. The capacitance detection device according to claim 8, further comprising an input unit capable of switching between a differential input and a single-ended input of the detected capacitance. A step of switching the charging operation by switching the voltage level for charging the detected capacitor to a plurality of voltage levels in a predetermined cycle and disconnecting the supply of the voltage level to the detected capacitor;
Initializing a plurality of distribution capacitors to which charges charged in the detected capacitors are distributed at a plurality of voltage levels in accordance with a charging operation of the detected capacitors;
A step of distributing charge from the detected capacitor as a charge amount having a reverse polarity in a complementary manner to the plurality of distribution capacitors;
Converting the charge charged in the distribution capacitor into a voltage;
A capacity detection method comprising: Charging the detected capacitance at a first voltage level;
Distributing the charge charged in the detected capacitor to a first distribution capacitor initialized at a predetermined voltage level;
Charging the detected capacitance at a second voltage level;
The charge charged in the detected capacitor is complementarily charged to a second distribution capacitor that is equal in capacity to the first distribution capacitor and initialized at a voltage level different from that of the first distribution capacitor. Distributing as a quantity;
Converting charges charged in the first distribution capacitor and the second distribution capacitor into a voltage;
A capacity detection method comprising:

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