JP2011209528A - Liquid crystal device, method for driving the same, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal device which is capable of improving display quality by suppressing occurrence of display defects such as a flicker, a method for driving the liquid crystal device, and an electronic apparatus.SOLUTION: The liquid crystal device includes a first alignment film 13 provided on the side of a liquid crystal layer of an element substrate 10 and a second alignment film 23 provided on the side of the liquid crystal layer of a counter substrate 20. A first pre-tilt angle of the first alignment film 13 is set lower than a second pre-tilt angle of the second alignment film 23. A counter electrode potential which is set so as to reduce flickers caused by a parasitic capacitance of a switching element 40, is applied to a counter electrode 22. When a higher voltage is defined as positive and a lower voltage is defined as negative with the counter electrode potential as a reference, a positive voltage and a negative voltage are alternately applied to the pixel electrode 12, and a length of a first period for which the positive voltage is applied is set shorter than that of a second period for which the negative voltage is applied.

Description

  The present invention relates to a liquid crystal device, a driving method of the liquid crystal device, and an electronic apparatus.

  Conventionally, there is an active matrix type liquid crystal device in which a pixel electrode is driven by a thin film transistor (hereinafter referred to as “TFT”). In this liquid crystal device, in order to suppress display defects such as flicker and burn-in of a display image, for example, the polarity of the driving voltage applied to each pixel electrode is set for each scanning line or data line, or for a frame in an image signal. Inversion driving (AC driving) for inversion every time is employed.

  This is intended to eliminate flicker and the like by applying a DC voltage component to the liquid crystal layer by inversion driving and suppressing the bias of charge between the substrates. However, simply performing inversion driving does not completely solve the application of the DC voltage component, and display defects still occur.

In other words, even when inversion driving is performed, application of a DC voltage component to the liquid crystal layer and bias of electric charges occur, and it is necessary to take measures against them. In addition, the following two phenomena have been known as sources of display defects.
The first phenomenon is a so-called field-through (also called push-down or punch-through) phenomenon. This is a phenomenon in which the voltage of the pixel electrode connected to the drain terminal is lowered when switching from the on state to the off state due to parasitic capacitance between the gate and drain terminals of the TFT and between the source and drain terminals. It is. Specifically, this is a phenomenon in which the voltage of the pixel electrode is lowered due to redistribution of the charges accumulated in the parasitic capacitance and the storage capacitance at the timing when the TFT is turned off.
The second phenomenon is a direct-current voltage component resulting from a characteristic difference between the element substrate sandwiching the liquid crystal layer and the counter substrate. More specifically, the element substrate on which the pixel electrode, the TFT, and the like are formed, and the counter electrode are formed. This is because the electric characteristics are asymmetric in the counter substrate thus formed, thereby causing a bias in charge.

  A method of driving a liquid crystal device focusing on the two phenomena described above has been proposed. For example, in Patent Document 1, a counter electrode potential serving as a reference for polarity inversion in inversion driving is set in advance by using the first phenomenon (field-through) and A technique for shifting so as to correct the influence of the second phenomenon (voltage fluctuation due to the difference in electrical characteristics between the element substrate and the counter substrate) is disclosed. Specifically, in Patent Document 1, in the initial stage, the voltage fluctuation due to the first phenomenon and the voltage fluctuation due to the second phenomenon are measured under a predetermined measurement condition, and a value obtained by adding them is fixed. The correction voltage is added to the set potential (Vcom) of the counter electrode.

JP 2002-189460 A

In the technique of Patent Document 1, a correction voltage obtained by adding the voltage fluctuations due to the first phenomenon and the second phenomenon is added to the counter electrode potential, thereby suppressing display quality deterioration due to generation of a DC voltage component. It is considered possible.
However, when the correction voltage of the second phenomenon has a certain level with respect to the correction voltage of the first phenomenon, the counter electrode potential is greatly shifted to either positive or negative. That is, if the correction voltage for the second phenomenon is large, the amplitude difference between the positive and negative driving voltages becomes large. For this reason, display defects such as flicker may occur.

  The present invention has been made in view of such circumstances, and provides a liquid crystal device, a driving method of the liquid crystal device, and an electronic apparatus capable of improving display quality by suppressing the occurrence of display defects such as flicker. The purpose is to provide.

  In order to solve the above problems, a liquid crystal device of the present invention includes a plurality of scanning lines, a plurality of data lines, a switching element and a pixel electrode provided corresponding to the intersections of the scanning lines and the data lines, An element substrate including: a counter substrate provided with a counter electrode disposed opposite to the element substrate; a liquid crystal layer sandwiched between the element substrate and the counter substrate; and the liquid crystal layer of the element substrate A first alignment film provided on the liquid crystal layer side of the counter substrate, and a first pretilt angle in the first alignment film having the second alignment film. The counter electrode is set to be smaller than a second pretilt angle in the film, and a counter electrode potential set to reduce flicker due to parasitic capacitance of the switching element is applied to the counter electrode. Is the counter-current When the high voltage is positive and the low voltage is negative with reference to the potential, the positive voltage and the negative voltage are alternately applied, and the positive voltage is applied. In a predetermined period including one period and a second period in which the negative voltage is applied, the length of the first period is set shorter than the length of the second period. It is characterized by that.

  According to this liquid crystal device, since the counter electrode potential is set in advance so as to reduce the flicker caused by the parasitic capacitance of the switching element, the correction for the first phenomenon is incorporated. In addition, since the length of the first period of the predetermined period is set shorter than the length of the second period, correction for the second phenomenon is included. In this correction, the inventor sets the first pretilt angle in the first alignment film to be smaller than the second pretilt angle in the second alignment film (the first pretilt angle is perpendicular to the second pretilt angle). This is because the effective voltage waveform is shifted in the negative direction of the potential by being set close to the orientation. This point has also been confirmed from the results of experiments conducted by the present inventors. That is, when the first pretilt angle in the first alignment film on the element substrate side is set smaller than the second pretilt angle in the second alignment film on the counter substrate side, the first pretilt angle and the second pretilt angle are the same. Compared to the above, it is clear that Vcom shifts in the negative direction (the counter electrode potential after the shift is shifted in the negative direction from the counter electrode potential before the shift). As described above, since the shift direction of the Vcom shift is determined in advance, the correction for the Vcom shift can be accurately performed as compared to the case where the shift direction is uncertain as in the prior art. Therefore, it is possible to provide a liquid crystal device capable of improving the display quality by suppressing the occurrence of display defects such as flicker.

  The liquid crystal device according to the present invention includes an element substrate including a plurality of scanning lines, a plurality of data lines, a switching element and a pixel electrode provided corresponding to an intersection of the scanning lines and the data lines, A counter substrate having a counter electrode disposed opposite to the element substrate, a liquid crystal layer sandwiched between the element substrate and the counter substrate, and a first liquid crystal layer provided on the element substrate on the liquid crystal layer side. An alignment film and a second alignment film provided on the liquid crystal layer side of the counter substrate, wherein a first pretilt angle in the first alignment film is larger than a second pretilt angle in the second alignment film. The counter electrode is applied with a counter electrode potential set to reduce flicker due to the parasitic capacitance of the switching element, and the pixel electrode has the counter electrode potential as a reference. As high-order electric The positive polarity voltage and the negative polarity voltage are alternately applied, the first period during which the positive polarity voltage is applied, and the negative polarity The length of the first period is set to be longer than the length of the second period in a predetermined period including a second period in which a sex voltage is applied.

  According to this liquid crystal device, since the counter electrode potential is set in advance so as to reduce the flicker caused by the parasitic capacitance of the switching element, the correction for the first phenomenon is incorporated. In addition, since the length of the first period of the predetermined period is set longer than the length of the second period, correction for the second phenomenon is included. In this correction, the inventor sets the first pretilt angle in the first alignment film to be larger than the second pretilt angle in the second alignment film (the second pretilt angle is perpendicular to the first pretilt angle). This is because the effective voltage waveform shifts in the positive direction of the potential by being set close to the orientation. This point is also estimated from the results of experiments conducted by the present inventors. That is, when the first pretilt angle in the first alignment film on the element substrate side is set larger than the second pretilt angle in the second alignment film on the counter substrate side, the first pretilt angle and the second pretilt angle are the same. Compared with the above, it is clear that Vcom shifts in the positive direction (the counter electrode potential after the shift is shifted in the positive direction from the counter electrode potential before the shift). As described above, since the shift direction of the Vcom shift is determined in advance, the correction for the Vcom shift can be accurately performed as compared to the case where the shift direction is uncertain as in the prior art. Therefore, it is possible to provide a liquid crystal device capable of improving the display quality by suppressing the occurrence of display defects such as flicker.

  In the liquid crystal device, the pixel electrode may be made of Al, and the counter electrode may be made of ITO.

  According to this liquid crystal device, it is clear that Vcom shifts in either the positive direction or the negative direction as compared with the case where the pixel electrode and the counter electrode are made of the same material (for example, ITO). The asymmetry of the characteristics becomes remarkable. This point has also been confirmed from the results of experiments conducted by the present inventors. For this reason, as compared with the case where the pixel electrode and the counter electrode are made of, for example, ITO, a DC voltage component due to the characteristic difference between the element substrate sandwiching the liquid crystal layer and the counter substrate is significantly generated. Therefore, it is possible to improve display quality by suppressing the occurrence of display defects such as flicker.

  A driving method of a liquid crystal device according to the present invention includes an element substrate including a plurality of scanning lines, a plurality of data lines, and switching elements and pixel electrodes provided corresponding to intersections of the scanning lines and the data lines. A counter substrate provided with a counter electrode disposed opposite to the element substrate, a liquid crystal layer sandwiched between the element substrate and the counter substrate, and the liquid crystal layer side of the element substrate. A first alignment film and a second alignment film provided on the liquid crystal layer side of the counter substrate, wherein a first pretilt angle in the first alignment film is a second pretilt angle in the second alignment film. A driving method of a liquid crystal device set to be smaller than a corner, wherein a counter electrode potential set to reduce flicker caused by parasitic capacitance of the switching element is applied to the counter electrode, and the pixel electrode The counter-current When the high voltage is positive and the low voltage is negative with reference to the potential, the positive voltage and the negative voltage are alternately applied, and the positive voltage is applied. The length of the first period is set to be shorter than the length of the second period in a predetermined period consisting of one period and a second period in which the negative voltage is applied. It is characterized by.

  According to the driving method of the liquid crystal device of the present invention, since the counter electrode potential is set in advance so as to reduce the flicker caused by the parasitic capacitance of the switching element, the correction for the first phenomenon is incorporated. ing. In addition, since the length of the first period of the predetermined period is set shorter than the length of the second period, correction for the second phenomenon is also incorporated. In this correction, the inventor sets the first pretilt angle in the first alignment film to be smaller than the second pretilt angle in the second alignment film, so that the effective voltage waveform shifts in the negative direction of the potential. By finding out. This point has also been confirmed from the results of experiments conducted by the present inventors. Therefore, it is possible to improve display quality by suppressing the occurrence of display defects such as flicker.

  A driving method of a liquid crystal device according to the present invention includes an element substrate including a plurality of scanning lines, a plurality of data lines, and switching elements and pixel electrodes provided corresponding to intersections of the scanning lines and the data lines. A counter substrate provided with a counter electrode disposed opposite to the element substrate, a liquid crystal layer sandwiched between the element substrate and the counter substrate, and the liquid crystal layer side of the element substrate. A first alignment film and a second alignment film provided on the liquid crystal layer side of the counter substrate, wherein a first pretilt angle in the first alignment film is a second pretilt angle in the second alignment film. A driving method of a liquid crystal device set to be larger than a corner, wherein a counter electrode potential set to reduce flicker due to parasitic capacitance of the switching element is applied to the counter electrode, and the pixel electrode The counter-current When the high voltage is positive and the low voltage is negative with reference to the potential, the positive voltage and the negative voltage are alternately applied, and the positive voltage is applied. The length of the first period is set to be longer than the length of the second period in a predetermined period including one period and a second period in which the negative voltage is applied. It is characterized by.

  According to the driving method of the liquid crystal device of the present invention, since the counter electrode potential is set in advance so as to reduce the flicker caused by the parasitic capacitance of the switching element, the correction for the first phenomenon is incorporated. ing. In addition, since the length of the first period of the predetermined period is set longer than the length of the second period, correction for the second phenomenon is also incorporated. In this correction, the effective voltage waveform is shifted in the positive direction of the potential when the inventor sets the first pretilt angle in the first alignment film to be larger than the second pretilt angle in the second alignment film. By finding out. This point is also estimated from the results of experiments conducted by the present inventors. Therefore, it is possible to improve display quality by suppressing the occurrence of display defects such as flicker.

  In the method for driving the liquid crystal device, when the first pretilt angle is set to be 6 ° smaller than the second pretilt angle, the length of the first period and the length of the second period The ratio may be set in a range greater than 50.0 / 50.0 and not greater than 52.0 / 48.0.

  According to the driving method of the liquid crystal device, since the optimal time distribution ratio corresponding to the flicker allowable limit is obtained, the second phenomenon can be effectively corrected. On the other hand, if the ratio between the length of the first period and the length of the second period is smaller than 50.0 / 50.0, the length of the first period is too long and effective correction is achieved. May not be. In addition, when the ratio of the length of the first period to the length of the second period is larger than 52.0 / 48.0, the length of the first period is too short to be an effective correction. There is.

  An electronic apparatus according to the present invention includes the above-described liquid crystal device.

  According to this electronic apparatus, since the above-described liquid crystal device is provided, it is possible to provide an electronic apparatus capable of improving display quality by suppressing the occurrence of display defects such as flicker.

1 is a block diagram illustrating a schematic configuration of a liquid crystal device according to a first embodiment of the present invention. It is a figure which shows schematic structure of the liquid crystal panel which concerns on 1st Embodiment. It is an equivalent circuit diagram of a pixel. It is a top view of the liquid crystal panel which looked at the element substrate concerning a 1st embodiment from the counter substrate side with each component formed on it. It is sectional drawing which shows schematic structure of the liquid crystal panel which concerns on 1st Embodiment. It is a figure which shows the chart which shows the gate voltage and drive voltage waveform which concern on 1st Embodiment. It is a figure which shows the relationship of time passage and Vcom shift which concern on 1st Embodiment. It is a figure which shows the relationship between the time ratio which concerns on 1st Embodiment, and Vcom shift. It is a figure which shows the timing chart of a scanning signal system when a designated value is "-1". It is a figure which shows the timing chart in the 1st field of a data signal system. It is a figure which shows the timing chart in the 2nd field of a data signal system. It is the figure which showed the writing state of each line with progress of time over the continuous frame in case a designated value is "-1." It is sectional drawing which shows schematic structure of the liquid crystal panel which concerns on 2nd Embodiment. It is a figure which shows the chart which shows the gate voltage and drive voltage waveform which concern on 2nd Embodiment. It is a figure which shows the relationship between the time ratio which concerns on 2nd Embodiment, and Vcom shift. It is a figure which shows the timing chart of a scanning signal system when a designated value is "+1". FIG. 10 is a diagram showing the writing state of each row as time passes over successive frames when the designated value is “+1”. It is a schematic diagram which shows schematic structure of the projector which is an example of an electronic device.

  Embodiments of the present invention will be described below with reference to the drawings. This embodiment shows one aspect of the present invention, and does not limit the present invention, and can be arbitrarily changed within the scope of the technical idea of the present invention. Moreover, in the following drawings, in order to make each structure easy to understand, an actual structure and a scale, a number, and the like in each structure are different.

(First embodiment)
FIG. 1 is a block diagram showing a schematic configuration of a liquid crystal device 100 according to the first embodiment of the present invention. The liquid crystal device 100 includes a liquid crystal panel 100A, a processing circuit 150, a voltage generation circuit 160, and an operator 170. The liquid crystal panel 100A is of a reflective active matrix type. The detailed configuration of the liquid crystal panel 100A will be described later.

  The processing circuit 150 includes a control circuit 152 and a display data processing circuit 156, and is a circuit module that controls the operation of the liquid crystal panel 100A in accordance with the output of the data signal Vid. The processing circuit 150 is connected to the liquid crystal panel 100A by, for example, an FPC (Flexible Printed Circuit) substrate.

  The control circuit 152 includes a timing signal generation circuit 153. A clock generation circuit 154 is attached to the timing signal generation circuit 153. The clock generation circuit 154 generates a clock signal that serves as a reference for the control operation of each unit and outputs the clock signal to the timing signal generation circuit 153. The timing signal generation circuit 153 generates various control signals for controlling the liquid crystal panel 100A in synchronization with the vertical synchronization signal Vs, the vertical synchronization signal Hs, and the dot clock signal Dclk supplied from an external device (not shown). To do. The control circuit 152 controls various circuits such as a timing signal generation circuit 153, a display data processing circuit 156, which will be described later, and a voltage generation circuit 160.

  The voltage generation circuit 160 includes a DC / DC converter. The voltage generation circuit 160 generates a plurality of DC voltages used in each unit from DC power supplied from an external device. The voltage generation circuit 160 generates a counter electrode potential Vcom applied to the counter electrode 22 of the liquid crystal panel 100A, and supplies the counter electrode potential Vcom to the liquid crystal panel 100A.

  The operator 170 is operated by a user or the like, for example, and outputs a designated value Q corresponding to the operation in a range from “−10” to “0”, for example. Specifically, when the operation element 170 is mounted on an electronic device, the operation element 170 is provided so as to be operable by an operation unit such as an operation panel or a remote controller. Note that the output value of the second start pulse Dyb is moved back and forth by the designated value Q, as will be described later.

  A frame memory 157 and a DA converter 158 are attached to the display data processing circuit 156. The display data processing circuit 156 stores the display data Video supplied from the external device in the frame memory 157 according to the control by the control circuit 152, and then reads it in synchronization with the driving of the liquid crystal panel 100A. Data signal Vid (drive voltage) is converted. The display data Video defines the gradation of the pixels in the liquid crystal panel 100A, and is supplied for one frame triggered by the supply timing of the vertical synchronization signal Vs, and 1 by the supply timing of the vertical synchronization signal Hs. Lines are supplied.

  Here, the vertical synchronization signal Vs in the present embodiment has a frequency of 120 Hz (period of 8.33 milliseconds), but is not limited thereto. For the dot clock signal Dclk, a period during which one pixel of the display data Video is supplied is defined. That is, the control circuit 152 controls each unit in synchronization with the supply of the display data Video.

FIG. 2 is a diagram illustrating a schematic configuration of the liquid crystal panel 100A according to the first embodiment. FIG. 3 is a transmissive circuit diagram of the pixel.
As shown in FIG. 2, the liquid crystal panel 100 </ b> A has a configuration in which a scanning line driving circuit 130 and a data line driving circuit 140 are built around the display area 70. In the display area 70, 480 scanning lines 61 are provided so as to extend in the row (X) direction. Further, 640 columns of data lines 62 are provided in the display area 70 so as to extend in the column (Y) direction. Each data line 62 is arranged so as to be electrically insulated from each scanning line 61. A plurality of pixels 70 a are formed corresponding to the intersections of the scanning lines 61 in 480 rows and the data lines 62 in 640 columns. Specifically, the plurality of pixels 70a are arranged in a matrix of 480 rows × 640 columns.

  Note that, in the present embodiment, the resolution is FHD (full HD), in which a plurality of pixels 70a are actually arranged in a matrix of vertical 1080 rows × horizontal 1920 columns, but for ease of explanation. The resolution is VGA (Video Graphics Array). The resolution is not limited to this, and may be a resolution such as XGA (eXtended Graphics Array) or SXGA (Super-XGA).

  FIG. 3 shows a total of 4 pixels of 2 × 2 corresponding to the intersection of the i row and the (i + 1) row adjacent to it by 1 row and the j column and the (j + 1) column adjacent to the right by 1 column. The structure of is shown. Note that i and (i + 1) indicate rows in which pixels are arranged, and are integers of 1 to 480 in this example. J and (j + 1) indicate columns in which pixels are arranged, and are integers of 1 to 640 in this example. In the vicinity of each intersection of the scanning line 61 and the data line 62, a switching element 40 corresponding to each pixel 70a is provided. This switching element is constituted by a thin film transistor (hereinafter referred to as TET). Specifically, each of the plurality of pixels 70 a includes an n-channel TFT 40 and a liquid crystal capacitor 120.

  Here, since the respective pixels 70a have the same configuration, the pixel 70a is representatively described. The gate electrode 41 of the TFT 40 in the pixel in the i row and j column is connected to the i-th scanning line 61. On the other hand, the source electrode of the TFT 40 is connected to the data line 62 in the j-th column, and the drain electrode thereof is connected to the pixel electrode 12 that is one end of the liquid crystal capacitor 120. The other end of the liquid crystal capacitor 120 is connected to the counter electrode 22. The counter electrode 22 is common to all the pixels, and a counter electrode potential Vcom that is constant in time is applied thereto. Although details will be described later, the counter electrode potential Vcom is a value shifted from the reference value by a correction voltage for compensating for the DC voltage component in the first phenomenon described above.

  The liquid crystal panel 100A has a configuration in which a pair of substrates of the element substrate 10 and the counter substrate 20 are bonded together with a certain gap therebetween, and liquid crystal is sealed in the gap. Among these, the scanning line 61, the data line 62, the TFT 40, and the pixel electrode 12 are formed on the element substrate 10 together with the scanning line driving circuit 130 and the data line driving circuit 140. On the other hand, a counter electrode 22 is formed on the counter substrate 20. Then, these electrode forming surfaces are bonded together with a certain gap so as to face each other. For this reason, the liquid crystal capacitor 120 is configured by the pixel electrode 12 and the counter electrode 22 sandwiching the liquid crystal 120a.

  In the present embodiment, if the effective voltage value held in the liquid crystal capacitor 120 is close to zero, the transmittance of light passing through the liquid crystal capacitor 120 is minimized and a black display is obtained. On the other hand, the amount of transmitted light increases as the effective voltage value held in the liquid crystal capacitor 120 increases, and finally the white display with the maximum transmittance is obtained. That is, it is assumed that the liquid crystal panel 100A is set to a normally black mode.

  In this configuration, a selection voltage is applied to the scanning line 61 to turn on (conduct) the TFT 40, and the voltage corresponding to the gradation (brightness) is applied to the pixel electrode 12 via the data line 62 and the on-state TFT 40. When the data signal Vid is supplied, the liquid crystal capacitor 120 corresponding to the intersection of the scanning line 61 to which the selection voltage is applied and the data line 62 to which the data signal Vid is supplied holds the effective voltage value corresponding to the gradation. it can.

  Note that when the scanning line 61 becomes a non-selection voltage, the TFT 40 is turned off (non-conducting). However, since the off-resistance at this time is not ideally infinite, the charge accumulated in the liquid crystal capacitor 120 is not small. To leak. In order to reduce the influence of off-leakage, a storage capacitor 50 is formed for each pixel. One end of the storage capacitor 50 is connected to the pixel electrode 12 (the drain of the TFT 40). On the other hand, the other end of the storage capacitor 50 is commonly connected to the capacitor line 64 over all pixels. The capacitor line 64 is maintained at a constant potential, for example, the same counter electrode potential as that of the counter electrode 22.

  The scanning line driving circuit 130 supplies scanning signals G1, G2, G3,..., G480 to the scanning lines 61 in the 1, 2, 3,. The scanning line driving circuit 130 sets the scanning signal to the selected scanning line 61 to the H level corresponding to the voltage, and sets the other scanning signals to the scanning line 61 to the L level corresponding to the non-selection voltage (ground potential). .

  The data line driving circuit 140 includes a sampling signal output circuit 142 and n-channel TFTs 40 provided corresponding to the data lines 62, respectively. The data line driving circuit 140 supplies a data signal Vid (driving voltage) that defines the gradation of the pixel to each pixel 70a in the selected scanning line 61.

  FIG. 4 is a plan view of the liquid crystal panel 100A when the element substrate 10 according to the first embodiment is viewed from the counter substrate 20 side together with the components formed thereon. FIG. 5 is a cross-sectional view illustrating a schematic configuration of the liquid crystal panel 100A according to the first embodiment. In FIG. 4, illustration of various drive circuits such as the scanning line drive circuit 130 and the data line drive circuit 140 is omitted for convenience. In FIG. 5, the liquid crystal layer and the sealing material 71 are not shown for convenience.

  As shown in FIG. 4, a display region 70 is formed in the center of the element substrate 10. A frame-shaped light shielding region 74 is provided at the peripheral edge of the display region 70, and a sealing material 71 is disposed so as to surround the light shielding region 74. The element substrate 10 and the counter substrate 20 are bonded together by the sealing material 71, and a liquid crystal layer (not shown) is sealed in a region surrounded by both the substrates and the sealing material 71. Then, the liquid crystal inlet provided in the sealing material 71 is sealed by the sealing portion 72.

  A scanning line driving circuit 130 that supplies a scanning signal to the scanning line 61 and a data line driving circuit 140 that supplies an image signal to the data line 62 are mounted outside the sealing material 71, although not shown. A plurality of connection terminals 75 connected to an external circuit are provided at the end of the element substrate 10. Although not shown, the connection terminal 75 is formed with a wiring extending from the drive circuit. Inter-substrate conducting portions 73 that electrically connect the element substrate 10 and the counter substrate 20 are provided at the four corners of the sealing material 71. The inter-substrate conduction part 73 is also electrically connected to the connection terminal 75 through wiring.

  As shown in FIG. 5, the liquid crystal panel 100 </ b> A includes an element substrate 10, a counter substrate 20 disposed so as to face the element substrate 10, and a liquid crystal layer sandwiched therebetween. The element substrate 10 includes a substrate main body 11 made of a light-transmitting material such as glass or quartz, the TFT 40 and the pixel electrode 12 formed on the inner side (liquid crystal layer side), a reflective reflection film 37 covering the TFT 40 and the pixel electrode 12, and a first alignment. The base film 38A, the first alignment film 13 and the like are provided. One counter substrate 20 includes a substrate body 21 made of a translucent material such as glass or quartz, a light shielding film 24 formed on the inner side (liquid crystal layer side), a counter electrode 22 covering the light shielding film 24, and The second alignment base film 38B and the second alignment film 23 are provided.

  A pixel electrode 12 is provided on the element substrate 10 side, and a first alignment film 13 is provided above the pixel electrode 12. The pixel electrode 12 is made of a conductive film such as aluminum (Al).

  On the other hand, a counter electrode 22 is provided on the entire surface of the counter substrate 20, and a second alignment film 23 is provided on the upper side thereof. The counter electrode 22 is made of a transparent conductive film such as an ITO film. The thickness of the counter electrode 22 is 120 nm or more and 160 nm or less, for example. The film thickness of the second alignment film 23 is, for example, not less than 40 nm and not more than 80 nm.

  Between the element substrate 10 and the counter substrate 20 arranged so as to face each other, liquid crystal is sealed in a space surrounded by the sealing material 71 described above to form a liquid crystal layer. The liquid crystal layer assumes a predetermined alignment state by the alignment film in a state where an electric field from the pixel electrode 12 is not applied. Note that the liquid crystal in the liquid crystal layer may be twisted nematic liquid crystal or liquid crystal for vertical alignment.

  On the other hand, on the element substrate 10, in addition to the pixel electrode 12 and the first alignment film 13, various configurations including these are provided in a laminated structure. This stacked structure includes, in order from the bottom, a first layer including the scanning line 61, a second layer including the TFT 40 including the gate electrode 41, a third layer including the storage capacitor 50, a fourth layer including the data line 62, and the like. It comprises a fifth layer including the capacitor line 64 and the like, and a sixth layer (uppermost layer) including the pixel electrode 12 and the alignment film.

  Also, a base insulating film 30 is provided between the first layer and the second layer, a first interlayer insulating film 31 is provided between the second layer and the third layer, and a second interlayer insulating film 32 is provided between the third layer and the fourth layer. A third interlayer insulating film 33 is provided between the fourth layer and the fifth interlayer, and a fourth interlayer insulating film 34 and a fifth interlayer insulating film 35 are provided between the fifth layer and the sixth layer, respectively. The short circuit between each element is prevented. These various insulating films are also provided with, for example, contact holes for electrically connecting the high concentration source region in the semiconductor layer 44 of the TFT 40 and the data lines 62. Hereinafter, each of these elements will be described in order from the bottom.

  In the first layer, a scanning line 61 made of, for example, tungsten silicide (WSi) is provided. The film thickness (thickness in the Z direction) of the scanning line 61 is, for example, not less than 180 nm and not more than 220 nm. Further, the scanning line 61 has a light shielding property, and is formed so as to substantially fill a region where the pixel electrode 12 is not formed. For this reason, the scanning line 61 has a function of blocking light that enters the TFT 40 from below.

  In the second layer, the TFT 40 including the gate electrode 41 is provided. The TFT 40 has an LDD (Lightly Doped Drain) structure. As its constituent elements, the gate electrode 41 described above, for example, a channel region of the semiconductor layer 44 formed of a conductive polysilicon film and having a channel formed by an electric field from the gate electrode 41, the gate electrode 41 and the semiconductor layer 44 are insulated. A gate insulating film 42 including a thermally oxidized gate insulating film 43, a low concentration source region and a low concentration drain region, and a high concentration source region and a high concentration drain region in the semiconductor layer 44 are provided. The film thickness of the gate electrode 41 is, for example, 15 nm or more and 105 nm or less. The film thickness of the semiconductor layer 44 is about 40 nm, for example. The thickness of the thermally oxidized gate insulating film 43 is, for example, not less than 28 nm and not more than 35 nm. The film thickness of the gate insulating film 42 is, for example, 43 nm or more and 56 nm or less.

  A base insulating film 30 made of, for example, tetraethoxysilane (TEOS) is provided on the scanning line 61 and below the TFT 40. The thickness of the base insulating film 30 is, for example, not less than 380 nm and not more than 420 nm. The base insulating film 30 has a function of insulating the TFT 40 from the scanning line 61 between layers. The base insulating film 30 is formed on the entire surface of the element substrate 10.

  In the third layer, a storage capacitor 50 is provided. The storage capacitor 50 includes a lower capacitance electrode 51 as a pixel potential side capacitance electrode connected to the high concentration drain region of the TFT 40 and the pixel electrode 12 and an upper capacitance electrode 53 as a fixed potential side capacitance electrode. It is formed by arrange | positioning through. According to the storage capacitor 50, the potential holding characteristic of the pixel electrode 12 can be remarkably improved.

  The lower capacitor electrode 51 is made of, for example, a conductive polysilicon film and functions as a pixel potential side capacitor electrode. The film thickness of the lower capacitor electrode 51 is, for example, not less than 95 nm and not more than 105 nm. In addition to the function as a pixel potential side capacitor electrode, the lower capacitor electrode 51 has a function of relay-connecting the pixel electrode 12 and the high concentration drain region of the TFT 40.

  The upper capacitor electrode 53 is made of, for example, a layer made of titanium nitride (TiN) (for example, a film thickness of 47 nm or more and 53 nm or less), a layer made of aluminum (Al) (for example, a film thickness of 142 nm or more and 158 nm or less), and titanium nitride (TiN). It has a three-layer structure of layers (for example, a film thickness of 97 nm or more and 103 nm or less). The upper capacitor electrode 53 functions as a fixed potential side capacitor electrode of the storage capacitor 50. The upper capacitor electrode 53 has the same shape as the lower capacitor electrode 51, and constitutes an island-like electrode like the lower capacitor electrode 51. In order to set the upper capacitor electrode 53 to a fixed potential, electrical connection is made to the capacitor line 64 having a fixed potential. Further, the upper capacitor electrode 53 has a function of blocking light that is about to enter the TFT 40 from above.

  The capacitive insulating film 52 is made of, for example, an HTO (High Temperature Oxide) film. The thickness of the capacitive insulating film 52 is, for example, 3 nm or more and 5 nm or less. Note that the capacitor insulating film 52 is preferably as thin as possible from the viewpoint of increasing the storage capacitor 50 as long as the reliability of the film is sufficiently obtained. Further, the capacitor insulating film 52 may be configured to have a two-layer structure, a three-layer structure, or a stacked structure having more layers.

  A first interlayer insulating film 31 made of, for example, tetraethoxysilane (TEOS) is formed on the TFT 40 to the gate electrode 41 and the relay electrode and below the storage capacitor 50. The film thickness of the first interlayer insulating film 31 is, for example, not less than 280 nm and not more than 320 nm.

  In the first interlayer insulating film 31, a contact hole 31 a that electrically connects a high-concentration source region of the TFT 40 and a data line 62 to be described later is opened through the second interlayer insulating film 32 described later. . The first interlayer insulating film 31 is provided with a contact hole 31b that electrically connects the high-concentration drain region of the TFT 40 and the lower capacitor electrode 51 constituting the storage capacitor 50.

  A data line 62 is provided in the fourth layer. The data line 62 includes, for example, a layer made of titanium (Ti) (for example, a film thickness of 19 nm to 21 nm), a layer of titanium nitride (TiN) (for example, a film thickness of 47 nm to 53 nm), aluminum (Al ) (For example, a film thickness of 332 nm or more and 368 nm or less) and a layer of titanium nitride (TiN) (for example, a film thickness of 142 nm or more and 158 nm or less).

  In the fourth layer, a capacitor line relay layer (not shown), the first relay electrode 63 and the double contact portion 66 are formed as the same film as the data line 62. These are not formed so as to have a planar shape continuous with the data line 62 when viewed in plan, but are formed so as to be divided by patterning. Since the capacitor line relay layer, the first relay electrode 63, and the double contact portion 66 are formed as the same film as the data line 62, the Ti layer, the TiN layer, and the Al layer are formed in order from the lower layer. And a four-layer structure of TiN. The double contact portion 66 is provided outside the display region 70, and after being routed by a wiring (not shown), is drawn to the surface layer of the element substrate 10 and connected to the scanning line driving circuit 130.

  A plasma CVD method using a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like, or preferably TEOS gas, is provided above the storage capacitor 50 and the data line 62. A second interlayer insulating film 32 made of a film formed by (hereinafter referred to as P-TEOS) is formed. The film thickness of the second interlayer insulating film 32 is not less than 380 nm and not more than 420 nm, for example. The second interlayer insulating film 32 is provided with the contact hole 31a for electrically connecting the high-concentration source region of the TFT 40 and the data line 62, and the capacitor line relay layer and the storage capacitor. A contact hole (not shown) for electrically connecting 50 upper capacitor electrodes 53 is opened.

  A capacitor line 64 is formed in the fifth layer. The capacitor line 64 has, for example, a two-layer structure of a layer made of aluminum (Al) (for example, a film thickness of 315 nm to 385 nm) and a layer (for example, a film thickness of 135 nm to 165 nm) made of titanium nitride (TiN) in order from the lower layer. It is formed as a film having The capacitor line 64 is formed on the third interlayer insulating film 33. The surface of the third interlayer insulating film 33 is flattened by performing a flattening process such as a CMP (Chemical Mechanical Polishing) process.

  In the fifth layer, a second relay electrode 65 is formed as the same film as the capacitor line 64. The second relay electrode 65 has a function of relaying electrical connection between the first relay electrode 63 and the pixel electrode 12 through a contact hole 33a described later. Note that the space between the capacitor line 64 and the second relay electrode 65 is not continuously formed in a planar shape, but is formed so as to be divided for patterning. Similar to the capacitor line 64, the second relay electrode 65 has a two-layer structure in which a lower layer is made of Al and an upper layer is made of TiN. As described above, the capacitor line 64 and the second relay electrode 65 include aluminum that is relatively excellent in light reflection performance and include titanium nitride that is relatively excellent in light absorption performance, and thus can function as a light shielding layer. . That is, it is possible to block the progress of incident light on the semiconductor layer 44 of the TFT 40 on its upper side.

  A third interlayer insulating film 33 made of, for example, P-TEOS is formed on the data line 62 and below the capacitor line 64 and the like. The film thickness of the third interlayer insulating film 33 is not less than 570 nm and not more than 630 nm, for example. In the third interlayer insulating film 33, a contact hole (not shown) for electrically connecting the capacitor line 64 and the capacitor line relay layer, and the second relay electrode 65 and the first relay electrode 63 are provided. Contact holes 33a for electrically connecting the two are opened.

  Finally, on the sixth layer, the pixel electrodes 12 are formed in a matrix as described above. The pixel electrode 12 is made of, for example, aluminum (Al), and has a film thickness of, for example, 180 nm or more and 220 nm or less.

  Further, as the same film as the pixel electrode 12 described above, a planarizing film 36 made of, for example, P-TEOS is formed in the peripheral region. The thickness of the planarizing film 36 is, for example, not less than 180 nm and not more than 220 nm.

  Further, a reflection enhancing film 37 is formed on the pixel electrode 12 and the planarizing film 36. The increased reflection film 37 includes, for example, a layer made of P-TEOS (for example, a film thickness of 67 nm or more and 83 nm or less) and a layer made of plasma silicon nitride (P-SiN) (for example, a film thickness of 58 nm or more and 72 nm or less) in order from the lower layer. It is formed as a film having a two-layer structure.

  Further, a first alignment base film 38A made of P-TEOS, for example, is formed on the increased reflection film 37. The film thickness of the first alignment base film 38A is, for example, not less than 90 nm and not more than 110 nm.

  The first alignment film 13 is formed on the first alignment base film 38A. The film thickness of the first alignment film 13 is, for example, 40 nm or more and 80 nm or less. Further, the first pretilt angle in the first alignment film 13 with respect to the thickness direction of the element substrate 10 is, for example, 1.2 °. Specifically, the first alignment film 13 is formed, for example, by vapor deposition (oblique vapor deposition) or sputtering of an inorganic material such as silicon oxide in an oblique direction with respect to the element substrate 10. When an inorganic material is vapor-deposited or sputtered with respect to the element substrate 10, the vapor deposition particles or sputtered particles are deposited obliquely with respect to the element substrate 10 to form a columnar crystal. The first alignment film 13 is formed by a large number of columnar crystals grown obliquely. The liquid crystal molecules are aligned along the growth direction of the columnar crystal. The alignment direction of the liquid crystal molecules is controlled by the incident angle of the deposited particles or sputtered particles with respect to the element substrate 10. The first alignment film 13 aligns liquid crystal molecules in a direction inclined by a predetermined pretilt angle from a direction perpendicular to the element substrate 10 (that is, the thickness direction of the element substrate 10). If the pretilt angle when the liquid crystal molecules are aligned in a direction perpendicular to the element substrate 10 is defined as 0 degree, the first pretilt angle in the first alignment film 13 is 1.2 °, for example.

  An electrode pad 39 made of, for example, an ITO film is formed on the first alignment base film 38A in the peripheral region other than the element portion (for example, the mounting terminal portion and the vertical conduction terminal portion). The film thickness of the electrode pad 39 is, for example, not less than 135 nm and not more than 165 nm. A part of the electrode pad 39 is embedded in a contact hole penetrating the fourth interlayer insulating film 34, the fifth interlayer insulating film 35, the planarizing film 36, the reflective reflection film 37, and the first alignment base film 38A. The capacitor line 64 is electrically connected.

  Under the pixel electrode 12 and the planarizing film 36, for example, in order from the lower layer, a fourth interlayer insulating film 34 (for example, a film thickness of 350 nm or more and 850 nm) made of P-TEOS and a first glass made of silicate glass such as BSG or NSG. A five-layer insulating film 35 (for example, a film thickness of 55 nm or more and 95 nm or less) is formed. In the fourth interlayer insulating film 34 and the fifth interlayer insulating film 35, a contact hole 34a for electrically connecting the pixel electrode 12 and the second relay electrode 65 is opened.

  Between the pixel electrode 12 and the TFT 40, the contact hole 34a, the second relay electrode 65, the contact hole 33a, the first relay electrode 63, the contact hole 32a, the lower capacitor electrode 51, and the contact hole 31b are electrically connected. Will be connected. Note that the surface of the fifth interlayer insulating film 35 is planarized by performing a planarization process such as a CMP process as described above. As a result, alignment defects of the liquid crystal layer due to steps due to various wirings, elements, etc. existing therebelow are reduced.

  On the other hand, on the counter substrate 20 side, a second alignment base film 38B made of, for example, P-TEOS is formed between the counter electrode 22 and the second alignment film 23. The film thickness of the second alignment base film 38B is, for example, not less than 90 nm and not more than 110 nm. The second pretilt angle in the second alignment film 23 with respect to the thickness direction of the counter substrate 20 is, for example, 7.2 °. Specifically, the second alignment film 13 is formed, for example, by vapor deposition (oblique vapor deposition) or sputtering of an inorganic material such as silicon oxide in an oblique direction with respect to the counter substrate 20. When the inorganic material is vapor-deposited or sputtered in the oblique direction with respect to the counter substrate 20, the vapor deposition particles or sputtered particles are deposited in the diagonal direction with respect to the counter substrate 20 to form a columnar crystal. A second alignment film 23 is formed by a large number of columnar crystals grown obliquely. The liquid crystal molecules are aligned along the growth direction of the columnar crystal. The alignment direction of the liquid crystal molecules is controlled by the incident angle of the deposited particles or sputtered particles with respect to the counter substrate 20. The second alignment film 23 aligns liquid crystal molecules in a direction inclined by a predetermined pretilt angle from a direction perpendicular to the counter substrate 20 (that is, a thickness direction of the counter substrate 20). If the pretilt angle when the liquid crystal molecules are aligned in a direction perpendicular to the counter substrate 20 is defined as 0 degree, the second pretilt angle in the second alignment film 23 is, for example, 7.2 °.

  In the present embodiment, the first pretilt angle (1.2 °) in the first alignment film 13 on the element substrate 10 side is greater than the second pretilt angle (7.2 °) in the second alignment film 23 on the counter substrate 20 side. Is set too small. The first pretilt angle is set by increasing the vapor deposition rate when forming the first alignment film 13 on the element substrate 10 side as compared with the vapor deposition rate when forming the second alignment film 23 on the counter substrate 20 side. Can be made smaller than the second pretilt angle.

  By the way, in the conventional liquid crystal device, in order to suppress display defects such as flicker and burn-in of a display image, for example, the polarity of the driving voltage applied to each pixel electrode is set for each scanning line or data line, or for an image. Inversion driving (AC driving) for inverting each frame in the signal has been adopted.

  This is intended to eliminate flicker and the like by applying a DC voltage component to the liquid crystal layer by inversion driving and suppressing the bias of charge between the substrates. However, even if inversion driving is simply performed, application of a DC voltage component to the liquid crystal layer and bias of electric charges have occurred, and display defects still occurred. The following two phenomena have been known as the source of this display defect.

As described above, the first phenomenon is a voltage drop due to a field-through phenomenon (also called push-down or penetration). This can be corrected by compensating for the DC voltage corresponding to the voltage drop.
On the other hand, the second phenomenon is a bias of electric charges caused by a difference in electrical characteristics between the element substrate and the counter substrate. In order to compensate for this, it is necessary to apply an extra DC voltage that cancels out the charge bias.

  Here, the first phenomenon and the second phenomenon will be described with reference to FIG. FIG. 6A is a chart showing the gate voltage and drive voltage waveforms. FIG. 6B is a chart showing the effective voltage waveform of the liquid crystal layer. FIG. 6C is a chart showing the effective voltage waveform of the liquid crystal layer after a certain amount of driving time has elapsed from FIG. In FIGS. 6A to 6C, the horizontal axis indicates the passage of time and the vertical axis indicates the potential.

  As shown in FIG. 6A, the potential of the drive voltage waveform VD is switched alternately between a high potential EH (for example, 12V) and a low potential EL (for example, 2V) in synchronization with the rise of the gate voltage VG. It has become.

  As shown in FIG. 6B, when the gate voltage VG rises, the switching element is turned on and the pixel electrode 12 is charged. The potential of the effective voltage waveform VL1 of the liquid crystal layer generally rises from the low potential EL to the high potential EH.

  By the way, when the switching element is configured by a thin film transistor, a punch-through voltage may be generated when the switching element is turned off. That is, the electric charge accumulated in the capacitance between the gate electrode 41 and the channel region of the switching element flows to the pixel electrode 12, thereby causing a voltage drop V 1 (punch-through voltage). In addition, a voltage drop V2 may occur due to leakage current flowing through the channel region with the switching element turned off. Thus, when the gate voltage rises next time, the potential of the effective voltage waveform VL1 is lower than the high potential EH by the voltage drops V1 and V2.

  Next, when the gate voltage VG rises, the drive voltage waveform VD becomes a low potential, and the pixel electrode 12 is discharged. Then, the potential of the effective voltage waveform VL1 of the liquid crystal layer drops to the low potential EL. When the switching element is turned off, a voltage drop V3 due to a punch-through voltage occurs, and a voltage rise due to a leak current occurs.

  The potential of the counter electrode 22 is held at the counter electrode potential Vcom1. The counter electrode potential Vcom1 is set in advance so as to balance the high potential side and the low potential side with respect to the counter electrode potential Vcom1 of the effective voltage waveform VL1. The counter electrode potential Vcom1 is set in consideration of the voltage drops V1 to V3 and the voltage rise V4, and generally has a value different from an intermediate potential EM (for example, 7 V) between the high potential EH and the low potential EL. For example, the absolute value of the time integral value of the difference between the effective voltage waveform VL1 and the counter electrode potential Vcom1 is optimized so as to be approximately equal between the period when the drive voltage waveform VD is the high potential EH and the period when the drive voltage waveform VD is the low potential EL. This value is set as the counter electrode potential Vcom1.

  As shown in FIG. 6C, the effective voltage waveform VL2 after driving the liquid crystal layer for a certain period often shifts from the effective voltage waveform VL1 immediately after the start of driving. Note that the effective voltage waveform VL2 may shift in either the positive or negative direction of the potential, but FIG. 6C shows a state in which the effective voltage waveform VL2 is shifted in the negative direction. Consider a counter electrode potential Vcom2 that is optimized to balance positive and negative with respect to the shifted effective voltage waveform VL2. The counter electrode potential Vcom2 after the shift is shifted in the negative direction from the counter electrode potential Vcom1 before the shift.

  Here, in the conventional technique, it is uncertain whether the effective voltage waveform VL2 shifts in the positive or negative direction of the potential. That is, it is uncertain whether the counter electrode potential Vcom2 after the shift is shifted in the positive or negative direction from the counter electrode potential Vcom1 before the shift.

  However, the inventor sets the first pretilt angle in the first alignment film 13 on the element substrate 10 side to be smaller than the second pretilt angle in the second alignment film 23 on the counter substrate 20 side (first By setting the pretilt angle closer to the vertical orientation than the second pretilt angle), the effective voltage waveform VL2 optimized to achieve a positive / negative balance is shifted in the negative direction of the potential (the Vcom shift is in the negative direction). To shift to). This point has also been confirmed from the results of experiments conducted by the present inventors.

  FIG. 7 is a diagram showing the relationship between the elapsed time and the Vcom shift obtained by an experiment conducted by the present inventor. In FIG. 7, the horizontal axis represents elapsed time, and the vertical axis represents Vcom shift. Here, the Vcom shift is a difference between the counter electrode potential Vcom1 before the shift and the counter electrode potential Vcom2 after the shift, that is, a value of Vcom2−Vcom1. In FIG. 7, “▲” indicates that the first pretilt angle (1.2 °) in the first alignment film 13 on the element substrate 10 side is the second pretilt angle (7 in the second alignment film 23 on the counter substrate 20 side). .. 2 °) is set smaller. “◯” indicates that both the first pretilt angle and the second pretilt angle are 1.2 °, that is, the first pretilt angle in the first alignment film 13 on the element substrate 10 side and the first pretilt angle on the counter substrate 20 side. The state in which the second pretilt angle in the two-alignment film 23 is set to be the same is shown. In FIG. 7, the Vcom shift is measured when a rectangular wave having an amplitude of 5V is applied.

  As shown in FIG. 7, Vcom in a state “◯” where the first pretilt angle in the first alignment film 13 on the element substrate 10 side and the second pretilt angle in the second alignment film 23 on the counter substrate 20 side are set to be the same. The shift amount increases as the elapsed time becomes longer. The relationship between the Vcom shift amount and the elapsed time is a proportional relationship. The Vcom shift amount is about +0.02 V when the elapsed time is 7200 s. On the other hand, the first pretilt angle (1.2 °) in the first alignment film 13 on the element substrate 10 side is smaller than the second pretilt angle (7.2 °) in the second alignment film 23 on the counter substrate 20 side. The Vcom shift amount in the set state “▲” decreases as the elapsed time becomes longer. The relationship between the Vcom shift amount and the elapsed time is a proportional relationship. The Vcom shift amount is about -0.03 V when the elapsed time is 7200 s. The first pretilt angle (1.2 °) in the first alignment film 13 on the element substrate 10 side is set to be smaller than the second pretilt angle (7.2 °) in the second alignment film 23 on the counter substrate 20 side. In the Vcom shift direction in the state “▲”, the first pretilt angle in the first alignment film 13 on the element substrate 10 side and the second pretilt angle in the second alignment film 23 on the counter substrate 20 side are the same over the entire elapsed time. Compared with the state “○” set to, the shift is in the negative direction. This confirms that the Vcom shift is −0.05 V when the difference between the first pretilt angle and the second pretilt angle is 6 °. Further, since the Vcom shift amount and the elapsed time are in a proportional relationship, it is conceivable that the Vcom shift is shifted by 0.01 V when the difference between the first pretilt angle and the second pretilt angle is shifted by 1 degree. .

  When the Vcom shift becomes larger than a certain level, the difference in the modulation effect of the liquid crystal layer increases between the low potential side period and the high potential side period. Then, in the displayed image, the difference between the amount of light modulated during the low potential side period and the amount of light modulated during the high potential side period is visually recognized, causing flickering of the image. End up.

  As a result of careful consideration based on knowledge from experimental data, the present inventor has come up with the idea that it is effective to divide and correct the correction for the first phenomenon and the correction for the second phenomenon. That is, as a correction method for the first phenomenon, a constant correction voltage is applied regardless of the drive voltage, and as a correction method for the second phenomenon, depending on the direction and magnitude of the DC voltage component due to the characteristic difference, In this method, the ratio of the period length in which the positive polarity is maintained is shorter than the ratio of the period length in which the negative polarity is maintained.

On the other hand, searching for a polar time ratio that minimizes the change in flicker over time (hereinafter simply referred to as “searching”) required an enormous amount of time. For example, the adjustment at the time of search required energization time of about 10 to 60 minutes per one measurement point.
However, the inventor sets the first pretilt angle in the first alignment film 13 on the element substrate 10 side to be smaller than the second pretilt angle in the second alignment film 23 on the counter substrate 20 side. Has been found to shift in the negative direction, it has become possible to shorten the time required for the search.

  FIG. 8 is a diagram showing the relationship between the time ratio (Duty) and the Vcom shift obtained by the search performed by the present inventor. In FIG. 8, the horizontal axis indicates Duty (time ratio between the application time of the positive polarity voltage and the application time of the negative polarity voltage), and the vertical axis indicates the Vcom shift (Vcom2−Vcom1). Here, the intersection of the horizontal axis and the vertical axis is Duty 50:50, and the right side of the horizontal axis is the direction in which the positive voltage application time becomes longer. The upper side of the vertical axis is the direction in which the Vcom shift is positive. Also, in FIG. 8, reference numeral P1 is the first (first) measurement point, reference numeral P2 is the second measurement point, reference sign P3 is the third measurement point, reference sign P4 is the fourth measurement point, reference sign P5 is the fifth measurement point. The (last) measurement point is shown. Further, in FIG. 8, the search is performed by measuring five times in total, but the number of measurements may be changed as necessary without being limited to this number.

  As shown in FIG. 8, the first measurement point P1 is arranged in an area where the duty is 50% or less. This point becomes clear from the above-described experimental results that the Vcom shift direction is shifted in the negative direction when the above-described dielectric film is disposed between the counter electrode 22 on the counter substrate 20 side and the second alignment film 23. . That is, since it becomes a downward-sloping line and the fifth measurement point P5 is smaller than the time ratio 50%, at least within the range excluding the region where the duty is larger than 50% (the duty is 50% or less). In the region). For this reason, it is not necessary to arrange the first measurement point P1 in a region where the duty is larger than 50%, and the measurement frequency can be reduced.

  Next, the second measurement point P2 is arranged on the smaller duty side than the first measurement point P1 across the horizontal axis. Thus, the positive / negative direction in which the parameter (Duty) is changed can be determined based on the first measurement result. That is, it is not necessary to arrange the second measurement point P2 on the larger duty side than the first measurement point P1, and the measurement frequency can be reduced. In addition, by plotting the first measurement point P1 and the second measurement point P2, it is possible to approximately calculate the slope of the right-downward line.

  Next, the third measurement point P3 is arranged between the first measurement point P1 and the horizontal axis along the approximately calculated inclination. Further, the fourth measurement point P4 is arranged between the second measurement point P2 and the horizontal axis along the approximately calculated inclination. In this way, the search range is narrowed while estimating the value of (Vcom2-Vcom1) at which the Vcom shift is approximately zero. By plotting the third measurement point P3 and the fourth measurement point P4, it is possible to approximately calculate the Vcom shift corresponding to the flicker tolerance.

  Then, the fifth measurement point P5 is arranged on the horizontal axis. Specifically, the fifth measurement point P5 is an intersection of a straight line and a horizontal axis that approximately connect the measurement points P1 to P4. From the above, it is possible to calculate the polar time ratio that minimizes the flicker change with time. Therefore, according to this adjustment method, the time required for searching can be shortened by reducing the measurement frequency.

(Driving method of liquid crystal device)
The driving method of the liquid crystal device described below has been created by the present inventor with careful consideration and ingenuity in order to realize the conceived contents specifically.
FIG. 9 is a timing chart of the scanning signal system when the designated value Q is “−1”. In the present embodiment, the plurality of scanning lines 61 are divided into the first scanning line group and the second scanning line group, and in one frame, any one scanning line 61 in the first scanning line group, Any one scanning line 61 in the two scanning line groups is alternately selected, and each scanning line 61 is selected twice in one frame. So-called double speed area scanning inversion driving is used.

  First, a method for driving the scanning line 61 will be described. FIG. 9 is a timing chart showing the scanning signals G1 to G480 output from the scanning line driving circuit 130 in relation to the start pulse and the clock signal. Here, the frame refers to a period required to display one image on the liquid crystal panel 100A. Further, a period from the output of the first start pulse Dya to the output of the second start pulse Dyb in the period of one frame (predetermined period) is defined as a first field (first period), and the second A period from when the start pulse Dyb is output until the next first start pulse Dya is output is defined as a second field (second period). One scanning line 61 is selected once for each field, that is, twice in one frame period.

  Since the vertical synchronization signal Vs in this embodiment has a frequency of 120 Hz as described above, the period of one frame is also fixed at 8.33 milliseconds. The control circuit 152 (see FIG. 1) outputs a clock signal having a duty ratio of 50% for 480 periods equal to the number of scanning lines 61 over a period of one frame. Note that a period of one cycle of the clock signal is denoted as H.

  Further, the control circuit 152 outputs a start pulse having a pulse width corresponding to one cycle of the clock signal when the clock signal rises to the H level as follows. That is, the control circuit 152 outputs the first start pulse Dya at the beginning of one frame period (the first field). On the other hand, since the designated value Q is a negative value, the control circuit 152 causes the second start pulse Dyb to be “Q” more than the timing Tm at which 240 cycles of the clock signal are output after the first start pulse Dya is output. Outputs “X” earlier.

  Therefore, as shown in FIG. 9, when the specified value Q is “−1”, the second start pulse Dyb is output at timing Tm (−1) preceding the timing Tm by one cycle of the clock signal. Is done.

  Here, while the start pulses are alternately output, the output timing of the first start pulse Dya is not changed regardless of the designated value Q. For this reason, if the first start pulse Dya output every frame (8.33 milliseconds) is specified, the second start pulse Dyb which inevitably defines the start of the second field can also be specified.

  The scanning line driving circuit 130 outputs the following operation signal from the start pulse and the clock signal. That is, when the first start pulse Dya is supplied, the scanning line driving circuit 130 sequentially sets the scanning signals G1 to G480 to the H level each time the clock signal changes to the L level. On the other hand, when the second start pulse Dyb is supplied, the scanning line driving circuit 130 sequentially sets the scanning signals G1 to G480 to the H level each time the clock signal changes to the H level.

  Since the first start pulse Dya is supplied at the beginning of one frame period (first field), the selection of the scanning line 61 triggered by the supply of the first start pulse Dya does not change depending on the designated value Q. Since the selection of the scanning line 61 triggered by the supply of the first start pulse Dya is executed in a period in which the clock signal is at the L level, the scanning of the first row over the first field and the second field is performed. It is executed with a half cycle period of the clock signal in the order of the second, third, fourth,.

  On the other hand, since the second start pulse Dyb is supplied at the beginning of the second field, the selection of the scanning line 61 triggered by the start pulse is entirely changed by the designated value Q. Since the selection of the scanning line 61 triggered by the supply of the second start pulse Dyb is executed during a period in which the clock signal is at the H level, 1 is selected from the second field of one frame to the first field of the next frame. Executed between the selections triggered by the supply of the first start pulse Dya in the order of rows 2, 3, 4,..., 480 from the scanning line 61 of the row toward the bottom of the screen. become. That is, selection of the 1st to 240th lines in the second field of a certain frame has a relationship that precedes the timing Tm by one cycle of the clock signal as a whole if the specified value Q is “−1”, for example. .

  FIG. 10 is a timing chart in the first field of the data signal Vid system. FIG. 11 is a timing chart in the second field of the data signal Vid system. Next, a method for driving the data line 62 will be described with reference to FIGS.

  The sampling signal output circuit 142 of the data line driving circuit 140 is in accordance with a control signal from the control circuit 152 over a period in which one of the scanning lines 61 is selected and the operation signal supplied to the scanning line 61 is at the H level. The sampling signals S1, S2, S3,..., S640 that sequentially become H level are output to each of the data lines 62. The control signal is actually a start pulse or a clock signal, but the description is omitted.

The period during which the scanning signal is at the H level is actually slightly narrower than the half period of the clock signal. In this case, as shown in FIG. 10, in the first field, after the scanning signal G (i + 240) becomes H level, the scanning signal Gi becomes H level.
Further, as shown in FIG. 11, in the second field, the scanning signal G (i + 240) becomes the H level after the scanning signal Gi becomes the H level.

  Further, the display data processing circuit 156 (see FIG. 1) displays the display data Video for one row on the selected scanning line 61 in accordance with the output of the sampling signals S1 to S640 by the sampling signal output circuit 142 as follows. Is converted to a data signal Vid having a correct polarity. That is, the display data processing circuit 156 converts the pixel data signal Vid in the selected pixel row to the positive polarity (+) when the clock signal is at the L level, and the pixel selected when the clock signal is at the H level. The pixel data signal Vid in the row is converted to negative polarity (-). In other words, the display data processing circuit 156 converts the pixel data signal Vid in the selected pixel row to the positive polarity (+) with the supply of the first start pulse Dya, and supplies the second start pulse Dyb. The pixel data signal Vid in the selected pixel row is converted into negative polarity (−).

  Here, the positive polarity (+) and the negative polarity (-) mean that the higher side from the reference voltage Vc is positive (+) and the lower side is negative (-). In addition, although the reference potential is set to 0 V here, the present invention is not limited to this.

  Further, the counter electrode potential Vcom is set to be shifted to the negative (−) side from the reference voltage Vc. Specifically, the counter electrode potential Vcom is set to a voltage value within a range of about −0.1 V to −0.2 V, for example. This is because the voltage fluctuation due to the first phenomenon (field-through) is about −0.1 V to −0.2 V, and this is used as the correction voltage, and the set value of the counter electrode potential Vcom is changed from the reference voltage Vc. This is because they are shifted. That is, the counter electrode potential Vcom is shifted so as to reduce the influence of the first phenomenon.

  In addition, the correction voltage in the first phenomenon is preferably obtained by measuring each individual liquid crystal panel 100A. Specifically, when the positive and negative drive voltages corresponding to the same gradation are alternately applied, the counter electrode potential Vcom at which the flicker is sufficiently small is obtained and corrected from the difference between the value and the reference voltage Vc. Find the voltage. In addition, the driving voltage at this time is preferably a voltage corresponding to an intermediate gradation in which flicker is easily visible.

  In this way, the correction voltage is obtained and set in the control circuit 152 (see FIG. 1) or the voltage generation circuit 160. Then, the voltage generation circuit 160 generates the counter electrode potential Vcom shifted by the correction voltage and supplies it to the counter electrode 22 of the liquid crystal panel 100A.

Next, the overall driving method will be described.
First, in FIG. 1, the control circuit 152 stores display data Video supplied from an external device in the frame memory 157. Thereafter, when the scanning line 61 of a certain pixel row is selected in the liquid crystal panel 100A, the display data Video of the pixel row is read at a speed twice the storage speed. Then, it is converted into an analog data signal Vid by the DA converter 158. At the same time, the sampling signal output circuit 142 is controlled via the control signal so that the sampling signals S1 to S640 sequentially become H level in accordance with the reading of the display data Video.

  As shown in FIG. 9, when the designated value Q is “−1”, for example, the second start pulse Dyb is output at a timing earlier than the timing Tm by one cycle of the clock signal. Therefore, if the designated value Q is “−1”, the period of the first field is 239 periods of the clock signal, whereas the period of the second field is 241 periods of the clock signal.

  In the first field, the scanning lines 61 are selected in the order of 242, 1, 243, 2, 244, 3,. Therefore, the control circuit 152 first controls the scanning line driving circuit 130 so that the scanning line 61 in the 242nd row is selected. On the other hand, the control circuit 152 causes the display data processing circuit 156 to read the display data Video corresponding to the 242nd row stored in the frame memory 157 at double speed. Then, the DA converter 158 generates a negative data signal Vid, and the sampling signals S1 to S640 are sequentially set to the H level exclusively as shown in FIG. 10 in accordance with the reading of the data signal Vid. The sampling signal output circuit 142 is controlled. When the sampling signals S1 to S640 are sequentially set to the H level, the TFTs 40 are sequentially turned on, and the data signal Vid supplied to the image signal lines is sampled on the data lines 62 in the 1st to 640th columns.

  On the other hand, when the scanning line 61 is selected, since the scanning signal G242 becomes H level, all the TFTs 40 of the pixels located in the 242nd row are turned on. Therefore, the negative voltage of the data signal Vid sampled on the data line 62 is applied to the pixel electrode 12 as it is. As a result, the negative voltage corresponding to the gradation specified by the display data Video is written in the liquid crystal capacitor 120 in the pixels of the 242nd row and the columns 1, 2, 3, 4,..., 639, 640. Held. Hereinafter, in the first field, the same voltage writing operation is executed in the order of 1, 2, 243, 2, 244, 3,. Thereby, a positive voltage corresponding to the gradation is written to the pixels in the first to 239th rows, and a negative voltage corresponding to the gradation is written to the pixels in the 240th to 480th rows. Retained respectively.

  On the other hand, in the second field, the scanning line 61 is selected in the order of 1, 240, 2, 241, 3, 242, ..., 241, 480th row, and the writing polarity in the same row is inverted. For this reason, a negative voltage corresponding to the gradation is written to the pixels in the first to 239th rows, and a positive voltage corresponding to the gradation is written to the pixels in the 240th to 480th rows. Retained respectively.

  FIG. 12 is a diagram showing the writing state of each row as time passes over successive frames when the designated value Q is “−1”. Note that the writing to the scanning line 61 at the top, that is, the start time of the positive polarity holding period, is precisely the timing preceding the half cycle of the clock signal after the first start pulse Dya is supplied. In FIG. 12, it is simplified and matched with the first start pulse Dya.

  As shown in FIG. 12, in the first field, negative writing is performed on the pixels in the 242, 243, 244,..., 480th rows, and positive writing is performed on the pixels in the 1, 2, 3,. Is held until the next writing. On the other hand, negative-polarity writing is performed on the pixels in the first, second, third,..., And 241st rows in the second field, and positive-polarity writing is performed on the pixels on the 242nd, 243, 244,. Until the next write. That is, it can be understood that two scanning lines 61 for writing positive polarity and two scanning lines 61 for writing negative polarity are selected in each field.

  Thus, when the designated value Q is “−1”, the output timing of the second start pulse Dyb is advanced. Therefore, the holding time of the negative voltage written by the selection triggered by the supply of the second start pulse Dyb is longer than the holding time of the positive voltage written by the selection triggered by the supply of the first start pulse Dya. Become. That is, if the specified value Q is a negative value, as the absolute value thereof increases, the negative voltage holding time written by selection triggered by the supply of the second start pulse Dyb is the first start pulse Dya. It becomes longer than the holding time of the positive voltage written by the selection triggered by the supply. For this reason, the negative voltage effective value applied to the liquid crystal capacitor 120 exceeds the positive voltage effective value.

  That is, the first field to which the positive voltage is applied is shorter than the second field to which the negative voltage is applied. Therefore, since the application time of the positive voltage in one frame is set shorter than the application time of the negative voltage, correction corresponding to the Vcom shift can be effectively performed.

(How to determine the time ratio)
The Vcom shift is considered to occur because a potential difference is induced by accumulation of charges due to a difference in polarity of current. The relational expression between the accumulated charge amount and current (voltage, resistance) is as follows. When the application time ratio of the positive voltage is (1 + X), the application time ratio of the negative voltage is (1-X), and the application time is T, Equations 1 and 2 are obtained. Here, the positive accumulated charge amount is q +, the negative accumulated charge amount is q−, the current is i, the voltage is v, and the resistance is R.

  According to this idea, the Vcom shift can be prevented by controlling the amount of accumulated charge per unit time. An optimal time distribution ratio can be estimated from the rectangular wave amplitude during energization and the Vcom shift at that time. In order to satisfy q + = q−, when the application time ratio of the positive voltage is (1 + X) and the application time ratio of the negative voltage is (1−X), the following expressions 3 and 4 are obtained. Here, the rectangular wave amplitude is E, and the Vcom shift is δV. The Vcom shift is a difference between the counter electrode potential Vcom1 before the shift and the counter electrode potential Vcom2 after the shift, that is, a value of Vcom2−Vcom1.

  For example, when the rectangular wave amplitude applied to the pixel electrode 12 is ± 5 V and the Vcom shift is −0.05 V, X = −0.005. For this reason, if the application time of positive polarity voltage: application time of negative polarity voltage = 49.5: 50.5, the shift of Vcom does not occur.

  From the experiment results of the present inventor, it is empirically known that the Vcom shift corresponding to the flicker tolerance is ± 0.15 V when the frame rate is 120 fps. Therefore, in practice, X may be set to −0.020 to 0.010. Therefore, when the first pretilt angle is set to be 6 ° smaller than the second pretilt angle, the ratio of the length of the first field to the length of the second field is 49.0 / 51.0 or more and 52.0 / What is necessary is just to set to the range of 48.0 or less. That is, the application time of the positive polarity voltage: the application time of the negative polarity voltage = 48.0: 52.0 to 52.0: 48.0. However, since it is assumed that the length of the first field is set shorter than the length of the second field, the ratio between the length of the first field and the length of the second field is 50.0 / 50. It is set to a range larger than 0.0 and not more than 52.0 / 48.0. When the frame rate is 120 fps, since one frame period is 8.3 milliseconds, application time of positive voltage: application time of negative voltage = 8.42 milliseconds: 8.25 milliseconds to 8.92 milliseconds: 7.75 milliseconds.

  According to the liquid crystal device 100 according to the present embodiment, the counter electrode potential Vcom is shifted and set in advance so as to reduce the flicker caused by the parasitic capacitance of the switching element, so that the correction for the first phenomenon is incorporated. It is. In addition, since the length of the first period of the predetermined period is set shorter than the length of the second period, correction for the second phenomenon is included. In this correction, the inventor sets the first pretilt angle in the first alignment film 13 on the element substrate 10 side to be smaller than the second pretilt angle in the second alignment film 23 on the counter substrate 20 side ( This is because the effective voltage waveform is shifted in the negative direction of the potential by setting the first pretilt angle closer to the vertical orientation than the second pretilt angle. This point has also been confirmed from the results of experiments conducted by the present inventors. That is, the first pretilt angle in the first alignment film 13 on the element substrate 10 side is set to be smaller than the second pretilt angle in the second alignment film 23 on the counter substrate 20 side. Compared with the case where the pretilt angles are the same, it is clear that Vcom shifts in the negative direction (the counter electrode potential Vcom2 after the shift is shifted in the negative direction from the counter electrode potential Vcom1 before the shift). As described above, since the shift direction of the Vcom shift is determined in advance, the correction for the Vcom shift can be accurately performed as compared to the case where the shift direction is uncertain as in the prior art. Therefore, it is possible to provide the liquid crystal device 100 capable of improving display quality by suppressing occurrence of display defects such as flicker.

  Further, according to this configuration, it is clear that Vcom shifts in the negative direction as compared with the case where the pixel electrode 12 and the counter electrode 22 are made of the same material (for example, ITO). The characteristic asymmetry becomes remarkable. This point has also been confirmed from the results of experiments conducted by the present inventors. For this reason, compared with the case where the pixel electrode 12 and the counter electrode 22 are made of, for example, ITO, a direct-current voltage component due to the characteristic difference between the element substrate 10 and the counter substrate 20 sandwiching the liquid crystal layer is significantly generated. . Therefore, it is possible to improve display quality by suppressing the occurrence of display defects such as flicker.

  According to the driving method of the liquid crystal device 100 according to the present embodiment, the counter electrode potential Vcom is set in advance so as to reduce flicker due to the parasitic capacitance of the switching element. Correction is incorporated. In addition, since the length of the first period of the predetermined period is set shorter than the length of the second period, correction for the second phenomenon is also incorporated. This correction is made by the inventor that the first pretilt angle in the first alignment film 13 on the element substrate 10 side is set smaller than the second pretilt angle in the second alignment film 23 on the counter substrate 20 side. This is because the effective voltage waveform has been found to shift in the negative direction of the potential. This point has also been confirmed from the results of experiments conducted by the present inventors. Therefore, it is possible to improve display quality by suppressing the occurrence of display defects such as flicker.

  Further, according to the driving method of the liquid crystal device 100, since the optimal time distribution ratio corresponding to the flicker tolerance is obtained, the second phenomenon can be effectively corrected. On the other hand, if the ratio between the length of the first period and the length of the second period is smaller than 50.0 / 50.0, the length of the first period is too long and effective correction is achieved. May not be. In addition, when the ratio of the length of the first period to the length of the second period is larger than 52.0 / 48.0, the length of the first period is too short to be an effective correction. There is.

  In the present embodiment, the case where the first pretilt angle in the first alignment film 13 on the element substrate 10 side is set smaller than the second pretilt angle in the second alignment film 23 on the counter substrate 20 side is taken as an example. However, this is not restrictive. Hereinafter, a liquid crystal panel including an alignment film having a different form from the present embodiment will be described with reference to FIG.

(Second Embodiment)
FIG. 13 is a cross-sectional view illustrating a schematic configuration of a liquid crystal panel 100B according to the second embodiment. FIG. 13 is a cross-sectional view showing a schematic configuration of a liquid crystal panel 100B corresponding to FIG. In the liquid crystal panel 100B according to the present embodiment, the first pretilt angle in the first alignment film 13A on the element substrate 10A side is set larger than the second pretilt angle in the second alignment film 23A on the counter substrate 20A side (first). The second pretilt angle is set closer to the vertical alignment than the first pretilt angle), and is different from the liquid crystal panel 100A in the first embodiment. In FIG. 13, elements similar to those in FIG. 5 are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIG. 13, the liquid crystal panel 100B includes an element substrate 10A, a counter substrate 20A disposed to face the element substrate 10A, and a liquid crystal layer sandwiched therebetween. The element substrate 10A includes a substrate body 11 made of a translucent material such as glass and quartz, the TFT 40 and the pixel electrode 12 formed on the inside (liquid crystal layer side), a first alignment base film 38A and a first alignment film 1 alignment film 13A etc. are provided. One counter substrate 20A includes a substrate body 21 made of a translucent material such as glass or quartz, a light shielding film 24 formed on the inner side (liquid crystal layer side), a counter electrode 22 covering the light shielding film 24, and further A second alignment base film 38B and a second alignment film 23A are provided.

  The pixel electrode 12 is provided on the element substrate 10A side, and the first alignment film 13A is provided on the upper side. The pixel electrode 12 is made of a conductive film such as aluminum (Al). The thickness of the pixel electrode 12 is, for example, not less than 180 nm and not more than 220 nm. The thickness of the first alignment film 13A is, for example, not less than 40 nm and not more than 80 nm. Further, the first pretilt angle in the first alignment film 13A with respect to the thickness direction of the element substrate 10A is, for example, 7.2 °.

  On the other hand, a counter electrode 22A is provided on the entire surface of the counter substrate 20A, and a second alignment film 23A is provided on the upper side thereof. The counter electrode 22A is made of a transparent conductive film such as an ITO film. The thickness of the counter electrode 22A is, for example, not less than 120 nm and not more than 160 nm. The film thickness of the second alignment film 23A is, for example, not less than 40 nm and not more than 80 nm. In addition, the second pretilt angle with respect to the thickness direction of the counter substrate 20A in the second alignment film 23A is, for example, 1.2 °.

  In the present embodiment, the first pretilt angle (7.2 °) in the first alignment film 13A on the element substrate 10A side is greater than the second pretilt angle (1.2 °) in the second alignment film 23A on the counter substrate 20A side. Is also set larger. Note that the first pretilt angle is reduced by making the vapor deposition rate when forming the first alignment film 13A on the element substrate 10A side smaller than the vapor deposition rate when forming the second alignment film 23A on the counter substrate 20A side. Can be made larger than the second pretilt angle.

  FIG. 14 is a diagram showing a chart showing gate voltage and drive voltage waveforms according to the second embodiment. FIG. 14A is a chart showing the gate voltage and drive voltage waveforms corresponding to FIG. FIG. 14B is a chart showing the effective voltage waveform of the liquid crystal layer corresponding to FIG. FIG. 14C is a chart showing the effective voltage waveform of the liquid crystal layer after a certain amount of driving time has elapsed from FIG. 14B, corresponding to FIG. The effective voltage waveform of the liquid crystal layer in the present embodiment is different from the effective voltage waveform of the liquid crystal layer in the first embodiment in that it shifts in the negative potential direction after a certain amount of driving time has elapsed. 14, elements similar to those in FIG. 6 are denoted by the same reference numerals, and detailed description thereof is omitted. Note that in FIGS. 14A to 14C, the horizontal axis indicates the passage of time, and the vertical axis indicates the potential.

  As shown in FIG. 14A, the potential of the drive voltage waveform VD is switched between a high potential EH (for example, 12 V) and a low potential EL (for example, 2 V) alternately in synchronization with the rising of the gate voltage VG. It has become.

  As shown in FIG. 14B, when the gate voltage VG rises, the switching element is turned on and the pixel electrode 12 is charged. The potential of the effective voltage waveform VL1 of the liquid crystal layer generally rises from the low potential EL to the high potential EH.

  As shown in FIG. 14C, the effective voltage waveform VL2 after driving the liquid crystal layer for a certain period often shifts from the effective voltage waveform VL1 immediately after the start of driving. Note that the effective voltage waveform VL2 may be shifted in either the positive or negative direction of the potential, but FIG. 14C illustrates a state in which the effective voltage waveform VL2 is shifted in the positive direction. Consider a counter electrode potential Vcom2 that is optimized to balance positive and negative with respect to the shifted effective voltage waveform VL2. The counter electrode potential Vcom2 after the shift is shifted in the positive direction from the counter electrode potential Vcom1 before the shift.

  Here, in the conventional technique, it is uncertain whether the effective voltage waveform VL2 shifts in the positive or negative direction of the potential. That is, it is uncertain whether the counter electrode potential Vcom2 after the shift is shifted in the positive or negative direction from the counter electrode potential Vcom1 before the shift.

  However, the inventor of the present invention sets the first pretilt angle in the first alignment film 13A on the element substrate 10A side to be larger than the second pretilt angle in the second alignment film 23A on the counter substrate 20A side (second pretilt angle). By setting the angle closer to the vertical orientation than the first pretilt angle), the effective voltage waveform VL2 optimized to balance positive and negative shifts in the positive direction of the potential (Vcom shift in the positive direction). I found out to shift. This point is also estimated from the results of experiments conducted by the inventor (see FIG. 7).

  When the Vcom shift becomes larger than a certain level, the difference in the modulation effect of the liquid crystal layer increases between the low potential side period and the high potential side period. Then, in the displayed image, the difference between the amount of light modulated during the low potential side period and the amount of light modulated during the high potential side period is visually recognized, causing flickering of the image. End up.

  As a result of careful consideration based on knowledge from experimental data, the present inventor has come up with the idea that it is effective to divide and correct the correction for the first phenomenon and the correction for the second phenomenon. That is, as a correction method for the first phenomenon, a constant correction voltage is applied regardless of the drive voltage, and as a correction method for the second phenomenon, depending on the direction and magnitude of the DC voltage component due to the characteristic difference, In this method, the ratio of the period length in which the positive polarity is maintained is made longer than the ratio of the period length in which the negative polarity is maintained.

On the other hand, searching for a polar time ratio that minimizes the change in flicker over time (hereinafter simply referred to as “searching”) required an enormous amount of time. For example, the adjustment at the time of search required energization time of about 10 to 60 minutes per one measurement point.
However, the inventor has set the effective voltage by setting the first pretilt angle in the first alignment film 13A on the element substrate 10A side to be larger than the second pretilt angle in the second alignment film 23A on the counter substrate 20A side. By finding that the waveform VL2 shifts in the positive direction of the potential, the time required for the search can be shortened.

  FIG. 15 is a diagram showing the relationship between the time ratio (Duty) and the Vcom shift obtained by the search performed by the present inventor. In FIG. 15, the horizontal axis indicates Duty (time ratio between the application time of the positive voltage and the application time of the negative voltage), and the vertical axis indicates the Vcom shift (Vcom2−Vcom1). Here, the intersection of the horizontal axis and the vertical axis is Duty 50:50, and the right side of the horizontal axis is the direction in which the positive voltage application time becomes longer. The upper side of the vertical axis is the direction in which the Vcom shift is positive. In FIG. 15, reference sign P1 is the first (first) measurement point, reference sign P2 is the second measurement point, reference sign P3 is the third measurement point, reference sign P4 is the fourth measurement point, reference sign P5 is the fifth measurement point. The (last) measurement point is shown. In FIG. 15, the search is performed by measuring a total of five times, but the number of measurements may be changed as necessary without being limited to this number of times.

  As shown in FIG. 15, the first measurement point P1 is arranged in a region where the duty is 50% or more. This point is clarified from the experimental results described above because the Vcom shift direction is shifted in the positive direction when the above-described dielectric film is disposed between the pixel electrode 12 on the element substrate 10 side and the first alignment film 13. . That is, since it is a line that falls to the right and the fifth measurement point P5 is larger than Duty 50%, at least within the range excluding the region where Duty is smaller than 50% (region where Duty is 50% or more) )). For this reason, it is not necessary to arrange the first measurement point P1 in an area where the duty is smaller than 50%, and the measurement frequency can be reduced.

  Next, the second measurement point P2 is arranged in a region where the duty is larger than the first measurement point P1 across the horizontal axis. Thus, the positive / negative direction in which the parameter (Duty) is changed can be determined based on the first measurement result. In other words, it is not necessary to arrange the second measurement point P2 on the smaller duty side than the first measurement point P1, and the measurement frequency can be reduced. In addition, by plotting the first measurement point P1 and the second measurement point P2, it is possible to approximately calculate the slope of the right-downward line.

  Next, the third measurement point P3 is arranged between the first measurement point P1 and the horizontal axis along the approximately calculated inclination. Further, the fourth measurement point P4 is arranged between the second measurement point P2 and the horizontal axis along the approximately calculated inclination. In this way, the search range is narrowed while estimating the value of (Vcom2-Vcom1) at which the Vcom shift is approximately zero. By plotting the third measurement point P3 and the fourth measurement point P4, it is possible to approximately calculate the Vcom shift corresponding to the flicker tolerance.

  Then, the fifth measurement point P5 is arranged on the horizontal axis. Specifically, the fifth measurement point P5 is an intersection of a straight line and a horizontal axis that approximately connect the measurement points P1 to P4. From the above, it is possible to calculate the polar time ratio that minimizes the flicker change with time. Therefore, according to this adjustment method, the time required for searching can be shortened by reducing the measurement frequency.

(Driving method of liquid crystal device)
The driving method of the liquid crystal device described below has been created by the present inventor with careful consideration and ingenuity in order to realize the conceived contents specifically.
FIG. 16 is a timing chart of the scanning signal system when the designated value Q is “+1”. In the present embodiment, the plurality of scanning lines 61 are divided into the first scanning line group and the second scanning line group, and in one frame, any one scanning line 61 in the first scanning line group, Any one scanning line 61 in the two scanning line groups is alternately selected, and each scanning line 61 is selected twice in one frame. So-called double speed area scanning inversion driving is used. In this embodiment, the operator 170 (see FIG. 1) is operated by a user or the like, for example, and outputs a designated value Q corresponding to the operation in a range from “0” to “+10”, for example. ing.

  First, a method for driving the scanning line 61 will be described. FIG. 16 is a timing chart showing the scanning signals G1 to G480 output from the scanning line driving circuit 130 in relation to the start pulse and the clock signal. Here, the frame refers to a period required to display one image on the liquid crystal panel 100A. Further, a period from the output of the first start pulse Dya to the output of the second start pulse Dyb in the period of one frame (predetermined period) is defined as a first field (first period), and the second A period from when the start pulse Dyb is output until the next first start pulse Dya is output is defined as a second field (second period). One scanning line 61 is selected once for each field, that is, twice in one frame period.

  Since the vertical synchronization signal Vs in this embodiment has a frequency of 120 Hz as described above, the period of one frame is also fixed at 8.33 milliseconds. The control circuit 152 (see FIG. 1) outputs a clock signal having a duty ratio of 50% for 480 periods equal to the number of scanning lines 61 over a period of one frame. Note that a period of one cycle of the clock signal is denoted as H.

  Further, the control circuit 152 outputs a start pulse having a pulse width corresponding to one cycle of the clock signal when the clock signal rises to the H level as follows. That is, the control circuit 152 outputs the first start pulse Dya at the beginning of one frame period (the first field). On the other hand, since the designated value Q is a negative value, the control circuit 152 causes the second start pulse Dyb to be “Q” more than the timing Tm at which 240 cycles of the clock signal are output after the first start pulse Dya is output. Output is delayed by “× H”.

  Therefore, as shown in FIG. 16, when the designated value Q is “+1”, the second start pulse Dyb is output at timing Tm (+1) delayed by one cycle of the clock signal from timing Tm. .

  Here, while the start pulses are alternately output, the output timing of the first start pulse Dya is not changed regardless of the designated value Q. For this reason, if the first start pulse Dya output every frame (8.33 milliseconds) is specified, the second start pulse Dyb which inevitably defines the start of the second field can also be specified.

  The scanning line driving circuit 130 outputs the following operation signal from the start pulse and the clock signal. That is, when the first start pulse Dya is supplied, the scanning line driving circuit 130 sequentially sets the scanning signals G1 to G480 to the H level each time the clock signal changes to the L level. On the other hand, when the second start pulse Dyb is supplied, the scanning line driving circuit 130 sequentially sets the scanning signals G1 to G480 to the H level each time the clock signal changes to the H level.

  Since the first start pulse Dya is supplied at the beginning of one frame period (first field), the selection of the scanning line 61 triggered by the supply of the first start pulse Dya does not change depending on the designated value Q. Since the selection of the scanning line 61 triggered by the supply of the first start pulse Dya is executed in a period in which the clock signal is at the L level, the scanning of the first row over the first field and the second field is performed. It is executed with a half cycle period of the clock signal in the order of the second, third, fourth,.

On the other hand, since the second start pulse Dyb is supplied at the beginning of the second field, the selection of the scanning line 61 triggered by the start pulse is entirely changed by the designated value Q. Since the selection of the scanning line 61 triggered by the supply of the second start pulse Dyb is executed during a period in which the clock signal is at the H level, 1 is selected from the second field of one frame to the first field of the next frame. Executed between the selections triggered by the supply of the first start pulse Dya in the order of rows 2, 3, 4,..., 480 from the scanning line 61 of the row toward the bottom of the screen. become. That is, the selection of the 1st to 240th rows in the second field of a certain frame has a relationship delayed as much as one cycle of the clock signal from the timing Tm if the specified value Q is “+1”, for example.
Since the driving method of the data line 62 is the same as that of the first embodiment, the detailed description thereof is omitted (see FIGS. 10 and 11).

Next, the overall driving method will be described.
First, in FIG. 1, the control circuit 152 stores display data Video supplied from an external device in the frame memory 157. Thereafter, when the scanning line 61 of a certain pixel row is selected in the liquid crystal panel 100A, the display data Video of the pixel row is read at a speed twice the storage speed. Then, it is converted into an analog data signal Vid by the DA converter 158. At the same time, the sampling signal output circuit 142 is controlled via the control signal so that the sampling signals S1 to S640 sequentially become H level in accordance with the reading of the display data Video.

  As shown in FIG. 16, when the designated value Q is “+1”, for example, the second start pulse Dyb is output at a timing later in time by one cycle of the clock signal than the timing Tm. Therefore, if the designated value Q is “+1”, the period of the first field is 241 periods of the clock signal, whereas the period of the second field is 239 periods of the clock signal.

  In the first field, the scanning lines 61 are selected in the order of 240, 1, 241, 2, 242, 3,. Therefore, the control circuit 152 first controls the scanning line driving circuit 130 so that the scanning line 61 in the 240th row is selected. On the other hand, the control circuit 152 causes the display data processing circuit 156 to read the display data Video corresponding to the 240th row stored in the frame memory 157 at double speed. Then, the DA converter 158 generates a negative data signal Vid, and the sampling signals S1 to S640 are sequentially set to the H level exclusively as shown in FIG. 10 in accordance with the reading of the data signal Vid. The sampling signal output circuit 142 is controlled. When the sampling signals S1 to S640 are sequentially set to the H level, the TFTs 40 are sequentially turned on, and the data signal Vid supplied to the image signal lines is sampled on the data lines 62 in the 1st to 640th columns.

  On the other hand, when the scanning line 61 is selected, the scanning signal G240 becomes H level, so that all the TFTs 40 of the pixels located in the 240th row are turned on. Therefore, the negative voltage of the data signal Vid sampled on the data line 62 is applied to the pixel electrode 12 as it is. As a result, the negative voltage corresponding to the gradation specified by the display data Video is written into the liquid crystal capacitor 120 in the pixels of the 240th row and the columns 1, 2, 3, 4,..., 639, 640. Held. Hereinafter, in the first field, the same voltage writing operation is executed in the order of the 1st, 241, 242, 242,. Thereby, a positive voltage corresponding to the gradation is written to the pixels in the 1st to 241st rows, and a negative voltage corresponding to the gradation is written to the pixels in the 242nd to 480th rows. Retained respectively.

  On the other hand, in the second field, the scanning line 61 is selected in the order of the 1st, 24th, 2nd, 24th, 3rd, 244th,... For this reason, a negative voltage corresponding to the gradation is written to the pixels in the 1st to 241st rows, and a positive voltage corresponding to the gradation is written to the pixels in the 242nd to 480th rows. Retained respectively.

  FIG. 17 is a diagram showing the writing state of each row as time passes over successive frames when the designated value Q is “+1”. Note that the writing to the scanning line 61 at the top, that is, the start time of the positive polarity holding period, is precisely the timing delayed by a half cycle of the clock signal after the first start pulse Dya is supplied. In FIG. 17, it is simplified and matched with the first start pulse Dya.

  As shown in FIG. 17, in the first field, pixels having 240, 241, 242,..., 480th row are written with negative polarity, and pixels in rows 1, 2, 3,. Is held until the next writing. On the other hand, in the second field, negative polarity writing is performed on the pixels in the first, second, third,..., 239th rows, and positive polarity writing is performed on the pixels in the 240th, 241, 242,. Until the next write. That is, it can be understood that two scanning lines 61 for writing positive polarity and two scanning lines 61 for writing negative polarity are selected in each field.

  Thus, when the designated value Q is “+1”, the output timing of the second start pulse Dyb is delayed. Therefore, the holding time of the negative voltage written by the selection triggered by the supply of the second start pulse Dyb is shorter than the holding time of the positive voltage written by the selection triggered by the supply of the first start pulse Dya. Become. That is, if the specified value Q is a positive value, the holding time of the negative voltage written by selection triggered by the supply of the second start pulse Dyb increases as the absolute value increases. It becomes shorter than the holding time of the positive voltage written by the selection triggered by the supply. For this reason, the negative voltage effective value applied to the liquid crystal capacitor 120 is lower than the positive voltage effective value.

  That is, the first field to which the positive voltage is applied is longer than the second field to which the negative voltage is applied. Therefore, since the application time of the positive polarity voltage is set longer than the application time of the negative polarity voltage in one frame, the correction corresponding to the Vcom shift can be effectively performed.

  According to the liquid crystal device according to the present embodiment, the counter electrode potential Vcom is shifted and set in advance so as to reduce the flicker caused by the parasitic capacitance of the switching element, so that the correction for the first phenomenon is incorporated. ing. In addition, since the length of the first period of the predetermined period is set longer than the length of the second period, correction for the second phenomenon is included. This correction is performed by the inventor so that the first pretilt angle in the first alignment film 13A on the element substrate 10A side is set larger than the second pretilt angle in the second alignment film 23A on the counter substrate 20A side (first 2) that the pre-tilt angle is set closer to the vertical orientation than the first pre-tilt angle), the effective voltage waveform shifts in the positive direction of the potential. This point is also estimated from the results of experiments conducted by the present inventors. That is, the first pretilt angle and the second pretilt angle in the first alignment film 13A on the element substrate 10A side are set larger than the second pretilt angle in the second alignment film 23A on the counter substrate 20A side. Compared to the case where the pretilt angles are the same, it is clear that Vcom shifts in the positive direction (the counter electrode potential Vcom2 after the shift is shifted in the positive direction from the counter electrode potential Vcom1 before the shift). As described above, since the shift direction of the Vcom shift is determined in advance, the correction for the Vcom shift can be accurately performed as compared to the case where the shift direction is uncertain as in the prior art. Therefore, it is possible to provide a liquid crystal device capable of improving the display quality by suppressing the occurrence of display defects such as flicker.

  Further, according to this configuration, it is clear that Vcom shifts in the positive direction as compared with the case where the pixel electrode 12 and the counter electrode 22 are made of the same material (for example, ITO), and the element substrate 10A and the counter substrate 20A The characteristic asymmetry becomes remarkable. This point is also estimated from the results of experiments conducted by the present inventors. For this reason, compared with the case where the pixel electrode 12 and the counter electrode 22 are made of, for example, ITO, a DC voltage component due to the characteristic difference between the element substrate 10A holding the liquid crystal layer and the counter substrate 20A is significantly generated. . Therefore, it is possible to improve display quality by suppressing the occurrence of display defects such as flicker.

  According to the driving method of the liquid crystal device according to the present embodiment, the counter electrode potential Vcom is shifted and set in advance so as to reduce the flicker caused by the parasitic capacitance of the switching element. Is included. In addition, since the length of the first period of the predetermined period is set longer than the length of the second period, correction for the second phenomenon is also incorporated. This correction is performed by the inventor when the first pretilt angle in the first alignment film 13A on the element substrate 10A side is set larger than the second pretilt angle in the second alignment film 23A on the counter substrate 20A side. This is because the effective voltage waveform has been found to shift in the positive direction of the potential. This point is also estimated from the results of experiments conducted by the present inventors. Therefore, it is possible to improve display quality by suppressing the occurrence of display defects such as flicker.

(Electronics)
FIG. 19 is a schematic diagram illustrating a schematic configuration of a projector that is an example of an electronic apparatus using the liquid crystal panel 100A (100B) described above as a light valve. As shown in FIG. 19, the projector 1 includes a light source 2, an integrator optical system 3, a color separation optical system 4, three systems of image forming systems 5, a color composition element 6, and a projection optical system 7. As three image forming systems 5, a first image forming system 5a, a second image forming system 5b, and a third image forming system 5c are provided. The projector 1 generally operates as follows.

  The light source light emitted from the light source 2 enters the integrator optical system 3. The light source light incident on the integrator optical system 3 is emitted with uniform illuminance and uniform polarization. The light source light emitted from the integrator optical system 3 is separated into a plurality of color lights by the color separation optical system 4 and enters the image forming system 5 of a different system for each color light. The color light incident on each of the three image forming systems 5 is modulated based on the image data of the image to be displayed and becomes modulated light. The three colors of modulated light emitted from the three image forming systems 5 are combined by the color combining element 6 to become multicolor light and enter the projection optical system 7. The polychromatic light incident on the projection optical system 7 is projected onto a projection surface (not shown) such as a screen. Thereby, a full-color image is displayed on the projection surface.

Next, components of the projector 1 will be described in detail.
The light source 2 includes a light source lamp 2a and a parabolic reflector 2b. The light emitted from the light source lamp 2a is reflected in one direction by the parabolic reflector 2b to become a substantially parallel light bundle, and enters the integrator optical system 3 as light source light. The light source lamp 2a is constituted by, for example, a metal halide lamp, a xenon lamp, a high-pressure mercury lamp, a halogen lamp, or the like. Moreover, you may comprise a reflector with an elliptic reflector, a spherical reflector, etc. instead of the paraboloid reflector 2b. Depending on the shape of the reflector, a collimating lens that collimates the light emitted from the reflector may be used.

  The integrator optical system 3 includes a first lens array, a second lens array, an incident side aperture stop, a polarization conversion element, and a superimposing lens. The optical axis of the integrator optical system 3 is substantially coincident with the optical axis of the light source 2, and each of the components of the integrator optical system 3 is arranged so that the center position is aligned with the optical axis of the integrator optical system 3. Has been.

  The color separation optical system 4 includes first to third dichroic mirrors having wavelength selection surfaces, and first and second reflection mirrors. The first dichroic mirror has characteristics of reflecting red light and transmitting green light and blue light. The second dichroic mirror has characteristics of transmitting red light and reflecting green light and blue light. The third dichroic mirror has characteristics of reflecting green light and transmitting blue light. The first and second dichroic mirrors are arranged so that each wavelength selection plane is substantially orthogonal to each other, and each wavelength selection plane is at an angle of about 45 ° with the optical axis of the integrator optical system 3. Yes.

The red light L10, the green light L20, and the blue light L30 included in the light source light incident on the color separation optical system 4 are separated in the following manner, and are supplied to the image forming system 5 corresponding to each separated color light. Incident.
The light L10 is transmitted through the second dichroic mirror, reflected by the first dichroic mirror, then reflected by the first reflecting mirror, and enters the first image forming system 5a.
The light L20 is transmitted through the first dichroic mirror and reflected by the second dichroic mirror, then reflected by the second reflecting mirror, and then reflected by the third dichroic mirror, and the second image forming system 5b. Is incident on.
The light L30 is transmitted through the first dichroic mirror, reflected by the second dichroic mirror, then reflected by the second reflective mirror, and then transmitted through the third dichroic mirror, thereby causing the third image forming system 5c to be transmitted. Is incident on.

  The three colors of modulated light emitted from the three image forming systems 5 are combined by the color combining element 6 to become multicolor light and enter the projection optical system 7. The polychromatic light incident on the projection optical system 7 is projected onto a projection surface (not shown) such as a screen. Thereby, a full-color image is displayed on the projection surface.

  According to this electronic apparatus, since the above-described liquid crystal device 100 is provided, it is possible to provide an electronic apparatus that can improve display quality by suppressing the occurrence of display defects such as flicker.

  Other electronic devices include, for example, mobile phones, personal computers, video camera monitors, car navigation devices, pagers, electronic notebooks, calculators, word processors, workstations, videophones, POS terminals, digital still cameras, Examples include a device equipped with a touch panel. The liquid crystal device 100 according to the present invention can also be applied to these electronic devices.

Further, in the above-described embodiment, the voltage corresponding to the gradation is sequentially sampled from the data signal Vid of the first column to the 640th column with respect to the pixels along the scanning line 61 of one row. The so-called dot-sequential configuration in which the pixels are sequentially written from the first column to the 640th column is not limited to this. For example, the data signal Vid is expanded by n (n is an integer of 2 or more) on the time axis, and the so-called phase expansion (also referred to as serial-parallel conversion) driving for supplying to n image signal lines is used together. (See JP 2000-112437 A).
Alternatively, a so-called line-sequential configuration in which data signals Vid are collectively supplied to all the data lines 62 may be employed.
Even with these driving methods, it is possible to obtain the same functions and effects as in the above embodiment.
In the above-described embodiment, a description is given of a mode in which either a normally black mode that displays black when no voltage is applied or a normally white mode that displays white when no voltage is applied is applied as the liquid crystal mode. However, the present invention can also be applied to another different liquid crystal mode.

DESCRIPTION OF SYMBOLS 1 ... Projector (electronic device) 10, 10A ... Element substrate, 12 ... Pixel electrode, 13, 13A ... 1st orientation film, 20, 20A ... Opposite substrate, 22 ... Counter electrode, 23, 23A ... 2nd orientation film, 40 ... TFT (switching element), 61 ... scanning line, 62 ... data line, 100 ... liquid crystal device, Vcom ... counter electrode potential

Claims (7)

An element substrate comprising a plurality of scanning lines, a plurality of data lines, and switching elements and pixel electrodes provided corresponding to the intersections of the scanning lines and the data lines;
A counter substrate having a counter electrode disposed opposite to the element substrate;
A liquid crystal layer sandwiched between the element substrate and the counter substrate;
A first alignment film provided on the liquid crystal layer side of the element substrate;
A second alignment film provided on the liquid crystal layer side of the counter substrate,
A first pretilt angle in the first alignment film is set to be smaller than a second pretilt angle in the second alignment film;
The counter electrode is applied with a counter electrode potential set to reduce flicker due to parasitic capacitance of the switching element,
The pixel electrode is applied with the positive voltage and the negative voltage alternately when the high voltage is positive and the low voltage is negative with reference to the counter electrode potential,
In a predetermined period composed of a first period in which the positive voltage is applied and a second period in which the negative voltage is applied, the length of the first period is the second period. A liquid crystal device characterized in that it is set shorter than the length of the LCD. An element substrate comprising a plurality of scanning lines, a plurality of data lines, and switching elements and pixel electrodes provided corresponding to the intersections of the scanning lines and the data lines;
A counter substrate having a counter electrode disposed opposite to the element substrate;
A liquid crystal layer sandwiched between the element substrate and the counter substrate;
A first alignment film provided on the liquid crystal layer side of the element substrate;
A second alignment film provided on the liquid crystal layer side of the counter substrate,
A first pretilt angle in the first alignment film is set to be larger than a second pretilt angle in the second alignment film;
The counter electrode is applied with a counter electrode potential set to reduce flicker due to parasitic capacitance of the switching element,
The pixel electrode is applied with the positive voltage and the negative voltage alternately when the high voltage is positive and the low voltage is negative with reference to the counter electrode potential,
In a predetermined period composed of a first period in which the positive voltage is applied and a second period in which the negative voltage is applied, the length of the first period is the second period. A liquid crystal device characterized in that it is set longer than the length of the liquid crystal device.   The liquid crystal device according to claim 1, wherein the pixel electrode is made of Al, and the counter electrode is made of ITO. An element substrate comprising a plurality of scanning lines, a plurality of data lines, and switching elements and pixel electrodes provided corresponding to the intersections of the scanning lines and the data lines;
A counter substrate having a counter electrode disposed opposite to the element substrate;
A liquid crystal layer sandwiched between the element substrate and the counter substrate;
A first alignment film provided on the liquid crystal layer side of the element substrate;
A second alignment film provided on the liquid crystal layer side of the counter substrate,
A driving method of a liquid crystal device, wherein a first pretilt angle in the first alignment film is set smaller than a second pretilt angle in the second alignment film,
Applying a counter electrode potential set to reduce flicker due to parasitic capacitance of the switching element to the counter electrode,
When the high voltage is positive and the low voltage is negative with respect to the counter electrode potential as a reference, the positive voltage and the negative voltage are alternately applied to the pixel electrode,
In a predetermined period consisting of a first period in which the positive voltage is applied and a second period in which the negative voltage is applied, the length of the first period is set to the second period. A method for driving a liquid crystal device, characterized in that it is set shorter than the length of the liquid crystal device. An element substrate comprising a plurality of scanning lines, a plurality of data lines, and switching elements and pixel electrodes provided corresponding to the intersections of the scanning lines and the data lines;
A counter substrate having a counter electrode disposed opposite to the element substrate;
A liquid crystal layer sandwiched between the element substrate and the counter substrate;
A first alignment film provided on the liquid crystal layer side of the element substrate;
A second alignment film provided on the liquid crystal layer side of the counter substrate,
A liquid crystal device driving method in which a first pretilt angle in the first alignment film is set larger than a second pretilt angle in the second alignment film,
Applying a counter electrode potential set to reduce flicker due to parasitic capacitance of the switching element to the counter electrode,
When the high voltage is positive and the low voltage is negative with respect to the counter electrode potential as a reference, the positive voltage and the negative voltage are alternately applied to the pixel electrode,
In a predetermined period consisting of a first period in which the positive voltage is applied and a second period in which the negative voltage is applied, the length of the first period is set to the second period. A method of driving a liquid crystal device, characterized in that it is set longer than the length of the liquid crystal device.   When the first pretilt angle is set 6 ° smaller than the second pretilt angle, the ratio of the length of the first period to the length of the second period is 50.0 / 50.0. 5. The method of driving a liquid crystal device according to claim 4, wherein the range of 52.0 / 48.0 or less is set. An electronic apparatus comprising the liquid crystal device according to claim 1.

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