JP2011204773A - Method of manufacturing nonvolatile semiconductor memory device, and nonvolatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a nonvolatile semiconductor memory device reducing malfunctions of transistors caused by a coupling capacitance when reducing a space between vertically adjacent transistors in a configuration with the transistors three-dimensionally arranged, and the nonvolatile semiconductor memory device.SOLUTION: The method of manufacturing the nonvolatile semiconductor memory device includes the step of forming a plurality of structures, in each of which at least a plurality of second semiconductor films are respectively held by semiconductor or conductor columnar members via gate insulating films, in a laminated film formed by alternately laminating fist semiconductor films and the second semiconductor films on a semiconductor substrate a plurality of times, the removing step of selectively removing the plurality of first semiconductor films from the laminated film while maintaining the state that the plurality of second semiconductor films are held by the columnar members in each of the plurality of structures formed in the forming step, and the embedding step of embedding an interlayer insulating film so that cavities are left among the plurality of second semiconductor films in each of the plurality of structures passed through the removing step.

Description

  The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device, and a nonvolatile semiconductor memory device.

  Non-volatile semiconductor memory devices, particularly high-integration memories such as flash memories, products for which high integration of memory elements (memory cells) does not remain, and products using fine elements with a minimum processing dimension of about 30 nm or less Has been developed. The improvement of integration by reducing the minimum processing dimension will increase the physical limit of increasing the variation of transistor operation within the device, and the cost of lithography process and processing process will increase rapidly. It is about to reach an economic limit. Therefore, in order to realize further high integration, introduction of a technique for arranging memory elements (memory cells) in a three-dimensional manner has been demanded.

  In Non-Patent Document 1, a plurality of gate plates (control gates) are stacked on a silicon substrate via an insulating film, a plurality of holes penetrating the plurality of gate plates are opened, and then an ONO film is formed in each hole. , Silicon is sequentially deposited. Thus, according to Non-Patent Document 1, it is said that a BiCS (Bit Cost Scalable) flash memory having a plurality of memory strings in which memory cells accessible by a control gate are connected in the vertical direction can be obtained.

  In Non-Patent Document 2, a multiple active layer in which a plurality of interlayer insulating films and polysilicon are alternately stacked is formed and patterned on a substrate, and then an ONO film and a plurality of layers are formed on the side surface of the patterned multiple active layer. The vertical word lines are sequentially formed. Thus, according to Non-Patent Document 2, it is said that a VG (Vertical Gate) NAND flash memory in which a plurality of active strings in which memory cells are respectively connected in the horizontal direction is stacked can be obtained.

  In these three-dimensional memory cell (transistor) arrangements, if the spacing between adjacent transistors in the vertical direction is reduced to improve the memory cell (transistor) arrangement density, the coupling capacitance between the adjacent transistors in the vertical direction is reduced. Cannot be ignored. In the technique of Non-Patent Document 1, when the interval between adjacent transistors in the vertical direction is reduced, the coupling capacitance between the stacked control gates is not negligible. In the technique of Non-Patent Document 2, when the interval between transistors adjacent in the vertical direction is reduced, the coupling capacitance between the stacked polysilicons (active regions) becomes a size that cannot be ignored. As a result, the potential of the control gate or the active region becomes unstable due to the coupling capacitance between the adjacent transistors in the vertical direction, and the transistor may malfunction.

  On the other hand, if the interval between transistors adjacent in the vertical direction is increased in order to weaken the coupling capacitance between the transistors adjacent in the vertical direction, it becomes difficult to improve the arrangement density of the memory cells (transistors). In the technique of Non-Patent Document 1, if the insulating film between the stacked control gates is formed thick, the number of memory cells (transistors) that can be arranged in the vertical direction is reduced. Even in the technique of Non-Patent Document 2, when the insulating film between the stacked polysilicons (active regions) is formed thick, the number of memory cells (transistors) that can be arranged in the vertical direction is reduced.

H. Tanaka et al., Symp. On VLSI Tech. Dig., Pp14-15, 2007 W. Kim, et. Al., Symp. On VLSI Tech. Dig., Pp188-189, 2009

  The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device that can reduce malfunction of a transistor due to coupling capacitance when a distance between adjacent transistors in the vertical direction is reduced in a three-dimensionally arranged transistor. An object of the present invention is to provide a nonvolatile semiconductor memory device.

  According to one embodiment of the present invention, at least a plurality of second semiconductor films in a stacked film in which a first semiconductor film and a second semiconductor film are alternately stacked a plurality of times on a semiconductor substrate are gate insulating films. Forming a plurality of structures each held by a columnar member of a semiconductor or a conductor, and the plurality of second semiconductor films for each of the plurality of structures formed in the forming step A removal step of selectively removing the plurality of first semiconductor films from the stacked film while maintaining the state held by the columnar member, and a plurality of the first in each of the plurality of structures that have undergone the removal step There is provided a method for manufacturing a nonvolatile semiconductor memory device, comprising a step of embedding an interlayer insulating film so as to leave a cavity between the two semiconductor films.

  According to one embodiment of the present invention, a semiconductor substrate, a plurality of semiconductor films stacked on the semiconductor substrate at intervals in a direction perpendicular to the surface of the semiconductor substrate, and a charge storage capability, respectively A plurality of gate insulating films respectively disposed in side surfaces of the plurality of semiconductor films, and extending in a direction perpendicular to the surface of the semiconductor substrate; A plurality of columnar members of a semiconductor or a conductor each holding the plurality of semiconductor films via an insulating film, and an interlayer insulating film having a cavity in each region between the plurality of semiconductor films A non-volatile semiconductor memory device is provided.

  According to one embodiment of the present invention, a semiconductor substrate, a plurality of semiconductor films stacked on the semiconductor substrate at intervals in a direction perpendicular to the surface of the semiconductor substrate, and a charge storage capability, respectively A plurality of gate insulating films respectively disposed on peripheral surfaces of the plurality of semiconductor films, each of which penetrates the plurality of semiconductor films and faces each hole penetrating the plurality of semiconductor films; A plurality of semiconductor columnar members each penetrating the film and holding the plurality of semiconductor films via the gate insulating film; and an interlayer insulating film having a cavity in each region between the plurality of semiconductor films A non-volatile semiconductor memory device is provided.

  According to the present invention, in a configuration in which transistors are arranged three-dimensionally, a nonvolatile semiconductor memory device that can reduce malfunction of transistors due to coupling capacitance when the interval between vertically adjacent transistors is reduced Obtainable.

1 is a diagram showing a configuration of a nonvolatile semiconductor memory device according to a first embodiment. 1 is a diagram showing a configuration of a nonvolatile semiconductor memory device according to a first embodiment. FIG. 3 is a diagram showing a method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment. FIG. 3 is a diagram showing a method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment. FIG. 3 is a diagram showing a method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment. FIG. 3 is a diagram showing a method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment. FIG. 3 is a diagram showing a method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment. FIG. 3 is a diagram showing a method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment. FIG. 3 is a diagram showing a method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment. FIG. 3 is a diagram showing a method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment. FIG. 6 is a diagram showing a method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment. FIG. 6 is a diagram showing a method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment. The figure which shows the structure of the non-volatile semiconductor memory device concerning 3rd Embodiment. FIG. 10 is a diagram showing a method for manufacturing the nonvolatile semiconductor memory device according to the third embodiment. FIG. 10 is a diagram showing a method for manufacturing the nonvolatile semiconductor memory device according to the third embodiment.

  Hereinafter, a nonvolatile semiconductor memory device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

(First embodiment)
The configuration of the nonvolatile semiconductor memory device 1 according to the first embodiment will be described with reference to FIGS. FIG. 1A is a perspective view showing a configuration of the nonvolatile semiconductor memory device 1. FIG. 1B is a diagram showing an equivalent circuit in the nonvolatile semiconductor memory device 1. FIG. 2A is a diagram showing a cross section including a word line in the nonvolatile semiconductor memory device 1. FIG. 2B is a diagram illustrating a cross section that does not include the word line in the nonvolatile semiconductor memory device 1. 2A and 2B, a four-layer semiconductor film is shown, but in FIG. 1A, the third and fourth semiconductor films are omitted for the sake of simplicity. is doing. In the following, the description will focus on the three rows of semiconductor films shown in the cross-sectional views of FIGS. 1A, 2A, and 2B, but the configuration is repeatedly arranged on the left and right in FIG. Is the same.

  The nonvolatile semiconductor memory device 1 includes a semiconductor substrate SB, a plurality of semiconductor films (a plurality of second semiconductor films) 12a-1 to 12d-3 (see FIG. 2A), and a plurality of gate insulating films 31-11 to 31-11. 32-32, a plurality of columnar members 21-1 to 22-4, a plurality of word lines WL1, WL2, and an interlayer insulating film 40 (see FIG. 2B).

  The semiconductor substrate SB is made of, for example, silicon.

  The plurality of semiconductor films 12a-1 to 12d-3 are stacked on the semiconductor substrate SB with an interval in a direction perpendicular to the surface SBa of the semiconductor substrate SB. The stacked semiconductor films 12a-1, 12b-1, 12c-1, and 12d-1 (aligned in a direction perpendicular to the surface SBa of the semiconductor substrate SB) have columnar members 21-1 and 21- on both side surfaces, respectively. 2 between. Other stacked semiconductor films are the same as the stacked semiconductor films 12a-1, 12b-1, 12c-1, and 12d-1. Each of the semiconductor films 12a-1 to 12d-3 is formed of a material containing silicon as a main component, for example, single crystal silicon.

  Specifically, the first-layer semiconductor films 12a-1, 12a-2, and 12a-3 are arranged at positions spaced apart from each other by a distance D (see FIG. 2) in a direction perpendicular to the surface SBa of the semiconductor substrate SB. Yes. The first semiconductor films 12a-1, 12a-2, 12a-3 extend along the surface SBa of the semiconductor substrate SB (for example, in parallel), and are aligned with each other (for example, in parallel with each other). . The first semiconductor films 12a-1, 12a-2, and 12a-3 have, for example, a substantially rectangular parallelepiped shape.

  The second-layer semiconductor films 12b-1, 12b-2, and 12b-3 are spaced from each other in the direction D perpendicular to the first-layer semiconductor films 12a-1, 12a-2, and 12a-3 (see FIG. 2). It is arranged at a position separated from each other. The second-layer semiconductor films 12b-1, 12b-2, and 12b-3 extend along the surface SBa of the semiconductor substrate SB (for example, in parallel), and are aligned with each other (for example, in parallel with each other). . The second-layer semiconductor films 12b-1, 12b-2, 12b-3 have, for example, a substantially rectangular parallelepiped shape. The third-layer semiconductor films 12c-1, 12c-2, and 12c-3 are the same as the second-layer semiconductor films 12b-1, 12b-2, and 12b-3.

  The upper surfaces of the fourth semiconductor films 12d-1, 12d-2, and 12d-3 are covered with silicon nitride films 13-1, 13-2, and 13-3, respectively. In other respects, the fourth-layer semiconductor films 12d-1, 12d-2, and 12d-3 are the same as the second-layer semiconductor films 12b-1, 12b-2, and 12b-3. As structurally shown in FIG. 1A, between the silicon nitride films 13-1, 13-2, 13-3 and the uppermost semiconductor films 12d-1, 12d-2, 12d-3. Alternatively, a structure formed at a predetermined interval may be used.

  Here, each of the semiconductor films 12a-1 to 12d-3 functions as an active region. That is, in each of the semiconductor films 12a-1 to 12d-3, a portion intersecting with the columnar members 21-1 to 22-4 becomes a channel region of the transistor, and portions adjacent to both sides of the portion are the source region of the transistor or It becomes a drain region.

  For example, in the semiconductor film 12a-1, the portions intersecting with the columnar members 21-1 and 22-1 are channel regions of the transistors M1 and M2 (see FIG. 1B), respectively. For example, if the transistors M1 and M2 are NMOS transistors (PMOS transistors), the semiconductor film 12a-1 has a source region (drain region) that is adjacent to the source line side with respect to the intersecting portion. A portion adjacent to the portion on the bit line side becomes a drain region (source region). The semiconductor film 12a-1 has a source line (not shown) connected to one end in the longitudinal direction and a bit line (not shown) connected to the other end.

  Similarly, for example, in the semiconductor film 12b-1, the portions intersecting with the columnar members 21-1 and 22-1 are channel regions of the transistors M3 and M4 (see FIG. 1B), respectively. For example, if the transistors M3 and M4 are NMOS transistors (PMOS transistors), the semiconductor film 12b-1 has a source region (drain region) that is adjacent to the source line side with respect to the intersecting portion. A portion adjacent to the portion on the bit line side becomes a drain region (source region). The semiconductor film 12b-1 has a source line (not shown) connected to one end in the longitudinal direction and a bit line (not shown) connected to the other end.

  Each of the plurality of gate insulating films 31-11 to 32-32 extends in a direction perpendicular to the surface SBa of the semiconductor substrate SB. Each of the plurality of gate insulating films 31-11 to 32-32 is disposed on the side surfaces of the plurality of semiconductor films 12a-1 to 12d-3. For example, the gate insulating film 31-11 is disposed on the side surfaces of the stacked semiconductor films 12a-1, 12b-1, 12c-1, and 12d-1 (see FIG. 2A). The other gate insulating films 31-12 to 32-32 are similar to the gate insulating film 31-11.

  Each of the gate insulating films 31-11 to 32-32 includes a charge storage film having charge storage capability. Each gate insulating film 31-11 to 32-32 is formed of, for example, an ONO film. The ONO film has a three-layer structure in which two silicon oxide films sandwich a silicon nitride film. Each of the gate insulating films 31-11 to 32-32 includes the silicon nitride film in the ONO film as a charge storage film, and can store charges in the silicon nitride film.

  In the gate insulating film 31-11, the charge storage films (silicon nitride films) in the portions 310-1, 31ab-1, and 31bc-1 that do not intersect the semiconductor films 12a-1 and 12b-1 are the semiconductor films 12a- 1, 12b-1 is formed of a material (composition) containing more oxygen than the charge storage film (silicon nitride film) in the portions 31a-1 and 31b-1 intersecting with each other. Thereby, in the gate insulating film 31-11, the charge storage capability of the portions 310-1, 31ab-1, and 31bc-1 that do not intersect the semiconductor films 12a-1 and 12b-1 is the same as that of the semiconductor films 12a-1 and 12b. -1 is lower than the charge storage ability of the portions 31a-1 and 31b-1. The other gate insulating films 31-12 to 32-32 are similar to the gate insulating film 31-11.

  Each of the plurality of columnar members 21-1 to 22-4 extends in a direction perpendicular to the surface SBa of the semiconductor substrate SB. Each of the plurality of columnar members 21-1 to 22-4 holds the plurality of semiconductor films 12a-1 to 12d-3 via the gate insulating films 31-11 to 32-32. For example, the columnar member 21-1 includes a plurality of stacked semiconductor films 12a-1, 12b-1, 12c-1, and 12d-1 (see FIG. 2A) via the gate insulating film 31-11. keeping. The other columnar members 21-2 to 22-4 are the same as the columnar member 21-1. Each of the columnar members 21-1 to 22-4 is formed of a semiconductor (for example, a material mainly containing silicon). Each of the columnar members 21-1 to 22-4 is made of, for example, polysilicon. Each of the columnar members 21-1 to 22-4 may be formed of a conductor (for example, a material containing tungsten as a main component). Each of the columnar members 21-1 to 22-4 may be formed of, for example, tungsten silicide.

  Here, each of the columnar members 21-1 to 22-4 functions as a control gate of the transistor. For example, in the columnar member 21-1, the portions intersecting with the semiconductor films 12a-1 and 12b-1 are the control gates of the transistors M1 and M3, respectively. For example, in the columnar member 22-1, the portions intersecting with the semiconductor films 12a-1 and 12b-1 are the control gates of the transistors M2 and M4, respectively.

  Each of the plurality of word lines WL1 and WL2 extends along the surface SBa of the semiconductor substrate SB (for example, in parallel) in a direction crossing the longitudinal direction of each of the semiconductor films 12a-1 to 12d-3. The word line WL1 connects a plurality of columnar members 21-1 to 21-4 arranged in a line along the surface SBa of the semiconductor substrate SB. The word line WL2 connects a plurality of columnar members 22-1 to 22-4 arranged in a line along the surface SBa of the semiconductor substrate SB. The word line WL1 is formed of a conductive material and has, for example, a two-layer structure in which a polysilicon layer WL1b and a nickel silicon layer WL1a are sequentially stacked. The word line WL2 is the same as the word line WL1.

  The interlayer insulating film 40 is buried around the semiconductor substrate SB, the plurality of semiconductor films 12a-1 to 12d-3, the plurality of columnar members 21-1 to 22-4, and the word lines WL1 and WL2 (FIG. 2 ( b)). The interlayer insulating film 40 has cavities V21 to V43 in each region between the plurality of semiconductor films 12a-1 to 12d-3. Furthermore, the interlayer insulating film 40 has cavities V11 to V13 in a region between the semiconductor substrate SB and the first semiconductor films 12a-1 to 12a-3. The interlayer insulating film 40 is made of, for example, silicon oxide. Each of the cavities V11 to V43 has a substantially rectangular parallelepiped shape.

  As described above, the nonvolatile semiconductor memory device 1 has a configuration in which transistors are three-dimensionally arranged.

  Here, suppose that the interlayer insulating film 40 does not have the cavities V21 to V43 in each region between the plurality of semiconductor films 12a-1 to 12d-3. In this case, in the arrangement of the three-dimensional memory cells (transistors) of the nonvolatile semiconductor memory device 1, in order to improve the arrangement density of the memory cells (transistors), if the interval between adjacent transistors in the vertical direction is reduced, the vertical direction The coupling capacitance between adjacent transistors cannot be ignored. For example, in the configuration shown in FIG. 1B, when the interval between the transistor M1 and the transistor M3 adjacent in the vertical direction is reduced, the stacked semiconductor film (active region) 12a-1 and semiconductor film (active region) 12b- The coupling capacity C13 between 1 and 1 is not negligible. As a result, the potentials of the active regions (back gate, source region, drain region, channel region, etc.) of the transistors M1 and M3 are unstable due to the coupling capacitance between the transistors M1 and M3 adjacent in the vertical direction. Therefore, the transistors M1 and M3 may malfunction.

  On the other hand, in the first embodiment, the interlayer insulating film 40 has cavities V21 to V43 in each region between the plurality of semiconductor films 12a-1 to 12d-3. As a result, even when the interval between the transistors adjacent in the vertical direction is reduced, the coupling capacitance between the transistors adjacent in the vertical direction can be easily reduced to a level at which it can be ignored. For example, in the configuration shown in FIG. 1B, the stacked semiconductor film (active region) 12a-1 and the semiconductor film (active region) even if the distance between the transistor M1 and the transistor M3 adjacent in the vertical direction becomes small. Since the cavity V21 (see FIG. 2A) is formed between the semiconductor film (active region) 12a-1 and the semiconductor film (active region) 12b-1, a coupling capacitance is formed between the semiconductor film (active region) 12b-1 and the cavity V21. C13 can be easily reduced to a negligible level. That is, according to the first embodiment, in a configuration in which transistors are arranged three-dimensionally, when the interval between adjacent transistors in the vertical direction is reduced, transistor malfunction due to coupling capacitance can be reduced. .

  Alternatively, if the interlayer insulating film 40 does not have the cavities V21 to V43 in the regions between the plurality of semiconductor films 12a-1 to 12d-3, the coupling capacitance between the transistors adjacent in the vertical direction. In order to weaken the above, consider a case where the interval between vertically adjacent transistors is increased. In this case, it is difficult to improve the arrangement density of the memory cells (transistors). That is, when the interlayer insulating film 40 between the stacked polysilicons (active regions) is formed thick, the number of memory cells (transistors) that can be arranged in the vertical direction is reduced.

  On the other hand, in the first embodiment, a cavity V21 (see FIG. 2A) is formed between the laminated semiconductor film (active region) 12a-1 and semiconductor film (active region) 12b-1. Therefore, it is possible to weaken the coupling capacitance between the transistors adjacent in the vertical direction without increasing the interval between the transistors adjacent in the vertical direction, and to improve the arrangement density of the memory cells (transistors). It becomes easy.

  Alternatively, consider a case where the charge storage capability of the gate insulating film 31-11 is uniform. In this case, when the interval between transistors adjacent in the vertical direction is reduced, charge may move between the transistors adjacent in the vertical direction. For example, if the charge storage capabilities of the portions 31a-1, 31ab-1, and 31b-1 in the gate insulating film 31-11 are equal, the charge stored in the portion 31a-1 in the gate insulating film 31-11 is reduced. It can be easily moved to the portion 31b-1 via the portion 31ab-1. Alternatively, the charge accumulated in the portion 31b-1 in the gate insulating film 31-11 can easily move to the portion 31a-1 through the portion 31ab-1. That is, in the configuration shown in FIG. 1B, when the distance between the transistors M1 and M3 adjacent in the vertical direction becomes small, it is easy to connect between the transistor M1 and the transistor M3, as indicated by a dashed line arrow. Charge transfer may occur. As a result, in a configuration in which transistors are three-dimensionally arranged, when the interval between adjacent transistors in the vertical direction is reduced, the transistors M1 and M3 may malfunction due to charge movement (leakage current).

  In contrast, in the first embodiment, the charge storage capability of the portions 310-1, 31ab-1, and 31bc-1 of the gate insulating film 31-11 that do not intersect the semiconductor films 12a-1 and 12b-1 However, the charge storage capability of the portions 31a-1 and 31b-1 intersecting with the semiconductor films 12a-1 and 12b-1 is lower. As a result, even when the interval between the transistors adjacent in the vertical direction is reduced, the charge hardly moves between the transistors adjacent in the vertical direction. As a result, in a configuration in which transistors are three-dimensionally arranged, when the interval between adjacent transistors in the vertical direction is reduced, transistor malfunction due to charge movement (leakage current) can be reduced.

  Next, a method for manufacturing the nonvolatile semiconductor memory device 1 according to the first embodiment will be described with reference to FIGS. The perspective views shown in FIG. 3A to FIG. 9A correspond to the perspective view of FIG. The cross-sectional views shown in FIGS. 3B to 9B, 6D, 10A, and 10C correspond to the cross-sectional view of FIG. 3 (b) to 9 (b), 6 (d), 10 (a), and 10 (c) are respectively cross-sectional views shown in FIGS. 3 (c) to 9 (c) and 6 (c). e) shows a cross section formed by a one-dot chain line in the plan views of FIGS. 10 (b) and 10 (d).

  In the steps shown in FIGS. 3A to 3C, a stacked film SF in which the first semiconductor film and the second semiconductor film are alternately stacked a plurality of times is formed on the semiconductor substrate SB. Specifically, the first semiconductor film 11a1 is deposited on the semiconductor substrate SB. The first semiconductor film 11a1 is formed of a material containing silicon germanium as a main component. For example, the first semiconductor film 11a1 is formed of single crystal silicon germanium by using an epitaxial growth technique. A second semiconductor film 12a1 is deposited on the first semiconductor film 11a1. The second semiconductor film 12a1 is formed of a material containing silicon as a main component. The second semiconductor film 12a1 is formed of single crystal silicon using, for example, an epitaxial growth technique. By repeating the same processing, the first semiconductor film 11a1 to the second semiconductor film 12d1 are sequentially stacked on the semiconductor substrate SB. Then, a silicon nitride film 131 is deposited on the second semiconductor film 12d1. Thus, the first semiconductor film 11a1, the second semiconductor film 12a1, the first semiconductor film 11b1, the second semiconductor film 12b1, the first semiconductor film 11c1, the second semiconductor film 12c1, and the first semiconductor film. A stacked film SF in which 11d1, the second semiconductor film 12d1, and the silicon nitride film 131 are stacked in this order is obtained.

  FIG. 3B illustrates the case where the stacked film SF includes four layers of the second semiconductor films 12a1 to 12d1, but the stacked film SF includes a multilayer second semiconductor film. Even in this case, there is no significant difference in the manufacturing method.

  In the steps shown in FIGS. 4A to 4C, a first resist pattern (not shown) including a plurality of first line patterns aligned with each other (for example, in parallel with each other) is stacked by a photolithography process. It is formed on the film SF. Then, the stacked film SF is etched by dry etching (for example, RIE) using the first resist pattern as a mask. Thereby, a plurality of laminated films SF1 to SF3 are formed. Thereafter, the first resist pattern is removed.

  Each of the stacked films SF1 to SF3 has a fin shape extending in a direction perpendicular to the surface SBa of the semiconductor substrate SB. In the stacked film SF1, the first semiconductor film and the second semiconductor film are alternately stacked a plurality of times. That is, in the stacked film SF1, the first semiconductor film 11a-1, the second semiconductor film 12a-1, the first semiconductor film 11b-1, the second semiconductor film 12b-1, and the first semiconductor film 11c- 1, the second semiconductor film 12c-1, the first semiconductor film 11d-1, the second semiconductor film 12d-1, and the silicon nitride film 13-1 are sequentially stacked. The other laminated films SF2 and SF3 are the same as the laminated film SF1.

  In the steps shown in FIGS. 5A to 5C, a gate insulating film 311 is formed so as to cover the semiconductor substrate SB and the plurality of stacked films SF1 to SF3. The gate insulating film 311 is formed by, for example, an ONO film. Specifically, a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially deposited on the entire surface. As a result, a gate insulating film 311 having a three-layer structure in which two silicon oxide films sandwich a silicon nitride film is formed.

  6A to 6E, a predetermined film is embedded so as to cover the gate insulating film 311, and the upper surface is planarized by a CMP method or the like to form the film 20 (FIGS. 6B and 6). c)). The film 20 is formed of a semiconductor (for example, a material containing silicon as a main component). The film 20 is made of, for example, polysilicon. Note that the film 20 may be formed of a conductor (for example, a material containing tungsten as a main component). The film 20 may be formed of tungsten silicide, for example.

  Then, a second resist pattern (not shown) including a plurality of second line patterns that are aligned with each other (for example, parallel to each other) and extend in a direction intersecting with each of the stacked films SF1 to SF3 by a photolithography process. Is formed on the membrane 20. Then, the film 20 is etched by dry etching (for example, RIE) using the second resist pattern as a mask. Thus, a plurality of columnar members 21-1 to 22-4 and a plurality of word lines WL11 and WL21 are formed (see FIGS. 6D and 6E).

  7A to 7C, portions of the gate insulating film 311 that are not covered with the plurality of columnar members 21-1 to 22-4 and the plurality of word lines WL11 and WL21 are selectively removed. . That is, the gate insulating film 311 is etched by dry etching (for example, RIE) and / or wet etching using the plurality of word lines WL11 and WL21 as a mask. Thereby, a plurality of gate insulating films 31-111 to 32-321 are formed.

  Thereafter, the vapor phase diffusion method is applied to the exposed side surfaces of the first semiconductor films 11a-1 to 11d-3 and the side surfaces of the second semiconductor films 12a-1 to 12d-3 in the stacked films SF1 to SF3. A source region and a drain region (not shown) are formed by implanting an impurity by an ion implantation method or the like, and an activation heat treatment is performed.

  As described above, in the process (formation process) illustrated in FIGS. 3 to 7, at least the plurality of second semiconductor films 12 a-1 to 12 d-3 in the stacked films SF <b> 1 to SF <b> 3 are gate insulating films 31-11 to 13-321. A plurality of structures ST1 to ST6 (see FIG. 7B) respectively held by the columnar members 21-1 to 22-4 are formed. For example, in the structure ST1, the plurality of first semiconductor films 11a-1 to 11d-1 and the plurality of second semiconductor films 12a-1 to 12d-1 (see FIG. 4B) in the stacked film SF1 are gate-insulated. It is held by the columnar member 21-1 through the film 31-111. The other structures ST2 to ST6 are the same as the structure ST1.

  In the process (removal process) shown in FIGS. 8A to 8C, a plurality of second semiconductor films 12a-1 to 12d-3 are provided for each of the structures ST1 to ST6 (see FIG. 7B). Are selectively removed from the stacked films SF1 to SF3 while maintaining the state held by the columnar members 21-1 to 22-4. For example, in the structure ST1, the plurality of second semiconductor films 12a-1 to 12d-1 are maintained from the stacked member SF1 (see FIG. 4B) while maintaining the state held by the columnar member 21-1. The first semiconductor films 11a-1 to 11d-1 are selectively removed.

  Specifically, the first semiconductor film 11a-1 is formed by at least one of dry etching using high-temperature HCl gas and wet etching using acid such as SPM (mixed solution treatment of sulfuric acid and hydrogen peroxide solution). ˜11d-3 (silicon germanium) is selectively etched away. At this time, the first semiconductor films 11a-1 to 11d-3 (silicon germanium) with respect to the second semiconductor films 12a-1 to 12d-3 (silicon) have a first etching selectivity ratio sufficiently high. The germanium concentration contained in the semiconductor films 11a-1 to 11d-3 (silicon germanium) can be 30 at% or more.

  Thereby, a plurality of structures ST1a to ST6a having undergone the removal step are obtained. For example, in the structure ST1a after the removal process, cavities V21 to V41 are formed between the plurality of second semiconductor films 12a-1 to 12d-1. Further, in the structure ST1a after the removal step, a cavity V11 is formed between the lowermost second semiconductor film 12a-1 and the semiconductor substrate SB.

  In the steps (oxidation step) shown in FIGS. 9A to 9C, the exposed surfaces of each of the plurality of structures ST1a to ST6a (see FIG. 8B) that have undergone the removal step are exposed by a thermal oxidation method or the like. Oxidize. For example, in the plurality of structures ST1a that have undergone the removal step, the exposed upper and lower surfaces of the second semiconductor films 12a-1 to 12c-1 and the exposed lower surface of the second semiconductor film 12d-1 are oxidized. . Thereby, an oxide film (thermal oxide film) 50 covering the exposed surfaces of the plurality of second semiconductor films 12a-1 to 12d-1 is formed.

  Further, the exposed surface of the gate insulating film 31-111 is oxidized. Of the gate insulating film (ONO film) 31-111, the regions in contact with the first semiconductor films (silicon germanium) 11a-1 to 11d-1 are directly subjected to thermal oxidation treatment. As the silicon nitride film becomes a silicon oxide film, the charge storage capability of the silicon nitride film can be reduced. That is, the charge storage film (silicon nitride film) in the portions 310-1, 31ab-1, 31bc-1, and 31cd-1 that do not intersect with the second semiconductor films 12a-1 to 12d-1 A material (composition) containing more oxygen than the charge storage film (silicon nitride film) in the portions 31a-1, 31b-1, 31c-1, and 31d-1 crossing the semiconductor films 12a-1 to 12d-1 The gate insulating film 31-11 is formed. Thereby, in the obtained gate insulating film 31-11, the charge accumulation of the portions 310-1, 31ab-1, 31bc-1, and 31cd-1 that do not intersect with the second semiconductor films 12a-1 to 12d-1 The capability is lower than the charge storage capability of the portions 31a-1, 31b-1, 31c-1, and 31d-1 intersecting with the second semiconductor films 12a-1 to 12d-1. The other gate insulating films 31-12 to 32-32 are similar to the gate insulating film 31-11.

  In the process (embedding process) shown in FIGS. 10A and 10B, the plurality of second semiconductor films 12a-1 to 12A-1 in each of the plurality of structures ST1a to ST6a (see FIG. 8B) that have undergone the removal process. The interlayer insulating film 40 is embedded so as to leave the cavities V21 to V43 between 12d-3. Specifically, the interlayer insulating film 40 is formed on a region sandwiched between the word lines WL11 and WL21 when viewed from a direction perpendicular to the surface SBa of the semiconductor substrate SB by a plasma CVD process having relatively poor step coverage. Embed. For example, an insulating film is embedded in a region sandwiched between the word line WL11 and the word line WL21 (see FIG. 10B), and the upper surface of the insulating film embedded by a CMP method or the like is planarized to form the interlayer insulating film 40. Form. By using such a process, cavities V21 to V43 remain in a region surrounded by the columnar members 21-1 to 22-4 and the second semiconductor films 12a-1 to 12d-3. For example, the cavities V21 to V41 remain in the region surrounded by the columnar members 21-1 and 21-2 and the second semiconductor films 12a-1 to 12d-1. In addition, cavities V11, V12, and V13 remain between the lowermost second semiconductor films 12a-1, 12a-2, and 12a-3 and the semiconductor substrate SB. Thereby, the interlayer insulating film 40 is formed so as to fill around the semiconductor substrate SB, the plurality of semiconductor films 12a-1 to 12d-3, the plurality of columnar members 21-1 to 22-4, and the word lines WL11 and WL21 ( FIG. 2 (b)). The interlayer insulating film 40 is made of, for example, silicon oxide.

  In the steps shown in FIGS. 10C and 10D, the upper portions of the word lines WL11 and WL21 are made into metal silicide (for example, nickel silicide) by a salicide process. Thereby, for example, a word line WL1 in which a polysilicon layer WL1b and a nickel silicon layer WL1a are sequentially stacked is formed.

  Here, in the process shown in FIGS. 4A to 4C, a member that holds any side surface of each of the stacked films SF1 to SF3 is formed, and the state held by the member is maintained. Consider a case where the plurality of first semiconductor films 11a-1 to 11d-3 are selectively removed from the stacked films SF1 to SF3. For example, when removing the plurality of first semiconductor films 11a-1 to 11d-1 from the stacked film SF1, the inside of the cavities V21 to V41 formed between the plurality of second semiconductor films 12a-1 to 12d-1. The gate insulating film 311 may be deposited in the steps shown in FIGS. 5A to 5C, and the film 20 may be deposited in the steps shown in FIGS. 6A to 6E. . As a result, the cavities V21 to V41 are filled with the gate insulating film 311 and the film 20, and it becomes difficult to leave the cavities V21 to V41.

  On the other hand, in the first embodiment, the plurality of columnar members 21 are not removed without removing the plurality of first semiconductor films 11a-1 to 11d-3 in the steps shown in FIGS. -1 to 22-4 and a plurality of first semiconductor films 11a-1 to 11d-3 in the steps shown in FIGS. 8A to 8C after the formation of the plurality of word lines WL11 and WL21. Remove. Then, in the steps shown in FIGS. 10A and 10B, the plurality of second semiconductor films 12a-1 to 12d- in each of the plurality of structures ST1a to ST6a (see FIG. 8B) that have undergone the removal step. 3, the interlayer insulating film 40 is embedded so as to leave the cavities V21 to V43. As a result, the transistors are three-dimensionally arranged, and the interlayer insulating film 40 is a nonvolatile memory having cavities V21 to V43 in each region between the plurality of second semiconductor films (active regions) 12a-1 to 12d-3. The semiconductor memory device 1 can be manufactured.

  In this case, even if the interval between the transistors adjacent in the vertical direction is reduced, the coupling capacitance between the transistors adjacent in the vertical direction can be easily reduced to a level at which it can be ignored. For example, in the configuration shown in FIG. 1B, the stacked semiconductor film (active region) 12a-1 and the semiconductor film (active region) even if the distance between the transistor M1 and the transistor M3 adjacent in the vertical direction becomes small. Since the cavity V21 (see FIG. 2A) is formed between the semiconductor film (active region) 12a-1 and the semiconductor film (active region) 12b-1, a coupling capacitance is formed between the semiconductor film (active region) 12b-1 and the cavity V21. C13 can be easily reduced to a negligible level. That is, according to the first embodiment, in a configuration in which transistors are arranged three-dimensionally, when the interval between adjacent transistors in the vertical direction is reduced, transistor malfunction due to coupling capacitance can be reduced. .

  Here, suppose that a plurality of structures ST1a to ST6a (see FIG. 8B) that have undergone the removal process by a process with relatively good step coverage in the processes shown in FIGS. Consider a case where the interlayer insulating film 40 is buried so as to fill the cavities V21 to V43 between the second semiconductor films 12a-1 to 12d-3. In this case, even in a process with good step coverage, in order to sufficiently fill the cavities V21 to V43, the plurality of second semiconductor films 12a-1 to 12d-3 in the direction perpendicular to the surface SBa of the semiconductor substrate SB is used. To increase the vertical width of the cavities V21 to V43. In this case, in order to weaken the coupling capacitance between the transistors adjacent in the vertical direction, it is necessary to increase the interval between the transistors adjacent in the vertical direction. This makes it difficult to improve the arrangement density of memory cells (transistors). That is, when the interlayer insulating film 40 between the stacked polysilicons (active regions) is formed thick, the number of memory cells (transistors) that can be arranged in the vertical direction is reduced.

  On the other hand, in the first embodiment, the stacked semiconductor film (active region) 12a-1 and semiconductor film (active region) 12b-1 are formed in the steps shown in FIGS. The cavity V21 (see FIG. 2A) is left unfilled. As a result, the coupling capacitance between the transistors adjacent in the vertical direction can be weakened, and the interval between the plurality of second semiconductor films 12a-1 to 12d-3 in the direction perpendicular to the surface SBa of the semiconductor substrate SB is increased. Therefore, it is easy to improve the arrangement density of the memory cells (transistors).

  Alternatively, suppose that the second semiconductor films (active regions) 12a-1 to 12d-3 are formed of polysilicon. In this case, since the carrier mobility decreases, the parasitic resistance may increase and the writing / reading speed may decrease, and the number of memory cells (transistors) that can be controlled by one bit line may not be increased. There is. In addition, the variation in transistor characteristics of the memory cell increases depending on the location of the polysilicon crystal grain boundary (impurity distribution and channel distribution depending on whether or not the crystal grain boundary exists in the channel region of the transistor). The way the electric field is applied may change).

  In contrast, in the first embodiment, in the steps shown in FIGS. 3A to 3C, the first semiconductor films 11a1 to 11d1 and the second semiconductor films 12a1 to 12d1 are formed on the semiconductor substrate SB. Are stacked alternately several times to form a stacked film SF. That is, since the first semiconductor films 11a1 to 11d1 and the second semiconductor films 12a1 to 12d1 are deposited in layers, it is easy to epitaxially grow as a single crystal. That is, the second semiconductor films 12a1 to 12d1 can be formed of single crystal silicon using an epitaxial growth technique. Thereby, a decrease in carrier mobility can be suppressed, and variation in transistor characteristics of the memory cell depending on a position where a crystal grain boundary exists can be reduced.

  Alternatively, suppose that the steps shown in FIGS. 10A and 10B are performed without performing the steps shown in FIGS. In this case, since the charge storage capability in the gate insulating films 31-11 to 32-32 is uniform, if the interval between the transistors adjacent in the vertical direction is reduced, the charge may move between the transistors adjacent in the vertical direction. There is. For example, if the charge storage capabilities of the portions 31a-1, 31ab-1, and 31b-1 in the gate insulating film 31-11 are equal, the charge stored in the portion 31a-1 in the gate insulating film 31-11 is reduced. It can be easily moved to the portion 31b-1 via the portion 31ab-1. Alternatively, the charge accumulated in the portion 31b-1 in the gate insulating film 31-11 can easily move to the portion 31a-1 through the portion 31ab-1. That is, in the configuration shown in FIG. 1B, when the distance between the transistors M1 and M3 adjacent in the vertical direction becomes small, it is easy to connect between the transistor M1 and the transistor M3, as indicated by a dashed line arrow. Charge transfer may occur. As a result, in a configuration in which transistors are three-dimensionally arranged, when the interval between adjacent transistors in the vertical direction is reduced, the transistors M1 and M3 may malfunction due to charge movement (leakage current).

  In contrast, in the first embodiment, the steps shown in FIGS. 10A and 10B are performed after the steps shown in FIGS. That is, in the steps shown in FIGS. 9A to 9C, the plurality of second semiconductor films 12a-1 to 12d in each of the plurality of structures ST1a to ST6a (see FIG. 8B) that have undergone the removal step. The exposed surfaces of the gate insulating films 31-1111 to 32-321 are oxidized by thermal oxidation or the like so as to leave the cavities V21 to V43 between −3. For example, in the gate insulating film (ONO film) 31-111, the region in contact with the first semiconductor films (silicon germanium) 11a-1 to 11d-1 is directly subjected to the thermal oxidation treatment, so that the ONO film As the silicon nitride film becomes a silicon oxide film, the charge storage capability of the silicon nitride film can be reduced. That is, in the gate insulating film 31-11 formed in the steps shown in FIGS. 9A to 9C, portions 310-1, 31ab-1, 31bc that do not intersect with the semiconductor films 12a-1, 12b-1 −1 is lower than the charge storage capability of the portions 31a-1 and 31b-1 intersecting with the semiconductor films 12a-1 and 12b-1. As a result, even when the interval between the transistors adjacent in the vertical direction is reduced, the charge hardly moves between the transistors adjacent in the vertical direction. As a result, in a configuration in which transistors are three-dimensionally arranged, when the interval between adjacent transistors in the vertical direction is reduced, transistor malfunction due to charge movement (leakage current) can be reduced.

  Alternatively, tentatively, in the steps shown in FIGS. 3A to 3C, the silicon oxide films and the second semiconductor films (films of silicon-based material) 12a1 to 12d1 are alternately stacked a plurality of times. Consider the case of forming a laminated film. In this case, in the steps shown in FIGS. 4A to 4C, it is necessary to continuously process materials having significantly different properties such as the silicon oxide film and the second semiconductor films 12a1 to 12d1, and therefore the etching gas is alternately changed. It is necessary to perform dry etching (RIE) while switching to As a result, the processing time for the etching process becomes longer, and it becomes difficult to process so that continuous vertical side surfaces are formed.

  In contrast, in the first embodiment, the first semiconductor films 11a1 to 11d1 and the second semiconductor films 12a1 to 12d1 are alternately stacked a plurality of times in the steps shown in FIGS. The laminated film SF thus formed is formed. The first semiconductor films 11a1 to 11d1 are formed of a material containing silicon germanium as a main component. The second semiconductor films 12a1 to 12d1 are formed of a material containing silicon as a main component. Thus, in the steps shown in FIGS. 4A to 4C, similar material materials such as silicon germanium and silicon are continuously processed, so that dry etching (RIE) is performed collectively without switching the etching gas. can do. As a result, the processing time of the etching process can be shortened, and it becomes easy to process so that continuous vertical side surfaces are formed.

  In the nonvolatile semiconductor memory device 1, a plurality of semiconductor films (a plurality of second semiconductor films) 12a-1 to 12d-3 function as transistor control gates, and a plurality of columnar members 21-1 to 22-4 are provided. May function as an active region. In this case, the plurality of columnar members 21-1 to 22-4 are connected by bit lines instead of word lines. In addition, each semiconductor film (each second semiconductor film) 12a-1 to 12d-3 has a word line connected to one end in the longitudinal direction.

  In the steps shown in FIGS. 3A to 3C, the first semiconductor films 11a1 to 11d1 are formed of the first single crystal silicon containing germanium at the first content rate by using, for example, an epitaxial growth technique. You may form with germanium. That is, the first semiconductor films 11a1 to 11d1 may be formed of the first single crystal silicon germanium as a material mainly containing silicon germanium. Further, the second semiconductor films 12a1 to 12d1 may be formed of second single crystal silicon germanium containing germanium at a second content rate lower than the first content rate, for example, using an epitaxial growth technique. In other words, the second semiconductor films 12a1 to 12d1 may be formed of the second single crystal silicon germanium as a material mainly containing silicon.

  Here, the 1st content rate is 20 at% or more and 50 at% or less, for example, and the 2nd content rate is 10 at% or less, for example. At this time, the etching selectivity of the first semiconductor films (silicon germanium) 11a-1 to 11d-3 with respect to the second semiconductor film (silicon) in the steps shown in FIGS. In order to ensure a large amount, the difference between the first content rate and the second content rate can be 30 at% or more.

(Second Embodiment)
Next, a method for manufacturing the nonvolatile semiconductor memory device 1i according to the second embodiment will be described with reference to FIGS. The cross-sectional views shown in FIGS. 11A, 11C, 12A, and 12C correspond to the cross-sectional view of FIG. The cross-sectional views shown in FIGS. 11 (a), 11 (c), 12 (a), and 12 (c) are respectively the plan views of FIGS. 11 (b), 11 (d), 12 (b), and 12 (d). A cross section formed by a one-dot chain line is shown. The cross-sectional view shown in FIG. 11 (e) shows a cross section formed by a two-dot chain line in the plan view of FIG. 11 (d). Below, it demonstrates centering on a different part from 1st Embodiment.

  The steps shown in FIGS. 11A and 11B are performed after the steps shown in FIGS. An insulating film is embedded so as to cover the semiconductor substrate SB and the plurality of stacked films SF1 to SF3, and the upper surface of the embedded insulating film is planarized by a CMP method or the like to form a dummy insulating film 60i. The dummy insulating film 60i is made of, for example, silicon oxide.

  In the steps shown in FIGS. 11C to 11E, a third resist pattern (not shown) is formed on the dummy insulating film 60i. The third resist pattern is a pattern in which the lines and spaces in the second resist pattern used in the steps shown in FIGS. 7A to 7C of the first embodiment are reversed. Then, the dummy insulating film 60i is etched by dry etching (for example, RIE) using the third resist pattern as a mask. Accordingly, holes H1 to H4 (see FIG. 11C) and grooves TR1 and TR2 (FIG. 11E) for embedding the plurality of columnar members 21-1 to 22-4 and the plurality of word lines WL11 and WL21, respectively. )).

  In the steps shown in FIGS. 12A and 12B, an insulating film is deposited in the holes H1 to H4 and the trenches TR1 and TR2, and a plurality of gate insulating films 31-111 to 32-321 are formed. At this time, the plurality of gate insulating films 31-111 to 32-321 are also formed on the inner side surfaces of the trenches TR1 and TR2 (see FIG. 12B). Thereafter, a predetermined film is embedded in the holes H1 to H4 and the trenches TR1 and TR2, and the upper surface is flattened by a CMP method or the like to form a plurality of columnar members 21-1 to 22-4 and a plurality of word lines WL11 and WL21. . The predetermined film is formed of a semiconductor (for example, a material containing silicon as a main component). The predetermined film is made of, for example, polysilicon.

  In the steps shown in FIGS. 12C and 12D, the dummy insulating film 60i is removed by dry etching (for example, RIE). Then, the vapor phase diffusion method is applied to the exposed side surfaces of the first semiconductor films 11a-1 to 11d-3 and the side surfaces of the second semiconductor films 12a-1 to 12d-3 in the stacked films SF1 to SF3. A source region and a drain region (not shown) are formed by implanting an impurity by an ion implantation method or the like, and an activation heat treatment is performed. Thereafter, the steps shown in FIGS. 8A to 8C are performed.

  In the second embodiment, the gate insulating films 31-111 to 32-321 and a predetermined film are sequentially buried in the holes H1 to H4 and the trenches TR1 and TR2 to thereby form a plurality of gate insulating films 31-1111 to 32-321. A plurality of columnar members 21-1 to 22-4 and a plurality of word lines WL11 and WL21 are formed. Therefore, as compared with the case where the gate insulating film 311 and the film 20 are etched (see FIG. 6), the plurality of gate insulating films 31-111 to 32-321, the plurality of columnar members 21-1 to 22-4, and A plurality of word lines WL11 and WL21 can be formed easily.

(Third embodiment)
Next, the configuration of the nonvolatile semiconductor memory device 1j according to the third embodiment will be described with reference to FIG. FIG. 13A is a diagram showing a cross section including a bit line in the nonvolatile semiconductor memory device 1j. FIG. 13B is a diagram showing an equivalent circuit in the nonvolatile semiconductor memory device 1j. Below, it demonstrates centering on a different part from 1st Embodiment.

  The nonvolatile semiconductor memory device 1j includes a semiconductor substrate SBj, a plurality of semiconductor films (a plurality of second semiconductor films) 12a-1j to 12d-3j, a plurality of gate insulating films 31-1j to 31-3j, and a plurality of columnar members. 21-1j to 21-3j, a plurality of bit lines BL1j and BL2j (see FIG. 15F), and an interlayer insulating film 40j.

  The semiconductor substrate SBj has a base region SR2j and a well region SR1j. The base region SR2j contains a first conductivity type (eg, P-type) impurity (eg, boron) at a low concentration. The well region SR1j is formed on the base region SR2j. The well region SR1j has a second conductivity type (for example, N type) impurity (for example, phosphorus or arsenic) that is opposite to the first conductivity type, and has a concentration higher than the concentration of the first conductivity type impurity in the base region SR2j. Contains by concentration. Here, the well region SR1j functions as a source line.

  The stacked semiconductor films 12a-1j, 12b-1j, 12c-1j, and 12d-1j (aligned in the direction perpendicular to the surface SBja of the semiconductor substrate SBj) are respectively the gate insulating film 31-1j and the columnar member 21-. It is penetrated by 1j. The other stacked semiconductor films 12a-2j to 12d-3j are similar to the stacked semiconductor films 12a-1j, 12b-1j, 12c-1j, and 12d-1j.

  Here, each of the semiconductor films 12a-1j to 12d-3j functions as a control gate of the transistor. For example, in the semiconductor film 12b-1j, a portion intersecting with the columnar member 21-1j becomes a control gate of the transistor M11 (see FIG. 13B). For example, in the semiconductor film 12c-1j, a portion that intersects the columnar member 21-1j is a control gate of the transistor M12.

  Each of the plurality of gate insulating films 31-1j to 31-3j penetrates the plurality of semiconductor films 12a-1j to 12d-3j and faces a hole penetrating the plurality of semiconductor films 12a-1j to 12d-3j. Of the semiconductor films 12a-1j to 12d-3j. For example, the gate insulating film 31-1j penetrates the plurality of stacked semiconductor films 12a-1j, 12b-1j, 12c-1j, and 12d-1j, and the plurality of semiconductor films 12a-1j, 12b-1j, and 12c- 1j and 12d-1j are arranged on the inner peripheral surface. The other gate insulating films 31-2j and 31-3j are the same as the gate insulating film 31-1j.

  Each of the gate insulating films 31-1j to 31-3j includes a charge storage film having a charge storage capability. Each of the gate insulating films 31-1j to 31-3j is formed of, for example, an ONO film. The ONO film has a three-layer structure in which two silicon oxide films sandwich a silicon nitride film. Each of the gate insulating films 31-1j to 31-3j includes the silicon nitride film in the ONO film as a charge storage film, and can store charges in the silicon nitride film.

  In the gate insulating film 31-1j, the charge storage film (silicon nitride) in the portions 31ab-1j, 31bc-1j, 31cd-1j (see FIG. 15A) that do not intersect the semiconductor films 12b-1j, 12c-1j The film) contains more oxygen than the charge storage film (silicon nitride film) in the portions 31b-1j and 31c-1j (see FIG. 15A) intersecting the semiconductor films 12b-1j and 12c-1j. It is formed with the material (composition) containing. Thus, in the gate insulating film 31-1j, the charge storage capability of the portions 31ab-1j, 31bc-1j, and 31cd-1j that do not intersect the semiconductor films 12b-1j and 12c-1j is the same as that of the semiconductor films 12b-1j and 12c. The charge storage capability of the portions 31b-1j and 31c-1j intersecting with -1j is lower. The other gate insulating films 31-2j and 31-3j are the same as the gate insulating film 31-1j.

  Each of the plurality of columnar members 21-1j to 21-3j penetrates the plurality of semiconductor films 12a-1j to 12d-3j, and the plurality of semiconductor films 12a-1j through the gate insulating films 31-1j to 31-3j. ~ 12d-3j are held. For example, the columnar member 21-1j penetrates the stacked semiconductor films 12a-1j, 12b-1j, 12c-1j, and 12d-1j, and the plurality of semiconductor films 12a- through the gate insulating film 31-1j. 1j, 12b-1j, 12c-1j, 12d-1j. The other columnar members 21-2j and 21-3j are the same as the columnar member 21-1j. Each of the columnar members 21-1j to 21-3j is formed of a semiconductor (for example, a material mainly containing silicon). Each of the columnar members 21-1j to 21-3j is made of, for example, polysilicon.

  Here, each of the columnar members 21-1j to 21-3j functions as an active region. That is, in each of the columnar members 21-1j to 21-3j, a portion intersecting with the semiconductor films 12a-1j to 12d-3j becomes a channel region of the transistor, and portions adjacent to both sides (upper and lower) of the portion are the transistor regions. It becomes a source region or a drain region.

  For example, in the columnar member 21-1j, portions intersecting with the semiconductor films 12b-1j and 12c-1j are channel regions of the transistors M11 and M12, respectively. For example, if the transistors M11 and M12 are NMOS transistors (PMOS transistors), the columnar member 21-1j has a source region (drain region) that is adjacent to the source line side with respect to the intersecting portion. A portion adjacent to the portion on the bit line side becomes a drain region (source region). The columnar members 21-1j to 21-3j have one end connected to the well region SR1j as a source line and the other end connected to the bit line BL1j.

  Each of the plurality of bit lines BL1j and BL2j (see FIG. 15F) intersects with the longitudinal direction of each of the semiconductor films 12a-1j to 12d-3j along the surface SBa of the semiconductor substrate SB (for example, in parallel). It extends in the direction. The bit line BL1j connects a plurality of columnar members 21-1j to 21-3j arranged in a line along the surface SBa of the semiconductor substrate SB. The word line BL1j is formed of a conductive material and has, for example, a two-layer structure in which a barrier metal layer BL1bj and a metal layer BL1aj are sequentially stacked. The barrier metal layer BL1bj is made of, for example, titanium nitride. The metal layer BL1aj is made of tungsten, for example. The other bit lines BL2j are the same as the bit line BL1j.

  The interlayer insulating film 40j has cavities V21j to V43j in each region between the plurality of semiconductor films 12a-1j to 12d-3j. Further, the interlayer insulating film 40j has cavities V11j to V13j in a region between the semiconductor substrate SB and the first semiconductor films 12a-1j to 12a-3j. Each of the cavities V11j to V43j extends in a tubular shape so as to surround the columnar members 21-1j to 21-3j.

  Here, suppose that the interlayer insulating film 40j does not have the cavities V21j to V43j in each region between the plurality of semiconductor films 12a-1j to 12d-3j. In this case, in the arrangement of the three-dimensional memory cells (transistors) of the nonvolatile semiconductor memory device 1j, if the interval between adjacent transistors in the vertical direction is reduced in order to improve the arrangement density of the memory cells (transistors), the vertical direction The coupling capacitance between adjacent transistors cannot be ignored. For example, in the configuration shown in FIG. 13B, when the distance between the transistor M11 and the transistor M12 adjacent in the vertical direction becomes small, the stacked semiconductor film (control gate) 12b-1j and semiconductor film (control gate) 12c- The coupling capacitance C1112 between 1j becomes a size that cannot be ignored. As a result, the potentials of the control gates of the transistors M11 and M12 become unstable due to the coupling capacitance between the transistors M11 and M12 adjacent in the vertical direction, so that the transistors M11 and M12 may malfunction. .

  On the other hand, in the third embodiment, the interlayer insulating film 40j has cavities V21j to V43j in each region between the plurality of semiconductor films 12a-1j to 12d-3j. As a result, even when the interval between the transistors adjacent in the vertical direction is reduced, the coupling capacitance between the transistors adjacent in the vertical direction can be easily reduced to a level at which it can be ignored. For example, in the configuration shown in FIG. 13B, the stacked semiconductor film (control gate) 12b-1j and the semiconductor film (control gate) even if the distance between the transistor M11 and the transistor M12 adjacent in the vertical direction becomes small. Since the cavity V21j (see FIG. 13A) is formed between the semiconductor film (control gate) 12b-1j and the semiconductor film (control gate) 12c-1j. C1112 can be easily reduced to a negligible level. That is, according to the third embodiment, in the configuration in which the transistors are three-dimensionally arranged, the malfunction of the transistors due to the coupling capacitance can be reduced when the interval between the adjacent transistors in the vertical direction is reduced.

  Alternatively, consider a case where the charge storage capability of the gate insulating film 31-1j is uniform. In this case, when the interval between transistors adjacent in the vertical direction is reduced, charge may move between the transistors adjacent in the vertical direction. For example, if the charge storage capabilities of the portions 31b-1j, 31bc-1j, and 31c-1j (see FIG. 15A) in the gate insulating film 31-1j are equivalent, the portion 31b in the gate insulating film 31-1j The charge accumulated in -1j can easily move to the portion 31c-1j via the portion 31bc-1j. Alternatively, the charge accumulated in the portion 31c-1j in the gate insulating film 31-1j can easily move to the portion 31b-1j via the portion 31bc-1j. That is, in the configuration shown in FIG. 13B, when the interval between the transistors M11 and M12 adjacent in the vertical direction becomes small, the transistor M11 and the transistor M12 can be easily connected as indicated by the dashed-dotted arrow. Charge transfer may occur. As a result, in a configuration in which transistors are three-dimensionally arranged, when the distance between adjacent transistors in the vertical direction is reduced, the transistors M11 and M12 may malfunction due to charge movement (leakage current).

  On the other hand, in the third embodiment, in the gate insulating film 31-1j, the charge storage capability of the portions 31ab-1j, 31bc-1j, and 31cd-1j that do not intersect the semiconductor films 12b-1j and 12c-1j However, it is lower than the charge storage capability of the portions 31b-1j and 31c-1j intersecting with the semiconductor films 12b-1j and 12c-1j. As a result, even when the interval between the transistors adjacent in the vertical direction is reduced, the charge hardly moves between the transistors adjacent in the vertical direction. As a result, in a configuration in which transistors are three-dimensionally arranged, when the interval between adjacent transistors in the vertical direction is reduced, transistor malfunction due to charge movement (leakage current) can be reduced.

  Next, a method for manufacturing the nonvolatile semiconductor memory device 1j according to the third embodiment will be described with reference to FIGS. The cross-sectional views shown in FIGS. 14A, 14C, 14E, 15G, 15A, 15C, and 15E correspond to the cross-sectional view of FIG. is there. 14 (a), (c), (e), (g), and FIG. 15 (a), (c), (e) are cross-sectional views shown in FIGS. 14 (b), (d), ( f), (h), FIG. 15B, FIG. 15D, and FIG. Below, it demonstrates centering on a different part from 1st Embodiment.

  In the steps shown in FIGS. 14A and 14B, the well region SR1j is formed on the base region SR2j in the semiconductor substrate SBj. The base region SR2j contains a first conductivity type (eg, P-type) impurity (eg, boron) at a low concentration. The well region SR1j has a second conductivity type (for example, N type) impurity (for example, phosphorus or arsenic) that is opposite to the first conductivity type, and has a concentration higher than the concentration of the first conductivity type impurity in the base region SR2j. It is formed so as to include it at a concentration.

  Then, a stacked film SFj in which the first semiconductor films 11a1j to 11d1j and the second semiconductor films 12a1j to 12d1j are alternately stacked a plurality of times is formed on the semiconductor substrate SBj. Each of the second semiconductor films 12a1j to 12d1j is formed so as to contain a first conductivity type (for example, P-type) impurity (for example, boron) at a higher concentration than the base region SR2j. Here, among the plurality of second semiconductor films 12a1j to 12d1j to be deposited, the lowermost second semiconductor film 12a1j and the uppermost second semiconductor film 12d1j are used as the gate electrode of the selection transistor. It is formed thicker than the second semiconductor films 12b1j and 12c1j.

  In the steps shown in FIGS. 14C and 14D, a plurality of layers that respectively penetrate the stacked film SFj and expose the surface SBaj of the semiconductor substrate SBj by a photolithography process and a processing process such as dry etching (for example, RIE). Holes H11 to H13 are formed. The plurality of holes H11 to H13 are formed so as to be two-dimensionally arranged when viewed from a direction perpendicular to the surface SBaj of the semiconductor substrate SBj.

  14E and 14F, an insulating film is deposited on the entire surface so as to cover the inner surfaces of the holes H11 to H13. And the part which covers the bottom face of hole H11-H13 is etched away, leaving the part which covers the internal peripheral surface of hole H11-H13 among the deposited insulating films. Thereby, a plurality of gate insulating films 31-11j to 31-31j are formed on the inner peripheral surfaces of the holes H11 to H13.

  Then, a predetermined film is embedded in the holes H11 to H13, and the upper surface is flattened by a CMP method or the like to form a plurality of columnar members 21-1j to 21-3j. The predetermined film is formed of a semiconductor (for example, a material containing silicon as a main component). The predetermined film is made of, for example, polysilicon.

  In the steps shown in FIGS. 14G and 14H, a fourth resist pattern (not shown) including a plurality of fourth line patterns arranged in parallel (for example, in parallel with each other) is stacked by a photolithography process. It is formed on the film SFj. Each fourth line pattern is formed in a row pattern that exposes a plurality of columnar members 21-1j to 21-3j when viewed from a direction perpendicular to the surface SBaj of the semiconductor substrate SBj. . Then, the laminated film SFj is etched by dry etching (for example, RIE) using the fourth resist pattern as a mask. Thereby, a plurality of stacked films SF1j to SF3j are formed. Thereafter, the fourth resist pattern is removed.

  As described above, in the process (formation process) shown in FIGS. 14A to 14H, at least the plurality of second semiconductor films 12a-1j to 12d-3j in the stacked films SF1j to SF3j are formed into the gate insulating film 31-11j. A plurality of structures ST1j to ST3j (see FIG. 14G) respectively held by the columnar members 21-1j to 21-3j through ~ 31-31j are formed. For example, in the structure ST1j, the plurality of first semiconductor films 11a-1j to 11d-1j and the plurality of second semiconductor films 12a-1j to 12d-1j in the stacked film SF1j are columnar via the gate insulating film 31-11j. It is held by the member 21-1j (see FIG. 14E). The other structures ST2j and ST3j are similar to the structure ST1j.

  In the steps shown in FIGS. 15A and 15B, first (removal step), a plurality of second semiconductor films 12a-1j to 12d in each of the plurality of structures ST1j to ST3j (see FIG. 14G). −3j is selectively removed from the stacked film SF1j, for example, while maintaining the state where −3j is held by the columnar members 21-1j to 21-3j. Thereby, in the structure ST1aj after the removal step, cavities V21j to V41j are formed between the plurality of second semiconductor films 12a-1j to 12d-1j. In the structure ST1aj after the removal step, a cavity V11j is formed between the lowermost second semiconductor film 12a-1j and the semiconductor substrate SBj. The other structures ST2aj and ST3aj that have undergone the removal step are similar to the structure ST1aj.

  Next (oxidation step), in each of the plurality of structures ST1aj to ST3aj (see FIG. 15A) that have undergone the removal step, the exposed surface is oxidized by a thermal oxidation method or the like. For example, in the gate insulating film (ONO film) 31-11j, the region in contact with the first semiconductor films (silicon germanium) 11a-1j to 11d-1j is directly subjected to thermal oxidation treatment. As the silicon nitride film becomes a silicon oxide film, the charge storage capability of the silicon nitride film can be reduced. That is, the charge storage film (silicon nitride film) in the portions 310-1j, 31ab-1j, 31bc-1j, and 31cd-1j that do not intersect with the second semiconductor films 12a-1j to 12d-1j A material (composition) containing more oxygen than the charge storage film (silicon nitride film) in the portions 31a-1j, 31b-1j, 31c-1j, 31d-1j crossing the semiconductor films 12a-1j to 12d-1j Is formed. Thereby, in the obtained gate insulating film 31-1j, the charge accumulation of the portions 310-1j, 31ab-1j, 31bc-1j, and 31cd-1j that do not intersect with the second semiconductor films 12a-1j to 12d-1j. The capability is lower than the charge storage capability of the portions 31a-1j, 31b-1j, 31c-1j, and 31d-1j intersecting with the second semiconductor films 12a-1j to 12d-1j. The other gate insulating films 31-2j and 31-3j are the same as the gate insulating film 31-1j.

  In the steps (embedding step) shown in FIGS. 15C and 15D, the plurality of second semiconductor films 12a-1j in each of the plurality of structures ST1aj to ST3aj (see FIG. 15A) that have undergone the removal step. Interlayer insulating film 40j is embedded so as to leave cavities V21j to V43j between 12d-3j.

  In the steps shown in FIGS. 15E and 15F, a barrier metal film and a metal film are sequentially deposited on the entire surface. The barrier metal film is formed of, for example, titanium nitride. The metal film is made of tungsten, for example. A fifth resist pattern (not shown) including a plurality of fifth line patterns that are aligned with each other (for example, parallel to each other) and extending in a direction intersecting with each of the stacked films SF1j to SF3j is formed on the tungsten film. To do. Each fifth line pattern includes a plurality of columnar members 21-1j to 21-3j arranged in a line in a direction intersecting with the fourth line pattern when viewed from a direction perpendicular to the surface SBaj of the semiconductor substrate SBj. It is formed to cover. Then, the barrier metal film and the metal film are etched by dry etching (for example, RIE) using the fifth resist pattern as a mask. Thereby, for example, the bit line BL1j in which the barrier metal layer BL1bj and the metal layer BL1aj are sequentially stacked is formed. That is, a plurality of bit lines BL1j and BL2j are formed.

  Here, suppose that a plurality of first semiconductor films 11a1j to 11d1j are selectively removed from the stacked film SFj in which the holes H11 to H13 are formed in the steps shown in FIGS. 14C and 14D. . In this case, gate insulating films 31-11j to 31-31j are deposited in the gaps formed between the plurality of second semiconductor films 12a1j to 12d1j in the steps shown in FIGS. There is a possibility that a predetermined film to be the columnar members 21-1j to 21-3j is deposited. As a result, the gap is filled with the gate insulating films 31-11j to 31-31j and a predetermined film, and it becomes difficult to form the cavities V21j to V43j in a later process.

  On the other hand, in the first embodiment, the plurality of columnar members 21-1j-21 are removed without removing the plurality of first semiconductor films 11a1j-11d1j in the steps shown in FIGS. The plurality of first semiconductor films 11a-1j to 11d-1j are removed in the steps shown in FIGS. 15A and 15B, which are steps after forming -3j. Then, in the steps shown in FIGS. 15C and 15D, cavities V21j to V43j are provided between the plurality of second semiconductor films 12a-1j to 12d-3j in each of the plurality of structures ST1aj to ST3aj subjected to the removal step. The interlayer insulating film 40j is embedded so as to leave Thus, the transistors are three-dimensionally arranged, and the interlayer insulating film 40j is a nonvolatile memory having cavities V21j to V43j in each region between the plurality of second semiconductor films (active regions) 12a-1j to 12d-3j. The semiconductor memory device 1j can be manufactured.

  In this case, even if the interval between the transistors adjacent in the vertical direction is reduced, the coupling capacitance between the transistors adjacent in the vertical direction can be easily reduced to a level at which it can be ignored. For example, in the configuration shown in FIG. 13B, the stacked semiconductor film (control gate) 12b-1j and the semiconductor film (control gate) even if the distance between the transistor M11 and the transistor M12 adjacent in the vertical direction becomes small. Since the cavity V21j (see FIG. 13A) is formed between the semiconductor film (control gate) 12b-1j and the semiconductor film (control gate) 12c-1j. C1112 can be easily reduced to a negligible level. That is, according to the third embodiment, in the configuration in which the transistors are three-dimensionally arranged, the malfunction of the transistors due to the coupling capacitance can be reduced when the interval between the adjacent transistors in the vertical direction is reduced.

  In the third embodiment, the second semiconductor films (control gates) 12a-1j to 12d-3j can be formed of single crystal silicon. Thereby, the resistance of the control gate of each transistor can be reduced.

  Alternatively, let us consider a case where the steps shown in FIGS. 15C and 15D are performed without performing the step of oxidizing the exposed surfaces of each of the plurality of structures ST1aj to ST3aj that have undergone the removal step. In this case, since the charge storage capability in the gate insulating films 31-1j to 31-3j is uniform, if the interval between the transistors adjacent in the vertical direction is reduced, the charge may move between the transistors adjacent in the vertical direction. There is. For example, if the charge storage capabilities of the portions 31b-1j, 31bc-1j, and 31c-1j in the gate insulating film 31-1j are equivalent, the charges accumulated in the portion 31b-1j in the gate insulating film 31-1j are It can be easily moved to the portion 31c-1j via the portion 31bc-1j. Alternatively, the charge accumulated in the portion 31c-1j in the gate insulating film 31-1j can easily move to the portion 31b-1j via the portion 31bc-1j. That is, in the configuration shown in FIG. 13B, when the interval between the transistors M11 and M12 adjacent in the vertical direction becomes small, the transistor M11 and the transistor M12 can be easily connected as indicated by the dashed-dotted arrow. Charge transfer may occur. As a result, in a configuration in which transistors are three-dimensionally arranged, when the distance between adjacent transistors in the vertical direction is reduced, the transistors M11 and M12 may malfunction due to charge movement (leakage current).

  On the other hand, in the first embodiment, after performing the step of oxidizing the exposed surface in each of the plurality of structures ST1aj to ST3aj that have undergone the removal step, the steps shown in FIGS. Do. That is, in the step of oxidizing the exposed surface, between each of the plurality of second semiconductor films 12a-1j to 12d-3j in each of the plurality of structures ST1aj to ST3aj (see FIG. 15A) that has undergone the removal step. The exposed surfaces of the gate insulating films 31-11j to 31-31j (see FIG. 14E) are oxidized by thermal oxidation or the like so as to leave the cavities V21j to V43j. For example, in the gate insulating film (ONO film) 31-11j, the region in contact with the first semiconductor films (silicon germanium) 11a-1j to 11d-1j is directly subjected to thermal oxidation treatment. As the silicon nitride film becomes a silicon oxide film, the charge storage capability of the silicon nitride film can be reduced. That is, in the gate insulating film 31-1j formed in the step of oxidizing the exposed surface, the charges of the portions 31ab-1j, 31bc-1j, and 31cd-1j that do not intersect the semiconductor films 12b-1j and 12c-1j The storage capability is lower than the charge storage capability of the portions 31b-1j and 31c-1j intersecting with the semiconductor films 12b-1j and 12c-1j. As a result, even when the interval between the transistors adjacent in the vertical direction is reduced, the charge hardly moves between the transistors adjacent in the vertical direction. As a result, in a configuration in which transistors are three-dimensionally arranged, when the interval between adjacent transistors in the vertical direction is reduced, transistor malfunction due to charge movement (leakage current) can be reduced.

  1, 1i, 1j Nonvolatile semiconductor memory device, 11a-1 to 11d-3, 11a1 to 11d1, 11a-1j to 11d-1j, 11a1j to 11d1j First semiconductor film, 12a-1 to 12d-3, 12a1 12d1, 12a-1j to 12d-3j, 12a1j to 12d1j Second semiconductor film, 21-1 to 22-4, 21-1j to 21-3j Columnar members, 31-11 to 32-32, 31-1111 to 32 -321, 31-1j to 31-3j, 31-11j to 31-31j Gate insulating film, 40, 40j Interlayer insulating film, SB, SBj Semiconductor substrate, SF1-SF3, SF1j-SF3j Stacked film, ST1-ST6, ST1a ~ ST6a, ST1j ~ ST3j, ST1aj ~ ST3aj, structure, V11 ~ V43, V11j ~ V43j cavity

Claims (5)

At least a plurality of second semiconductor films in a stacked film in which a first semiconductor film and a second semiconductor film are alternately stacked a plurality of times on a semiconductor substrate are arranged in a columnar shape of a semiconductor or a conductor via a gate insulating film. Forming a plurality of structures respectively held by members;
For each of the plurality of structures formed in the forming step, the plurality of first semiconductor films are removed from the stacked film while maintaining the state where the plurality of second semiconductor films are held by the columnar member. A removal step to selectively remove;
A step of embedding an interlayer insulating film so as to leave a cavity between the plurality of second semiconductor films in each of the plurality of structures that have undergone the removal step;
A method for manufacturing a nonvolatile semiconductor memory device, comprising: 2. The nonvolatile semiconductor memory device according to claim 1, further comprising an oxidation step of oxidizing an exposed surface of each of the plurality of structures that has undergone the removal step before the filling step. Production method. The first semiconductor film is formed of a material mainly composed of silicon germanium,
The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the second semiconductor film is formed of a material containing silicon as a main component. A semiconductor substrate;
A plurality of semiconductor films stacked on the semiconductor substrate at intervals in a direction perpendicular to the surface of the semiconductor substrate;
A plurality of gate insulating films each having charge storage capability, each extending in a direction perpendicular to the surface of the semiconductor substrate, and disposed on side surfaces of the plurality of semiconductor films,
A plurality of semiconductor or conductor columnar members respectively extending in a direction perpendicular to the surface of the semiconductor substrate and holding the plurality of semiconductor films via the gate insulating film;
An interlayer insulating film having a cavity in each region between the plurality of semiconductor films;
A nonvolatile semiconductor memory device comprising: A semiconductor substrate;
A plurality of semiconductor films stacked on the semiconductor substrate at intervals in a direction perpendicular to the surface of the semiconductor substrate;
A plurality of gate insulating films each having a charge storage capability, respectively penetrating through the plurality of semiconductor films, and arranged on peripheral surfaces of the plurality of semiconductor films facing each hole penetrating the plurality of semiconductor films; ,
A plurality of semiconductor columnar members respectively penetrating the plurality of semiconductor films and holding the plurality of semiconductor films via the gate insulating film;
An interlayer insulating film having a cavity in each region between the plurality of semiconductor films;
A nonvolatile semiconductor memory device comprising:

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