JP2011150532A - Information processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processing apparatus for more highly accurately performing processing time limit management for each of a plurality of tasks processed in parallel. <P>SOLUTION: The information processing apparatus which can process multiple tasks in parallel with one unit processor, wherein processing time limits are respectively set for at least some of the multiple tasks, includes a hardware means for management of multiple processing time limits corresponding to those multiple tasks with processing time limits respectively set therefor among the multiple tasks. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an information processing apparatus that can process a plurality of tasks in parallel, and more particularly, to an information processing apparatus that performs multithreading and an information processing apparatus configured as a multicore processor.

  2. Description of the Related Art Conventionally, an information processing apparatus that can execute parallel processing by performing hardware multithreading or software multithreading is known. An information processing apparatus including a plurality of CPU cores in one unit CPU (processor) called a multi-core processor is also known. These information processing apparatuses can process a plurality of tasks in parallel.

  By the way, some tasks that are processed by the information processing apparatus have a processing time limit. Patent Document 1 describes a semiconductor integrated circuit having a TSS (Time Sharing System) function that gives a certain time to a task and switches to another task when that time elapses.

  This semiconductor integrated circuit includes a single timer for the processor, and operates a timer synchronized with either the execution of the program in the privileged mode or the execution of the program in the non-privileged mode. As a result, when task processing is interrupted by interruption or the like, the timer is temporarily stopped to control the processing time originally given to the task.

JP-A-10-247146

  However, since the semiconductor integrated circuit described in Patent Document 1 includes only one general-purpose timer for the processor, when a plurality of tasks are processed in parallel, the processing time limit management may be performed only for one task. It is not possible to manage the processing time limit for other tasks.

  Also, when an abnormality occurs in which a process is stuck within a specific task, it is normal to perform a corresponding process by an interrupt, etc.In this case, if one task violates the process deadline, It can be a task reset.

  In addition, since the on / off control of the timer is performed by software, there is a possibility that the timing accuracy by the timer may be reduced.

  The present invention is for solving such problems, and a main object of the present invention is to provide an information processing apparatus capable of performing processing deadline management for each of a plurality of tasks processed in parallel with higher accuracy. And

In order to achieve the above object, one embodiment of the present invention provides:
An information processing apparatus capable of processing a plurality of tasks in parallel by a single processor,
A processing deadline is set for at least some of the plurality of tasks,
A plurality of processing time limit management hardware means corresponding to a plurality of tasks for which a processing time limit is set among the plurality of tasks,
Information processing apparatus.

  Here, one unit of processor capable of processing a plurality of tasks in parallel refers to a processor enclosed in one package, such as a single core processor or a multicore processor that performs multithreading.

  According to this aspect of the present invention, since a plurality of processing time limit management hardware units corresponding to a plurality of tasks for which a processing time limit is set among a plurality of tasks are provided, for each of a plurality of tasks processed in parallel Processing time limit management can be performed with higher accuracy.

In one embodiment of the present invention,
The plurality of processing time management hardware means may include dedicated time measuring means.

  In this way, the processing time limit management for each of a plurality of tasks that may be processed in parallel can be performed with higher accuracy.

In one embodiment of the present invention,
The plurality of processing time limit management hardware means,
Program counter monitoring means for monitoring a value of a program counter of a program executed by the one unit of processor;
Storage means for storing information on the start position, end position, and processing deadline of the program counter corresponding to a plurality of tasks for which a processing deadline is set among the plurality of tasks;
With
When the program counter monitoring means determines that the value of the program counter has reached the start position, the time counting means starts measuring time, and after the time measurement starts, by the program counter monitoring means, the program counter monitoring means When it is not determined that the value reaches the end position, a predetermined abnormality detection operation may be performed.

  Here, the storage means that stores information on the start position, end position, and processing deadline of the program counter is a storage means that stores the start position, a storage means that stores the end position, and a separate storage that stores information on the processing deadline. It may be a set of storage means, or information regarding the start position, end position, and processing time limit may be stored in different storage areas of one storage means.

In one embodiment of the present invention,
The predetermined abnormality detection operation is, for example, an operation of writing a value indicating abnormality detection in an SFR (Special Function Register).

  This makes it possible to refer to whether or not an abnormality has been detected from software such as an OS (Operating System).

One embodiment of the present invention includes
The plurality of tasks mounted on the vehicle may include a calculation process for controlling the in-vehicle device.

  In a control device mounted on a vehicle, the same processing is repeatedly executed and the number of tasks is often fixed, so that the effect of the present invention can be sufficiently exerted.

  ADVANTAGE OF THE INVENTION According to this invention, the information processing apparatus which can perform the process time limit management for every several task processed in parallel with higher precision can be provided.

1 is a system configuration example of an information processing apparatus 1 according to an embodiment of the present invention. 4 is a flowchart showing a flow of processing started when the information processing apparatus 1 is turned on. 3 is a flowchart showing a flow of processing time limit violation monitoring processing executed by an OS (Operating System) (not shown) in the information processing apparatus 1. It is a figure which shows typically a mode that abnormality generate | occur | produced in the certain task in this conventional information processing apparatus provided with a single timer, and the process time limit violation occurred by this. It is a figure which shows typically a mode that abnormality occurred in a certain task in the information processing apparatus 1 which concerns on a present Example, and this, and the processing time limit violation occurred. In FIG. 6, there is an information processing apparatus 1A that performs processing of tasks A to C, and an information processing apparatus 1B that executes only processing of task D, and information on the processing of task C is received from the information processing apparatus 1A. It is a figure which shows a mode that it transfers to the processing apparatus 1B.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the accompanying drawings.

  Hereinafter, an information processing apparatus 1 according to an embodiment of the present invention will be described with reference to the drawings.

[overall structure]
FIG. 1 is a system configuration example of an information processing apparatus 1 according to an embodiment of the present invention. The information processing apparatus 1 includes a CPU (Central Processing Unit) 10 and a plurality of processing time limit management hardware 20 # 1 to 20 # n as main components.

  The CPU 10 is a single core CPU having, for example, an instruction decoder, various registers, an arithmetic circuit, a cache memory, a program counter 12 and the like. The CPU 10 can perform various processes by fetching a program (instruction) stored in a program memory (not shown) into a dedicated register, decoding it, and executing it. As the program memory, for example, a ROM (Read Only Memory), an EEPROM (Electrically Erasable and Programmable Read Only Memory), or the like is used.

  The CPU 10 can process a plurality of tasks in parallel by executing, for example, software multithreading. Specifically, for example, first, a certain time for processing the task A is given, and when the certain time elapses, the processing for the task A is temporarily stopped and the processing for the task B is started. Next, when a certain time given to the task B elapses, the process of the task B is temporarily stopped and the process of the task C is started. Thus, a plurality of tasks can be processed in parallel by sequentially processing a plurality of tasks.

  The CPU 10 may execute hardware multithreading instead of software multithreading. In this case, an instruction decoder or the like is provided for each task, and a part of hardware such as an arithmetic circuit is shared between threads.

  Further, the CPU 10 may be configured as a multi-core processor and thereby be capable of processing a plurality of tasks in parallel.

  The program counter 12 is a program register that holds information about an address on the program memory of an instruction currently executed by the CPU 10.

  The plurality of processing time limit management hardware 20 # 1 to 20 # n includes a plurality of tasks for which processing time limits are set among a plurality of tasks executed by the information processing apparatus 1 (may include those not executed in parallel). It is provided for each task. For example, when the number of tasks for which a processing time limit is set is 5, the information processing apparatus 1 desirably includes at least five processing time management hardware 20 # 1 to 20 # n.

  Each of the plurality of processing time limit management hardware 20 # 1 to 20 # n has a similar configuration. Accordingly, in the following description, only the contents of one of the processing deadline management hardwares will be referred to (simply referred to as the processing deadline management hardware 20), and which processing deadline management hardware is used. The code “#k” (k = 1 to n) for identification is omitted.

[Processing time management hardware]
The processing time limit management hardware 20 includes a timer setting register 22, a count start PC (program counter) register 24, a count stop PC (program counter) register 26, an initial value register 28, a timer processing unit 30, a count A register 32, an underflow detection unit 34, and an abnormality detection status register 36 are provided.

  The timer setting register 22 holds resolution of the timer realized by the timer processing unit 30 and the count register 32, and other configuration information.

  The count start PC register 24 holds the value of the program counter 12 when a task corresponding to the processing time limit management hardware (hereinafter simply referred to as “corresponding task”) is started.

  The count stop PC register 26 holds the value of the program counter 12 at the time when the corresponding task ends.

  The initial value register 28 holds the counter value of the count register 32 corresponding to the time until the processing deadline assigned to the task (referring to the target time until the processing is completed with reference to the start time).

  The count start PC register 24, the count stop PC register 26, and the initial value register 28 may be separate as shown in FIG. 1, but may indicate different storage areas on the same register. Absent.

  The timer processing unit 30 monitors the program counter 12, and when the value of the program counter 12 matches the value held in the count start PC register 24, the value held in the initial value register 28 is changed to the count register 32. And the register value of the count register 32 is decremented at a predetermined pace.

  Here, for example, a reference clock is supplied to the timer processing unit 30 from a clock generator that supplies a reference clock to the entire information processing apparatus 1. Then, the register value of the count register 32 is decremented by a predetermined value at a timing such as the rise of the reference clock.

  As a result, when the processing time limit assigned to the task arrives, the register value of the count register 32 becomes zero (underflows). The configuration information held by the timer setting register 22 includes information such as which clock in the information processing apparatus 1 is selected.

  Furthermore, the timer processing unit 30 stops the decrement process when the value of the program counter 12 matches the value held in the count stop PC register 26. This operation is performed when the task is completed normally. At the end of the decrement process, a process for writing the value held in the initial value register 28 to the count register 32 may be performed.

  On the other hand, when the register value of the count register 32 becomes zero (underflows), the underflow detection unit 34 writes a predetermined value in the abnormality detection status register 36 (“Operation at the time of predetermined abnormality detection” in the claims) Is an example). Such an operation is performed when the task is not completed by the processing deadline.

  The abnormality detection status register 36 is a so-called SFR (Special Function Register), and a register value can be referred to from software executed by the CPU 10 and other processors.

  The abnormality detection status register 36 may be referred to by the interrupt control unit 50 or the like. In this case, the interrupt control unit 50 periodically monitors whether or not a predetermined value is written in the abnormality detection status register 36, and when the predetermined value is written, stops the corresponding task. Etc. are executed.

  With such a configuration, in the information processing apparatus 1 of the present embodiment, the timer realized by the timer processing unit 30 and the count register 32 when the timer processing unit 30 determines that the value of the program counter 12 has reached the start position. When the timer processing unit 30 determines that the value of the program counter 12 has reached the end position by the processing deadline, the task is normally completed. On the other hand, if the timer processing unit 30 does not determine that the value of the program counter 12 has reached the end position after the timer starts counting, a predetermined abnormality detection operation is performed.

  This makes it possible to perform processing time limit management for a plurality of tasks for which processing time limits are set. In addition, when a processing time limit violation occurs in a certain task, it is only necessary to stop the task, so that it is possible to continuously execute processing for other tasks.

  Further, as described above, since the time is measured by the hardware means including the timer processing unit 30, the count register 32, and the supplied reference signal, the time measurement accuracy can be increased, and the processing time limit management can be performed with higher accuracy. It can be performed.

[Processing flow]
Hereinafter, the flow of processing executed in each processing stage of the information processing apparatus 1 will be described. FIG. 2 is a flowchart showing a flow of processing started when the information processing apparatus 1 is turned on.

  When the information processing apparatus 1 is powered on, various initialization processes are executed (S100). Specifically, CPU initialization, RAM initialization, peripheral hardware initialization, processing time limit management hardware initialization, and the like are executed.

  Here, initialization of the processing time limit management hardware is held in a timer setting register 22, a count start PC register 24, a count stop PC register 26, and an initial value register 28 from a non-volatile memory such as a ROM (not shown). A process of reading power values and writing them.

  When various initialization processes are completed, the information processing apparatus 1 starts a normal operation (S102).

  FIG. 3 is a flowchart showing a flow of processing time limit violation monitoring processing executed by an OS (Operating System) (not shown) in the information processing apparatus 1. This OS has functions such as a CPU dispatcher and a cache controller.

  This flow is started when an interrupt signal is output from the interrupt control unit 50, for example.

  First, the OS in the information processing apparatus 1 refers to the value of the abnormality detection status register 36 included in each processing time limit management hardware to determine whether there is a task in which a processing time limit violation has occurred (S200). ). If there is no task for which a processing time limit violation has occurred, one routine of this flow is terminated.

  If there is a task for which a processing time limit violation has occurred, it is determined whether or not a system reset is necessary based on the importance of the task for which the processing time limit violation has occurred (S202). The case where the system reset is necessary is a case where the task in which the processing time limit violation has occurred affects the processing of the entire apparatus.

  If it is determined that a system reset is necessary, the system reset is executed (S204), and one routine of this flow is terminated. In this case, for example, the initialization process described with reference to FIG. 2 is executed.

  On the other hand, when it is determined that the system reset is not necessary, a process for the task in which the processing time limit violation occurs is executed (S206). Specifically, a reinitialization or stop of the task in which the processing time limit violation has occurred is executed.

  Then, initialization processing of the processing time limit management hardware corresponding to the task in which the processing time limit violation has occurred is executed (S208), the processing is shifted to the next task (S210), and one routine of this flow is ended. . The task for which the processing time limit violation has occurred is started from the initial state when the next processing time is allocated.

[Comparison with conventional equipment]
Here, a comparison with a conventional information processing apparatus having a single timer will be described. FIG. 4 is a diagram schematically illustrating a state in which an abnormality has occurred in a task and a processing time limit violation has occurred in a conventional information processing apparatus having a single timer. In this figure, the conventional information processing apparatus executes a plurality of tasks A to C by software multithreading. Then, the processing time limit management is performed only for task C.

  As shown in FIG. 4, in the conventional information processing apparatus, when an abnormality occurs in task C, and a processing time limit violation occurs, the entire process must be reset. Therefore, the contents of other tasks that have been processed until then may not be taken over.

  On the other hand, FIG. 5 is a diagram schematically illustrating a state in which an abnormality has occurred in a certain task in the information processing apparatus 1 according to the present embodiment, thereby causing a processing time limit violation. In this figure, the information processing apparatus 1 according to the present embodiment executes a plurality of tasks A to C by software multithreading. And the process time limit management is performed about task AC.

  As shown in FIG. 5, in the information processing apparatus 1 according to the present embodiment, even if an abnormality occurs in the task C, and the processing time limit violation occurs, it is not necessary to reset the entire processing (described above). As in the case where task C affects the processing of the entire apparatus, as in FIG. Therefore, the contents of other tasks that have been processed so far can be succeeded.

[Summary]
According to the information processing apparatus 1 of the present embodiment described above, it is possible to perform processing time limit management for a plurality of tasks for which processing time limits are set. In addition, when a processing time limit violation occurs in a certain task, it is possible to continuously execute processing for other tasks.

  Furthermore, the timekeeping accuracy can be increased, and the processing time limit can be managed with higher accuracy.

  Therefore, the processing time limit management for each of a plurality of tasks processed in parallel can be performed with higher accuracy.

[Application example]
Note that the information processing apparatus of the present invention is suitably applied to a control apparatus that is mounted on a vehicle and performs in-vehicle device control. In this case, the plurality of tasks include, for example, calculation processing for performing on-vehicle equipment control, such as calculation of ignition timing of an injector attached to each cylinder of the engine. Output values of a crank angle sensor and an in-cylinder pressure sensor indicating the state of the engine are input to the control device, and the control device performs AD (Analog Digital) conversion and holds these as digital data to perform various calculations. In such a control device, the same processing is repeatedly executed, and the number n of tasks is often fixed, so that the effect of the present invention can be sufficiently exerted.

  In addition, when there are a plurality of information processing apparatuses according to the present invention (for example, when a plurality of information processing apparatuses according to the present invention as a control apparatus that performs in-vehicle device control is mounted in a vehicle) This makes it easier to port software.

  In FIG. 6, there is an information processing apparatus 1A that performs processing of tasks A to C, and an information processing apparatus 1B that executes only processing of task D, and information on the processing of task C is received from the information processing apparatus 1A. It is a figure which shows a mode that it transfers to the processing apparatus 1B. Such transfer of task processing is performed, for example, when it is necessary to reduce processing tasks due to a ROM capacity problem of the information processing apparatus 1A.

  In such a case, if both information processing apparatuses are provided with a plurality of processing time limit management hardwares in advance, the timer setting register 22, the count start PC register 24, and the count stop PC are transferred when task processing is transferred. By simply copying the values to be written to the register 26 and the initial value register 28, the processing time limit management performed in the information processing apparatus 1A can be taken over by the information processing apparatus 1B. Accordingly, it is not necessary to rewrite software related to the processing time limit management, and software can be easily transplanted between information processing apparatuses.

[Modification]
The best mode for carrying out the present invention has been described above with reference to the embodiments. However, the present invention is not limited to these embodiments, and various modifications can be made without departing from the scope of the present invention. And substitutions can be added.

  For example, the values written in the timer setting register 22, the count start PC register 24, the count stop PC register 26, the initial value register 28, etc. are described as if they were constant values stored in the ROM or the like. It is good also as a value which can be changed by. In this case, it is preferable to store these values in a nonvolatile memory such as an EEPROM instead of a mere ROM, and dynamically change the processing time limit according to the task processing load or the like.

  In addition, although the decrement counter using the count register 32 is illustrated as the time measuring means, the present invention is not limited to this, and time measuring means of other modes may be used.

1 Information processing apparatus 10 CPU 10
12 Program counter 20 (20 # 1 to 20 # n) Processing time limit management hardware 22 Timer setting register 24 Count start PC register 26 Count stop PC register 28 Initial value register 30 Timer processing unit 32 Count register 34 Underflow detection unit 36 Anomaly detection status register 50 Interrupt controller

Claims (5)

An information processing apparatus capable of processing a plurality of tasks in parallel by a single processor,
A processing deadline is set for at least some of the plurality of tasks,
A plurality of processing time limit management hardware means corresponding to a plurality of tasks for which a processing time limit is set among the plurality of tasks,
Information processing device. The information processing apparatus according to claim 1,
The plurality of processing time limit management hardware means each include a dedicated time measuring means,
Information processing device. An information processing apparatus according to claim 2,
The plurality of processing time limit management hardware means,
Program counter monitoring means for monitoring a value of a program counter of a program executed by the one unit of processor;
Storage means for storing information on the start position, end position, and processing deadline of the program counter corresponding to a plurality of tasks for which a processing deadline is set among the plurality of tasks;
With
When the program counter monitoring means determines that the value of the program counter has reached the start position, the time counting means starts measuring time, and after the time measurement starts, by the program counter monitoring means, the program counter monitoring means When it is not determined that the value of the value has reached the end position, a predetermined abnormality detection operation is performed,
Information processing device. The information processing apparatus according to claim 3,
The predetermined abnormality detection operation is an operation of writing a value indicating abnormality detection in an SFR (Special Function Register).
Information processing device.   5. The information processing apparatus according to claim 1, wherein the information processing apparatus is mounted on a vehicle, and the plurality of tasks includes a calculation process for controlling an in-vehicle device.

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