JP2011147056A - Image reading apparatus and image data rearranging method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image reading apparatus compatible with components of various configurations such as a line image sensor and an AFE. <P>SOLUTION: An image reading apparatus has a rearranging means for rearranging image data of each channel for each of RGB colors output from a three-line image sensor having one or more channels (ch) for RGB colors in the order of channel numbers (ch_no) so as to form one-line RGB image data. The rearranging means calculates a sensor ch_no of RGB image data for each channel, in accordance with a predetermined formula, based on various setting values and various counter values corresponding to the order of input RGB image data of channels, and rearranges the image data in the order of the sensor ch_no. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

The present invention relates to an image reading apparatus for processing image data read by an image sensor,
And an image data rearrangement method.

A line image sensor that is divided into a plurality of portions (channels) in the main scanning direction and outputs image data read in each channel in parallel is known. In addition, an image reading apparatus (for example, a scanner, a copier, a multifunction machine, etc.) on which this line image sensor is mounted.
It has been known. For example, Patent Document 1 describes an image reading apparatus as described above.

In addition, the line image sensor as described above is connected to R (red), G (green), B (
Blue) An image reading apparatus provided for each color, that is, a three-line image sensor is known.

Image data output in parallel from each channel of the above-described line image sensor is converted from analog data to digital data by an A / D converter (for example, AFE (Analog Front End)), and is stored in the image reading apparatus. Image processing ASIC (Applic
image processing units (SoC (System on a Chi)
also called p).

JP 2007-127404 A

Incidentally, in recent years, there has been an increasing demand for price reduction and downsizing (thinning) of image reading apparatuses. Therefore, the number of CIS image reading apparatuses is increasing. In recent years, there has been an increasing demand for faster processing of image reading apparatuses. Therefore, in particular, in a CIS type image reading apparatus, a line image sensor is being made into a plurality of channels.

In addition, in the future, various parts such as line image sensors with various configurations (for example, the number of channels) and AFE with various configurations (for example, the number of input channels, the number of output channels, the output data order, etc.) will be provided along with the formation of multiple channels It is assumed that it is mounted on an image reading apparatus.

However, generally, the SoC of the image reading apparatus is designed in advance according to the configuration of various parts such as a line image sensor and an AFE mounted on the image reading apparatus. For this reason, it is not possible to deal with parts having various configurations in general, and design changes are required each time according to the configuration of the parts.

Since SoC needs to generate correct image data in the end, it is necessary to arrange the input image data of each channel in the order of the channels in the main scanning direction in the line image sensor. In other words, the SoC is the image data input at which timing,
It has a mechanism for identifying which channel data. However, when the configuration of various parts such as a line image sensor and AFE is changed, the design of this mechanism needs to be changed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technique that enables an image reading apparatus to be used universally for parts such as line image sensors and AFEs having various configurations.

One embodiment of the present invention for solving the above-described problem is an image reading apparatus, in which each RGB color 1
The above-described 3-line image sensor of channel (ch), and A / D that outputs the image data of each channel of each color of RGB output from the 3-line image sensor after A / D conversion.
A conversion unit (AFE), RGB integration means for outputting image data of each channel of each RGB color output in a predetermined order from the A / D conversion unit to RGB image data for each same channel, and parallel input The parallel / serial conversion means for serially rearranging the RGB image data of each channel, and the rearrangement for rearranging the serially input RGB image data of each channel in order of channel number (ch_no) so as to become one line of image data An image processing unit (SoC), and the rearranging means uses various formulas shown below, and various setting values and various counter values corresponding to the order in which the RGB image data of each channel is input. Based on the above, the sensor ch_no of the RGB image data of each channel is calculated, and the sensor Sorted in order of ch_no, the image data of each RGB color is 1
When output from the A / D conversion unit in one channel, the total number of AFE input channels is set by dividing by 3, and when image data of each color of RGB is output from the A / D conversion unit in a different channel, the AFE The total number of input channels and the total number of AFE output channels are set by dividing by 3, respectively.
<Official>
Sensor ch_no = (Total number of AFE input channels / Number of SoC input channels) * (SoC input channel counter)
+ (data jump width in channel) * (SoC input data counter)
+ (Data skip width counter)
<Definition of counter>
-SoC input channel counter (ch_cnt): initial value 0, (number of parallel / serial conversion means input channels-1) count-SoC input data counter (datain_cnt): initial value 0, ((((AFE total number of input channels / Total number of AFE output channels
) / data jump width in ch) −1) count ・ Data jump counter (jump_cnt): Initial value 0, (data jump width in ch−1 minus) count ・ Counter priority: SoC input ch counter (ch_cnt) > SoC input data counter (
datain_cnt)> Data jump counter (jump_cnt)
<Setting value>
-Number of SoC input channels: Number of input channels of parallel / serial conversion means-Total number of AFE input channels: Total number of AFE input channels-Total number of AFE output channels: Total number of AFE output channels-Data jump width in channels: Interval between the channel number to be output next and the channel number output before it in AFE (1 or more)
・ Maximum counter values

Here, in the above-described image reading apparatus, the rearranging unit includes the calculated sensor ch_no
Is larger than (number of sensor ch of each RGB color −1), the processing on the RGB image data of the channel may be skipped.

Further, any one of the above image reading apparatuses, comprising a RAM, a ROM, and a CPU, wherein the rearrangement unit has a circuit for calculating and rearranging the sensor ch_no of the RGB image data of each channel, The various setting values are stored in advance in the ROM, and are set in the sorting unit by the CPU. The sorting unit writes the RGB image data of each channel sorted in the order of sensor ch_no into the RAM. It may be characterized by that.

The image reading apparatus according to any one of the above, further comprising a RAM, a ROM, and a CPU, wherein the rearranging unit executes each channel by executing a predetermined program stored in the ROM on the CPU. A circuit for writing the RGB image data of the respective channels rearranged in the order of the sensor ch_no into the RAM.

Further, in any of the above image reading devices, by changing the various setting values,
・ Number of sensor channels 3 (RGB 1ch each), 1 AFE (3ch input, 1ch output, data skip width 1)
-Number of sensor channels 3 (RGB each 1 channel), 3 AFEs (1 channel input, 1 channel output, data skip width 1)
・ Sensor channel number 6 (RGB each 2ch), 3 AFE (2ch input, 1ch output, data skip width 1)
-Number of sensor channels 18 (6 for each RGB), 3 AFE (6 channels input, 3 channels output, data skip width 1)
-Number of sensor channels 12 (RGB each 4 channels), 3 AFEs (4 channels input, 1 channel output, data skip width 2)
-Number of sensor channels 24 (RGB each 8 channels), 6 AFEs (4 channels input, 1 channel output, data skip width 2)
It may be characterized by corresponding to at least one of the configurations.

Another aspect of the present invention for solving the above problem is a method of rearranging image data in an image reading device, wherein the image reading device includes a three-line image sensor for channels (ch) of RGB colors 1 or more. A / D conversion unit (AFE) for A / D-converting and outputting image data of each RGB color channel output from the 3-line image sensor, and output from the A / D conversion unit in a predetermined order RGB image data for each channel of each RGB color, RGB integration processing for outputting together RGB image data for each channel, parallel / serial conversion processing for serially rearranging RGB image data for each channel input in parallel, The RGB image data of each channel that is input serially is changed to one line of image data. And an image processing unit (SoC) that performs rearrangement processing for rearranging in order of the channel number (ch_no). The rearrangement processing uses various formulas and RGB image data for each channel according to the formula shown below. Based on the various counter values corresponding to the input order, the sensor ch_no of the RGB image data of each channel is calculated, rearranged in the order of the sensor ch_no, and the image data of each RGB color is the A / D conversion unit in one channel. When output from the A / D conversion unit, set the total number of AFE input channels divided by 3, and output image data of each RGB color from the A / D conversion unit on different channels.
The number and the total number of AFE output channels are set by dividing by 3, respectively.
<Official>
Sensor ch_no = (Total number of AFE input channels / Number of SoC input channels) * (SoC input channel counter)
+ (data jump width in channel) * (SoC input data counter)
+ (Data skip width counter)
<Definition of counter>
-SoC input channel counter (ch_cnt): initial value 0, (number of parallel / serial conversion input channels-1) count-SoC input data counter (datain_cnt): initial value 0, ((((AFE total number of input channels / Total number of AFE output channels
) / data jump width in ch) −1) count ・ Data jump counter (jump_cnt): Initial value 0, (data jump width in ch−1 minus) count ・ Counter priority: SoC input ch counter (ch_cnt) > SoC input data counter (
datain_cnt)> Data jump counter (jump_cnt)
<Setting value>
-Number of SoC input channels: Number of input channels for parallel / serial conversion processing-Total number of AFE input channels: Total number of AFE input channels-Total number of AFE output channels: Total number of AFE output channels-Data jump width in channels: Interval between the channel number to be output next and the channel number output before it in AFE (1 or more)
・ Maximum counter values

1 is a block diagram showing an example of a schematic hardware configuration of an image reading apparatus according to an embodiment of the present invention. The figure which shows the formula for calculating a sensor channel number. The figure which shows the simplified formula corresponding to various conditions. FIG. 6 is a diagram for explaining setting of various conditions according to the configuration of the image reading apparatus. The figure which shows the data order corresponding to the example of various conditions. The figure which shows the 1st structural example of AFE and SoC. The figure explaining the relationship between the various counter values and channel number in the 1st example of composition. The figure which shows the 2nd structural example of AFE and SoC. The figure explaining the relationship between the various counter values and channel number in the 2nd example of composition. The figure which shows the 3rd structural example of AFE and SoC. The figure explaining the relationship between the various counter values and channel number in the 3rd example of composition. The figure which shows the 4th structural example of AFE and SoC. The figure explaining the relationship between the various counter values and channel number in the 4th example of composition. The figure which shows the 5th structural example of AFE and SoC. The figure explaining the relationship between the various counter values in a 5th structural example, and a channel number. The figure which shows the 6th structural example of AFE and SoC. The figure explaining the relationship between the various counter values in a 6th structural example, and a channel number. The flowchart which shows the rearrangement process of image data. The figure which shows the structural example of the table which converts the order of image data into a channel number.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an example of a schematic hardware configuration of an image reading apparatus 1 according to an embodiment of the present invention. This figure mainly shows a configuration relating to rearrangement of image data of each channel.

The image reading device 1 is a device that performs color reading, such as a so-called scanner, copier, or multifunction device. The image reading apparatus 1 is, for example, a CIS method. The image reading apparatus 1 includes a three-line image sensor 10, an AFE 20, and a SoC 30.

The 3-line image sensor 10 includes line image sensors corresponding to RGB colors. The three-line image sensor 10 generates image data (analog data) in units of one line for each RGB color and outputs the image data to the AFE 20.

Various specifications of the three-line image sensor 10 are assumed. For example, R
The line image sensor for each color of GB is configured by one channel or a plurality of channels arranged in the main scanning direction.

When there is one channel, image data (analog data) for one line generated by the line image sensor for each color of RGB by applying light to the document is composed of data for one channel. The image data of one line of each color of RGB is parallel to the AFE 20
Is output.

When there are a plurality of channels, the image data (analog data) for one line generated by the line image sensor for each color of RGB by irradiating the original with light is composed of data of a plurality of channels. Image data of each channel of one line of each color of RGB is output to the AFE 20 in parallel.

The AFE 20 receives the analog image data output from the three-line image sensor 10, converts it into digital image data, and outputs it to a circuit (SoC 30) at the subsequent stage. A
The FE 20 may be configured by one AFE circuit, or may be configured by combining a plurality of AFE circuits.

Various specifications are assumed for one AFE circuit. For example, there is a configuration in which one-channel image data of any one color among RGB input serially is serially output as one-channel data. In addition, RGB input in parallel
Some image data of each channel are serially output in one channel in a predetermined color order. For example, the order of the predetermined colors includes the order of R, G, and B.

In addition, for example, there is a configuration in which image data of a plurality of channels of any one color among RGB input in parallel is serially output in one channel in a predetermined channel order. The order of the predetermined channels includes the order of channel numbers (for example, when R channel number = 4, the order of R0, R1, R2, and R3) and the order in which channel numbers are skipped by a predetermined number (for example, R channels). When the number = 4 and the flying width is 2, R0, R2, R1, R
3). Further, for example, there is a configuration in which image data of a plurality of channels of any one color among RGB input in parallel is collectively output in a predetermined channel order for each of a plurality of channels smaller than the input. .

In addition, for example, image data of a plurality of RGB color channels input in parallel is converted into RGB.
There is a configuration in which each color is output in parallel in one channel in a predetermined channel order.

The SoC 30 is a unit that rearranges image data input from the AFE 20 and performs various image processing. The SoC 30 includes an RGB integration circuit 40 and a parallel / serial conversion circuit 5.
0, an image processing circuit 60, a RAM 70, a CPU 80, and a ROM 90.

The RGB integration circuit 40 receives image data of each RGB color channel output from the AFE 20 in parallel or serially, collects it into one data for each corresponding channel (same channel number) of each RGB color, The data is output in parallel or serial to the (parallel / serial conversion circuit 50 or image processing circuit 60).

For example, the RGB integration circuit 40, when image data of 2 channels of each RGB color is input in parallel in the channel order ((R0, G0, B0), (R1, G1, B1)), the 0 channel data (R0, G0, B0) is one data D0 and one channel data (
R1, G1, B1) are collectively output as one data D1 and serially output. In addition, for example, when image data of two channels of each RGB color are all input in parallel (R0, R1
, G0, G1, B0, B1), D0 and D1 are output in parallel.

The parallel / serial conversion circuit 50 includes a preceding circuit (AFE 20 or RGB integrated circuit 40).
), The image data output in parallel through a plurality of channels is received, collected into one channel in a predetermined channel order, and serially output to the subsequent circuit (image processing circuit 60). For example, when the parallel input is 2 channels, image data input from each channel is alternately obtained and serially output.

The image processing circuit 60 is supplied from the RGB integration circuit 40 or the parallel / serial conversion circuit 50.
The serially output image data of each channel of each color line of RGB is received, and predetermined image processing (for example, shading correction, gamma correction, etc.) is performed, and the image data of each channel is subjected to main scanning in the 3-line image sensor 10. The data is written in the RAM 70 so as to be in the order of the channels in the direction (aligned in order from the first pixel to the last pixel of the line).

The RAM 70 is a large-capacity storage device used to temporarily store programs executed by the CPU 80, image data whose data order has been rearranged by the image processing circuit 60, and the like. The RAM 70 is a volatile memory such as SDRAM or DDR-SDRAM, for example.

The CPU 80 implements various processes by reading a predetermined program from the ROM 90 into the RAM 70 and executing it. The CPU 80 controls the SoC 40 in an integrated manner,
For example, predetermined image processing is performed on the image data stored in the AM 70.

The ROM 90 is a storage device that stores various programs and data to be executed by the CPU 80. The ROM 90 is, for example, a nonvolatile flash ROM.

The above is the configuration related to the rearrangement of the image data of the image reading apparatus 1 according to the present embodiment. Therefore, the configuration of the image reading apparatus 1 described above is the main configuration for describing the features of the present invention, and is not limited to the above. Further, the configuration of the image reading apparatus 1 does not exclude other configurations included in a general image reading apparatus.

For example, the image processing circuit 60 may be a dedicated circuit that rearranges the image data of each channel of RGB colors. In this case, in addition to the image processing circuit 60, a circuit for performing various image processing such as shading correction and gamma correction may be provided.

As described above, the image reading apparatus 1 is a component having various specifications (three-line image sensor 10, AFE 20, RGB integration circuit 40, parallel / serial conversion circuit 50).
It is assumed that it is comprised by the combination of. For this reason, the order of the image data of the RGB color channels of the three-line image sensor 10 serially input to the image processing circuit 60 differs depending on the combination of the various components.

Therefore, the image processing circuit 60 according to the present embodiment can rearrange the image data in a general manner corresponding to various orders of the image data of each RGB color that varies depending on the combination of the various components. The circuit configuration is based on the formula described below. With this configuration, the image processing circuit 60 can specify the channel number of the image data of each channel of each line of RGB that is sequentially input.

FIG. 2 is a diagram illustrating a formula for calculating a sensor channel number. Hereinafter, the channel number will be described as “ch_no” and the channel as “ch” as appropriate.

<Sensor ch_no calculation formula>
Sensor ch_no = (Total number of AFE input channels / Number of SoC input channels) * (SoC input channel counter)
+ (data jump width in channel) * (SoC input data counter)
+ (Data skip width counter)

<Counter>
-SoC input (parallel / serial conversion circuit input) ch counter (ch_cnt): Initial value 0, (number of parallel / serial conversion circuit input channels-1) count-SoC input (parallel / serial conversion circuit input) data counter (datain_cnt ): Initial value 0
, (((AFE total number of input channels / AFE total output channels) / data jump width in ch) -1) count / data jump width counter (jump_cnt): initial value 0, (data jump width in ch-1) Minute count

-Counter priority: The priority for counting the various counters is as follows.
SoC input ch counter (ch_cnt)> SoC input data counter (datain_cnt)> Data jump counter (jump_cnt)
-Counting procedure of counter: Count up to the maximum value in order from the upper counter. When the upper counter reaches the maximum value, the lower counter is counted up by 1, and the upper counter is reset to 0 and counted up. That is, when the upper counter is counted up to the maximum value, it is incremented and added to the lower counter. For example, when the maximum value of each counter is 1, the value of each counter (ch_cnt, datain_cnt, jump_cnt) is (0,0,0
), (1,0,0), (0,1,0), (1,1,0), (0,0,1), (1,0,1), (0,1,1), It changes like (1,1,1).

<Condition (setting value)>
-Number of SoC input (parallel / serial conversion circuit input) channels: Number of input channels of parallel / serial conversion circuit-Total number of AFE input channels: Number of input channels of AFE (if AFE is composed of multiple AFE circuits, each If the total number of AFE input channels) and the total number of AFE input channels> number of sensor channels, it can be determined that there are unused input channels.
-Total number of AFE output channels: Number of AFE output channels (If the AFE is composed of multiple AFE circuits, the total number of output channels of each AFE circuit)
-Number of sensor channels: Total number of RGB sensor channels-Number of RGB sensor channels: Number of sensor channels / 3
In-channel data skip width: The interval between the channel number to be output next and the channel number output before it in each AFE circuit, a value of 1 or more is set.
-Number of data in each sensor channel: Used to read out the unnecessary data and the number of effective data to be acquired as image data from each sensor channel of each RGB color.
・ Maximum counter values

The above formula can be simplified according to conditions (set values). FIG. 3 is a diagram showing simplified formulas corresponding to various conditions.

<Simplified sensor ch_no calculation formula corresponding to various conditions (setting values)>
(1) SoC input (parallel / serial conversion circuit input) When the number of channels is 1ch and skip width is 1:
Sensor ch_no = (data skip width in ch) * (SoC input data counter)
(2) When the number of SoC input (parallel / serial conversion circuit input) channels is multiple and the jump width is 1:
Sensor ch_no = (Total number of AFE input channels / Number of SoC input channels) * (SoC input channel counter)
+ (data jump width in channel) * (SoC input data counter)
(3) SoC input (parallel / serial conversion circuit input) When the number of channels is 1ch and the jump width is 2 or more:
Sensor ch_no = (data skip width in ch) * (SoC input data counter)
+ (Data skip width counter)
(4) SoC input (parallel / serial conversion circuit input) When the number of channels is more than one and the skip width is 2 or more:
Sensor ch_no = (Total number of AFE input channels / Number of SoC input channels) * (SoC input channel counter)
+ (data jump width in channel) * (SoC input data counter)
+ (Data skip width counter)

The image processing circuit 60 has a circuit configuration for performing an operation based on the above-described formula. When the input of image data of each channel of the RGB color lines is started, the image processing circuit 60 counts up various counters according to the above-described procedure, and calculates a sensor ch_no for each combination of various counter values. In this way, the channel numbers corresponding to the RGB color image data sequentially serially input are specified, and the RGB color image data is stored in the RAM 70 so as to be in the order of the channels in the main scanning direction in the three-line image sensor 10. Can be written on.

The various conditions (setting values) are set before the calculation by the image processing circuit 60 is started. Specifically, the above-mentioned various conditions (setting values) are determined when the image reading device or the SoC 40 is manufactured.
Recorded in the ROM 90. The various conditions (setting values) are read from the ROM 90 when the CPU 80 executes a predetermined program at the time of starting the image reading apparatus 1 and set in a register or the like of the image processing circuit 60. To.

In this embodiment, when the calculation by the image processing circuit 60 based on the above formula is started,
The setting of the total number of AFE input channels and the total number of AFE output channels is changed according to the circuit configuration of the SoC 30.

Specifically, as shown in FIG. 4A, when the AFE 20 collectively outputs image data of RGB colors in one channel, AFE total input channel count = AFE total input channel count / 3. . The setting of the total number of AFE output channels is not changed. On the other hand, as shown in FIG.
When 0 outputs RGB color image data to different channels, the total number of AFE input channels = AFE
Total number of input channels / 3, AFE total number of output channels = AFE total number of output channels / 3

The information for determining the configuration of FIG. 4A or 4B is, for example, an image reading device or So
It is recorded in the ROM 90 as flag information when the C40 is manufactured. CPU 80
Reads the flag information from the ROM 90 by executing a predetermined program, and AF
E Calculate the total number of input channels and the total number of AFE output channels, and change the settings.

As described above, the image processing circuit 60 can perform an operation based on the above-described formula.

Note that the total number of AFE input channels and the total number of output AFE channels do not have to be changed when the image processing circuit 60 starts computation. For example, the total number of AFE input channels and AFE total output channels after changing in advance
The number may be recorded in the ROM 90 and the value may be set.

FIG. 5 shows the image data order (data arrangement) of each channel input to the image processing circuit 60 when specific conditions (setting values) are set in the above formula. Note that this figure does not cover all the assumed conditions, but lists examples of useful conditions.

How to read this figure is as follows.
・ "#"
Item number / Sensor configuration “Number of channels”
Total number of ch of each color line of RGB / AFE configuration “number”:
Number of AFEs constituting the AFE 20 / AFE configuration “input ch”:
Number of input channels of each AFE constituting the AFE 20 / AFE configuration “output ch”:
Number of output channels of each AFE constituting the AFE 20 and SoC configuration “input ch”:
Number of input channels of SoC 30 (in this figure, this is not the number of input channels of the parallel / serial conversion circuit)
-1ch data array “RGBx_y”:
“RGB sensor ch number_data number in ch”

6 to 17 show a configuration example of the image reading apparatus 1 and a relationship between a counter value and a channel number in each configuration example.

Note that “data_ch” in the figure indicates a channel input to the RGB integrated circuit 40. "C
“data_ch” indicates a channel input to the parallel / serial conversion circuit 50. "C_cnt
"Is a counter that is counted for each color of RGB when RGB are input to one channel at a time. “Data_cnt” is a counter counted for each data number in ch. “Sel_data” indicates the selected data.

“Rx_y” indicates “R sensor ch number_data number in ch”. “Gx_y” indicates “G sensor ch number_data number in ch”. “Bx_y” indicates “data number in B sensor ch number_ch”. “Dx_y” indicates “RGB sensor ch number_data number in ch”.
When the number of sensor channels is one, x may be omitted as in “R_y”.

In addition, “(0,... N)” in the formula in which various setting values are officially applied indicates a range and a value in which various counters are counted.

FIG. 6 is a diagram illustrating a first configuration example of AFE and SoC. FIG. 7 is a diagram for explaining the relationship between various counter values and channel numbers in the first configuration example.

The first configuration example is a configuration using a three-line image sensor (RGB each 1ch) and one AFE (3ch input 1ch output / jump width 1). In this configuration, image data for each color of RGB is data_ch
0 is combined into one. Therefore, the total number of AFE input channels is divided by 3. Various setting values of this configuration (SoC input (parallel / serial conversion circuit input) channel number 1, AFE total input channel number = 3/3, AFE
When the total number of output channels 1 and the data skip width 1) are officially applied, the following equations are obtained (see FIGS. 2 and 3 (1)).
Formula: 0 + 0 + 0
Therefore, the order of the sensor channel numbers of the image data input to the image processing circuit 60 is 0 for each line (see # 1 in FIG. 5 and ch_no in FIG. 7).

FIG. 8 is a diagram illustrating a second configuration example of AFE and SoC. FIG. 9 is a diagram illustrating the relationship between various counter values and channel numbers in the second configuration example.

The second configuration example is a configuration using a three-line image sensor (RGB each 1ch) and three AFEs (1ch input 1ch output / jump width 1). In this configuration, image data for each color of RGB is stored in each data_
Assigned to ch. Therefore, the total number of AFE input channels and the total number of AFE output channels are divided by three.
Various setting values of this configuration (SoC input (parallel / serial conversion circuit input) channel number 1, AFE total input c
When the number of h = 3/3, the number of AFE total output channels = 3/3, and the data skip width 1) are officially fitted, the following formula is obtained (see FIGS. 2 and 3 (1)).
Formula: 0 + 0 + 0
Therefore, the order of the sensor channel numbers of the image data input to the image processing circuit 60 is 0 for each line (see # 2 in FIG. 5 and ch_no in FIG. 9).

FIG. 10 is a diagram illustrating a third configuration example of AFE and SoC. FIG. 11 is a diagram for explaining the relationship between various counter values and channel numbers in the third configuration example.

The third configuration example is a configuration using a three-line image sensor (RGB each 2ch) and three AFEs (2ch input 1ch output / jump width 1). In this configuration, image data for each color of RGB is stored in each data_
Assigned to ch. Therefore, the total number of AFE input channels and the total number of AFE output channels are divided by three.
Various setting values of this configuration (SoC input (parallel / serial conversion circuit input) channel number 1, AFE total input c
When the number of h = 6/3, the number of AFE total output channels = 3/3, and the data skip width 1) are officially fitted, the following equations are obtained (see Fig. 2 and Fig. 3 (1)).
Formula: 0 + 1 * (0,1) +0
Accordingly, the order of the sensor channel numbers of the image data input to the image processing circuit 60 is 0, 1 for each line (see # 4 in FIG. 5 and ch_no in FIG. 11).

FIG. 12 is a diagram illustrating a fourth configuration example of AFE and SoC. FIG. 13 is a diagram illustrating the relationship between various counter values and channel numbers in the fourth configuration example.

The fourth configuration example is a configuration using a three-line image sensor (RGB each 6 ch) and three AFEs (6 ch input 3 ch output / jump width 1). In this configuration, image data for each color of RGB is stored in each data_
Assigned to ch. Therefore, the total number of AFE input channels and the total number of AFE output channels are divided by three.
Various setting values of this configuration (SoC input (parallel / serial conversion circuit input) channel number 3, AFE total input c
When the number of h = 18/3, total number of AFE output channels = 9/3, and data skipping width 1) are officially applied, the following formula is obtained (see Fig. 2 and Fig. 3 (2)).
Formula: 6/3 * (0,1,2) + 1 * (0,1) +0
Therefore, the order of the sensor channel numbers of the image data input to the image processing circuit 60 is 0, 2, 4, 1, 3, 5 for each line (see # 18 in FIG. 5 and ch_no in FIG. 13). ).

FIG. 14 is a diagram illustrating a fifth configuration example of AFE and SoC. FIG. 15 is a diagram for explaining the relationship between various counter values and channel numbers in the fifth configuration example.

The fifth configuration example is a configuration using a three-line image sensor (RGB each 4 ch) and three AFEs (4 ch input 1 ch output / jump width 2). In this configuration, image data for each color of RGB is stored in each data_
Assigned to ch. Therefore, the total number of AFE input channels and the total number of AFE output channels are divided by three.
Various setting values of this configuration (SoC input (parallel / serial conversion circuit input) channel number 1, AFE total input c
When the number of h = 12/3, the number of AFE total output channels = 3/3, and the data skip width 2) are officially fitted, the following equations are obtained (see FIGS. 2 and 3 (3)).
Formula: 0 + 2 * (0,1) + (0,1)
Therefore, the order of the sensor channel numbers of the image data input to the image processing circuit 60 is 0, 2, 1, 3 for each line (see # 12 in FIG. 5 and ch_no in FIG. 15).

FIG. 16 is a diagram illustrating a sixth configuration example of AFE and SoC. FIG. 17 is a diagram illustrating the relationship between various counter values and channel numbers in the sixth configuration example.

The sixth configuration example is a configuration using a three-line image sensor (RGB each 8 ch) and six AFEs (4 ch input 1 ch output / jump width 2). In this configuration, image data for each color of RGB is stored in each data_
Assigned to ch. Therefore, the total number of AFE input channels and the total number of AFE output channels are divided by three.
Various setting values of this configuration (SoC input (parallel / serial conversion circuit input) number of channels 2, AFE total input c
When the number of h = 24/3, the total number of AFE output channels = 6/3, and the data jump width 2) are officially fitted, the following equations are obtained (see Fig. 2 and Fig. 3 (4)).
Formula: 8/2 * (0,1) + 2 * (0,1) + (0,1)
Accordingly, the order of the sensor channel numbers of the image data input to the image processing circuit 60 is 0, 4, 2, 6, 1, 5, 3, 7 for each line (# 31 in FIG. 17 ch_no).

FIG. 18 is a flowchart showing image data rearrangement processing. In this flow, the image processing circuit 60 sequentially receives image data of each channel constituting one line of each RGB color.
The RAM is arranged so that the channel order in the main scanning direction in the line image sensor 10 is obtained.
The process of writing to 70 is shown. Note that at the start of this flow, the above-described various setting values and the initial value of the counter are set in the image processing circuit 60.

In S01, the CPU 80 determines whether one channel has three colors. In particular,
The AFE 20 determines whether to output RGB data in a single channel or to output RGB data in another channel based on information stored in the ROM 90 in advance. When one channel has three colors (S01: YES), the CPU 80 performs the process at S0.
Proceed to 2. When one channel is not three colors (S02: NO), the CPU 80 performs the process at S0.
Go to step 3.

In S02, the CPU 80 sets the number of input channels by dividing by 3. Specifically, CP
U80 reads the total number of AFE input channels from the ROM 90, divides the value by 3, and sets it in the register of the image processing circuit 60 or the like. Then, the process proceeds to S11.

In S03, the CPU 80 sets the number of input channels and the number of output channels by dividing by 3. Specifically, the CPU 80 reads the total number of AFE input channels and the total number of AFE output channels from the ROM 90, divides these values by 3, and sets them in the register of the image processing circuit 60 or the like.
Then, the process proceeds to S11.

Note that S01 to S03 may not be performed in this flow. For example, it may be set first when the image reading apparatus 1 is started, and thereafter, the set value may be used. Further, the processing of S01 to 03 may be executed by the image processing circuit 60.

In S11, the image processing circuit 60 determines the SoC input (parallel / serial conversion circuit input) ch.
Determine whether the number (set value) is 1ch. Parallel / serial conversion circuit input channel number is 1ch
(S11: YES), the process proceeds to S21. If the number of channels input to the parallel / serial conversion circuit is not 1 (S11: NO), the process proceeds to S12.

In S12, the image processing circuit 60 determines the SoC input (parallel / serial conversion circuit input) ch.
It is determined whether or not the counter is equal to the maximum value (setting value: (number of parallel / serial conversion circuit input channels −1)). If the SoC input ch counter is equal to the maximum value (S12: YES), the process proceeds to S21. When the SoC input channel counter is not equal to the maximum value (S12: NO)
), The process proceeds to S13.

In S13, the image processing circuit 60 determines whether the target image data is necessary data. Specifically, it is determined whether or not the sensor ch_no> (number of sensor ch of each RGB color-1) calculated by the formula. Calculated sensor ch_no is (number of RGB sensor ch-1 for each color-1)
If larger (S13: NO), S14 is skipped and the process proceeds to S15. When the calculated sensor ch_no is less than or equal to (the number of RGB sensor ch-1 minus 1) (S13: YES),
The process proceeds to S14.

In S <b> 14, the image processing circuit 60 writes the target RGB image data as the image data of the sensor ch_no calculated by the formula at a corresponding address in the RAM 70. Here, the data stored in the RAM 70 is the sensor c for each of the RGB colors of the calculated sensor ch_no.
Data within the range indicated by the number of valid data in h (set value). The image processing circuit 60 stores the data in the RAM 70 and advances the process to S15.

In S15, the image processing circuit 60 determines the SoC input (parallel / serial conversion circuit input) ch.
Increment the counter by 1. Then, the process returns to S12.

In S21, the image processing circuit 60 determines whether or not the ratio between the total number of AFE input channels (set value) and the total number of AFE output channels (set value) is 1: 1. When the ratio is 1: 1 (S21: YES),
The process proceeds to S31. If the ratio is not 1: 1 (S21: NO), the process proceeds to S22.

In S22, in the image processing circuit 60, the SoC input (parallel / serial conversion circuit input) data counter has a maximum value (setting value: (((AFE total number of input channels / total number of AFE output channels) / chest data jump width)).
−1)). When the SoC input data counter is equal to the maximum value (S
22: YES), the process proceeds to S31. If the SoC input data counter is not equal to the maximum value (S22: NO), the process proceeds to S23.

  The processes of S23 and S24 are the same as S13 and S14, respectively.

In S25, the image processing circuit 60 performs SoC input (parallel / serial conversion circuit input) ch.
The counter is cleared to 0 and the SoC input (parallel / serial conversion circuit input) data counter is incremented by 1. Then, the process returns to S11.

In S31, the image processing circuit 60 determines whether or not the data skip width (set value) is 1. If the data skip width is 1 (S31: YES), the process proceeds to S43. If the data skip width is not 1 (S31: NO), the process proceeds to S32.

In S32, the image processing circuit 60 determines whether or not the data skip width counter is equal to the maximum value (setting value: (data skip width in ch−1)). If the data skip width counter is equal to the maximum value (S32: YES), the process proceeds to S43. If the data skip width counter is not equal to the maximum value (S32: NO), the process proceeds to S33.

  The processes of S33 and S34 are the same as S13 and S14, respectively.

In S35, the image processing circuit 60 performs SoC input (parallel / serial conversion circuit input) ch.
The counter and SoC input (parallel / serial conversion circuit input) data counter are cleared to 0, and the data skip width counter is incremented by 1. Then, the process returns to S11.

  The processes of S43 and S44 are the same as S13 and S14, respectively.

In S45, the image processing circuit 60 performs SoC input (parallel / serial conversion circuit input) ch.
The counter, SoC input (parallel / serial conversion circuit input) data counter, and data skip width counter are cleared to zero. Then, this flow ends.

As described above, the image processing circuit 60 can specify the channel number of the RGB image data sequentially input. Further, the RGB image data can be rearranged in the order of channels according to the specified channel number.

The embodiment of the present invention has been described above. According to this embodiment, the image reading apparatus is
It is possible to provide a technology that can be used for a wide range of parts such as line image sensors and AFEs having various configurations.

In other words, it is not necessary to greatly change the SoC depending on the configuration of the AFE or sensor. Further, even if a part such as an AFE having a specification that does not exist is newly developed and the part is adopted in the image reading apparatus, it is possible to cope with it without major design change. Furthermore, since it is possible to examine combinations of various parts without major design changes so as to meet the performance and cost required for the product, it becomes easy to realize an optimum system configuration.

The above-described embodiments of the present invention are intended to illustrate the gist and scope of the present invention and are not intended to be limiting. Many alternatives, modifications, and variations will be apparent to those skilled in the art.

For example, in the above embodiment, the image processing circuit 60 has a circuit configuration for calculating a channel number for each input RGB image data, but the CPU 80 may calculate the channel number.

Specifically, the ROM 90 stores a predetermined program and various conditions (setting values) for executing a calculation based on the channel number calculation formula. Also, a conversion table for converting the input order of RGB image data into sensor channel numbers is prepared. The conversion table can be realized by, for example, an SRAM as shown in FIG. As shown in the figure, the SRAM is a capacitor having an area of the number of bits that can represent the number of sensor ch of each color of RGB for the number of sensor ch. For example, if the number of sensor channels for each RGB color is 32, 5
A bit x 32 word area may be prepared. The SRAM may be provided in the image processing circuit 60 or may be provided on the SoC 40 outside the image processing circuit 60.

The CPU 80 reads various setting values and a predetermined program from the ROM 90 and executes them when the image reading apparatus 1 is activated. Then, according to the program, the channel numbers are sequentially calculated by counting up various counters according to the above-described procedure. Further, the channel numbers sequentially calculated for each combination of counter values are stored sequentially (in order from the 0th area) in the SRAM.

After the channel numbers corresponding to the number of sensor channels of each RGB color are stored in the SRAM, the image processing circuit 60, for each line, for the RGB image data of each actually input channel, the channel number corresponding to the input order. Is specified with reference to the SRAM. Further, the RGB image data of each channel is stored at the address of the RAM 70 corresponding to the specified channel number.

When configured as described above, the same function as in the above-described embodiment can be realized, and the number of hardware gates can be significantly reduced.

Further, for example, in the above-described embodiment, in accordance with the maximum possible AFE configuration, S
The oC30 may be designed. In this way, it is not necessary to remake the SoC depending on the configuration of the AFE or sensor. Further, even if a part such as AFE having a specification that does not exist is newly developed and the part is adopted in the image reading apparatus, it is possible to cope with the design without any change. Specifically, it is not necessary to change the design of the RGB integrated circuit 40, the parallel / serial conversion circuit 50, the signal wiring, and the like. That is, the SoC 30 can be used in various image reading apparatuses 1 as a common component.

1: Image reading device, 10: 3 line image sensor, 20: AFE, 30: SoC, 4
0: RGB integration circuit, 50: parallel / serial conversion circuit, 60: image processing circuit, 70:
RAM, 80: CPU, 90: ROM

Claims (6)

An image reading device,
3 line image sensor of channel (ch) of RGB color 1 or more,
An A / D conversion unit (AFE) for A / D converting and outputting image data of each channel of RGB colors outputted from the three-line image sensor;
RGB integration means for outputting the RGB image data for each color of RGB in a predetermined order from the A / D conversion unit and outputting the RGB image data for each channel together, and the RGB image for each channel input in parallel Parallel / serial conversion means for rearranging data serially and RGB image data of each channel input serially as 1
An image processing unit (SoC) having rearrangement means for rearranging in order of channel numbers (ch_no) so as to become line image data,
The sorting means is
Based on various setting values and various counter values corresponding to the order in which the RGB image data of each channel is input, the sensor ch_no of the RGB image data of each channel is calculated according to the formula shown below, and arranged in the order of sensor ch_no. Change
When image data for each color of RGB is output from the A / D conversion unit in one channel, the total number of AFE input channels is divided by 3 to set the image data for each color of RGB in different channels. Output from AFE, set by dividing the total number of AFE input channels and the total number of AFE output channels by 3, respectively.
An image reading apparatus.
<Official>
Sensor ch_no = (Total number of AFE input channels / Number of SoC input channels) * (SoC input channel counter)
+ (data jump width in channel) * (SoC input data counter)
+ (Data skip width counter)
<Definition of counter>
-SoC input channel counter (ch_cnt): initial value 0, (number of parallel / serial conversion means input channels-1) count-SoC input data counter (datain_cnt): initial value 0, ((((AFE total number of input channels / Total number of AFE output channels
) / data jump width in ch) −1) count ・ Data jump counter (jump_cnt): Initial value 0, (data jump width in ch−1 minus) count ・ Counter priority: SoC input ch counter (ch_cnt) > SoC input data counter (
datain_cnt)> Data jump counter (jump_cnt)
<Setting value>
-Number of SoC input channels: Number of input channels of parallel / serial conversion means-Total number of AFE input channels: Total number of AFE input channels-Total number of AFE output channels: Total number of AFE output channels-Data jump width in channels: Interval between the channel number to be output next and the channel number output before it in AFE (1 or more)
・ Maximum counter values The image reading apparatus according to claim 1,
When the calculated sensor ch_no is larger than (number of sensor ch of each RGB color-1), the rearranging unit skips the process for the RGB image data of the channel.
An image reading apparatus. The image reading apparatus according to claim 1, wherein
RAM, ROM, and CPU,
The rearranging means includes a circuit for calculating and rearranging the sensor ch_no of the RGB image data of each channel,
The various setting values are stored in advance in the ROM and set in the sorting unit by the CPU.
The rearranger writes the RGB image data of each channel rearranged in the order of sensor ch_no into the RAM.
An image reading apparatus. The image reading apparatus according to claim 1, wherein
RAM, ROM, and CPU,
The sorting means is
The predetermined program stored in the ROM is executed by the CPU to calculate the sensor ch_no of the RGB image data of each channel,
A circuit for writing the RGB image data of each channel rearranged in the order of sensor ch_no into the RAM;
An image reading apparatus. An image reading apparatus according to any one of claims 1 to 5,
By changing the various setting values,
・ Number of sensor channels 3 (RGB 1ch each), 1 AFE (3ch input, 1ch output, data skip width 1)
-Number of sensor channels 3 (RGB each 1 channel), 3 AFEs (1 channel input, 1 channel output, data skip width 1)
・ Sensor channel number 6 (RGB each 2ch), 3 AFE (2ch input, 1ch output, data skip width 1)
-Number of sensor channels 18 (6 for each RGB), 3 AFE (6 channels input, 3 channels output, data skip width 1)
-Number of sensor channels 12 (RGB each 4 channels), 3 AFEs (4 channels input, 1 channel output, data skip width 2)
-Number of sensor channels 24 (RGB each 8 channels), 6 AFEs (4 channels input, 1 channel output, data skip width 2)
Corresponding to at least one configuration of
An image reading apparatus. A method for rearranging image data in an image reading apparatus, comprising:
The image reading device includes:
3 line image sensor of channel (ch) of RGB color 1 or more,
An A / D conversion unit (AFE) for A / D converting and outputting image data of each channel of RGB colors outputted from the three-line image sensor;
RGB integration processing for outputting image data of each channel of each RGB color output in a predetermined order from the A / D conversion unit to RGB image data for each same channel, and RGB images of each channel input in parallel Parallel / serial conversion processing for rearranging data serially and RGB image data of each channel input serially as 1
An image processing unit (SoC) that performs rearrangement processing for rearranging in order of channel numbers (ch_no) so as to be line image data,
The sorting process is
Based on various setting values and various counter values corresponding to the order in which the RGB image data of each channel is input, the sensor ch_no of the RGB image data of each channel is calculated according to the formula shown below, and arranged in the order of sensor ch_no. Change
When image data for each color of RGB is output from the A / D conversion unit in one channel, the total number of AFE input channels is divided by 3 to set the image data for each color of RGB in different channels. Output from AFE, set by dividing the total number of AFE input channels and the total number of AFE output channels by 3, respectively.
A method for rearranging image data.
<Official>
Sensor ch_no = (Total number of AFE input channels / Number of SoC input channels) * (SoC input channel counter)
+ (data jump width in channel) * (SoC input data counter)
+ (Data skip width counter)
<Definition of counter>
-SoC input channel counter (ch_cnt): initial value 0, (number of parallel / serial conversion input channels-1) count-SoC input data counter (datain_cnt): initial value 0, ((((AFE total number of input channels / Total number of AFE output channels
) / data jump width in ch) −1) count ・ Data jump counter (jump_cnt): Initial value 0, (data jump width in ch−1 minus) count ・ Counter priority: SoC input ch counter (ch_cnt) > SoC input data counter (
datain_cnt)> Data jump counter (jump_cnt)
<Setting value>
-Number of SoC input channels: Number of input channels for parallel / serial conversion processing-Total number of AFE input channels: Total number of AFE input channels-Total number of AFE output channels: Total number of AFE output channels-Data jump width in channels: Interval between the channel number to be output next and the channel number output before it in AFE (1 or more)
・ Maximum counter values

Images