JP2011124246A - Heterojunction field effect transistor and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a heterojunction FET having a recess gate structure that suppresses a gate leakage current and is made of a nitride semiconductor, and a method of manufacturing the same. <P>SOLUTION: The heterojunction field effect transistor is made of the nitride semiconductor, and includes a semiconductor layer including a barrier layer 4 and a cap layer 5 formed on the barrier layer 4, a gate electrode 9 provided on the semiconductor layer to have its lower part buried in the semiconductor layer, and an insulating film 10 provided between a side face of the gate electrode 9 and the semiconductor layer, the gate electrode 9 having only its lower surface in contact with the semiconductor layer. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a structure of a heterojunction field effect transistor made of a semiconductor containing nitride and a method for manufacturing the same.

  In a conventional heterojunction field effect transistor (heterojunction FET) made of a semiconductor containing nitride, in a structure in which a gate electrode is formed directly on the semiconductor surface, a pulse voltage is applied to the gate electrode to operate. In this case, a phenomenon (current collapse) in which the drain current is greatly reduced occurs, and this greatly reduces the output and efficiency that can be predicted from the DC characteristics when actually operating at a high frequency. Since current collapse caused by trap level is formed on the semiconductor surface, in order to suppress this is effective to distance the gate electrode / semiconductor interface takes strongest electric field from the semiconductor surface, the gate electrode to it A recess gate structure in which a gate electrode is formed after etching only a region to be formed is desirable. Furthermore, the deeper the etching depth, the greater the effect because the gate electrode / semiconductor interface is further away from the semiconductor surface.

  However, in order to apply the recess gate structure, it is necessary to etch the etching depth of the semiconductor layer directly under the gate electrode with good controllability, and it is difficult to control only by the etching rate. As a countermeasure, for example, in the case of a HEMT using AlGaN / GaN heterostructure system, a GaN / AlGaN / GaN structure by an etching depth equal GaN cap layer on the outermost surface, the etching rate of GaN and AlGaN A technique is employed in which only the GaN cap layer is selectively etched using the difference. For example, a heterojunction FET made of a nitride semiconductor described in Non-Patent Document 1 corresponds to the above structure.

IEEE Electron Device Letters, vol.29, p303, 2008

  As described in Non-Patent Document 1, when applying the deep recess gate structure heterojunction FET formed of a nitride semiconductor in order to suppress the current collapse, the effect of piezoelectric polarization of the AlGaN barrier layer is not extend to the vicinity of the surface Electrons are induced by activating n-type impurities present in the nitride semiconductor layer in which the recess is formed. As a result, the gate leakage current increases, resulting in a decrease in breakdown voltage that leads to a decrease in output and efficiency, noise characteristics, reliability, and the like.

  The present invention has been made in order to prevent the deterioration of characteristics and reliability as described above, and provides a heterojunction FET having a recessed gate structure made of a nitride semiconductor and suppressing the gate leakage current, and a method of manufacturing the same. Objective.

  The heterojunction field effect transistor of the present invention is formed of a nitride semiconductor, and includes a semiconductor layer including a barrier layer and a cap layer formed on the barrier layer, and the semiconductor layer is provided on the semiconductor layer so that a lower portion is buried in the semiconductor layer. And an insulating film provided between the side surface of the gate electrode and the semiconductor layer, and only the lower surface of the gate electrode is in contact with the semiconductor layer.

  Another heterojunction field effect transistor according to the present invention is a semiconductor layer made of a nitride semiconductor, including a barrier layer, a semiconductor layer including a cap layer formed on the barrier layer, and a semiconductor layer buried under the semiconductor layer. And a gate electrode provided on the layer, wherein a length from the bottom of the cap layer to an upper portion of the contact surface between the side surface of the cap layer and the gate electrode is 28 nm or less.

  The method of manufacturing a heterojunction field effect transistor according to the present invention is a method of manufacturing a heterojunction field effect transistor made of a nitride semiconductor. (A) A cap layer is formed on a barrier layer, and these two layers are formed as a semiconductor layer. (B) forming a trench having a predetermined length by etching the semiconductor layer, and (c) forming a gate electrode in the trench, and forming an insulating film between the side surface of the gate electrode and the semiconductor layer. A process.

  Another method of manufacturing a heterojunction field effect transistor according to the present invention is a method of manufacturing a heterojunction field effect transistor made of a nitride semiconductor. (A) A cap layer is formed on a barrier layer, and A step of forming a layer as a semiconductor layer, (b) a step of etching the semiconductor layer to form a trench having a predetermined length, and (c) from the bottom of the cap layer to the top of the contact surface of the side surface of the cap layer and the gate electrode Forming a gate electrode in the trench so as to have a length of 28 nm or less.

  A heterojunction field effect transistor of the present invention includes a gate electrode provided on a semiconductor layer so that the lower part is buried in the semiconductor layer, and an insulating film provided between a side surface of the gate electrode and the semiconductor layer. The gate electrode is characterized in that only the lower surface is in contact with the semiconductor layer. By limiting the portion in contact with the semiconductor layer only to the bottom surface of the gate electrode, gate leakage current can be suppressed in the recessed gate structure.

  Another heterojunction field effect transistor according to the present invention is a semiconductor layer made of a nitride semiconductor, including a barrier layer, a semiconductor layer including a cap layer formed on the barrier layer, and a semiconductor layer buried under the semiconductor layer. And a gate electrode provided on the layer, wherein a length from the bottom of the cap layer to an upper portion of the contact surface between the side surface of the cap layer and the gate electrode is 28 nm or less. By limiting the portion in contact with the semiconductor layer to a part of the bottom surface and side surface of the gate electrode, gate leakage current can be suppressed in the recessed gate structure.

  The method for producing a heterojunction field effect transistor of the present invention is a method for producing a heterojunction field effect transistor made of a nitride semiconductor, and (b) a step of etching a semiconductor layer to form a trench having a predetermined length; c) forming a gate electrode in the trench and forming an insulating film between the side surface of the gate electrode and the semiconductor layer. The gate electrode is in contact only a lower surface thereof and the semiconductor layer, side by forming so as to be covered with an insulating film, even thicker recess gate structure is a cap layer, the current collapse while the gate leakage current was maintained the effect of suppressing Can be kept sufficiently low.

  Another method for manufacturing a heterojunction field effect transistor according to the present invention is a method for manufacturing a heterojunction field effect transistor made of a nitride semiconductor, and (b) a semiconductor layer is etched to form a trench having a predetermined length. And (c) forming a gate electrode in the trench so that the length from the bottom of the cap layer to the upper part of the contact surface of the side surface of the cap layer and the gate electrode is 28 nm or less. Only part of the lower and side surfaces of the gate electrode are in contact with the semiconductor layer, and by forming an insulating film between the other parts of the gate electrode, the current collapse can be suppressed even in a recessed gate structure with a thick cap layer. It is possible to keep the gate leakage current sufficiently low while maintaining the effect. Further, since the gate electrode is formed so that part of the side surface is in contact with the semiconductor layer, the adhesion is increased and the reliability is improved.

FIG. 3 is a cross-sectional view of the heterojunction FET according to the first embodiment. FIG. 3 is a cross-sectional view of the heterojunction FET according to the first embodiment. FIG. 3 is a cross-sectional view of the heterojunction FET according to the first embodiment. FIG. 3 is a cross-sectional view of the heterojunction FET according to the first embodiment. FIG. 3 is a cross-sectional view of the heterojunction FET according to the first embodiment. FIG. 3 is a cross-sectional view of the heterojunction FET according to the first embodiment. FIG. 3 is a cross-sectional view of the heterojunction FET according to the first embodiment. FIG. 3 is a cross-sectional view of the heterojunction FET according to the first embodiment. FIG. 3 is a cross-sectional view of the heterojunction FET according to the first embodiment. FIG. 3 is a cross-sectional view of the heterojunction FET according to the first embodiment. FIG. 6 is a diagram showing a manufacturing process of the heterojunction FET of the first embodiment. FIG. 6 is a diagram showing a manufacturing process of the heterojunction FET of the first embodiment. FIG. 6 is a diagram showing a manufacturing process of the heterojunction FET of the first embodiment. FIG. 6 is a diagram showing a manufacturing process of the heterojunction FET of the first embodiment. FIG. 6 is a diagram showing a manufacturing process of the heterojunction FET of the first embodiment. It is a figure which shows the relationship between a cap layer film thickness, a gate current, and a gate electrode end electric field. FIG. 6 is a cross-sectional view of a heterojunction FET according to a second embodiment. FIG. 6 is a cross-sectional view of a heterojunction FET according to a second embodiment. FIG. 6 is a cross-sectional view of a heterojunction FET according to a second embodiment. FIG. 6 is a cross-sectional view of a heterojunction FET according to a second embodiment. FIG. 6 is a cross-sectional view of a heterojunction FET according to a second embodiment. FIG. 10 is a diagram showing a manufacturing process of the heterojunction FET of the second embodiment. FIG. 10 is a diagram showing a manufacturing process of the heterojunction FET of the second embodiment. FIG. 10 is a diagram showing a manufacturing process of the heterojunction FET of the second embodiment.

(Embodiment 1)
<Configuration>
FIG. 1 is a cross-sectional view showing the structure of a heterojunction FET made of a nitride semiconductor according to the present embodiment. The heterojunction FET of the present embodiment includes a semi-insulating substrate 1 made of SiC, a buffer layer 2 formed on the substrate 1, a channel layer 3 made of GaN formed on the buffer layer 2, and a channel layer. A barrier layer 4 made of AlGaN formed on the gate electrode 3, a gate electrode 9 made of Ni / Au formed on the barrier layer 4, and a cap layer 5 having a narrower band gap than the barrier layer 4 made of GaN. ing.

  Further, the heterojunction FET of the present embodiment includes a source electrode 7 and a drain electrode 8 made of Ti / Al on both sides of the gate electrode 9, and further includes an element isolation region 6.

  The gate electrode 9 has a recessed gate structure formed so as to be buried in the trench of the cap layer 5. In FIG. 1, the lower surface of the gate electrode 9 is in contact with the barrier layer 4 as an example. The trench is formed longer than the gate length, and the insulating film 10 is provided not only on the semiconductor surface but also between the cap layer 5 and the gate electrode 9.

  That is, the heterojunction FET made of a nitride semiconductor according to the present embodiment includes a semiconductor layer including a barrier layer 4 and a cap layer 5 formed on the barrier layer 4, and a semiconductor layer embedded in a lower portion thereof. A gate electrode 9 provided on the layer; and an insulating film 10 provided between a side surface of the gate electrode 9 and the semiconductor layer, wherein only the lower surface of the gate electrode 9 is in contact with the semiconductor layer. To do. Thus, the gate electrode 9 is in contact only a lower surface thereof and the semiconductor layer, side by the structure covered with the insulating film 10, even recess gate structure in which the cap layer 5 is formed thick, the current collapse suppression The gate leakage current can be kept sufficiently low while maintaining the above effect.

<Modification>
The modification of the heterojunction FET as shown in FIGS. 2 to 10, the same or corresponding components as those in FIG. 1 are denoted by the same reference numerals.

  For example, as shown in FIG. 2, a spacer layer 100 made of a material (for example, AlN) having a larger band gap than the material forming these layers may be formed between the channel layer 3 and the barrier layer 4. As a result, the confinement effect of the two-dimensional electron gas 11 generated on the barrier layer 4 side of the channel layer 3 is increased, so that the carrier concentration is increased and the alloy scattering is also reduced, so that the mobility is improved and the current of the transistor is increased. And higher output.

When the band gaps of the channel layer 3, the spacer layer 100, the barrier layer 4, and the cap layer 5 are E ₃ , E ₁₀₀ , E ₄ , and E ₅ , respectively, these are E ₃ <E ₄ <E ₁₀₀ , E ₅ ≦ E If the relationship is ₄ , the heterojunction FET is operated, the concentration and mobility of the two-dimensional electron gas 11 by the spacer layer 100 are improved, and only the cap layer 5 in the region of the gate electrode 9 is selectively removed. I can do it. Therefore, as described above, the cap layer is not necessarily made of GaN, the spacer layer is not necessarily made of AlN, and the barrier layer is not made of AlGaN. From Al, Ga and N having different compositions of constituent elements, at least two elements including N are used. What is necessary is just to be comprised with the nitride semiconductor which consists.

For example, the compound semiconductors constituting the channel layer 3, the spacer layer 100, the barrier layer 4, and the cap layer 5 are Al _X3 Ga _{1 -X3} N, Al _X100 Ga _{1 -X100} N, Al _X4 Ga _{1 -X4} N, and Al _{X5, respectively.} Assuming Ga _{1 -X5} N, 0 ≦ X ₃ <1, 0 ≦ X ₁₀₀ <1, 0 ≦ X ₄ <1, 0 ≦ X ₅ <1, X ₃ <X ₄ <X ₁₀₀ , X ₅ ≦ X ₄ Satisfy this relationship. That is, it is only necessary that the above-described four-layer band gap is made of a nitride semiconductor that satisfies the relationship of E ₃ <E ₄ <E ₁₀₀ and E ₅ ≦ E ₄ .

  When the channel layer 3, the spacer layer 100, the barrier layer 4, and the cap layer 5 are made of a nitride semiconductor composed of at least two elements including N among Al, Ga, and N, a large polarization effect is generated in the barrier layer 4. Therefore, the high-concentration two-dimensional electron gas 11 can be generated on the barrier layer 4 side of the channel layer 3, which is advantageous for increasing the current and output of the transistor.

  Furthermore, it is not necessary to be composed of a compound composed of at least two elements including N among Al, Ga, and N. For example, a nitride semiconductor composed of at least two kinds including N among In, Al, Ga, and N It may be configured.

The heterojunction FET has a higher breakdown voltage as the dielectric breakdown field of the semiconductor material used for the channel layer 3 is higher. Since Al _X Ga _1-X N has a higher band gap and a higher breakdown electric field as the Al composition is higher, the Al composition is higher when the channel layer 3 is made of Al _X3 Ga _1-X3 N as described above. (X ₃ is close to 1) is preferred. In addition, since the gate leakage current flowing from the gate electrode 9 to the hetero interface through the barrier layer 4 is suppressed as the band gap of the semiconductor material used for the barrier layer 4 is larger, Al _X4 Ga _{1 -X4} used as the barrier layer _4. Similarly, N preferably has a higher Al composition (X ₃ <X ₄ ).

  The channel layer 3, the spacer layer 100, the barrier layer 4, and the cap layer 5 do not necessarily have a single-layer structure with the same composition. As long as the above-described band gap is satisfied, the In composition and the Al composition The Ga composition may be spatially changed, or a multilayer film composed of several different layers may be used. These layers may contain n-type and p-type impurities.

  The semi-insulating substrate 1 is made of SiC, but may be Si, sapphire, GaN, AlN, or the like. However, when GaN is used for the substrate 1, the channel layer 3, the spacer layer 100, the barrier layer 4 and the like thereon can be formed without forming the buffer layer 2. Therefore, it is not necessary to form the buffer layer 2 on the substrate 1.

  Further, as shown in FIG. 3, a doping region 110 doped with an n-type impurity at a high concentration may be formed in at least a part of the semiconductor layer below the source electrode 7 and the drain electrode 8. . With such a structure, not only the contact resistance between the source electrode 7 and drain electrode 8 and the semiconductor layer (cap layer 5) is reduced, but also two-dimensional electrons generated on the barrier layer 4 side of the channel layer 3. It can be said that the resistance between the gas 11 (see FIG. 1) and the source / drain electrode can be reduced, which is advantageous for increasing the efficiency of the transistor and increasing the output by increasing the current, and is a more preferable structure. As the n-type impurity, not only Si but also a material that forms an n-type impurity level in the nitride semiconductor, such as O, C, and N vacancies, is doped. Although the doping region 110 is formed from the semiconductor surface to the channel layer 3 in the drawing, it is not necessarily limited to this region, and the source electrode 7 and the drain electrode may be large or small. If it is formed in at least a part of the semiconductor layer on the lower side of 8, the above-described effects are exhibited.

  At least a part of the semiconductor layer below the source electrode 7 and the drain electrode 8 may be removed as shown in FIG. With such a structure, it is possible to reduce the two-dimensional electron gas 11 (see FIG. 1) generated on the barrier layer 4 side of the channel layer 3 and the resistance on the source / drain electrode side, thereby improving the efficiency of the transistor. It is advantageous for higher output by increasing current and current, and can be said to be a more preferable structure. In FIG. 4, the region from the semiconductor surface to the barrier layer 4 is removed for forming the source / drain electrodes. However, the region is not necessarily limited to this region, and the region may be large or small. If the inside of at least a part of the semiconductor layer under the source electrode 7 and the drain electrode 8 is removed, the above-described effect can be obtained.

  Moreover, it is not necessary the source electrode 7 and drain electrode 8 are always Ti / Al, if ohmic characteristics Rarere give Ti, Al, Nb, Hf, Zr, Sr, Ni, Ta, Au, Pt, V, Mo, It may be formed of a metal such as W or a multilayer film composed of these metals.

  The gate electrode 9, if the bottom is not in contact with the surface of the cap layer 5, since the case can be suppressed current collapse compared to that in contact, the lower surface of the gate electrode 9 is not in contact with the barrier layer 4 Also good. For example, a structure in which the lower surface of the gate electrode 9 is in contact with the inside of the cap layer 5 (FIG. 5) or a structure in which the lower surface of the gate electrode 9 is in contact with the inside of the barrier layer 4 (FIG. 6) may be used. However, in order to etch the etching depth of the semiconductor layer immediately below the gate electrode 9 with good controllability, it is preferable to use a difference in rate when etching layers having different structures. In this case, FIG. As shown in FIG. 4, a structure in which the bottom surface of the gate electrode 9 is in contact with the top surface of the barrier layer 4 is more preferable.

  The gate electrode 9 does not necessarily have a square cross section, and may be a gate electrode 91 having a T-type or Y-type structure as shown in FIG. With such a structure, the gate resistance can be reduced while maintaining the area where the gate electrode 91 is in contact with the semiconductor. Although FIG. 7 shows a structure in which the umbrella of the T-type gate electrode 91 is not in contact with the insulating film 10, the structure in which the umbrella of the gate electrode 91 is in contact with the insulating film 10 as shown in FIG. In operation, the electric field concentrated on the edge portion of the gate electrode 91 on the drain electrode 8 side can be relaxed, current collapse can be suppressed, and the breakdown voltage can be increased. Further, as shown in FIG. 9, by forming the insulating film 10 only under the umbrella of the gate electrode 91, the capacitance generated between the source electrode 7 and the gate electrode 91 or between the gate electrode 91 and the drain electrode 8 can be reduced. The gain and efficiency at the time of high frequency operation can be improved.

  In addition, the insulating film 10 shown in FIGS. 1 to 9 includes an oxide, nitride, oxynitride, or the like of at least one atom among Al, Ga, Si, Hf, Ti, Zr, Ta, V, and the like. Alternatively, it may be formed of a multilayer film composed of these.

Further, the gate electrode 9 shown in FIGS. 1 to 6 and the gate electrode 91 shown in FIGS. 7 to 9 are not necessarily made of Ni / Au, but a metal such as Ti, Al, Pt, Au, Ni, and Pd. Further, it may be formed of silicide such as IrSi, PtSi, NiSi ₂ , nitride metal such as TiN, WN, TaN, or a multilayer film composed of these.

  Although various modifications have been described above, it is not necessary to employ all of the above-described structures individually. For example, as shown in FIG.

  Although only the minimum necessary elements that operate as a transistor are described above, the element is finally used as a device in a structure in which a protective film, a wiring, a via hole, and the like are formed.

<Manufacturing process>
A manufacturing process of the heterojunction FET of the present embodiment will be described with reference to FIG. In FIG. 11, the same or corresponding components as those in FIGS. 1 to 10 are denoted by the same reference numerals.

  First, a semi-insulating MOCVD method on the substrate 1, by applying an epitaxial growth method such as MBE method, a buffer layer 2, the lower channel layer 3 made of GaN, the barrier layer 4 made of AlGaN, the cap layer 5 made of GaN, respectively These are formed in order (FIG. 11A). Trimethylammonium comprising a nitride semiconductor material gas, trimethyl gallium, flow rate and pressure, such as trimethyl indium, ammonia silanes or as a raw material gas of n-type dopant, the temperature, by adjusting the time, the channel layer 3, the barrier layer 4. Cap layer 5 can be formed to a desired composition, film thickness, and doping concentration.

  In the case of providing the spacer layer 100 as shown in FIG. 2, after the channel layer 3 is grown on the buffer 2, the spacer layer made of a material having a larger band gap than the material forming the channel layer 3 and the barrier layer 4. 100 is formed, and then the barrier layer 4 is formed on the spacer layer 100.

  Next, a source electrode 7 and a drain electrode 8 made of a metal such as Ti, Al, Nb, Hf, Zr, Sr, Ni, Ta, Au, Pt, V, Mo, W, or a multilayer film composed of these metals. Are deposited by vapor deposition or sputtering, and formed by lift-off (FIG. 11B).

In the case where the doping region 110 is provided as in the heterojunction FET shown in FIG. 3, the source electrode 7 and the drain electrode 8 are formed using the resist pattern as a mask 15b before the source electrode 7 and the drain electrode 8 are formed. With respect to at least a part of the semiconductor layer under the region, ions that are n-type with respect to a nitride semiconductor such as silicon are implanted into a desired region by an ion implantation method or the like. The implantation dose is 1 × 10 ¹³ to 1 × 10 ¹⁷ cm ⁻² and the implantation energy is 10 to 1000 keV. Thereafter, a doped region 110 is formed by activating the implanted ions by performing heat treatment (FIG. 12).

In addition, when the lower surface of the source / drain electrode is inside the barrier layer 4 as in the heterojunction FET shown in FIG. 4, the resist pattern is formed before forming the source electrode 7 and the drain electrode 8 as shown in FIG. Is used as a mask 15c to remove at least a portion of the semiconductor layer below the region where the source electrode 7 and the drain electrode 8 are to be formed by a dry etching method using Cl ₂ or the like. Then, the source electrode 7 and the drain electrode 8 are formed.

  Then, an element isolation region 6 is formed in the channel layer 3, the barrier layer 4, and the cap layer 5 outside the region where the transistor is to be formed by using, for example, an ion implantation method or etching (FIG. 11C).

Next, using the resist pattern or the like as a mask 15a, the cap layer 5 in the region where the gate electrode 9 is to be formed is removed by a dry etching method using Cl ₂ or the like to form a recess region 12 (FIG. 11D). )). The length of the recess region 12 in the gate length direction is longer than the gate length of the gate electrode 9. In this step, by adjusting the depth of the recess region 12 by changing the etching time and the gas flow rate, heterojunction FETs having various recess depths shown in FIGS. 5 and 6 can be manufactured. When the Al composition ratios of the cap layer 5 and the barrier layer 4 are different, the cap layer can be selectively capped by using, for example, a fluorine-based gas such as oxygen or SF ₆ in addition to a chlorine-based gas such as Cl _{2 at} the time of etching. Only the layer 5 can be etched, and the controllability of the etching depth is improved.

After removing the mask 15a, a metal such as Ti, Al, Pt, Au, Ni, and Pd, a silicide such as IrSi, PtSi, and NiSi ₂ , a nitride metal such as TiN, WN, and TaN, or these are used. A gate electrode 9 made of a multilayer film is deposited by a vapor deposition method or a sputtering method, and formed by a lift-off method or the like (FIG. 11E). At this time, the gate length of the gate electrode 9 is shorter than the length of the recess region 12 in the gate length direction, and the side surface of the gate electrode 9 is formed so as not to contact the side surface of the recessed cap layer 5. Here, if an electrode is deposited by a vapor deposition method or the like using a resist pattern wider than the recess region 12 of the cap layer 5, a gate electrode 9 having a cross-sectional shape shown in FIG. 8 is formed.

  The insulating film 10 is made of an oxide, nitride, oxynitride, or the like of at least one atom among Al, Ga, Si, Hf, Ti, Zr, Ta, and V, or a multilayer film composed of these. Is formed by plasma CVD, cat-CVD, or sputtering.

  That is, in the method for manufacturing a heterojunction FET made of a nitride semiconductor according to the present embodiment, (a) a step of forming a cap layer 5 on the barrier layer 4 and using these two layers as semiconductor layers; Etching the semiconductor layer to form a trench having a predetermined length; and (c) forming a gate electrode 9 in the trench and forming an insulating film 10 between the side surface of the gate electrode 9 and the semiconductor layer. Prepare. As described above, the gate electrode 9 is formed so that only the lower surface thereof is in contact with the semiconductor layer and the side surface is covered with the insulating film 10, thereby suppressing the current collapse even when the cap layer 5 has a thick recessed gate structure. The gate leakage current can be kept sufficiently low while maintaining the above.

  With the above method, the heterojunction FET of this embodiment can be manufactured. The manufacturing process after the epicrystal fabrication was described in the order of forming the source / drain electrodes 7 and 8, forming the element isolation region 6, forming the recess region 12 of the cap layer 5, forming the gate electrode 9, and forming the insulating film 10. However, the source / drain electrodes 7 and 8 forming step, the element isolation region 6 forming step, and the gate electrode 9 forming step are not necessarily performed in this order, and the order of the steps may be changed. For example, the element isolation region 6 may be formed before the source / drain electrode is formed, or the element isolation region 6 may be formed after the gate electrode 9 is formed. Alternatively, the insulating film 10 may be formed after the recess region 12 is formed, and the gate electrode 9 may be formed after the insulating film 10 in the gate forming region is removed.

  That is, after the recess region 12 shown in FIG. 11D is etched, at least one of Al, Ga, Si, Hf, Ti, Zr, Ta, and V is used by using, for example, a vapor deposition method or a plasma CVD method. An insulating film 10 made of oxide, nitride, oxynitride or the like of more than kinds of atoms is deposited (FIG. 14). Thereafter, the insulating film 10 in the region for forming the gate electrode 9 is removed by dry etching or wet etching through a resist mask or an oxide film mask, and a resist pattern having an opening wider than the bottom of the gate electrode 9 to be formed is formed. Utilizing this, the gate electrode 9 is formed by depositing an electrode metal by vapor deposition. Thereafter, the insulating film 10 may be covered on the semiconductor surface. Thereby, the heterojunction FET having the structure shown in FIGS. 7 and 8 can be manufactured.

  In the step of etching the insulating film 10 in the region where the gate electrode is to be formed, the opening of the resist pattern is narrower than the recess region 12 of the cap layer 5, so that it is necessary to form a fine pattern with high positional accuracy. When the insulating film 10 is not thick, the cross section of the recess region 12 where the insulating film 10 is deposited after the recess etching shown in FIG. 11D has a shape reflecting the recess step as shown in FIG. Thereafter, if the insulating film 10 is etched back, the recess region has a cross section as shown in FIG. 15B, and the opening 16 of the insulating film 10 narrower than the recess region 12 is formed on the barrier layer 4. If a resist pattern having an opening wider than the opening 16 of the insulating film 10 is used as a mask 15d (FIG. 15C), an electrode metal is deposited by vapor deposition, and the mask 15d is removed, the gate structure shown in FIG. Is formed (FIG. 15D). Thereafter, the semiconductor surface may be covered with an insulating film for protection.

  In addition, after forming the gate structure of the heterojunction FET shown in FIG. 8, the insulating film 10 is left only around the gate electrode by adjusting the processing conditions (time and concentration) of wet etching using hydrofluoric acid or the like. A heterojunction FET having the structure shown in FIG. 9 can be manufactured.

  Note that it is not necessary to individually adopt all the processes described above, and a process combining them may be used.

  Although the minimum necessary elements that operate as a transistor have been described above, they are finally used as a device through a formation process of a protective film, a wiring, a via hole, and the like.

<Effect>
The heterojunction FET of this embodiment has the following effects as already described. That is, the heterojunction FET made of a nitride semiconductor according to the present embodiment includes a semiconductor layer including a barrier layer 4 and a cap layer 5 formed on the barrier layer 4, and a semiconductor layer embedded in a lower portion thereof. A gate electrode 9 provided on the layer; and an insulating film 10 provided between a side surface of the gate electrode 9 and the semiconductor layer, wherein only the lower surface of the gate electrode 9 is in contact with the semiconductor layer. To do. As described above, the gate electrode 9 has a structure in which only the lower surface thereof is in contact with the semiconductor layer and the side surface is covered with the insulating film 10. The gate leakage current can be kept sufficiently low while maintaining the above effect.

  Further, the lower surface of the gate electrode 9 is in contact with the upper surface of the barrier layer 4. Such a structure has an advantage in the manufacturing process that only the cap layer 5 can be etched with good controllability by using the difference in etching rate between the cap layer 5 and the barrier layer 4 therebelow.

  Alternatively, the lower surface of the gate electrode 9 may be located in the barrier layer 4. Even with such a structure, the gate leakage current can be reduced, and the current collapse can be suppressed as compared with the case where the lower surface of the gate electrode 9 is in contact with the surface of the cap layer 5.

  Alternatively, the lower surface of the gate electrode 9 may be located in the cap layer 5. Even with such a structure, the gate leakage current can be reduced, and the current collapse can be suppressed as compared with the case where the lower surface of the gate electrode 9 is in contact with the surface of the cap layer 5.

  In addition, according to the method of manufacturing the heterojunction FET of the present embodiment, the following effects can be obtained as already described. That is, in the method for manufacturing a heterojunction FET made of a nitride semiconductor according to the present embodiment, (a) a step of forming a cap layer 5 on the barrier layer 4 and using these two layers as semiconductor layers; Etching the semiconductor layer to form a trench having a predetermined length; and (c) forming a gate electrode 9 in the trench and forming an insulating film 10 between the side surface of the gate electrode 9 and the semiconductor layer. Prepare. Thus, the gate electrode 9 is in contact only a lower surface thereof and the semiconductor layer, by forming such side is covered with the insulating film 10, even thicker recess gate structure cap layer 5, the effect of current collapse suppression The gate leakage current can be kept sufficiently low while maintaining the above.

(Embodiment 2)
<Configuration>
In the heterojunction FET of the first embodiment, the gate electrode 9 is configured such that only the lower surface is in contact with the semiconductor layer and the side surface thereof is not in contact with the semiconductor layer by the insulating film. The electrode 9 is allowed to have a contact height of 28 nm or less with the cap layer 5 on its side surface.

<Contact height>
The grounds for setting the contact height on the side surfaces of the cap layer 5 and the gate electrode 9 to 28 nm or less will be described below.

  FIG. 16 shows the result of measuring the value of the current that flows between the gate electrode 9 and the drain electrode 8 when a voltage of −10 V is applied to the gate electrode using an actually manufactured device. The horizontal axis represents the film thickness of the cap layer 5, and the vertical axis represents the gate current and the gate electrode end electric field strength. Four types of devices having a thickness of the GaN cap layer 5 different from 0, 20, 50, and 100 nm were prepared, and the gate electrode 9 was formed on the barrier layer 4 after the cap layer 5 was recess-etched. At this time, the side wall of the gate electrode 9 and the side wall of the cap layer 5 are in contact with each other and have a contact height corresponding to the thickness of each cap layer. Therefore, it can be said that the horizontal axis of FIG. 16 represents the contact height between the cap layer 5 and the side surface of the gate electrode 9.

When the cap layer 5 is thinner than 20 nm, the gate leakage current is a sufficiently low value of 2.0 × 10 ⁻⁶ (A / mm) or less, but when the cap layer 5 is thicker than 50 nm, the gate leakage current is 2 The magnitude is increased to about 1.0 × 10 ⁻⁴ (A / mm), and there is a concern about breakdown voltage and reliability deterioration. As a factor that causes such a large gate leakage current, there is a carrier due to n-type impurities mixed mainly in the surface side in the GaN cap layer 5 during the process of epi growth or HEMT fabrication process. The n-type impurity in the cap layer 5 mixed on the interface side with the barrier layer 4 is depleted by the polarization effect from the barrier layer 4 and does not act as a carrier, so that it does not form a current leak path. On the other hand, since the polarization effect does not reach on the surface side of the cap layer 5 far away from the barrier layer 4, the n-type impurity existing there can behave as a carrier without being depleted, and becomes a current leakage path, resulting in leakage current. Will occur.

  FIG. 16 shows the calculated value of the gate leakage current together with the actually measured value. In this calculation, first, the concentration of carriers generated on the surface side of the cap layer 5 was derived from a band structure calculated using the Poisson equation for structures having different cap layer 5 thicknesses. Subsequently, the current flowing through the Schottky barrier from the gate electrode 9 into the cap layer 5 was calculated using them. Finally, it is assumed that the current value (actually measured value) measured by the HEMT without the cap layer 5 is a current value flowing through a portion other than the cap layer 5, and this is added to the tunnel current to obtain a gate current (calculated value) in FIG. Plotted. The calculated value agrees well with the actually measured value, and it can be seen that a large leakage current occurs when the thickness of the cap layer 5 is 28 nm or more. Accordingly, it can be said that the thickness of the cap layer needs to be 28 nm or less in order to suppress the gate leakage current to a sufficiently small value.

  Further, FIG. 16 also shows the result of calculating the electric field strength generated at the electrode end of the gate electrode 9 on the drain electrode side with a device simulator while changing the thickness of the cap layer 5. Thus, it can be seen that the thicker the cap layer 5 is, the lower the electric field strength generated at the electrode end of the gate electrode 9 on the drain electrode 8 side is. The current collapse becomes smaller as the electric field strength generated at the electrode end of the gate electrode 9 on the drain electrode 8 side is weaker. Therefore, it can be understood that the current collapse is suppressed by increasing the thickness of the cap layer 5.

  From the above, the leakage current and the current collapse are in a trade-off relationship with the thickness of the cap layer 5, and the thickness of the cap layer 5 is preferably as large as possible from the viewpoint of suppressing the current collapse. Therefore, as described above, when the horizontal axis of FIG. 16 is regarded as the contact height on the side surface of the cap layer 5 and the gate electrode 9, the contact height on the side surface of the cap layer 5 and the gate electrode 9 is reduced to 28 nm or less. The current can be reduced.

  That is, when the thick cap layer 5 is used to suppress current collapse, the contact height on the side surface between the gate layer 9 formed after removing the cap layer 5 by gate recess etching and the cap layer 5 is 28 nm or less. If so, the leakage current is reduced. Furthermore, if the insulating film 10 is formed between the side surfaces of the cap layer 5 and the gate electrode 9, the insulation between the two layers is further increased to further reduce the leakage current. Further, by covering the surface of the cap layer 5 with the insulating film 10, it is possible to reduce trapping of the semiconductor surface and further suppress current collapse.

<Example of structure>
FIG. 17 shows a structural example of the heterojunction FET of this embodiment. In FIG. 17, the gate electrode 9 has a trapezoidal shape that becomes narrower from the bottom to the top, and the contact height 13 on the side surface of the gate electrode 9 and the cap layer 5 is 28 nm or less.

  As described above, the heterojunction FET made of the nitride semiconductor of the present embodiment is configured such that the barrier layer 4 and the semiconductor layer including the cap layer 5 formed on the barrier layer 4 are buried in the semiconductor layer. And the length from the bottom of the cap layer 5 to the upper part of the contact surface of the side surface of the cap layer 5 and the gate electrode 9 is 28 nm or less. Thereby, in the recess gate structure having the thick cap layer 5, the effect of keeping the gate leakage current sufficiently low while suppressing the current collapse can be obtained. Further, the gate electrode 9 also comes into contact with the semiconductor layer on the side surface, thereby increasing adhesion and improving reliability.

  Alternatively, the gate electrode 9 may have a two-stage structure in which the upper gate length is shorter than the lower portion as shown in FIG. 18, and the insulating film 10 may be provided between the upper side surface of the gate electrode 9 and the semiconductor layer (cap layer). . The contact height 13 at which the lower part (first stage) of the gate electrode 9 is in contact with the cap layer 5 is 28 nm or less. Even with such a configuration, it is possible to achieve both low leakage current and reduced current collapse.

  Incidentally, FIG. 17, the gate electrode 9 in the heterojunction FET shown in FIG. 18, if the bottom is not in contact with the surface of the cap layer 5, since it is possible to suppress the current collapse as compared with the case in contact, The lower surface of the gate electrode 9 may not be in contact with the barrier layer 4. For example, a structure (FIG. 20) in which the lower surface of the gate electrode 9 is located in the cap layer 5 or a structure (FIG. 21) located in the barrier layer 4 may be used. However, when the lower surface of the gate electrode 9 is located in the cap layer 5 as shown in FIG. 20, the thickness of the cap layer 5 remaining below the gate electrode 9 is 28 nm or less, and the side surface of the gate electrode 9 and the cap When the contact height 13 of the layer 5 is within a height obtained by subtracting the thickness 14 of the cap layer 5 remaining under the gate electrode 9 from 28 nm, the gate leakage current can be reduced.

  In the case where the lower portion of the gate electrode 9 is in contact with the inside of the barrier layer 4 as shown in FIG. 21, the contact height 13 between the side surface of the gate electrode 9 and the cap layer 5 is 28 nm or less, and the bottom surface of the gate electrode. It is desirable that the side surface is in contact with the barrier layer 4. However, from the viewpoint of etching with good controllability of the etching depth of the semiconductor layer directly under the gate electrode, it is preferable to use a difference in rate when etching layers having different structures. Thus, it is preferable that the bottom surface of the gate electrode 9 is in contact with the vicinity of the interface between the barrier layer 4 and the cap layer 5.

<Modification>
In the heterojunction FET shown in FIGS. 17 and 18, the recess etching side surface of the cap layer 5 is substantially perpendicular to the semiconductor surface, but FIG. 19 shows an example in which the recess etching side surface has a forward mesa shape. By setting the contact height 13 on the side surface of the gate electrode 9 and the cap layer 5 to 28 nm or less, it is possible to achieve both low leakage current and reduced current collapse.

  When the recess region 12 (trench) provided in the semiconductor layer for forming the gate electrode 9 is formed in a forward mesa shape, compared to the case where the side surface of the recess region 12 is formed substantially perpendicular to the semiconductor surface, FIG. As shown in b), the shape of the gate end is formed at an obtuse angle, so that the electric field strength is reduced and the breakdown voltage can be improved. Further, when the angle of the recess sides and bottom and θ as shown in FIG. 19 (c), the opening size of the resist pattern in forming the gate electrode 9 can afford one side -28 / tanθ (nm) (FIG. 18), process margin is widened.

  Even in the gate structure as shown in FIG. 19, the lower surface of the gate electrode 9 can be inside the cap layer 5 or inside the barrier layer 4 as shown in FIGS. 20 and 21.

  In the modification of the present embodiment, the structure around the gate electrode 9 has been described. However, the components other than the gate electrode 9 constituting the heterojunction FET have various configurations as described in the modification of the first embodiment. Is applicable.

<Manufacturing process>
A manufacturing process of the heterojunction FET of the present embodiment will be described with reference to FIG. In FIG. 22, the same reference numerals are given to the same or corresponding components as those in the drawings shown so far.

  In the same manner as in the heterojunction FET manufacturing process of the first embodiment (FIG. 11), the buffer layer 2, the channel layer 3, the barrier layer 4, and the cap layer 5 are formed in this order on the semi-insulating substrate 1, and the cap layer is formed. A source electrode 7 and a drain electrode 8 are formed on 5, an element isolation region 6 is formed, and a recess region 12 is formed in the cap layer 5.

A resist mask 15 having the same opening as the recess region 12 of the cap layer 5 is formed by photolithography (FIG. 22A), and a metal such as Ti, Al, Pt, Au, Ni, Pd, IrSi, PtSi, A gate electrode 9 made of a silicide such as NiSi ₂ , a nitride metal such as TiN, WN, TaN, or a multilayer film composed of these is deposited by vapor deposition. Ideally, the particles that become the gate metal that have passed through the opening of the mask 15 are deposited and deposited on the recess region 12 of the cap layer 5, and the side surface of the gate electrode 9 is formed on the cap layer 5 as shown in FIG. In contact with the side of the recess. However, in reality, the particles that become the gate metal gradually adhere to and deposit on the opening side surface of the mask 15, so that the opening diameter of the mask 15 gradually decreases. Therefore, the cross-sectional shape of the gate electrode 9 is gradually narrowed as shown in FIG. 22C, and the gate electrode 9 shown in FIG. 17 whose side surface is not in contact with the recessed side surface of the cap layer 5 is formed.

  The lower part of the gate electrode 9 that is initially deposited is in contact with the cap layer 5, but the contact height is about 10 to 15 nm at the most, so that the condition of the heterojunction FET of this embodiment is 28 nm. Is not exceeded. However, the positional relationship between the vapor deposition source and the sample in the vapor deposition apparatus needs to be adjusted so that the deposited particles are perpendicularly incident on the substrate surface.

  Thereafter, when the insulating film 10 is formed on the semiconductor surface, the heterojunction FET shown in FIG. 17 is formed.

  As described above, the method for manufacturing a heterojunction FET made of a nitride semiconductor according to the present embodiment includes (a) a step of forming a cap layer 5 on the barrier layer 4 and using these two layers as semiconductor layers; b) etching the semiconductor layer to form a recess region 12 (trench) having a predetermined length; and (c) the length from the bottom of the cap layer 5 to the upper part of the contact surface between the side surfaces of the cap layer 5 and the gate electrode 9. Forming a gate electrode in the recess region 12 so as to be 28 nm or less. As a result, in the recessed gate structure having the thick cap layer 5, a heterojunction FET capable of keeping the gate leakage current sufficiently low while suppressing the current collapse can be formed. Further, since the gate electrode 9 is formed so as to be in contact with the semiconductor layer also on the side surface, the adhesion is increased and the reliability is improved.

  Next, a manufacturing process of the heterojunction FET shown in FIG. 18 will be described with reference to FIG. In the manufacturing process of the heterojunction FET shown in FIG. 17, a resist mask 15 having the same opening as that of the recess region 12 of the cap layer 5 is formed by photolithography (FIG. 23 (a)). a)). A first-stage gate electrode 9a is deposited by sputtering and formed by lift-off or the like. At this time, the deposition thickness is set to 28 nm or less. The reason why the sputtering method is used here is to improve the contact between the gate electrode 9a and the cap layer. Since the diffusion of the particles is superior to the vapor deposition method, the deposited particles adhere to the side surface of the mask 15e. A gate electrode 9a having a deposition thickness of 28 nm or less that is difficult and has good adhesion with the cap layer 5 is formed.

  Thereafter, after removing the mask 15e and forming the insulating film 10, the insulating film is processed using the insulating film mask 15f such as a resist mask or an oxide film so as to have the opening 16 shown in FIG. A second-stage gate electrode is formed using a sputtering method or the like, and the heterojunction FET shown in FIG. 18 is formed.

  Here, the method of forming the second-stage gate electrode by processing the insulating film 10 using the mask 15f is shown. However, as shown in FIG. The opening 16 of the insulating film 10 may be formed on the gate electrode 9a at the stage to form the gate electrode at the second stage. Further, after the first-stage gate electrode 9a is formed, a second-stage gate electrode may be formed by a vapor deposition method or a lift-off method using a resist mask, and then covered with the insulating film 10.

  Next, a manufacturing process of the heterojunction FET having the structure shown in FIG. 19 will be described with reference to FIG. The process until the recess region 12 is formed in the cap layer 5 is the same as the manufacturing process of the heterojunction FET shown in FIGS. 17 and 18. However, the cap layer 5 is removed by etching under the condition that the recess region 12 has a forward mesa shape ( FIG. 24 (a)). After removing the resist, a resist pattern 15g having the same opening size as that of the upper surface of the opened barrier layer 4 is formed, gate metal is deposited by the above-described vapor deposition method, and gate metal 9 is formed by lift-off (FIG. 24B). )). Since the recess side surface of the cap layer 5 has a forward mesa shape, the side surface of the gate electrode 9 can be formed without contacting the recess side surface of the cap layer 5. Thereafter, the semiconductor surface is covered with an insulating film 10 to form a heterojunction FET having the structure shown in FIG.

  FIG. 24C shows a state in which a resist pattern 15g having a predetermined opening is formed and the gate electrode 9 is deposited after the cap layer 5 is recess-etched into a forward mesa shape. In this figure, the side surface of the gate electrode 9 is not in contact with the recessed side surface of the cap layer 5, and the contact height 13 is 0 nm. FIG. 24D shows the case where the contact height 13 is 28 nm. When the angle 17 formed between the surface of the barrier layer 4 and the side wall surface etched by the forward mesa is θ, the opening size of the resist pattern 15g when the contact height 13 is 28 nm (FIG. 24D) is the contact size. Compared with the case where the height is 0 nm (FIG. 24 (c)), the opening is wider by −28 / tan θ nm (18 in the figure).

  As shown in FIG. 16, in order to obtain a low gate leakage current, the contact height 13 between the side surface of the gate electrode 9 and the recessed cap layer 5 needs to be 28 nm or less, but the recessed region of the cap layer 5 has a forward mesa shape. Thus, the opening dimension of the resist pattern 15g can have a margin of −28 / tan θ nm on one side, which contributes to the expansion of the manufacturing process margin.

  In the case where the lower surface of the gate electrode 9 is located inside the cap layer 5 as shown in FIG. 20, in the step of recess-etching the cap layer 5, the thickness 14 of the cap layer 5 left without being etched, It is necessary to adjust the thickness 14 and the contact height 13 of the remaining cap layer 5 so that the sum of the contact height 13 between the side surface of the gate electrode 9 and the cap layer 5 is 28 nm or less. If the thickness 14 of the remaining cap layer 5 is 28 nm, the contact height 13 needs to be 0 nm, and the gate electrode 9 has a structure as shown in FIG. Alternatively, a forward mesa-shaped recess etching is performed on the cap layer 5 so that only the lower surface of the gate electrode 9 is in contact with the recess region.

  When the recess etching is performed up to the barrier layer 4 as shown in FIG. 21, the side surfaces of the gate electrode 9 and the barrier layer 4 may be in close contact, and the contact height 13 between the gate electrode 9 and the side surface of the cap layer 5 is 28 nm or less. It is necessary to. Therefore, for example, as shown in FIG. 23, a first-stage gate electrode 9a of 28 nm or less is formed on the bottom surface of the recess region 12, and then a mask having an opening narrower than the recess region 12 or an etch back of the insulating film is formed. Thus, a second-stage gate electrode having a shape narrower than that of the first-stage gate electrode 9a may be formed.

  Note that it is not necessary to individually adopt all the processes described above, and a process combining them may be used. Further, although only the minimum necessary elements that operate as a transistor are described above, the element is finally used as a device in a structure in which a protective film, a wiring, a via hole, and the like are formed.

<Effect>
According to the heterojunction FET of the present embodiment, the following effects can be obtained as described above. That is, the heterojunction FET of this embodiment is a heterojunction FET made of a nitride semiconductor, and includes a barrier layer 4, a semiconductor layer including the cap layer 5 formed on the barrier layer 4, and a lower portion of the semiconductor layer. And a gate electrode 9 provided on the semiconductor layer so as to be buried, and the length from the bottom of the cap layer 5 to the upper part of the contact surface of the side surface of the cap layer 5 and the gate electrode 9 is 28 nm or less To do. Thereby, in the recess gate structure having the thick cap layer 5, the effect of keeping the gate leakage current sufficiently low while suppressing the current collapse can be obtained. Further, the gate electrode 9 also comes into contact with the semiconductor layer on the side surface, thereby increasing the adhesion and improving the reliability.

  The lower surface of the gate electrode 9 is in contact with the upper surface of the barrier layer 4. Such a structure has an advantage in the manufacturing process that only the cap layer 5 can be etched with good controllability by using the difference in etching rate between the cap layer 5 and the barrier layer 4 therebelow.

  Alternatively, the lower surface of the gate electrode 9 may be located in the barrier layer 4. Even with such a structure, the gate leakage current can be reduced, and the current collapse can be suppressed as compared with the case where the lower surface of the gate electrode 9 is in contact with the surface of the cap layer 5.

  Further, the lower surface of the gate electrode 9 may be located in the cap layer 5. Even with such a structure, current collapse can be suppressed as compared with the case where the lower surface of the gate electrode 9 is in contact with the surface of the cap layer 5. Further, the thickness of the cap layer 5 remaining below the gate electrode 9 is set to 28 nm or less, and the contact height 13 between the side surface of the gate electrode 9 and the cap layer 5 is changed from 28 nm to the thickness of the cap layer 5 remaining below the gate electrode 9. If the height is within the height minus 14, the gate leakage current can be reduced.

  In the heterojunction FET of the present embodiment, the gate electrode 9 has a two-stage structure in which the upper gate length is shorter than the lower portion, and the insulating film 10 provided between the upper side surface of the gate electrode 9 and the semiconductor layer is further provided. I will prepare. Thereby, in the recess gate structure having the thick cap layer 5, the effect of keeping the gate leakage current sufficiently low while suppressing the current collapse can be obtained. Further, when the lower portion of the gate electrode 9 is in contact with the semiconductor layer, adhesion is increased and reliability is improved.

  Also, the recess region 12 (trench) provided in the semiconductor layer for forming the gate electrode 9 may have a forward mesa shape. With such a structure, compared to the case where the side surface of the recess region 12 is formed substantially perpendicular to the semiconductor surface, the gate end shape is formed at an obtuse angle, so that the electric field strength is reduced and the breakdown voltage can be improved. Become. Further, when forming the gate electrode 9, a certain margin is formed in the opening size of the resist pattern, and the process margin is widened.

  Further, according to the method of manufacturing the heterojunction FET of the present embodiment, the following effects can be obtained as described above. That is, the method of manufacturing a heterojunction FET made of a nitride semiconductor according to the present embodiment is a method of manufacturing a heterojunction FET made of a nitride semiconductor, and (a) a cap layer 5 is formed on the barrier layer 4. A step of forming these two layers as a semiconductor layer, (b) a step of etching the semiconductor layer to form a recess region 12 (trench) having a predetermined length, and (c) a cap layer 5 and a gate from the bottom of the cap layer 5 Forming a gate electrode in the recess region 12 so that the length of the side surface of the electrode 9 up to the top of the contact surface is 28 nm or less. As a result, in the recessed gate structure having the thick cap layer 5, a heterojunction FET capable of keeping the gate leakage current sufficiently low while suppressing the current collapse can be formed. Further, since the gate electrode 9 is formed so as to be in contact with the semiconductor layer also on the side surface, the adhesion is increased and the reliability is improved.

  1 semi-insulating substrate, 2 buffer layer, 3 channel layer, 4 barrier layer, 5 cap layer, 6 element isolation region, 7 source electrode, 8 drain electrode, 9, 9a, 91 gate electrode, 10 insulating film, 12 recess region , 15 mask, 100 spacer layer, 110 doping region.

Claims (12)

A heterojunction field effect transistor made of a nitride semiconductor,
A semiconductor layer including a barrier layer and a cap layer formed on the barrier layer;
A gate electrode provided on the semiconductor layer so as to bury a lower part in the semiconductor layer;
An insulating film provided between a side surface of the gate electrode and the semiconductor layer;
The heterojunction field effect transistor according to claim 1, wherein only the lower surface of the gate electrode is in contact with the semiconductor layer.   The heterojunction field effect transistor according to claim 1, wherein a lower surface of the gate electrode is in contact with an upper surface of the barrier layer.   The heterojunction field effect transistor according to claim 1, wherein a lower surface of the gate electrode is located in the barrier layer.   The heterojunction field effect transistor according to claim 1, wherein a lower surface of the gate electrode is located in the cap layer. A heterojunction field effect transistor made of a nitride semiconductor,
A semiconductor layer including a barrier layer and a cap layer formed on the barrier layer;
A gate electrode provided on the semiconductor layer so as to bury a lower part in the semiconductor layer,
A heterojunction field effect transistor characterized in that the length from the bottom of the cap layer to the upper part of the contact surface of the side surface of the cap layer and the gate electrode is 28 nm or less.   6. The heterojunction field effect transistor according to claim 5, wherein the lower surface of the gate electrode is in contact with the upper surface of the barrier layer.   The heterojunction field effect transistor according to claim 5, wherein a lower surface of the gate electrode is located in the barrier layer.   The heterojunction field effect transistor according to claim 5, wherein a lower surface of the gate electrode is located in the cap layer. The gate electrode has a two-stage structure in which an upper gate length is shorter than a lower portion,
The heterojunction field effect transistor according to claim 5, further comprising an insulating film provided between the upper side surface of the gate electrode and the semiconductor layer.   9. The heterojunction field effect transistor according to claim 5, wherein a trench provided in the semiconductor layer to form the gate electrode has a forward mesa shape. A method of manufacturing a heterojunction field effect transistor made of a nitride semiconductor,
(A) forming a cap layer on the barrier layer and using these two layers as semiconductor layers;
(B) etching the semiconductor layer to form a predetermined length trench;
(C) forming a gate electrode in the trench and forming an insulating film between a side surface of the gate electrode and the semiconductor layer. A method of manufacturing a heterojunction field effect transistor made of a nitride semiconductor,
(A) forming a cap layer on the barrier layer and using these two layers as semiconductor layers;
(B) etching the semiconductor layer to form a predetermined length trench;
(C) forming a gate electrode in the trench so that the length from the bottom of the cap layer to the upper part of the contact surface between the cap layer and the side surface of the gate electrode is 28 nm or less. A method of manufacturing a heterojunction field effect transistor.

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