JP2011108739A - Thin film transistor substrate, method of manufacturing the same, and image display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a thin film transistor substrate of a higher ON/OFF ratio of a drain current of a thin film transistor substrate containing an InMZnO semiconductor film. <P>SOLUTION: In a thin film transistor substrate 1, a gate electrode 13, a gate insulating film 14, an InMZnO (M is at least one from among Ga, Al, and Fe) semiconductor film 15, a source electrode 16s, and a drain electrode 16d are formed on a substrate 10. The method of manufacturing it includes a step of forming the InMZnO semiconductor film 15 in a predetermined pattern, a step of providing a protective film 17 comprising any one of metal oxide, metal nitride, metal carbide, and metal oxynitride which contains at least one of metal element covering the InMZnO semiconductor film 15, a step of providing a metal film 18 comprising any one of aluminum, titanium, and molybdenum covering the protective film 17, and a step of thermal treatment after the metal film 18 is provided. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a thin film transistor substrate, a method for manufacturing the same, and an image display device. More specifically, in a thin film transistor substrate having an InMZnO-based semiconductor film, a thin film transistor substrate manufacturing method capable of increasing the ON / OFF ratio of drain current even by low-temperature heat treatment that does not cause thermal damage to the substrate, thin film transistor substrate, and image display device About.

  A thin film transistor (TFT) substrate is used as a drive element substrate for a liquid crystal display (LCD) or an organic EL display. Thin film transistors include structural forms such as an inverted staggered type (top gate) and a staggered type (bottom gate), and an amorphous silicon semiconductor film or a polysilicon semiconductor film is generally applied as a semiconductor film constituting the thin film transistor. Has been. However, although the amorphous silicon semiconductor film has stable characteristics but has low mobility, the polysilicon semiconductor film requires high temperature (for example, 600 ° C. or higher) heat treatment process although it has high mobility.

  Under such circumstances, research and development have been actively conducted on flexible display devices (organic EL display, electrophoretic display, etc.) using organic EL elements and electrophoretic elements. As a constituent member of a TFT substrate used for a flexible display device, a plastic substrate or a general-purpose glass substrate which is poor in heat resistance but excellent in flexibility has been studied. Since a thin film transistor which is a driving element is directly formed on a substrate constituting a display device, a process temperature in manufacturing the thin film transistor is applied to such a plastic substrate. However, the plastic substrate has poor heat resistance, and a high-temperature heat treatment process that damages the plastic substrate cannot be included in the thin film transistor manufacturing process.

  On the other hand, research on thin film transistors using an oxide thin film as a semiconductor film has been actively conducted in recent years. Patent Document 1 proposes an example in which a polycrystalline thin film of an oxide composed of In, Ga, and Zn (abbreviated as “IGZO”) is used as a semiconductor film of a TFT. In Non-Patent Document 1 and Patent Document 2, IGZO is proposed. An example in which the amorphous thin film is used as a semiconductor film of a TFT has been proposed. TFTs using these IGZO as a semiconductor film can be formed at room temperature and can be formed without damaging the plastic substrate.

  Further, in Patent Document 3, in a TFT using an IGZO thin film as a semiconductor film, in order to obtain stable TFT operation characteristics without causing unstable operation due to a change in atmosphere, the IGZO semiconductor film is covered with a protective film. To improve stability. In Patent Document 4, the IGZO semiconductor film is subjected to heat treatment at 200 ° C. or more and 600 ° C. or less, usually 400 ° C. in an oxidizing gas atmosphere, thereby improving stability during long-term driving.

K. Nomura et.al., Nature, vol.432, p.488-492 (2004)

JP 2004-103957 A JP 2005-88726 A JP 2007-73705 A JP 2007-311404 A

  In a manufacturing process of a TFT having an IGZO semiconductor film, film formation or etching of another film (insulating film or electrode) after forming the IGZO semiconductor film causes the semiconductor characteristics of the IGZO semiconductor film to deteriorate. For example, in the case where the protective film described in Patent Document 3 is provided, it is considered effective against subsequent environmental changes, but the damage applied to the IGZO semiconductor film before the formation of the protective film has been eliminated. For example, a large ON / OFF ratio cannot be obtained. Moreover, in patent document 4, although the heat processing of 200 degreeC or more and 600 degrees C or less (usually 400 degreeC) is applied and the stability of an IGZO semiconductor film is improved, when a plastic substrate with poor heat resistance is used as a board | substrate. The thermal damage to the substrate is large, and such means cannot be applied. For example, a polyethylene naphthalate substrate preferably used as a flexible substrate has a glass transition temperature of 150 ° C. or lower, and heat treatment at a temperature generally exceeding 200 ° C. should be avoided.

  The present invention has been made in view of the above situation, and an object thereof is to provide a method of manufacturing a thin film transistor substrate capable of increasing the ON / OFF ratio of the drain current of the thin film transistor substrate having an InMZnO-based semiconductor film. There is to do.

  Another object of the present invention is to provide a thin film transistor having a large drain current ON / OFF ratio even in a low-temperature heat treatment that does not cause thermal damage to the plastic substrate when a plastic substrate to which high-temperature heat treatment cannot be applied is used as a substrate for forming an InMZnO-based semiconductor film It is an object to provide a substrate and an image display device having the thin film transistor substrate.

  The present inventor formed a specific compound film on or above the formed InMZnO-based semiconductor film in the course of research on improving the quality of the thin-film transistor substrate having the InMZnO-based semiconductor film, and further formed a specific compound film on the compound film. It was discovered that the ON / OFF ratio of the drain current of the thin film transistor can be increased by performing a heat treatment after forming the metal film, and the present invention has been completed.

  That is, in the method of manufacturing a thin film transistor substrate according to the present invention, a gate electrode, a gate insulating film, an InMZnO (M is at least one of Ga, Al, and Fe) based semiconductor film, a source electrode, and a drain electrode are formed on the substrate. A method of manufacturing a thin film transistor substrate, comprising: forming an InMZnO-based semiconductor film having a predetermined pattern; and a metal oxide, metal nitride, and metal carbide containing at least one metal element covering the InMZnO-based semiconductor film And a step of providing a protective film made of any one of metal oxynitrides, a step of providing a metal film made of any of aluminum, titanium, and molybdenum covering the protective film, and a step of performing a heat treatment after providing the metal film It is characterized by having.

  The InMZnO-based semiconductor film has a defect or the like when it is patterned or another film (for example, a gate insulating film, a source / drain electrode, or a protective film) is formed on the InMZnO-based semiconductor film, and the semiconductor characteristics deteriorate (for example, become a conductor). . According to this invention, a protective film (a film made of at least one metal element-containing metal oxide, metal nitride, metal carbide, or metal oxynitride) is provided to cover the InMZnO-based semiconductor film having a predetermined pattern. Further, by applying a heat treatment after providing a metal film (a film made of any of aluminum, titanium, and molybdenum), the ON / OFF ratio of the drain current of the thin film transistor can be increased. By laminating these specific types of films on an InMZnO-based semiconductor film and performing a heat treatment, atomic hydrogen generated at the interface between the protective film and the metal film during the heat treatment deteriorates the semiconductor characteristics in the InMZnO-based semiconductor film. This is thought to be because the defect to be terminated was terminated. The thin film transistor substrate thus obtained can be used as a stable and high-quality drive element substrate, and is particularly preferable as a TFT substrate for a large-area display device.

  The manufacturing method of the thin film transistor substrate according to the present invention can be specified as shown in the following (1) to (4) depending on the structure.

  (1) A method of manufacturing a thin film transistor substrate according to a bottom gate top contact structure includes a step of forming a gate electrode having a predetermined pattern on a substrate, a step of forming a gate insulating film covering the gate electrode, Forming a predetermined pattern of InMZnO-based semiconductor film, forming a predetermined pattern of source and drain electrodes on the InMZnO-based semiconductor film, and forming a protective film covering the source and drain electrodes. And a step of forming a metal film on the protective film, a step of performing a heat treatment after providing the metal film, and a step of removing the metal film.

  (2) A method of manufacturing a thin film transistor substrate according to a bottom gate bottom contact structure includes a step of forming a gate electrode having a predetermined pattern on a substrate, a step of forming a gate insulating film covering the gate electrode, Forming a predetermined pattern of source and drain electrodes, forming a predetermined pattern of InMZnO-based semiconductor film across the source and drain electrodes, and forming a protective film covering the InMZnO-based semiconductor film And a step of forming a metal film on the protective film, a step of performing a heat treatment after providing the metal film, and a step of removing the metal film.

  (3) A method of manufacturing a thin film transistor substrate according to a top gate top contact structure includes a step of forming an InMZnO-based semiconductor film having a predetermined pattern on a substrate, and forming a source electrode and a drain electrode having a predetermined pattern on the InMZnO-based semiconductor film A step of forming a gate insulating film that is also a protective film covering the source electrode and the drain electrode, a step of forming a metal film on the gate insulating film, and a step of performing a heat treatment after providing the metal film, And etching the metal film to form a gate electrode having a predetermined pattern.

  (4) A method of manufacturing a thin film transistor substrate according to a top gate bottom contact structure includes a step of forming a source electrode and a drain electrode having a predetermined pattern on a substrate, and an InMZnO-based semiconductor film having a predetermined pattern across the source electrode and the drain electrode. A step of forming, a step of forming a gate insulating film which is also a protective film covering the InMZnO-based semiconductor film, a step of forming a metal film on the gate insulating film, and a step of performing a heat treatment after providing the metal film And etching the metal film to form a gate electrode having a predetermined pattern.

  According to the inventions of (1) to (4), the thin film transistor substrate having each structure is provided with a specific type of protective film (or a gate insulating film that is also a protective film) covering the InMZnO-based semiconductor film of a predetermined pattern, and further specified. By performing heat treatment after providing the seed metal film, the ON / OFF ratio of the drain current of the thin film transistor can be increased.

  In the method for manufacturing a thin film transistor substrate according to the present invention, the heat treatment is preferably performed in a nitrogen gas atmosphere, an oxidizing gas atmosphere, or a water vapor atmosphere.

  According to the present invention, the above effects can be realized by heat treatment in these atmospheres.

  In the method of manufacturing a thin film transistor substrate according to the present invention, the heat treatment is a heat treatment at a temperature of 200 ° C. or less that does not cause thermal damage to the substrate.

  According to this invention, ON / OFF of the drain current can be increased even at a low temperature heat treatment of 200 ° C. or lower.

  In the method of manufacturing a thin film transistor substrate according to the present invention, the substrate is a plastic substrate.

  According to the present invention, when a plastic substrate which is a non-heat-resistant substrate is used, the drain current can be turned ON / OFF even by low-temperature heat treatment that does not adversely affect the plastic substrate. In addition, since the thin film transistor substrate formed of a plastic substrate can realize flexibility and weight reduction, the obtained thin film transistor substrate can be preferably applied as a thin film transistor substrate of a large area flexible display.

A thin film transistor substrate according to the present invention for solving the above problems includes a plastic substrate, a gate electrode, a gate insulating film, an InMZnO (M is at least one of Ga, Al, and Fe) based semiconductor film, a source electrode, A thin film transistor substrate having at least a drain electrode is characterized in that an ON / OFF ratio of a drain current of the thin film transistor is at least 10 ⁵ or more.

According to this invention, it has not been possible to obtain in the prior art that has a non-heat-resistant plastic substrate as a substrate, an InMZnO-based semiconductor film as a semiconductor film, and the ON / OFF ratio of the thin film transistor is at least 10 ⁵ or more. A thin film transistor substrate can be provided.

  In the thin film transistor substrate according to the present invention, the thin film transistor has a bottom gate top contact structure, a bottom gate bottom contact structure, a top gate top contact structure, or a top gate bottom contact structure.

  According to the present invention, it is possible to provide a thin film transistor substrate having a large drain current ON / OFF ratio in the thin film transistor having each structure.

  An image display device according to the present invention for solving the above-described problems is characterized in that the thin film transistor substrate according to the present invention is used as an active matrix switching element substrate.

  According to the present invention, since the thin film transistor substrate having a large ON / OFF ratio is used, an image display device having a high-quality active matrix switching element substrate is obtained. Further, when a plastic substrate is applied as the substrate, it can be preferably applied as a switching element substrate for a flexible display having a large area.

  According to the method for manufacturing a thin film transistor substrate according to the present invention, the protective film covering the InMZnO-based semiconductor film having a predetermined pattern is provided, and the heat treatment is performed after the metal film is provided, so that the ON / OFF ratio of the drain current of the thin film transistor is increased. can do. The obtained thin film transistor substrate can be used as a stable and high-quality drive element substrate, and is particularly preferable as a TFT substrate of a large-area display device.

The thin film transistor substrate according to the present invention has a non-heat-resistant plastic substrate as a substrate, has an InMZnO-based semiconductor film as a semiconductor film, and can be obtained in the prior art in which the ON / OFF ratio of the thin film transistor is at least 10 ⁵ or more. The thin film transistor substrate that has not been used can be preferably used for display devices such as a flexible organic EL display using an organic EL element and a flexible electrophoretic display (electronic paper) using an electrophoretic element.

  Since the image display device according to the present invention is an image display device having a high-quality active matrix switching element substrate, it is preferable as a switching element substrate for a large area flexible display, particularly when a plastic substrate is applied as the substrate. Applicable.

It is explanatory drawing which shows the example of the thin-film transistor element substrate which concerns on the 1st form of this invention, and its manufacturing method. It is explanatory drawing which shows the example of the thin-film transistor element substrate which concerns on the 2nd form of this invention, and its manufacturing method. It is explanatory drawing which shows the example of the thin-film transistor element substrate which concerns on the 3rd form of this invention, and its manufacturing method. It is explanatory drawing which shows the example of the thin-film transistor element substrate which concerns on the 4th form of this invention, and its manufacturing method. 6 is a graph showing changes in drain current with respect to gate voltage in the thin film transistor substrates obtained in Examples and Comparative Examples.

  Hereinafter, a thin film transistor element substrate, a manufacturing method thereof, and an image display device according to the present invention will be described in detail. In addition, this invention is not limited to the form of drawing or the following embodiment.

[Basic configuration]
A method of manufacturing a thin film transistor substrate (hereinafter abbreviated as “TFT substrate”) 1 according to the present invention is abbreviated as a gate electrode 13, a gate insulating film 14, and an InMZnO-based semiconductor film (hereinafter “IMZO semiconductor film”) on a substrate 10. ) 15, a manufacturing method of the TFT substrate on which the source electrode 16s and the drain electrode 16d are formed. The feature is that a step of forming an IMZO semiconductor film 15 having a predetermined pattern and a metal oxide, metal nitride, metal carbide, and metal oxynitride containing at least one metal element covering the IMZO semiconductor film 15 are provided. A step of providing any one of the protective films 17, a step of providing a metal film 18 made of any of aluminum, titanium and molybdenum covering the protective film 17, and a step of performing a heat treatment after providing the metal film 18. Is to have.

  In the course of research on improving the quality of the TFT substrate 1 having the IMZO semiconductor film 15, the present inventor has applied the IMZO semiconductor film 15 to other patterns (for example, the gate insulating film 14, the source electrode 16 s. When the drain electrode 16d and the protective film 17) were formed, a defect or the like was generated, resulting in a problem that semiconductor characteristics deteriorated (for example, a conductor). In response to this problem, the present inventor has provided a protective film 17 (a metal oxide, metal nitride, metal carbide, and metal acid containing at least one metal element) covering the IMZO semiconductor film 15 on or above the IMZO semiconductor film 15. A drain current ON / OFF ratio can be increased by providing a heat treatment after providing a metal film 18 (a film made of any of aluminum, titanium and molybdenum). discovered.

The TFT substrate 1 (1A to 1D) obtained by such a manufacturing method includes a substrate 10 and a gate as shown in FIGS. 1 (B), 2 (B), 3 (B), and 4 (B). The electrode 13, the gate insulating film 14, the IMZO semiconductor film 15, the source electrode 16 s, and the drain electrode 16 d have at least a large value of ON / OFF ratio of the drain current of at least 10 ⁵ or more. It has become. In particular, when the substrate 10 is a non-heat-resistant plastic substrate that cannot be heat-treated at a high temperature, the ON / OFF ratio of the drain current is at least 10 ⁵ or more, and a high-quality TFT substrate 1 that cannot be obtained conventionally is provided. it can. Such a TFT substrate 1 can be preferably used for display devices such as a flexible organic EL display using an organic EL element and a flexible electrophoretic display (electronic paper) using an electrophoretic element.

  The structure form of the TFT substrate 1 is not particularly limited, and may be the bottom gate bottom contact structure of the form (first form) shown in FIG. 1B, or the form (second form) shown in FIG. ) Bottom gate top contact structure, or a top gate top contact structure of the form shown in FIG. 3B (third form), or shown in FIG. Top gate / bottom contact structure, and any structure can be used as a stable and high-quality driving element substrate, and particularly a TFT substrate for a large-area display device. Can be preferably applied.

  Next, the manufacturing method of the TFT substrate 1 according to the present invention will be described in detail in the following first to fourth embodiments according to the structure. Note that “on” means that it is provided on itself, and “cover” means that it is provided on itself and is also provided around itself.

[First Embodiment]
As shown in FIG. 1, the manufacturing method of the TFT substrate 1A according to the bottom gate top contact structure includes a step of forming a gate electrode 3 having a predetermined pattern on the substrate 10 and a gate insulating film 14 covering the gate electrode 13. A step of forming an IMZO semiconductor film 15 having a predetermined pattern on the gate insulating film 14, a step of forming a source electrode 16s and a drain electrode 16d having a predetermined pattern on the IMZO semiconductor film 15, and a source electrode 16s and a drain electrode. A step of forming a protective film 17 covering 16d, a step of forming a metal film 18 on the protective film 17, a step of heat treatment after providing the metal film 18, and a step of removing the metal film 18. 1A shows the TFT substrate 1A ′ before the metal film 18 is removed, and FIG. 1B shows the TFT substrate 1A after the metal film 18 is removed. Further, FIG. 1 shows a first base film 11 provided as necessary on the substrate 10 and a second base film 12 formed as needed on the first base film 11. However, the process of forming the first base film 11 and the process of forming the second base film 12 are optional.

(Gate electrode formation process)
First, the gate electrode 3 having a predetermined pattern is formed on the substrate 10. The type and structure of the substrate 10 are not particularly limited, and a flexible material, a rigid material, or the like is selected according to the application. Specific examples of materials that can be used include glass, quartz, polyethylene, polypropylene, polyethylene terephthalate, polymethacrylate, polymethyl methacrylate, polymethyl acrylate, polyester, polycarbonate, polysulfone, polyarylate, polyethersulfone, and polyamide. And polyetherimide. Usually, a glass substrate with ITO or a plastic substrate with ITO, which is a transparent electrode, is preferably used.

  The thickness of the substrate 10 differs depending on whether or not the obtained TFT substrate is flexible and is not particularly limited, but a flexible plastic substrate having a thickness of 5 to 300 μm is preferably used. In the case of a glass substrate, a glass substrate having a thickness of about 50 μm to 3 mm is used. The shape of the substrate 10 is not particularly limited, and examples thereof include a panel shape, a chip shape, a card shape, and a disk shape. In addition, after forming the TFT substrate on the single-wafer or continuous substrate 10, it may be cut into individual panels, chips, cards, or disks.

  In the manufacturing method according to the present invention, as will be described later, since the heat treatment can be performed at a low temperature of about 200 ° C. or lower, a plastic substrate that is a non-heat-resistant substrate having poor heat resistance, or somewhat inferior in heat resistance. There is a remarkable effect in that an inexpensive alkali-free glass substrate can be used as the substrate 10.

  A first base film 11 and a second base film 12 are formed on the substrate 10 as necessary. The first base film 11 and the second base film 12 may be formed only in a necessary region according to the function or purpose, or may be formed on the entire surface. The first base film 11 and the second base film 12 are any materials selected from the group consisting of chromium, titanium, aluminum, silicon, chromium oxide, titanium oxide, aluminum oxide, silicon oxide, silicon nitride, and silicon oxynitride. Formed with. For example, when used as an adhesion film, a metal-based inorganic film made of chromium, titanium, aluminum, or silicon is preferably used. When used as a stress relaxation film or a buffer film (thermal buffer film), chromium oxide, A compound film made of titanium oxide, aluminum oxide, silicon oxide, silicon nitride, silicon oxynitride or the like is preferably used. When used as a barrier film, a compound film made of silicon oxide or silicon oxynitride is preferably used. These films may be provided as a single layer or two or more layers may be laminated depending on the function or purpose.

  As a preferred example, a metal-based inorganic film made of chromium, titanium, aluminum, silicon, or the like is formed using the first base film 11 as an adhesion film, and chromium oxide or titanium oxide is used using the second base film 12 as a buffer film. It is preferable to laminate a compound film made of aluminum oxide, silicon oxide, silicon nitride, silicon oxynitride, or the like.

  The thickness of the first base film 11 formed as an adhesion film varies slightly depending on the material constituting the film, but is preferably in the range of about 1 nm to 200 nm, preferably about 3 nm to 50 nm. It is more preferable to be within the range. On the other hand, the thickness when the second underlayer 12 is formed as a buffer film is slightly different depending on the material of the actually formed film, but the thickness is usually in the range of about 100 nm to 1000 nm. In view of film formation time, it is more preferably in the range of about 100 nm to 500 nm.

  The first base film 11 and the second base film 12 can be formed by various methods such as various vapor deposition methods, DC sputtering methods, RF magnetron sputtering methods, and plasma CVD methods. A preferred method according to the material to be constructed is adopted. Usually, a DC sputtering method, an RF magnetron sputtering method, or the like is preferably used.

The gate electrode 13 is formed in a predetermined pattern on the substrate 10 or when the first base film 11 or the second base film 12 is provided. Examples of the gate electrode material include transparent conductive materials such as ITO (indium tin oxide), indium oxide, IZO (indium zinc oxide), SnO ₂ and ZnO, Al, W, Ta, Mo, Cr, Ti, Cu, and Au. Metal materials such as AlMg, MoW, and MoNb can be preferably mentioned. Note that a transparent conductive polymer such as polyaniline, polyacetylene, a polyalkylthiophene derivative, or a polysilane derivative may be used as long as it has desired conductivity.

  The gate electrode 13 is formed by a film forming unit and a patterning unit corresponding to the type of gate electrode material and the heat resistance of the substrate 10. For example, when the gate electrode 13 is formed of a transparent conductive material or a metal material, a sputtering method or various CVD methods can be applied as a film forming unit, and photolithography can be applied as a patterning unit, but low temperature film formation is required. In this case, a sputtering method or a plasma CVD method capable of forming at a low temperature can be preferably applied as the film forming means. When the gate electrode 13 is formed of a conductive polymer, a vacuum deposition method, a pattern printing method, or the like can be applied as a film forming unit, and photolithography can be applied as a patterning unit. The thickness of the gate electrode 13 is usually about 0.05 to 0.1 μm.

(Gate insulation film formation process)
Next, a gate insulating film 14 that covers the gate electrode 13 is formed. Various materials can be used for the gate insulating film 14 as long as it has a high insulating property and a relatively high dielectric constant and is suitable as a gate insulating film of a TFT. For example, silicon oxides such as silicon oxide, silicon nitride, and silicon oxynitride, nitrides, oxynitrides, and the like can be preferably exemplified. In addition, at least one or more of yttrium oxide, aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, niobium oxide, scandium oxide, and barium strontium titanate can be given.

  The gate insulating film 14 is formed by film forming means and patterning means corresponding to the type of gate insulating film material and the heat resistance of the substrate 10. For example, when the gate insulating film 14 is formed of silicon oxide, nitride, oxynitride or the like, a DC sputtering method, an RF magnetron sputtering method, a plasma CVD method, or the like can be applied as a film forming means, and as a patterning means Photolithography can be applied. The thickness of the gate insulating film 14 is usually about 0.1 to 0.3 μm. Further, the gate insulating film 14 may be formed by coating using a known coating type gate insulating film forming material. In this case, the thickness is usually about 0.2 to 1.0 μm.

(IMZO semiconductor film formation process)
Next, an IMZO semiconductor film 15 having a predetermined pattern is formed on the gate insulating film 14. The oxide constituting the IMZO semiconductor film 15 is an amorphous oxide containing InMZnO (M is at least one of Ga, Al, and Fe) as a main constituent element.

In particular, an InGaZnO-based amorphous oxide in which M is Ga is preferable. In this case, the ratio of In: Ga: Zn is preferably 1: 1: m (m <6). When Mg is further included, it is preferable that the ratio of In: Ga: Zn _1-x Mg _x is 1: 1: m (m <6) and 0 <x ≦ 1. The composition ratio is measured by a fluorescent X-ray (XRF) apparatus. The InGaZnO-based amorphous oxide exhibits an amorphous phase in a wide composition range of In, Ga, and Zn. The composition range stably showing the amorphous phase in this ternary system is In _x Ga _y Zn _z O _{(3x / 2 + 3y / 2 + z)} and the ratio x / y is in the range of 0.4 to 1.4, and the ratio It can be expressed such that z / y is in the range of 0.2-12. In addition, crystalline is shown with a composition close to ZnO and a composition close to In ₂ O ₃ . Amorphous oxides include In _x Ga _1-x oxide (0 ≦ x ≦ 1), In _x Zn _1-x oxide (0.2 ≦ x ≦ 1), In _x Sn _1-x oxide ( Any amorphous oxide selected from 0.8 ≦ x ≦ 1) and In _x (Zn, Sn) _1-x oxide (0.15 ≦ x ≦ 1) may be used.

  In the present invention, the InGaZnO-based semiconductor film (IGZO semiconductor film) used in Examples described later can be preferably exemplified. In addition, the IGZO semiconductor film may be added with Al, Fe, Sn or the like as a constituent element, if necessary. Since the IGZO semiconductor film 15 transmits a visible light and becomes a transparent film or a semi-transparent film, if it is used as a semiconductor film of a TFT for driving a liquid crystal or an organic EL, the semiconductor film can be provided also in the opening region. And the optical aperture can be enlarged. As a result, it can be used for a semiconductor film constituting a driving TFT substrate such as a liquid crystal display device, an organic EL display device, and electronic paper. Since this IGZO semiconductor film can be formed at room temperature to a low temperature of about 150 ° C., it can be preferably applied to a plastic substrate or a glass substrate having poor heat resistance.

  Whether the IMZO semiconductor film 15 is amorphous or not is a clear indication of the presence of crystallinity when X-ray diffraction is performed on the IMZO semiconductor film to be measured at a low incident angle of about 0.5 °. It can be confirmed that a diffraction peak is not detected, that is, a so-called halo pattern is seen. Such a halo pattern is also observed in the IMZO semiconductor film in the microcrystalline state. Therefore, the IMZO semiconductor film 15 includes such an IMZO semiconductor film in the microcrystalline state.

  The IMZO semiconductor film 15 is formed by a film forming unit and a patterning unit corresponding to the type of semiconductor material and the heat resistance of the substrate 10. For example, a DC sputtering method, an RF magnetron sputtering method, a plasma CVD method, or the like can be applied as a film forming unit, and photolithography can be applied as a patterning unit. Note that as a sputtering target in the case of forming a film by sputtering, it is preferable to use a sputtering target adjusted so as to obtain a desired film formation composition under predetermined sputtering conditions. Usually, a sputtering target having the same composition as the target film-forming composition is preferably used. The thickness of the IMZO semiconductor film 15 is not generally specified because it is arbitrarily designed depending on the deposition conditions, but it is usually preferably in the range of 10 to 150 nm, and preferably in the range of 30 to 100 nm. More preferred.

  In the step of forming the IMZO semiconductor film 15 having a predetermined pattern, (i) the IMZO semiconductor film 15 is formed on the entire surface covering the gate insulating film 14, and then the IMZO semiconductor film 15 formed on the entire surface is formed using a photoresist. A method of patterning (exposure, development, etching) and processing into the pattern shown in FIG. 1, or (ii) forming an IMZO semiconductor film 15 on the entire surface covering the gate insulating film 14 and further covering the IMZO semiconductor film 15 Then, the passivation film is patterned into a predetermined pattern (exposure, development, etching) by a photoresist method, and the IMZO semiconductor film 15 is patterned (etched) using the patterned passivation film as a mask, Any of the methods for processing the pattern shown in FIG. 1 can be applied.

The passivation film used here can be formed by forming a passivation film material such as liquid silica (SiO ₂ hydrate) or polyimide resin by a coating method, and then patterning using a resist. Alternatively, a passivation film material having photosensitivity may be formed by a coating method, followed by exposure and development to form a passivation film having a predetermined pattern. The thickness of such a passivation film is usually about 0.1 to 3 μm.

(Source / drain electrode formation process)
Next, a source electrode 16 s and a drain electrode 16 d having a predetermined pattern are formed on the IMZO semiconductor film 15. The source electrode material and the drain electrode material are selected in consideration of ohmic contact with the IGZO semiconductor film 15, and for example, metal films such as Ti, Ag, Mo, MoW, ITO (indium tin oxide), indium oxide, IZO Preferred examples include transparent conductive films such as (indium zinc oxide), SnO ₂ , and ZnO. Further, a conductive polymer such as polyaniline, polyacetylene, polyalkylthiophene derivative, polysilane derivative, or the like may be used as long as it has desired conductivity.

  For the formation of the source electrode 16s and the drain electrode 16d, film forming means and patterning means corresponding to the type of electrode material and the heat resistance of the substrate 10 are applied. For example, when the source electrode 16s and the drain electrode 16d are formed using a metal film or a transparent conductive film, a DC sputtering method, an RF magnetron sputtering method, a plasma CVD method, or the like can be applied as a film forming unit, and photolithography can be used as a patterning unit. Applicable. The thickness of the source electrode 16s and the drain electrode 16d is usually about 0.1 to 0.3 μm.

  When a passivation film is formed on the IMZO semiconductor film 15 (not shown), a contact hole is formed in the passivation film other than the channel region of the IMZO semiconductor film 15 prior to the formation of the source electrode 16s and the drain electrode 16d. May be formed. Such a passivation film is provided to form the source electrode connection portion and the drain electrode connection portion in the contact hole portion while protecting the channel region of the IMZO semiconductor film 15.

  By the way, after providing a passivation film having a contact hole, an activation process is usually performed. By this activation treatment, the conductivity of the IMZO semiconductor film 15 exposed at the contact hole portion can be increased to form a source electrode connection portion and a drain electrode connection portion. When the source electrode 16s and the drain electrode 16d are formed in a pattern on the source electrode connection portion and the drain electrode connection portion with enhanced conductivity, the ohmic resistance of the source electrode 16s and the drain electrode 16d with respect to the source electrode connection portion and the drain electrode connection portion, respectively, is reduced. Can be reduced. Note that a typical plasma treatment as the activation treatment causes oxygen vacancies in the IMZO semiconductor film 15.

(Protective film formation process)
Next, the protective film 17 covering the source electrode 16s and the drain electrode 16d is formed. As shown in FIG. 1, the protective film 17 is a film that acts to protect the TFT constituting the TFT substrate 1. By providing the protective film 17, the operation of the TFT is not affected by the atmosphere (for example, moisture, vacuum, temperature), and an unstable operation due to a change in the atmosphere does not occur. can get. Therefore, the protective film 17 is provided so as to cover the whole after the basic structure of the TFT is formed.

Examples of the material for forming the protective film 17 include metal oxides, metal nitrides, metal carbides, and metal oxynitrides containing at least one metal element. As the metal, silicon, aluminum and the like are preferable. Specifically, examples of the metal oxide include SiO ₂ and Al ₂ O ₃ , and examples of the metal nitride include Si _x N _y and AlN. Examples of the metal carbide include SiC and TiC, and examples of the metal oxynitride include SiON and SiAlON. Among these, a protective film made of SiO ₂ is preferable.

  Examples of the method for forming the protective film 17 include sputtering, resistance heating vapor deposition, laser vapor deposition, electron beam vapor deposition, and chemical vapor deposition (CVD). The thickness of the protective film 17 is not generally specified because it is arbitrarily designed depending on the film formation conditions, but is usually preferably in the range of 10 nm to 200 nm, and preferably in the range of 50 nm to 150 nm. Is more preferable.

(Metal film forming process)
Next, a metal film 18 is formed on the protective film 17. FIG. 1A shows the TFT substrate 1A ′ after the metal film 18 is formed. As the metal film 18, a film made of a metal such as Al, Ti, or Mo can be preferably cited, and a film made of Al is particularly preferable. Examples of the method for forming the metal film 18 include sputtering, resistance heating vapor deposition, laser vapor deposition, electron beam vapor deposition, and chemical vapor deposition (CVD). The thickness of the metal film 18 is not designed because it is arbitrarily designed depending on the film formation conditions, but it is usually preferably in the range of 20 nm to 250 nm, and preferably in the range of 20 nm to 200 nm. More preferred.

(Heat treatment process)
Next, heat treatment is performed after the metal film 18 is provided. The heat treatment here is performed in a mode in which the protective film 17 and the metal layer 18 are stacked on the IMZO semiconductor film 15, but may be performed in a mode in which the passivation film is provided on the IMZO semiconductor film 15. The heat treatment acts to enhance the semiconductor characteristics of the IMZO semiconductor film 15. Specifically, the ON / OFF ratio of the drain current of the TFT can be increased to at least 10 ⁵ or more.

  By the way, the IMZO semiconductor film 15 is formed by plasma during sputtering or plasma CVD in the formation process of the source electrode 16s and the drain electrode 16d formed on the IMZO semiconductor film 15, and during sputtering or plasma CVD in the formation process of the protective film 17. Takes a lot of damage from the plasma at times. Specifically, the plasma causes defects in the oxide of the IMZO semiconductor film 15 to become a conductor (higher electrical conductivity), and the semiconductor characteristics deteriorate. In the present invention, a protective film 17 (a film made of a metal oxide, metal nitride, metal carbide, or metal oxynitride containing at least one metal element) and a metal layer 18 (aluminum) are formed on the IMZO semiconductor film 15. , The characteristics of the IMZO semiconductor film 15 that has been made conductive and has significantly deteriorated semiconductor characteristics can be remarkably improved as described above.

  The reason why such an effect occurs is probably that the above-mentioned specific type of film (protective film 17 and metal film 18) is laminated on the IMZO semiconductor film 15 and subjected to heat treatment, so that the protective film 17 and It is considered that atomic hydrogen generated at the interface with the metal film 18 terminates defects generated in the IMZO semiconductor film 15. Specifically, the metal (for example, Al) in the metal film 18 and the water or the hydroxyl group in the protective film 17 react at the interface to oxidize the metal (for example, Al), and the atomic hydrogen generated as a result is the IMZO semiconductor. It is presumed that it diffuses to the film 15 and terminates the defective portion in the IMZO semiconductor film 15, and as a result, the semiconductor characteristics of the IMZO semiconductor film 15 made conductive by plasma damage are restored.

  Conventionally, the heat treatment temperature for stabilizing the semiconductor characteristics has been as high as several hundred degrees Celsius (about 400 degrees Celsius). However, in the present invention, even if the heat treatment temperature is as low as 200 degrees Celsius or less, the above-described effects are produced. This is significant in that the semiconductor characteristics of the IMZO semiconductor film 15 can be improved. Since semiconductor characteristics can be enhanced by heat treatment at such a low temperature, the formation of the source electrode 16s and the drain electrode 16d and the protective film by a sputtering method or plasma CVD method that generates plasma, particularly a sputtering method that enables efficient film formation at a low temperature. The formation of the film 17 and the formation of the passivation film can be applied without any problem, increasing the degree of freedom in the manufacturing process and increasing the efficiency of the manufacturing. In addition, even when a plastic substrate, which is a non-heat resistant substrate, or an alkali-free glass with slightly poor heat resistance, is used as the substrate 10, there is an advantage that the yield is not lowered during the heat treatment. If it can be made of a plastic substrate, the flexibility and weight reduction of the TFT substrate 1 can be realized. Therefore, the TFT substrate 1 of a large area flexible display can be manufactured at a low cost, and a large area as a stable and high quality driving element substrate. It can be preferably applied as a TFT substrate of the display device.

  The heat treatment temperature for improving the semiconductor characteristics of the IMZO semiconductor film 15 can be in the range of 100 ° C. to 400 ° C., particularly in the range of 100 ° C. to 200 ° C. when a non-heat resistant substrate is used. be able to.

  The heat treatment is preferably performed in any one of a nitrogen gas atmosphere, an oxidizing gas atmosphere, and a water vapor atmosphere. For example, by performing heat treatment in an oxidizing gas atmosphere containing oxygen gas, the semiconductor characteristics of the IMZO semiconductor film 15 can be enhanced, and the improvement of the semiconductor characteristics is further promoted by oxidation of Al. effective. In addition, by performing heat treatment in a water vapor atmosphere, the semiconductor characteristics of the IMZO semiconductor film 15 can be improved, and hydrogen in the water vapor terminates the unbonded portions of the semiconductor film and the insulating film, thereby further improving the TFT characteristics. There is an effect of improving.

  In the heat treatment in an oxidizing gas atmosphere, it is preferable that the atmospheric gas pressure is in the range of 0.01 to 1 atm in terms of promoting the oxidation of the metal (for example, Al). Further, in the heat treatment in a water vapor atmosphere, the water vapor pressure is preferably in the range of 1 to 20 atm from the viewpoint of promoting the effect of improving the TFT characteristics described above, and is a high pressure water vapor atmosphere of 5 to 15 atm. Is particularly preferred. Heat treatment in a high-pressure steam atmosphere is preferable because it can improve the semiconductor characteristics of the IMZO semiconductor film 15 and improve the interface state and insulating characteristics of the gate insulating film 14.

(Metal film removal process)
Finally, the metal film 18 is removed by etching. FIG. 1B shows the TFT substrate 1A after the metal film 18 is removed.

  The TFT substrate 1A according to the bottom gate top contact structure was obtained by the manufacturing method as described above. That is, as shown in FIG. 1B, the structural form is as follows: a substrate 10, a first base film 11 provided on the substrate 10 as necessary, and a first base film 11 as needed. A second base film 12 provided, a gate electrode 13 having a predetermined pattern provided on the second base film 12 (or the substrate 10 or the first base film 11), a gate insulating film 14 covering the gate electrode 13, An IMZO semiconductor film 15 having a predetermined pattern provided on the gate insulating film 14 and immediately above the gate electrode 13, and a source electrode 16 s provided by opening a central portion (channel region) on the IMZO semiconductor film 15 apart from each other. And a drain electrode 16d and a protective film 17 covering the whole. The TFT substrate 1A having such a structure may include other films as long as it is within the scope of the present invention.

In the case of having the IMZO semiconductor film 15 as a semiconductor film in the structure form of the obtained TFT substrate 1A, conventionally, there was no means other than enhancing or stabilizing the semiconductor characteristics by high-temperature heat treatment. The semiconductor characteristics could be improved even by heat treatment at. Therefore, there has been no example in which the TFT substrate 1A having a non-heat-resistant plastic substrate as the substrate 10 exhibits good semiconductor characteristics, but has good semiconductor characteristics in which the ON / OFF ratio of the TFT is at least 10 ⁵ or more. An unprecedented bottom gate top contact structure TFT substrate 1A is provided for the first time.

[Second Embodiment]
As shown in FIG. 2, the manufacturing method of the TFT substrate 1B according to the bottom gate bottom contact structure includes a step of forming a gate electrode 13 having a predetermined pattern on the substrate 10 and a gate insulating film 14 covering the gate electrode 13. A step of forming a source electrode 16s and a drain electrode 16d with a predetermined pattern on the gate insulating film 14, a step of forming an IMZO semiconductor film 15 with a predetermined pattern across the source electrode 16s and the drain electrode 16d, and an IMZO semiconductor film 15, forming a metal film 18 on the protective film 17, performing a heat treatment after providing the metal film 18, and removing the metal film 18. In the second embodiment, description of the same steps as those in the first embodiment will be omitted, and different points will be mainly described. 2A shows the TFT substrate 1B ′ before the metal film 18 is removed, and FIG. 2B shows the TFT substrate 1B after the metal film 18 is removed.

  In the manufacturing method of the TFT substrate 1B according to the second embodiment, the gate electrode forming step of forming the gate electrode 13 having a predetermined pattern on the substrate 10 and the gate insulating film forming step of forming the gate insulating film 14 covering the gate electrode 13 are: The process of forming the first base film 11 and the second base film 12 on the substrate 10 is also the same as in the case of the first embodiment. The description of is omitted here.

  In the second embodiment, a source electrode 16 s and a drain electrode 16 d having a predetermined pattern are formed on the gate insulating film 14. The film forming means and patterning means for the source electrode 16s and the drain electrode 16d in this step are the same as in the case of the first embodiment, and a description thereof will be omitted.

  Next, an IMZO semiconductor film 15 having a predetermined pattern is formed across the source electrode 16s and the drain electrode 16d formed in a predetermined pattern. In this step, (i) the IMZO semiconductor film 15 is formed on the entire surface covering the source electrode 16s and the drain electrode 16d formed in a predetermined pattern, and then the IMZO semiconductor film 15 formed on the entire surface is patterned using a photoresist. (Exposure, development, etching) and processing into the pattern shown in FIG. 2, or (ii) forming the IMZO semiconductor film 15 over the entire surface covering the source electrode 16s and the drain electrode 16d formed in a predetermined pattern; A passivation film is formed on the entire surface covering the IMZO semiconductor film 15, and then the passivation film is patterned into a predetermined pattern (exposure, development, etching) by a photoresist method, and the IMZO semiconductor film is formed using the patterned passivation film as a mask. 15 is patterned (etched), and the pattern shown in FIG. Any of the processing methods can be applied. The passivation film is the same as in the first embodiment, and is omitted here.

  In FIG. 2, the IMZO semiconductor film 15 is patterned by the method (i) above in which the passivation film does not remain on the IMZO semiconductor film 15. However, the passivation film (ii) in which the passivation film remains on the IMZO semiconductor film 15 is illustrated. A method of patterning the IMZO semiconductor film 15 by a method is preferable.

  Next, after a protective film 17 is formed on the entire surface covering the IMZO semiconductor film 15 having a predetermined pattern, a metal film 18 is further formed on the entire surface covering the protective film 17. Then, heat treatment is performed after the metal film 18 is provided, and the metal film 18 is removed after the heat treatment. Since the inference about the effect of improving the semiconductor characteristics in the protective film forming step, the metal film forming step, the heat treatment step, the metal film removing step, and the heat treatment step is the same as that in the first embodiment, the description thereof is omitted. To do.

  The TFT substrate 1B according to the bottom gate bottom contact structure was obtained by the manufacturing method as described above. That is, as shown in FIG. 2B, the structural form is as follows. The substrate 10, the first base film 11 provided on the substrate 10 as necessary, and the first base film 11 as needed. A second base film 12 provided, a gate electrode 13 having a predetermined pattern provided on the second base film 12 (or the substrate 10 or the first base film 11), a gate insulating film 14 covering the gate electrode 13, A source electrode 16s and a drain electrode 16d having a predetermined pattern provided on the gate insulating film 14 other than directly above the central portion of the gate electrode 13, and a source electrode 16s and a drain electrode 16d on the gate insulating film 14 provided. And an IMZO semiconductor film 15 formed so as to straddle (cross) the source electrode 16s and the drain electrode 16d, and a protective film 17 covering the whole. The TFT substrate 1B having such a structure may include other films within the scope of the present invention.

Also in the structure form of the obtained TFT substrate 1B, as in the case of the first embodiment, there was no example in which the TFT substrate 1B having a non-heat resistant plastic substrate as the substrate 10 showed good semiconductor characteristics. , TFT substrate 1B which oN / OFF ratio of the TFT according to the bottom-gate bottom-contact structure unprecedented having at least 10 ⁵ or more favorable semiconductor properties are provided for the first time.

[Third Embodiment]
As shown in FIG. 3, the manufacturing method of the TFT substrate 1C according to the top gate top contact structure includes a step of forming an InMZnO-based semiconductor film 15 having a predetermined pattern on the substrate 10, and a step of forming a predetermined pattern on the InMZnO-based semiconductor film 15. The step of forming the source electrode 16s and the drain electrode 16d, the step of forming the gate insulating film 14 that is also the protective film 17 covering the source electrode 16s and the drain electrode 16d, and the metal film 18 (13 ′) on the gate insulating film 14 Forming a metal film 18 (13 ′) and then performing a heat treatment, and etching the metal film 18 (13 ′) to form a gate electrode 13 having a predetermined pattern. In the third embodiment, the description of the same steps as those in the first and second embodiments will be omitted, and different points will be mainly described. 3A shows the TFT substrate 1C ′ before etching the metal film 18 (13 ′), and FIG. 3B shows the gate electrode 13 formed by etching the metal film 18 (13 ′). This is the later TFT substrate 1C.

  In the manufacturing method of the TFT substrate 1C of the third embodiment, the technical matters of the substrate 10 and the first base film 11 and the second base film 12 provided as necessary are the same as in the case of the first embodiment. Therefore, explanation here is omitted.

  In the first embodiment described above, as shown in FIG. 1, the IMZO semiconductor film forming step, the source / drain electrode forming step, and the protective film forming step are performed in this order on the gate insulating film 14. On the other hand, in the third embodiment, as shown in FIG. 3, on the substrate 10 (or the first base film 11 or the second base film 12), the IMZO semiconductor film forming step, the source / drain electrode forming step, the protection The substantial process order of both is the same in that the gate insulating film forming process, which is also a film forming process, is performed in that order. Therefore, the IMZO semiconductor film forming step, the source / drain electrode forming step, and the protective film forming step (gate insulating film forming step) are the same as those in the first embodiment, and thus the description thereof is omitted.

  In the third embodiment, the insulating material used in the gate insulating film forming step must also have a function as the protective film 17. Therefore, silicon oxides such as silicon oxide, silicon nitride, and silicon oxynitride, nitrides, oxynitrides, and the like that satisfy the function and effect as the gate insulating film 14 and the function and effect as the protective film 17 are preferable. be able to. The gate insulating film 14 is formed by a film forming means and a patterning means corresponding to the type of the gate insulating film material and the heat resistance of the substrate 10 as described in the first embodiment. The thickness of the gate insulating film 14 is usually about 0.1 to 0.3 μm.

  In the third embodiment, the material used in the metal film forming process is the metal film 18 laminated on the protective film 17 in the heat treatment process, and the semiconductor characteristics of the IMZO semiconductor film 15 are improved by the heat treatment effect described above. Therefore, the material of the metal film 18 used here is a material that can also be used as the gate electrode 13 and a material that exhibits the function and effect of the metal film 18. As such a material, Al, Ti, Mo or the like can be preferably used, and a film made of Al is particularly preferable. Examples of the method for forming the metal film 18 include sputtering, resistance heating vapor deposition, laser vapor deposition, electron beam vapor deposition, and chemical vapor deposition (CVD). The thickness of the metal film 18 is not designed because it is arbitrarily designed depending on the film formation conditions, but it is usually preferably in the range of 20 nm to 250 nm, and preferably in the range of 20 nm to 200 nm. More preferred. The metal layer 18 is then etched to form a gate electrode 13 having a predetermined pattern.

  Also in the third embodiment, a passivation film may be formed on the IMZO semiconductor film 15 as in the case of the first embodiment.

  With the manufacturing method as described above, the TFT substrate 1C according to the top gate top contact structure was obtained. That is, as shown in FIG. 3B, the structural form is as follows. The substrate 10, the first base film 11 provided on the substrate 10 as necessary, and the first base film 11 as needed. The provided second base film 12, the IMZO semiconductor film 15 having a predetermined pattern provided on the second base film 12 (or the substrate 10 or the first base film 11), and the IMZO semiconductor film 15 on the IMZO semiconductor film 15. The gate electrode provided so as to cover the source electrode 16s and the drain electrode 16d of a predetermined pattern provided apart from the central portion (channel region) of the film 15 and the source electrode 16s, the drain electrode 16d and the IMZO semiconductor film 15 A film 14 and a gate electrode 13 provided on the gate insulating film 14 are included. The TFT substrate 1C having such a structure may include other films as long as it is within the scope of the present invention.

Also in the structure form of the obtained TFT substrate 1C, as in the first and second embodiments, there can be no example in which the TFT substrate 1C having a non-heat-resistant plastic substrate as the substrate 10 exhibits good semiconductor characteristics. and although, TFT substrate 1C which oN / OFF ratio of the TFT according to the top-gate top-contact structure unprecedented having at least 10 ⁵ or more favorable semiconductor properties are provided for the first time.

[Fourth Embodiment]
As shown in FIG. 4, the manufacturing method of the TFT substrate 1D according to the top gate bottom contact structure includes a step of forming a source electrode 16s and a drain electrode 16d having a predetermined pattern on the substrate 10, and a step of forming the source electrode 16s and the drain electrode 16d. A step of forming an InMZnO-based semiconductor film 15 having a predetermined pattern, a step of forming a gate insulating film 14 that is also a protective film 17 covering the InMZnO-based semiconductor film 15, and a metal film 18 (13 ′) on the gate insulating film 14 Forming a metal film 18 (13 ′) and then performing a heat treatment, and etching the metal film 18 (13 ′) to form a gate electrode 13 having a predetermined pattern. In the fourth embodiment, description of the same steps as those in the first to third embodiments will be omitted, and different points will be mainly described. 4A shows the TFT substrate 1D ′ before the metal film 18 (13 ′) is etched, and FIG. 4B shows the gate electrode 13 formed by etching the metal film 18 (13 ′). This is the later TFT substrate 1D.

  In the manufacturing method of the TFT substrate 1C of the fourth embodiment, the technical matters of the substrate 10 and the first base film 11 and the second base film 12 provided as necessary are the same as in the case of the first embodiment. Therefore, explanation here is omitted.

  In the second embodiment already described, as shown in FIG. 2, the source / drain electrode forming step, the IMZO semiconductor film forming step, and the protective film forming step are performed in this order on the gate insulating film 14. On the other hand, in the fourth embodiment, as shown in FIG. 4, on the substrate 10 (or the first base film 11 or the second base film 12), the source electrode / drain electrode formation step, the IMZO semiconductor film formation step, the protection The substantial process order of both is the same in that the gate insulating film forming process, which is also a film forming process, is performed in that order. Accordingly, the source / drain electrode forming step, the IMZO semiconductor film forming step, and the protective film forming step (gate insulating film forming step) are the same as those in the second embodiment, and the description thereof is omitted.

  In the fourth embodiment, the insulating material used in the gate insulating film forming step must also have a function as the protective film 17 as in the case of the third embodiment. Therefore, silicon oxides such as silicon oxide, silicon nitride, and silicon oxynitride, nitrides, oxynitrides, and the like that satisfy the function and effect as the gate insulating film 14 and the function and effect as the protective film 17 are preferable. be able to. Since the formation of the gate insulating film 14 is the same as that described in the third embodiment, the description thereof is omitted.

  In the fourth embodiment, the material used in the metal film forming step is the same as that described in the third embodiment, and a description thereof will be omitted. Also in the fourth embodiment, a passivation film may be formed on the IMZO semiconductor film 15 as in the case of the second embodiment.

  With the manufacturing method as described above, a TFT substrate 1D having a top gate / bottom contact structure was obtained. That is, as shown in FIG. 4B, the structural form is as follows. The substrate 10, the first base film 11 provided on the substrate 10 as necessary, and the first base film 11 as needed. A source of a predetermined pattern provided on the second base film 12 and the second base film 12 (or the substrate 10 or the first base film 11) provided with a predetermined region (a region serving as a channel region) being spaced apart. An InMZnO-based semiconductor film 15 having a predetermined pattern provided to fill the predetermined region between the electrode 16s and the drain electrode 16d, and between the source electrode 16s and the drain electrode 16d and to cross the source electrode 16s and the drain electrode 16d, and Source electrode 16s-IMZO semiconductor film 15-drain electrode 16d) and gate insulating film 14 provided on gate insulating film 14 and IMZO semiconductor film And a gate electrode 13 provided immediately above the 5. The TFT substrate 1D having such a structure may include other films as long as it is within the scope of the present invention.

Also in the structure form of the obtained TFT substrate 1D, as in the case of the first to third embodiments, there can be no example in which the TFT substrate 1D having a non-heat-resistant plastic substrate as the substrate 10 exhibits good semiconductor characteristics. and although, oN / OFF ratio of the TFT is a TFT substrate 1D according to the top-gate bottom-contact structure unprecedented having at least 10 ⁵ or more favorable semiconductor properties are provided for the first time.

[Image display device]
In the image display device according to the present invention, the above-described TFT substrate according to the present invention is used as an active matrix type switching element substrate for a liquid crystal display device, an organic EL light emitting display device, an electronic paper or the like. If an organic EL light emitting display device is described as an image display device according to the present invention, it has a large number of TFT substrates 1 according to the present invention arranged in a matrix, for example, a gate bus line of a gate electrode 13 and a source electrode 16s. The source bus lines extend vertically and horizontally, and an output element is connected to the drain electrode 16d of each TFT. This output element is an organic EL element, and is composed of an equivalent circuit composed of a resistor and a capacitor. The area | region for every output element comprises the pixel of an organic electroluminescent light emission display apparatus.

  Hereinafter, the present invention will be described in more detail with reference to Examples and Comparative Examples.

[Example 1]
(Production of TFT substrate)
As an example, a TFT substrate in which a TFT having a bottom gate top contact structure shown in FIG. First, polyethersulfone (PES) having a thickness of 100 μm is prepared as a substrate 10, and a chromium film (adhesion film) having a thickness of 5 nm is formed on the entire surface of the substrate 10 as a first base film 11 by a sputtering method. Further, a silicon oxide film (buffer film) having a thickness of 300 nm was formed as a second base film 12 on the entire surface of the first base film 11 by sputtering. Next, after depositing an aluminum film having a thickness of 200 nm as a gate electrode film on the entire surface of the second base film 12, a resist pattern is formed by photolithography and then wet-etched with a phosphoric acid solution to form the aluminum film into a predetermined pattern. The gate electrode 13 was formed by patterning. Next, silicon oxide having a thickness of 100 nm was formed as a gate insulating film 14 on the entire surface so as to cover the gate electrode 13. This gate insulating film 14 is applied to an 8-inch SiO ₂ target using an RF magnetron sputtering apparatus. Electric power: 1.0 kW (= 3 W / cm ² ), pressure: 1.0 Pa, gas: argon + O ₂ (50%) The film was formed under the following film forming conditions. Thereafter, contact holes were formed by dry etching.

Next, an InGaZnO-based IGZO semiconductor film 15 (InGaZnO ₄ ) with an In: Ga: Zn ratio of 1: 1: 1 was formed on the entire surface so as to cover the gate insulating film 14 to a thickness of 100 nm. The IGZO semiconductor film 15 is 8 inches of InGaZnO (In: Ga: Zn = 1: 1: 1) under the conditions of room temperature (25 ° C.) and Ar: O ₂ of 30:50 using an RF magnetron sputtering apparatus. It was formed using a target. Next, after forming a resist pattern on the IGZO semiconductor film 15 by photolithography, wet etching was performed with an oxalic acid solution, and the IGZO semiconductor film 15 was patterned to form an IGZO semiconductor film 15 having a predetermined pattern.

  Next, after depositing a titanium film having a thickness of 200 nm on the entire surface of the IGZO semiconductor film 15 to form the source electrode 16s and the drain electrode 16d, a resist pattern is formed by photolithography, followed by wet etching with a phosphoric acid solution, and titanium. The film was patterned into a predetermined pattern to form a source electrode 16s and a drain electrode 16d. At this time, the source electrode 16s and the drain electrode 16d were formed on the IGZO semiconductor film 15 so as to have a pattern apart from other than just above the center of the IGZO semiconductor film 15 (see FIG. 1).

  Next, 100 nm thick silicon oxide is formed as a protective film 17 by RF magnetron sputtering so as to cover all of the source electrode 16 s, the drain electrode 16 d and the IGZO semiconductor film 15, and is further formed on the entire surface of the protective film 17. An aluminum film having a thickness of 100 nm was formed as a metal film 18 by a sputtering method. Thereafter, heat treatment at 190 ° C. for 60 minutes was performed in an air atmosphere. After the metal film 18 was removed by etching with phosphoric acid, a contact hole was formed by dry etching. Thus, a TFT substrate 1A according to Example 1 was produced.

[Example 2]
A TFT substrate of Example 2 was produced in the same manner as in Example 1 except that the heat treatment conditions were 210 ° C. and 60 minutes in an oxygen gas atmosphere.

[Comparative Example 1]
A TFT substrate of Comparative Example 1 was produced in the same manner as in Example 1, except that heat treatment was performed at 210 ° C. for 60 minutes in a mode in which the metal film 18 was not provided.

[Comparative Example 2]
A TFT substrate of Comparative Example 2 was produced in the same manner as in Example 1, except that heat treatment was performed at 300 ° C. for 60 minutes in a mode in which the metal film 18 was not provided.

[Characteristic evaluation]
With respect to the obtained TFT substrate, the ON / OFF characteristics of the drain current were evaluated. The measurement was performed by using a semiconductor parameter analyzer (Agilent Technology Co., Ltd., Model 4156C) to evaluate the TFT transfer characteristics and graph the drain current ON / OFF characteristics. As for the change of the substrate, the appearance and bending of the substrate constituting the TFT substrate were observed.

  FIG. 5 is a graph showing changes in drain current with respect to gate voltage in the TFT substrates obtained in Example 1 and Comparative Example 1. In FIG. 5, symbol a is the ON / OFF characteristic of the drain current when a drain voltage of 10 V is applied to the TFT of Example 1, and symbol b is the drain current ON when a drain voltage of 1 V is applied to the TFT of Example 1. The symbol c is the ON / OFF characteristic of the drain current when the drain voltage of 10 V is applied to the TFT of Comparative Example 1.

As can be seen from the results of the examples in Table 1, in Example 1, the ON / OFF ratio of the TFT was able to be about 7 digits (10 ⁷ ). In addition, since the heat treatment temperature is as low as 190 ° C., TFT characteristics can be improved without causing bending or deformation of the substrate even when a PES film having a glass transition temperature or higher is used as the substrate. I was able to. This result is considered to be because defects in the IGZO semiconductor film 15 generated during the manufacturing process of the TFT were recovered by the heat treatment performed in each example.

On the other hand, in Comparative Example 1, the ON / OFF ratio of the TFT was as extremely low as about two digits (10 ² ). In Comparative Example 2, although the TFT ON / OFF ratio was about 7 digits (10 ⁷ ), the TFT substrate was deformed.

1, 1A, 1B, 1C, 1D TFT substrate 10 Plastic substrate 11 First base film 12 Second base film 13 Gate electrode 14 Gate insulating film 15 IMZO semiconductor film 16s Source electrode 16d Drain electrode 17 Protective film 18 Metal film

Claims (11)

A method of manufacturing a thin film transistor substrate in which a gate electrode, a gate insulating film, an InMZnO (M is at least one of Ga, Al, and Fe) based semiconductor film, a source electrode, and a drain electrode are formed on a substrate,
A step of forming the InMZnO-based semiconductor film having a predetermined pattern, and a protection made of any one of a metal oxide, a metal nitride, a metal carbide, and a metal oxynitride containing at least one metal element covering the InMZnO-based semiconductor film A thin film transistor substrate comprising: a step of providing a film; a step of providing a metal film made of any one of aluminum, titanium, and molybdenum that covers the protective film; and a step of performing a heat treatment after providing the metal film. Production method.   Forming a gate electrode having a predetermined pattern on the substrate; forming a gate insulating film covering the gate electrode; forming an InMZnO-based semiconductor film having a predetermined pattern on the gate insulating film; Forming a source electrode and a drain electrode having a predetermined pattern on a semiconductor film; forming a protective film covering the source electrode and the drain electrode; forming a metal film on the protective film; and the metal film 2. The method of manufacturing a thin film transistor substrate according to claim 1, further comprising: a step of performing a heat treatment after providing the substrate and a step of removing the metal film.   Forming a gate electrode of a predetermined pattern on the substrate; forming a gate insulating film covering the gate electrode; forming a source electrode and a drain electrode of a predetermined pattern on the gate insulating film; and the source A step of forming an InMZnO-based semiconductor film having a predetermined pattern across the electrode and the drain electrode, a step of forming a protective film covering the InMZnO-based semiconductor film, a step of forming a metal film on the protective film, and the metal film 2. The method of manufacturing a thin film transistor substrate according to claim 1, further comprising: a step of performing a heat treatment after providing the substrate and a step of removing the metal film.   Forming a predetermined pattern of InMZnO-based semiconductor film on the substrate; forming a predetermined pattern of source and drain electrodes on the InMZnO-based semiconductor film; and a gate that is also a protective film covering the source and drain electrodes A step of forming an insulating film; a step of forming a metal film on the gate insulating film; a step of heat-treating after providing the metal film; and a step of etching the metal film to form a gate electrode of a predetermined pattern The manufacturing method of the thin-film transistor substrate of Claim 1 which has these.   Forming a predetermined pattern of source and drain electrodes on the substrate; forming a predetermined pattern of InMZnO-based semiconductor film across the source and drain electrodes; and a gate that is also a protective film covering the InMZnO-based semiconductor film A step of forming an insulating film; a step of forming a metal film on the gate insulating film; a step of heat-treating after providing the metal film; and a step of etching the metal film to form a gate electrode of a predetermined pattern The manufacturing method of the thin-film transistor substrate of Claim 1 which has these.   The method for manufacturing a thin film transistor substrate according to claim 1, wherein the heat treatment is performed in a nitrogen gas atmosphere, an oxidizing gas atmosphere, or a water vapor atmosphere.   The method for manufacturing a thin film transistor substrate according to claim 1, wherein the heat treatment is a heat treatment at a temperature of 200 ° C. or less.   The method for manufacturing a thin film transistor substrate according to claim 1, wherein the substrate is a plastic substrate. A thin film transistor substrate having at least a plastic substrate, a gate electrode, a gate insulating film, an InMZnO (M is at least one of Ga, Al, and Fe) based semiconductor film, a source electrode, and a drain electrode. A thin film transistor substrate having an ON / OFF ratio of current of at least 10 ⁵ or more.   The thin film transistor substrate according to claim 9, wherein the thin film transistor has a bottom gate top contact structure, a bottom gate bottom contact structure, a top gate top contact structure, or a top gate bottom contact structure.   11. An image display device comprising the thin film transistor substrate according to claim 9 or 10 as an active matrix switching element substrate.

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