JP2011054804A - Method and system for management of semiconductor manufacturing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method and system for management of a semiconductor device, capable of automatically resolving a failure in a manufacturing apparatus without engineers. <P>SOLUTION: A failed device causing the failure in a semiconductor integrated circuit is predetermined from a plurality of manufacturing devices. Principal component of EES data of the failed device is analyzed, and a principal component space for distinguishing a normal state from a failed one is obtained. A linear state equation for defining the time development of an internal state of the failed device which is expressed in the principal component is determined so as to investigate controllability. If there is controllability, the internal state as a principal component vector is calculated after the EES data of the failed device is acquired, and then it is determined whether the internal state belongs to a region for indicating the normal state in the principal space. If the internal state is beyond the region for indicating the normal state, an input is controlled so that the internal state is returned to the normal state based on the linear state equation. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor manufacturing apparatus management method and system related to the manufacture of a semiconductor integrated circuit.

  In the manufacturing process of a semiconductor integrated circuit, in order to manage a semiconductor manufacturing apparatus, monitoring (monitoring) of an EES (Equipment Engineering System) parameter which is an apparatus parameter indicating an internal state of the semiconductor manufacturing apparatus is performed (for example, Patent Document 1). Since a change in the state of the semiconductor manufacturing apparatus appears as a change in EES data, an abnormality occurring in the semiconductor manufacturing apparatus can be detected by monitoring the EES data. In addition, a method called statistical process control (SPC) is generally known as a method for detecting an abnormality in time series data such as EES data. In SPC, abnormality detection is performed according to a predetermined rule. There are various rules. As an example of this rule, there is one that detects an abnormality when the EES data deviates from a range of, for example, μ ± 3σ. Here, μ is an average value of EES data, and σ is the standard deviation (σ). As another example, there is abnormality detection due to a constant increase or decrease tendency from μ of EES data.

  However, there are some problems in monitoring EES data of a semiconductor manufacturing apparatus by conventional SPC. One is that when there are a large number of monitoring items of manufacturing equipment based on EES data, or when abnormality detection criteria are loose, abnormal reports (alarms) by SPC frequently occur. For example, thousands of alarms a day may be generated from SPC monitoring of one manufacturing apparatus, making it difficult for engineers to deal with all of them. In addition, not all alarms issued from SPCs are related to troubles, and there was a situation where there was no actual trouble when the engineers dealt with the alarms. Furthermore, there is a problem that alarms that are truly related to troubles are buried in a large number of false alarms.

  Therefore, in order to apparently reduce the number of alarms, it may be possible to tighten the SPC monitoring standards. For example, in the case of a monitoring standard that has issued an alarm when it exceeds ± 3σ from the average value of EES data, the number of alarms decreases by changing this to ± 4σ. Alternatively, it may be possible to narrow down the number of items of EES data to be acquired from the beginning. However, such a countermeasure has a problem that an alarm relating to a true trouble is overlooked.

  In recent years, the automation of semiconductor manufacturing processes has progressed, and the number of engineers in clean rooms tends to decrease. On the other hand, troubles related to semiconductor manufacturing tend to increase due to miniaturization and high integration of semiconductor integrated circuits. Therefore, as described above, the number of alarm occurrences may exceed the engineer's response limit. In that case, there is a problem that the abnormality of the manufacturing apparatus is left and the yield is lowered.

JP 2008-177534 A JP 2005-502947 A JP-T-2004-509407

Yoshikazu Kashiwagi, Satoshi Soeda, Takayoshi Nakamizo, "Basics of Stochastic System Control", Japanese edition, 2000

  It is an object of the present invention to provide a semiconductor manufacturing apparatus management method and system capable of automatically solving troubles in a manufacturing apparatus without using an engineer.

  According to one aspect of the present invention, there is provided a semiconductor manufacturing apparatus management method for monitoring each manufacturing apparatus by acquiring EES data representing an internal state of a plurality of manufacturing apparatuses involved in manufacturing a semiconductor integrated circuit, Applying a principal component analysis to the EES data acquired for a predetermined period of time for the specified manufacturing apparatus, identifying a manufacturing apparatus that causes a defect in the semiconductor integrated circuit from the plurality of manufacturing apparatuses, Obtaining a principal component space that divides a distribution of normal states and a distribution of trouble states into regions separated from each other with respect to the internal state of the manufacturing apparatus; and determining the internal state of the identified manufacturing apparatus as a main component in the principal component space. Linear state equation expressed in component vectors and defining the time evolution of the internal state depending on the input to the specified manufacturing equipment and the internal state linearly Setting and determining an unknown matrix included in the linear state equation based on the internal state and the time series data of the input, and determining controllability of the determined linear state equation of the coefficient matrix And, when it is determined that there is controllability, after obtaining the EES data for the specified manufacturing apparatus, calculate the internal state as a principal component vector from the obtained EES data, Determining whether the internal state belongs to the region representing the normal state in the principal component space; and, if it is determined that the internal state deviates from the region representing the normal state, the coefficient Controlling the input based on a determined linear state equation of a matrix so that the internal state returns to the normal state. Management method of the manufacturing apparatus is provided.

  According to the present invention, there is an effect that it is possible to automatically solve the trouble of the manufacturing apparatus without using an engineer.

FIG. 1 is a diagram illustrating an example of a wafer map. FIG. 2 is a diagram illustrating an example of a wafer map group having an electrical test failure. FIG. 3 is a diagram illustrating a result of specifying a failure cause device in the electrical test A. FIG. 4 is a diagram showing a time-series change in the electrical test A outer periphery defect rate according to the processing date and time of the exposure apparatus No. 3 which is a defect cause apparatus. FIG. 5 is a scatter diagram showing the result of applying principal component analysis to the EES data group. FIG. 6 is a diagram in which the contribution for each EES data item is calculated. FIG. 7 is a scatter diagram showing the result of applying principal component analysis to all EES data acquired for the exposure apparatus 3. FIG. 8 is a diagram illustrating an input control method for returning the apparatus state to a normal state in a system having controllability. FIG. 9 is a block diagram showing a configuration of a semiconductor manufacturing apparatus management system according to the embodiment. FIG. 10 is a flowchart for identifying a trouble device. FIG. 11 is a flowchart of controllability determination in the trouble device management server 14. FIG. 12 is a flowchart of automatic recovery processing from a trouble state. FIG. 13 is a flowchart of a principal component space search process.

  A semiconductor manufacturing apparatus management method and system according to embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In addition, this invention is not limited by this embodiment.

  In the present embodiment, an electrical failure is taken up as an example of a trouble related to semiconductor manufacturing, and after specifying a cause process, a cause device (trouble device) and a related EES (Equipment Engineering System) parameter causing the trouble, A method and system for automatically controlling a semiconductor manufacturing apparatus so that the same trouble does not occur will be described.

  FIG. 1 is a diagram showing an example of a wafer map, in which the occurrence locations of defective chips 21 on the wafer 20 are shown in black. Here, the wafer map is obtained by measuring the electrical characteristics of the semiconductor chips formed on the wafer 20 after the clean room process is finished, and expressing the measurement results on the wafer 20. An electrical test corresponding to the result of FIG. 1 is referred to as an electrical test A.

  Specifically, a probe is brought into contact with the metal electrode of each semiconductor chip, a predetermined electrical signal is given, and the response of the semiconductor chip is measured. If a predetermined electrical response is obtained, it is determined that the semiconductor chip has been formed normally, and after dicing, it is sealed in resin and shipped as a product. If a predetermined electrical response cannot be obtained, it is discarded as a defective chip. The wafer map shows the distribution of defective chips 21 in the wafer surface and serves as a clue to identify the cause process and the cause device of the occurrence of the defect. In FIG. 1, defective portions for one lot are shown superimposed on one wafer 20, and one lot is composed of, for example, 25 wafers.

  As shown in FIG. 1, defective chips 21 tend to be frequently found on the outer periphery of the wafer. The defective chips 21 are distributed in a horizontal stripe shape. Further, it was found that the interval d between the stripes corresponds to the chip period (Shot period) carved in the reticle of the lithography process. Specifically, it has been found that the distance d corresponds to, for example, the size of 3 chips. From this, it can be seen that the cause process of the defective chip 21 is related to the lithography process. 1 is referred to as an electrical test A outer periphery shot property defect.

  It has been found that there are other wafer maps similar to FIG. FIG. 2 is a diagram illustrating an example of a wafer map group having an electrical test failure. In FIG. 2, for example, six wafer maps are shown. In each wafer map, defective chips 21 for one lot (for example, 25 wafers) are represented on one wafer 20.

  In the three wafer maps shown in the upper part of FIG. 2, the electrical test A outer periphery shot property failure occurred as in FIG. 1. Further, in the three wafer maps shown in the lower part of FIG. 2, the defective chip 21 exists in the same manner, but the distribution in the wafer surface is different from that in the case of the electrical test A outer periphery shot defect. Further, with regard to the three wafer maps shown in the lower part, it was found that the interval between the defective chips 21 does not correspond to the chip period (Shot period) engraved on the reticle. That is, it is understood that the cause of defects in the lower three wafer maps in FIG. 2 is different from the upper three cases. From this result, it is considered that there is a common failure cause in the electrical test A outer periphery shot property failure seen in the three wafer maps in the upper part of FIG.

  Next, a manufacturing apparatus in which three lots (hereinafter referred to as “electrical test A outer periphery shot property defective lot”) in which the electrical test A outer periphery shot property defect shown in the upper part of FIG. Search from all processes by statistical test. That is, the manufacturing apparatus that caused the failure was searched. As a statistical test, for example, a chi-square test was used. The specific details of the failure cause device (trouble device) based on the statistical test will be described later. FIG. 3 is a diagram illustrating a result of specifying the failure cause device in the electrical test A. According to the above statistical test, in the “process 10” which is the 10th process among all processes, for example, the manufacture of the third of the four manufacturing apparatuses (exposure apparatuses 1 to 4) used. It was found that all the production of the electrical test A outer peripheral shot defective lot was concentrated on the apparatus (exposure apparatus No. 3). From this result, it is estimated that the electrical test A outer periphery shot property failure is caused by the third manufacturing apparatus (exposure apparatus No. 3) in “Step 10”.

  The “process 10” specified in this way is a lithography process, and the manufacturing apparatus related to this process is an exposure apparatus as described above. Further, it has been found that the chip period (Shot period) engraved on the reticle used in the exposure apparatus No. 3 and the defective chip distribution period (for example, the interval d between the defective chips 21) coincide with each other. It was also confirmed that the constituent parts of the semiconductor integrated circuit formed in “Step 10” correspond to the test parts of the electrical test A. From this result, it can be concluded that the electrical test A outer periphery shot property failure is caused by the exposure apparatus No. 3 in “Step 10”.

  Next, the processing date and time of the exposure apparatus No. 3 in “Step 10” is taken along the horizontal axis, and the defective rate in the wafer outer peripheral area of the electrical test A (hereinafter referred to as “electrical test A outer peripheral defective rate”) is taken as the vertical axis. FIG. 4 shows a time series change of the electrical test A outer peripheral defect rate. In FIG. 4, it can be seen that the outer peripheral defects of the electrical test A frequently occur after the processing date = Day 30 or later. From this result, it is presumed that some abnormality occurred in the exposure apparatus No. 3 after the processing date = Day 30.

  As described above, it was found that the electrical test A outer periphery shot property failure was caused by the exposure apparatus No. 3 in “Step 10”, and the apparatus abnormality occurred after Day 30.

  In this embodiment, an EES parameter that is an apparatus parameter indicating the internal state of the semiconductor manufacturing apparatus is monitored. For the above exposure apparatus No. 3, for example, 300 items of data have been acquired as EES data. Examples of the acquired EES data include synchronization accuracy, focus followability, and exposure amount.

  These EES data groups were analyzed by PLS-DA (Partial Least Discriminant Analysis) using PLS-DA (Partial Least Discriminant Analysis) with the processing date = Day 30 as the normal period and the processing date = Day 30 and after as the abnormal period. Here, the PLS-DA performs principal component analysis of the EES data group and finds an EES parameter that characterizes a difference between response values (normal / abnormal (trouble) classification corresponding to processing date = Day 30 before and after in this embodiment). This is a known analysis method. In FIG. 4, each point is characterized by 300 EES data, but it is difficult to find the difference in the device state before and after Day 30 by comparing these 300 data with each other. Therefore, the principal component analysis is applied to the data of 13 lots in FIG. 4, and the difference in the apparatus state before and after the Day 30 is clarified based on the obtained principal components. For example, when the first and second principal components are used, the difference between the device states before and after Day 30 is efficiently and accurately found by using these two principal components in which statistical information is aggregated instead of 300 EES data. be able to. This analysis may be executed by, for example, U-Metrix multivariate analysis software “SIMCAP + 11”.

  FIG. 5 is a scatter diagram showing the result of applying principal component analysis to the EES data group. FIG. 5 shows the result of applying the principal component analysis to the 13 lots of EES data group shown in FIG. 4, for example, a scatter diagram by the first and second principal components. In this scatter diagram, the principal components relating to 7 lots processed before processing date = Day 30 (normal period) are distributed in the hatched area marked “normal” in the figure, and after processing date = Day 30 (abnormal) The main components related to the six lots processed in the period) are distributed in the shaded area marked “Electrical test A outer periphery shot poor” in FIG. From this, it can be seen that both distributions are clearly separated before Day 30 (normal period) and after (abnormal period). This indicates that the apparatus state of the exposure apparatus 3 monitored by the EES data is different between normal / abnormal periods. In addition, when normal / abnormal phase classification cannot be performed in the first and second principal component spaces, a higher-order principal component (for the m-th principal component) The analysis including that which is larger than m) is performed.

  FIG. 6 is a diagram in which the contribution for each EES data item is calculated. Here, the degree of contribution is the difference between the principal component distributions shown in FIG. 5, that is, the difference between the “normal” region and the “electrical test A outer periphery shot property failure” region. This indicates the degree of contribution and is an amount defined by principal component analysis. Moreover, FIG. 6 is the result obtained by PLS-DA by the above-mentioned multivariate analysis software. EES data in which the bar graph has a large value in the positive or negative direction characterizes the difference in the apparatus state. Note that, as described above, there are 300 EES data items, for example, but in the example shown in the figure, two items with particularly high contribution are shown. That is, FIG. 6 shows that the exposure amount measurement value and the synchronization accuracy are EES data characterizing the difference between normal / abnormal periods. Here, the exposure amount measurement value is a measurement value of the light intensity applied to the resist on the wafer surface from the light source through the reticle / optical lens. The synchronization accuracy is an indicator of the positional accuracy of the reticle and wafer during the exposure process. In the present embodiment, after the processing date and time = Day 30 and after, the exposure amount measurement value of the exposure apparatus No. 3 in “Step 10” decreases (irradiation light intensity decreases), and the synchronization accuracy value increases (position accuracy deteriorates). As a result, it was found that an electrical test A outer peripheral shot property failure occurred.

  Thus, since the EES data parameter (in this case, the exposure amount measurement value and the synchronization accuracy) related to the cause of the electrical failure can be specified, the exposure amount measurement value and the synchronization accuracy within the predetermined period can be specified. Each of the fluctuation ranges can be obtained, and based on each of the fluctuation ranges, a management width can be set as a reference for issuing an alarm in SPC monitoring. Then, by performing SPC (Statistical Process Control) monitoring based on the management width, it is possible to detect the occurrence of the electrical test A outer peripheral shot defect from the result of the exposure process without waiting for the end of the clean room process. it can. That is, instead of SPC monitoring EES data for all manufacturing apparatuses involved in semiconductor manufacturing, EES data that caused electrical failure is identified, and these EES data (for example, exposure measurement values and synchronization accuracy) are identified. Develop SPC rules for As a result, the occurrence of an electrical failure can be detected at the manufacturing stage, and a decrease in yield can be minimized.

  However, in recent years, troubles related to semiconductor manufacturing have been increasing due to miniaturization and high integration of semiconductor integrated circuits. On the other hand, the number of engineers in clean rooms tends to decrease due to automation of semiconductor manufacturing processes. When the above analysis is executed for each trouble case and converted to SPC monitoring, about several tens of alarms may be issued every day for each engineer. In this case, the engineer cannot respond to all SPC alarms, and many device abnormalities are left unattended.

  Thus, in the present embodiment, a method for solving troubles that can be repaired by the manufacturing apparatus itself without trouble of an engineer by automatic control will be described below for troubles related to semiconductor manufacturing.

  First, as a mathematical model of the dynamic system, the following model is considered using the internal state x (t) of the system, the input u (t), the output y (t), and the noise w (t).

  Here, t is a variable representing time or time-series order. In the present embodiment, the internal state x (t) is an internal state of the manufacturing apparatus, and is also referred to as an apparatus state below. The above (1) and (2) are called linear state equations and are described in Non-Patent Document 1, for example. The state equation (1), which is a differential equation, indicates that the state at the next time point is determined by the current state x (t) and the input u (t). The observation equation (2) indicates that at least a part of the internal state can be measured as an observed value (ie, y (t)), and the observed noise w (t) is superimposed on the observed value. . Further, x (t) is an nx-dimensional vector if there are nx internal states. u (t) is a nu-dimensional vector if there are nu inputs. y (t) is a ny-dimensional vector if there are ny observed values. w (t) is the same ny-dimensional vector as y (t). Therefore, A (t) is a matrix having components of nx rows and nx columns. B (t) is a matrix having components of nx rows and nu columns. C (t) is a matrix having components of ny rows and nx columns.

  In Non-Patent Document 1, a general control theory is developed in which coefficient matrices A, B, and C are time-varying matrices and w is white noise. However, in this embodiment, some simplifications are performed in consideration of application to semiconductor manufacturing.

  First, the coefficient matrices A, B, and C are constant matrices that do not change with time. This is an approximation that the linear model of the manufacturing apparatus and the characteristics of the observation device (EES data acquisition device) are constant, and this approximation is considered to be appropriate unless the device is modified.

  Next, the observation noise w (t) is a constant that does not change over time. This is because the noise of the EES data acquirer is sufficiently small compared with the fluctuation of the apparatus state to be detected, and it is considered that there is no problem as a constant term.

  The coefficient matrix C is a unit matrix. This means that only the state measured as EES data is used as the internal state. Further, it is assumed that the internal state of the manufacturing apparatus is covered by the currently acquired EES data.

  As the input u (t), an item that acts on the operation of the manufacturing apparatus such as a recipe setting value of the manufacturing apparatus is set. In the present embodiment, for example, the exposure setting value I, the focus setting value F, the stage speed setting value V, and the like, and these recipe setting values are used as the input u (t).

  Furthermore, in this embodiment, it is assumed that t representing time represents the processing lot order of the exposure apparatus as a natural number.

  There are various troubles related to semiconductor manufacturing. For example, for trouble caused by the exposure apparatus No. 3 of the present embodiment, in addition to the electrical test A outer peripheral shot property failure (abbreviated as “trouble A”), a failure in electrical test B (“trouble B”). "And a defect in electric test C (abbreviated as" trouble C ") were also found to have occurred. That is, it was found that the exposure apparatus No. 3 caused three troubles.

  Next, in the present embodiment, principal component analysis is performed on all EES data acquired for a predetermined period with respect to the exposure apparatus No. 3, and a principal component space that separates normal / trouble A / trouble B / trouble C from each other is searched. The result is shown in FIG. That is, FIG. 7 is a scatter diagram showing the result of applying principal component analysis to all EES data acquired for the exposure apparatus No. 3. As shown in FIG. 7, in the space of the first principal component and the second principal component, the areas indicating normal, trouble A, trouble B, and trouble C are separated from each other, and normal / trouble A / trouble B / trouble C It became clear that the classification of was possible. Also, if it is found that normal / each trouble cannot be classified unless the principal component space is three or more dimensions, such higher-order principal component space is searched. That is, if it is found that normal / each trouble cannot be classified in the two-dimensional principal component space as shown in FIG. 7, then normal / each trouble can be classified in the first to third principal component spaces. Check whether or not. As a result, when the classification is possible, the three-dimensional principal component space is used. When the classification is impossible, a higher-dimensional principal component space is searched.

  Further, the search for the principal component space for classifying normal / each trouble is performed as follows. That is, each distribution in the principal component space of normal / each trouble is approximated by an ellipse around the center of the distribution (in the case of a two-dimensional space, an ellipsoid in the case of three or more dimensions), and the overlap between distribution areas is a predetermined threshold value For example, the principal component space having the lowest dimension in two or more dimensions is obtained. Specifically, a distribution consisting of points representing normal states and a distribution consisting of points representing trouble states are approximated by an elliptical area around the center of the distribution, respectively, and the overlap between the distribution areas approximated by the elliptical area is a predetermined threshold value. It is determined whether or not. If there is no principal component space in which the overlap between the distribution areas is equal to or less than the threshold value by a predetermined dimension (for example, three dimensions), the process is stopped here. In FIG. 7, the distribution areas of normal / trouble A / trouble B / trouble C are all represented by elliptical areas, and there is no overlap between the distribution areas. The above requirement is satisfied. Note that when the principal component space is obtained as shown in FIG. 5 or FIG. 7, a principal component value calculation coefficient for calculating a principal component vector from arbitrary EES data is also obtained. The principal component vector can be expressed as a linear combination of EES data, and the principal component value calculation coefficient gives the coefficient of this linear combination.

  Next, a method for determining the coefficient matrices A and B will be described. First, main components (P1 (t), P2 (t)) as time series vectors are set in the internal state x (t) in the equation (1). As described above, since the principal component is expressed by a linear combination of EES data, the principal component (P1 (t), P2 (t)) can be obtained by performing linear transformation on the EES data acquired in each lot processing. it can. In the present embodiment, since the time t represents the lot processing order, the time differentiation of the internal state x (t) in the equation (1) is replaced with the difference x (t + 1) −x (t). Therefore, the equation of state (1) is

と表される。ここで、係数行列Ａ，Ｂは上述のように定数行列で近似される。

It is expressed. Here, the coefficient matrices A and B are approximated by a constant matrix as described above.

  Next, the internal state x (t) in each lot process expressed by the principal component calculated from the EES data and the input (recipe setting status) to the manufacturing apparatus (specifically, exposure apparatus No. 3) in each lot process ) Collect u (t) for a period of time. In this embodiment, for example, one month of processing was collected.

  Subsequently, the collected time series data of x (t) and u (t) is substituted into the above equation (3) to obtain coefficient matrices A and B as simultaneous equations. At this time, if the coefficient matrix of the simultaneous equations for obtaining the unknown matrices A and B does not have an inverse matrix, A and B cannot be obtained, so the processing is stopped here. For example, if the recipe setting is not changed within the data collection period, the unknown matrix B cannot be obtained because the input y (t) is not changed. That is, the matrix B represents the influence of each input u (t) on the apparatus state change x (t + 1) −x (t). However, if the recipe setting is not changed, the influence on the apparatus state change is shown. Cannot be estimated, and the coefficient matrix B cannot be obtained. In the present embodiment, the coefficient matrices A and B of the state equation (3) can be calculated by actually collecting the input u (t) and the internal state x (t) for one month, for example.

  Non-Patent Document 1 describes a method for determining controllability of a dynamic system represented by a linear state equation by using Kalman filter theory from coefficient matrices A and B of the linear state equation. That is, for coefficient matrices A and B,

を満たしている場合、当該システムには可制御性があると判定される。ここで可制御性とは、入力ｕを制御して任意の状態にシステムを制御できることをいう。つまり、入力ｕを変化させることで、内部状態ｘの各成分値を所望の値に制御できることを意味する。なお、前述のようにｎｘは内部状態ベクトルｘ（ｔ）の次元である。

Is satisfied, it is determined that the system has controllability. Here, controllability means that the system can be controlled to an arbitrary state by controlling the input u. In other words, it means that each component value of the internal state x can be controlled to a desired value by changing the input u. As described above, nx is the dimension of the internal state vector x (t).

  In this embodiment, controllability is determined for the coefficient matrices A and B calculated for the exposure apparatus No. 3. As a result, it was found that the condition of the above formula (4) was satisfied. That is, it was found that the system has controllability. This means that the device can be controlled to an arbitrary principal component (P1, P2) state by controlling the input u (t) in the two-dimensional principal component space in FIG. ing.

  Next, a method for automatically controlling the apparatus state using controllability will be described. The desired device state is “normal”. Therefore, first, in the present embodiment, after obtaining EES data of the manufacturing apparatus (exposure apparatus No. 3), the principal components (P1, P2) are obtained by performing linear transformation on these data using the principal component value calculation coefficient. Is calculated, and it is determined whether or not the obtained principal components (P1, P2) belong to the normal range of FIG. At this time, when the main components (P1, P2) deviate from the normal range, each item of the input u (t) is changed so as to return to the normal range. That is, when the system is controllable, the apparatus state can be returned to the normal range by controlling the input u (t). The deviation from the normal range is determined by approximating the normal range with an ellipse (two-dimensional case) as described above, and determining whether or not the obtained principal component value belongs to the ellipse. Can do.

  FIG. 8 is a diagram illustrating an input control method for returning the apparatus state to a normal state in a system having controllability. In FIG. 8, the point P shows the internal state x (t) of the manufacturing apparatus calculated from the EES data, and the internal state x (t) is in a state deviating from the normal state. In the present embodiment, the state equation (3) in which the coefficient matrices A and B are determined is used to automatically determine the direction of change of the input u (t).

  As shown in FIG. 8, first, several candidates for input u (t) for a lot to be processed are prepared. In the illustrated example, for example, u1 to u4 are prepared. That is, the candidates (u1 to u4) of the input u (t) are slightly changed in vector quantity so that the direction of vector change is different from the input u (t-1) in the previous lot processing. Is. Note that a lot processed immediately before the processing target lot is referred to as a previous lot, and a lot processed next to the processing target lot is referred to as a next lot.

  Subsequently, for each candidate (u1 to u4) of the prepared input u (t), the internal state x (t + 1) for the next lot is obtained using the above equation (3). At this time, since the coefficient matrices A and B are known as described above, and x (t) is given as the point P, x (t + 1) can be calculated for u1 to u4, respectively. .

  Next, in the present embodiment, the input u (t) whose calculated x (t + 1) is closest to “normal” (elliptical region) is selected as the optimal input from u1 to u4, and this is selected. Automatically set in the recipe of the manufacturing equipment. In the illustrated example, u4 is automatically set as the optimum input in the recipe. With such a mechanism, even when a device trouble occurs and the device state deviates from the normal state, the trouble state is automatically restored to the normal state without intervention of an engineer. If there is no controllability, the process is stopped.

  In addition, the kind of trouble which a manufacturing apparatus induces changes in a long period. Therefore, the normal / each trouble category in the principal component space of FIGS. 7 and 8 may also change. Furthermore, it is conceivable that the coefficient matrices A and B of the state equation (3) also change. Therefore, in the present embodiment, the above-described processing is periodically performed (for example, every month), trouble types such as troubles A to C, normal / each trouble classification in the principal component space, and state equation (3) Etc. were updated. As a result, it has been found that automatic recovery from a trouble state to an automatic state is possible over a long period of time.

  In addition, the management method of the present embodiment is applied to other manufacturing apparatuses and troubles. As a result, each device can automatically return from the trouble state to the normal state, and even when the number of engineers is small, it is possible to cope with each trouble that has occurred.

  Next, a system configuration for realizing the above-described semiconductor manufacturing apparatus management method will be described. FIG. 9 is a block diagram showing the configuration of the semiconductor manufacturing apparatus management system according to the present embodiment.

  As shown in FIG. 9, the management system according to the present embodiment is a system that manages a plurality of manufacturing apparatuses 2 involved in manufacturing a semiconductor integrated circuit manufactured in a clean room 1. Management database 4, recipe server 5, recipe database 6, EES server 7, EES database 8, tester 9, test server 10, test database 11, trouble device identification server 12, trouble device database 13, trouble device management server 14, and trouble A device management database 15 is provided.

  The production management server 3 is a server that manages the entire clean room 1. The production management server 3 stores, for example, production management information such as product type, lot number, wafer number, processing date and time in the production management database 4. Information stored in the production management database 4 is used in processing by the trouble device management server 14 and the like as necessary.

  The recipe server 5 sets a recipe (corresponding to the input u described above) to be input to the manufacturing apparatus 2 based on data in the recipe database 6 and the like. The recipe set by the recipe server 5 is stored in the recipe database 6.

  The EES server 7 acquires various EES data from the manufacturing apparatus 2 via an EES data acquisition unit (not shown). The EES server 7 stores the acquired EES data in the EES database 8.

  The tester 9 performs, for example, an electrical test on each wafer after the clean room process is completed. The test server 10 stores the test result of the tester 9 in the test database 11.

  The trouble device specifying server 12 functions as a trouble device specifying unit that specifies a trouble device (cause device) in which a device trouble (abnormality) has occurred. That is, the trouble device specifying server 12 performs a statistical test based on the production management information acquired from the production management database 4, the electrical trouble information acquired from the test database 11, and the EES data group acquired from the EES database 8. Identify the trouble device. The trouble device specifying server 12 stores information on the specified trouble device (cause device) in the trouble device database 13.

  The trouble device management server 14 acquires the production management information acquired from the production management database 4, the EES data regarding the manufacturing device 2 acquired from the EES database 8, the recipe (input u) acquired from the recipe database 6, and the trouble device database 13. Based on the information related to the trouble device, the control amount of the input u is determined, and the determination result is stored in the trouble device management database 15. The recipe server 5 as an input setting unit acquires information on the control amount of the input u from the trouble device management database 15 and sets the recipe by reflecting the control amount on the recipe obtained from the recipe database 6. Thereby, automatic recovery from an abnormal state is possible without using an engineer.

  Next, the operation of the monitoring system, that is, the semiconductor manufacturing apparatus management method will be described with reference to FIGS. Although the following operation contents overlap with those already described, the relationship with the system configuration in FIG. 9 will be clarified and described.

  FIG. 10 is a flowchart for identifying the trouble device. As shown in FIG. 10, first, production management information is input from the production management database 4 to the trouble device specifying server 12 (S1).

  Next, i = 1 is set (S2), and the i-th electrical trouble information is input from the test database 10 to the trouble device specifying server 12 (S3). In the example of the exposure apparatus No. 3 described above, since three types of trouble have occurred (troubles A to C), i can take a value of 1 to 3, for example.

  Next, the trouble device specifying server 12 performs a statistical test on all the manufacturing devices 2 regarding the i-th electrical trouble information (S4), and specifies the trouble device. Then, the trouble device specifying server 12 stores the trouble device specifying result in the trouble device database 13 (S5).

  Next, the value of i is incremented by 1 (S6), and the trouble device specifying server 12 determines whether or not all electrical trouble information has been verified (S7). If not verified, the process returns to S3. If it is verified, the process for identifying the trouble device is terminated.

  Details of the statistical test process (the process of S4) will be described here. The trouble device specifying server 12 acquires EES data from the EES database 8, and generates a device alarm for each of the acquired EES data according to a preset rule (alarm generating function of the trouble device specifying server 12). The device alarm includes, for example, a device alarm based on a range abnormality or a device alarm based on a trend abnormality. Here, the device alarm based on the value range abnormality calculates the average value (μ) and the standard deviation (σ) for the EES parameter when no trouble occurs, and for example, a wafer exceeding μ ± 3σ is determined to be a value range abnormality. And generate an alarm. Further, the device alarm based on the trend abnormality is obtained by obtaining a section where the value range of the EES parameter in the analysis target period changes by 10%, for example, and changing by 10% based on the manufacturing date information of each wafer stored in the production management database 4 For example, when the section width to be performed is shorter than one day, it is determined that the trend is abnormal, and an alarm is generated. The analysis target period is a period for identifying the cause of the trouble. In the following, one type of device alarm is assumed for the sake of simplicity, but extension to the case of using a plurality of device alarms is also easy.

  Next, the trouble device specifying server 12 obtains the significance of the relationship between the device alarm and the electric trouble according to the following processing procedure. Hereinafter, the processing operation by the alarm selection function of the trouble device specifying server 12 will be described in order.

  First, the occurrence probability Pj of the j-th device alarm in the analysis target period is obtained. The device alarm occurrence probability Pj is obtained for each EES parameter. That is, j is 1 to 300 (the number of EES parameters to be acquired is 300), and the device alarm occurrence probability Pj is obtained by dividing the number of occurrences of the j-th device alarm by the number of wafers nt in the analysis target period. .

  Next, the i-th electrical trouble occurrence probability Qi in the analysis target period is obtained. Here, i is set in FIG. The electrical trouble occurrence probability Qi is obtained by dividing the number of occurrences of the i-th electrical trouble by the number of wafers nt in the analysis target period.

Further, assuming that the j-th device alarm and the i-th electrical trouble occur independently of each other, the following cases 1 to 4 are defined.
Case 1: The j-th device alarm and the i-th trouble occur simultaneously.
Case 2: Only the j-th device alarm occurs, and the i-th trouble does not occur.
Case 3: The j-th device alarm does not occur, and only the i-th trouble occurs.
Case 4: Neither the j-th device alarm nor the i-th trouble occurs.

  After the above process is completed, the expected values (cases e1 to e4) of cases 1 to 4 occurring during the analysis target period are obtained by the following equations (5) to (8).

  Next, the wafer processed at the time of the device alarm occurrence is checked based on the information in the production management database 4 to determine whether any electrical trouble has occurred. (O1-o4).

  Next, the trouble device specifying server 12 obtains a significant difference between the actual measurement value and the expected value (function as a significance detection unit of the trouble device specifying server 12). In the present embodiment, for example, chi-square test is used. The P value, which is the test value of the chi-square test, is obtained by the following equations (9) and (10).

ここで、χ２はカイ２乗値である。またｃｈｉｄｉｓｔはカイ２乗分布関数、３はこの統計検定の自由度が３であることを示す。ｏk（本例の場合ｏ１〜ｏ４）は実測値、ｅk（本例の場合ｅ１〜ｅ４）は期待値である。

Here, χ2 is a chi-square value. Chidist represents the chi-square distribution function, and 3 represents 3 degrees of freedom for this statistical test. ok (o1 to o4 in this example) is an actual measurement value, and ek (e1 to e4 in this example) is an expected value.

  e1 to e4 are calculated on the assumption that the device alarm and the electrical trouble occur independently of each other. If this assumption is correct, o1 to o4 and e1 to e4 take close values, and the P value is 1. Take a value close to. On the other hand, if the assumption is not correct and there is a relationship between the device alarm and the occurrence of electrical trouble, o1 to o4 and e1 to e4 take values apart from each other, and the P value takes a value close to zero. Therefore, the case where the P value is smaller than a predetermined threshold (for example, 0.05) is determined to be significant. The above processing is performed for all j.

  In this way, the trouble device specifying server 12 can extract a device alarm having a significant relationship with an electrical trouble from device alarms. Then, the trouble device specifying server 12 can specify the trouble device based on the information of the EES parameter that caused the extracted device alarm.

  In this embodiment, the significance of the relationship between the device alarm and the electrical trouble is determined by the chi-square test. However, when the difference between the expected value and the actually measured value exceeds a predetermined threshold, it is determined to be significant. The determination may be made by other statistical methods.

  FIG. 11 is a flowchart of the controllability determination in the trouble device management server 14. First, i = 1 is set (S10). Here, i is used to distinguish trouble devices, and one or a plurality of trouble devices are specified.

  Subsequently, information regarding the i-th trouble device is input from the trouble device database 13 to the trouble device management server 14 (S11). Further, EES data relating to the i-th trouble device is input from the EES database 8 to the trouble device management server 14 (S12). Furthermore, the recipe of the i-th trouble device is input from the recipe database 6 to the trouble device management server 14 (S13).

  Next, the trouble device management server 14 applies principal component analysis to the EES data acquired for a predetermined period with respect to the i-th trouble device (PLS-DA described above) to distinguish the normal state from the trouble state. A space is searched (S14, FIG. 5, FIG. 7). This is due to the function as the principal component space specifying unit of the trouble device management server 14.

  Next, the trouble device management server 14 applies principal component analysis to the EES data acquired for a predetermined period with respect to the i-th trouble device (PLS-DA described above) to distinguish the normal state from the trouble state. A space is searched (S14, FIG. 5, FIG. 7). As a result, when there is a principal component space for distinguishing between normal state / trouble state (S15, yes), the trouble device management server 14 uses the recipe input (u) and the principal component of EES data to calculate the equation (3). An attempt is made to determine a linear equation of state, that is, to determine coefficient matrices A and B. This is due to the function of the trouble device management server 14 as the linear state equation determination unit. If there is no principal component space for distinguishing between normal state / trouble state (S15, No), the process proceeds to S21.

  Next, when the linear state equation (3) can be determined (S17, Yes), the trouble device management server 14 determines the controllability of the linear state equation (3) based on, for example, the Kalman filter theory (S18). . This is due to the function as the controllability determination unit of the trouble device management server 14. When the linear state equation (3) has been determined (S17, No), the process proceeds to S21.

  Subsequently, when it is determined that there is controllability (S19, Yes), the trouble device management server 14 obtains a principal component value from EES data as device management information in the trouble device management database 15. The calculated coefficients and the coefficient matrices A and B of the linear state equation (3) are stored. The principal component value calculation coefficient is obtained at the time of principal component analysis. Moreover, when it determines with there being no controllability (S19, No), it progresses to S21.

  In S21, the value of i is incremented by one. Subsequently, the trouble device management server 14 checks whether or not the controllability of all trouble devices has been determined (S22). If the controllability of all trouble devices has been determined (S22, Yes), the processing is performed. Exit. If the controllability of all trouble devices has not been determined (No at S22), the process returns to S11.

  Here, the principal component space search process (S14) will be described in detail with reference to FIG. FIG. 13 is a flowchart of the principal component space search process. In FIG. 13, first, the trouble device management server 14 sets the maximum dimension D that may be searched (S51). For example, in the case of D = 3, if the principal component space for distinguishing between the normal state / trouble state is not found in two dimensions, it means searching up to three dimensions.

  Next, the trouble device management server 14 performs principal component analysis on the EES data (S52). Subsequently, in order to start the search from the two-dimensional principal component space, d = 2 is set (S53).

  Next, the trouble device management server 14 creates a scatter diagram of the internal state of the i-th trouble device in the principal component space composed of the first to d-th principal components (S54, FIG. 5, FIG. 7).

  Next, the trouble device management server 14 approximates a distribution composed of points representing the normal state and a distribution composed of points representing the trouble state by an elliptical region around the distribution region (S55, FIGS. 5 and 7). Then, the trouble device management server 14 determines whether or not the overlap between the distribution areas approximated by the elliptical area is equal to or less than a predetermined threshold (S56). As a result, if the overlap is larger than the predetermined threshold (S56, Yes), the value of d is increased by 1 (S58). If the overlap is less than or equal to a predetermined threshold (S56, No), the d-dimensional principal component space is specified as a desired principal component space (S57). In S59, it is determined whether or not d ≦ D. If d ≦ D (S59, Yes), the process returns to S54, and if d> D (S59, No), the process ends.

  FIG. 12 is a flowchart of an automatic recovery process from a trouble state. This automatic recovery processing is based on a function as a controllable device management unit of the trouble device management server 14. In FIG. 12, first, i = 1 is set (S30). Here, i is used to distinguish controllable devices. Here, the controllable device refers to a device determined to have controllability in the processing shown in FIG. 11 among trouble devices.

  Next, the trouble device management server 14 selects the i-th controllable device (S31), and for this i-th controllable device from the trouble device management database 15, the principal component value calculation coefficient and the linear state equation (3) Coefficient matrices A and B are acquired (S32).

  Subsequently, the trouble device management server 14 acquires EES data of the new processing lot from the EES database 8 (S33), and further acquires a recipe input value (u) of the new processing lot from the recipe database 6 (S34). Then, the trouble device management server 14 calculates a principal component value, that is, a principal component vector that is an internal state (device state) from the acquired EES data (S35). At this time, the principal component value calculation coefficient is used.

  Next, the trouble device management server 14 determines whether or not the calculated internal state (device state) belongs to a normal range (see FIG. 5 or FIG. 7) in the principal component space (S36). As a result, when it is determined that the internal state (device state) of the new lot process has deviated from the normal range (S37, Yes), the trouble device management server 14 returns the internal state (device state) to the normal state. The optimum value of the recipe input u is searched and determined so as to recover (S38). At this time, as described above, for example, u4 in FIG. 8 is selected as the optimum recipe input u using the linear state equation (3) in which the coefficient matrices A and B are determined. The trouble device management server 14 stores the optimum value of the recipe input u in the trouble device management database 15 and transmits the optimum value of the recipe input u to the recipe server 5 via the trouble device management database 15. The optimum value of the restoration recipe is instructed (S39). The recipe server 5 controls the input by setting the optimum value of the recipe input u in the i-th controllable device. If it is determined that the internal state (device state) of the new lot process has not deviated from the normal range (S37, No), the process proceeds to S40.

  In S40, the value of i is incremented by one. Subsequently, the trouble device management server 14 checks whether or not all controllable devices have been monitored and controlled (S41). If all controllable devices have been monitored and controlled (S41, Yes), the process ends. To do. If all the controllable devices are not monitored or controlled (S41, No), the process returns to S31.

  As described above, according to the present embodiment, it is determined whether or not the internal state belongs to the normal range in the principal component space for the controllable trouble device, and as a result, deviates from the normal range. If it is determined that the input state is determined, an input u for returning the internal state to the normal range is determined based on the linear state equation (3) of the coefficient matrix, and this is input to the trouble device. Therefore, it is possible to automatically solve the trouble of the manufacturing apparatus without using an engineer.

  In the present embodiment, the processing shown in FIG. 11 and the like are periodically performed, and the principal component space and the state equation (3) are regularly updated. It is possible to cope with changes in Other effects of the present embodiment are as described in the specification.

  In Patent Document 2, the state of a manufacturing apparatus is estimated, and scheduling is performed so that processing is preferentially allocated to a problem-free apparatus that can be normally estimated. However, this document does not describe a method for automatically recovering the apparatus state from the trouble state in consideration of controllability as in the present embodiment.

  In Patent Document 3, APC (Advanced Process Control) is performed by changing the sampling of QC (Quality Control) values according to the apparatus status and event. However, this document does not describe a method for automatically recovering the apparatus state from the trouble state in consideration of controllability.

  At least some of the functions of the trouble device management server 14 described in the above-described embodiment may be configured by software. When configured by software, a program for realizing the function may be stored in a recording medium such as a flexible disk or a CD-ROM and read and executed by a computer. The recording medium is not limited to a removable medium such as a magnetic disk or an optical disk, but may be a fixed recording medium such as a hard disk device or a memory. The program may be distributed via a communication line (including wireless communication) such as the Internet. Further, the program may be distributed in a state where the program is encrypted, modulated or compressed, and stored in a recording medium via a wired line such as the Internet or a wireless line.

  DESCRIPTION OF SYMBOLS 1 Clean room, 2 Manufacturing apparatus, 3 Production management server, 4 Production management database, 5 Recipe server, 6 Recipe database, 7 EES server, 8 EES database, 9 Tester, 10 Test server, 11 Test database, 12 Trouble device specific server, 13 Trouble device database, 14 Trouble device management server, 15 Trouble device management database, 20 Wafer, 21 Defective chip

Claims (5)

A method of managing a semiconductor manufacturing apparatus that monitors each manufacturing apparatus by acquiring EES data representing an internal state of a plurality of manufacturing apparatuses involved in manufacturing a semiconductor integrated circuit,
Identifying a manufacturing apparatus that causes a defect in the semiconductor integrated circuit from the plurality of manufacturing apparatuses;
A principal component that applies principal component analysis to the EES data acquired for a predetermined period with respect to the specified manufacturing apparatus and divides the distribution of the normal state and the distribution of the trouble state into regions separated from each other with respect to the internal state of the manufacturing apparatus A step for space,
The internal state of the specified manufacturing apparatus is represented by a principal component vector in the principal component space, and the time evolution of the internal state is defined linearly depending on the input to the specified manufacturing apparatus and the internal state. Setting a linear state equation and determining an unknown matrix included in the linear state equation based on the internal state and the time series data of the input;
Determining the controllability of the determined linear state equation of the coefficient matrix;
When it is determined that there is the controllability, after acquiring the EES data for the specified manufacturing apparatus, the internal state as a principal component vector is calculated from the acquired EES data, and the internal state Determining whether or not belongs to a region representing the normal state in the principal component space;
If it is determined that the internal state deviates from the region representing the normal state, the input is set so that the internal state returns to the normal state based on the determined linear state equation of the coefficient matrix. Controlling steps;
A method for managing a semiconductor manufacturing apparatus, comprising:   When the internal state deviates from a region representing the normal state, a plurality of different candidates as the set value of the input are prepared, and each candidate and the linear state equation determined in the coefficient matrix are prepared. By substituting the internal state, the time change of the internal state is examined, and the candidate is selected so that the internal state is closest to the region representing the normal state over time, and this is input to the specified manufacturing apparatus. The semiconductor manufacturing apparatus management method according to claim 1, wherein:   The principal component space and the coefficient matrix are periodically updated by periodically executing a process until it is determined whether or not the internal state belongs to a region representing the normal state. Item 3. A method for managing a semiconductor manufacturing apparatus according to Item 1 or 2.   For a set of points in the principal component space obtained by applying principal component analysis to the EES data acquired for the predetermined period, the distribution consists of points representing the normal state and points representing the trouble state. 4. The principal component space having a dimension such that the distribution is approximated by an elliptical area around the center of the distribution and the overlap between the elliptical areas is equal to or less than a predetermined threshold value. The management method of the semiconductor manufacturing apparatus of any one of these. A semiconductor manufacturing apparatus management system for monitoring each manufacturing apparatus by acquiring EES data representing an internal state of a plurality of manufacturing apparatuses involved in manufacturing a semiconductor integrated circuit,
A trouble device identifying unit for identifying a manufacturing device that causes a defect in the semiconductor integrated circuit from the plurality of manufacturing devices;
A principal component that applies principal component analysis to the EES data acquired for a predetermined period with respect to the specified manufacturing apparatus and divides the distribution of the normal state and the distribution of the trouble state into regions separated from each other with respect to the internal state of the manufacturing apparatus A principal component space specifying unit for obtaining a space;
The internal state of the specified manufacturing apparatus is represented by a principal component vector in the principal component space, and the time evolution of the internal state is defined linearly depending on the input to the specified manufacturing apparatus and the internal state. A linear state equation determining unit that sets a linear state equation and determines an unknown matrix included in the linear state equation based on the internal state and the time series data of the input;
A controllability determination unit that determines the controllability of the determined linear state equation of the coefficient matrix;
When it is determined that there is the controllability, after acquiring the EES data for the specified manufacturing apparatus, the internal state as a principal component vector is calculated from the acquired EES data, and the internal state Is determined to belong to the region representing the normal state in the principal component space, and if it is determined that the internal state deviates from the region representing the normal state, the coefficient matrix is determined. Based on the linear state equation, the controllable device manager that determines the input so that the internal state returns to the normal state;
An input setting unit for setting the input determined by the controllable device management unit in the specified control device;
A management system for semiconductor manufacturing equipment, comprising:

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