JP2011049601A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem wherein, in a conventional semiconductor device, it becomes difficult to form a normal contact and a shared contact at the same time, and a junction leak failure and increase of contact resistance occur, and the like. <P>SOLUTION: This semiconductor device includes: a sidewall 9 formed on a sidewall of a gate wire 6 of a logic SRAM part; a doped polysilicon 18 for electrically connecting a silicide layer 13 formed on a surface of a diffusion layer 11 to a silicide layer 15 of the gate wire 6; a W plug 26 for electrically connecting the doped polysilicon 18 to a first layer aluminum wire; and a W plug 25 for electrically connecting the silicide layer on the surface of the diffusion layer 11 of the logic SRAM part to the first layer aluminum wire. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which DRAM and SRAM are mixedly mounted, and particularly to a semiconductor device having a structure capable of easily forming a shared contact effective for reducing the cell area of the SRAM and a method for manufacturing the same.

  FIG. 9 is a circuit diagram showing an SRAM memory cell used in a conventional semiconductor device. In FIG. 9, 101 and 102 are PMOS load transistors that serve as loads, 103 and 104 are NMOS drive transistors that serve to extract charges, 105 and 106 are NMOS access transistors that serve to draw information to the bit lines, and Vcc is A power supply line, GND is a ground line, and WL is a word line. The NMOS access transistor 105 is connected to the bit line 'BL', and the NMOS access transistor 106 is connected to the bit bar line '/ BL'.

  FIG. 10 is a layout diagram showing SRAM memory cells used in a conventional semiconductor device, and shows an example in which the circuit diagram shown in FIG. 9 is laid out. 10, the same reference numerals as those in FIG. 9 denote the same or corresponding parts, and the description thereof is omitted. 111 is a gate of the PMOS load transistor 101 and the NMOS drive transistor 103, 112 is a gate of the PMOS load transistor 102 and the NMOS drive transistor 104, 113 is a gate of the NMOS access transistor 105, and 114 is a gate of the NMOS access transistor 106.

  In FIG. 10, reference numeral 115 denotes a contact on the active region of the NMOS drive transistor 103 and the NMOS access transistor 105, 116 denotes a contact on the gate of the PMOS load transistor 102 and the NMOS drive transistor 104, and 117 denotes a contact on the active region of the PMOS load transistor 101. , 118 is a contact on the active region of the PMOS load transistor 102, 119 is a contact on the gate of the PMOS load transistor 101 and the NMOS drive transistor 103, 120 is a contact on the active region of the NMOS drive transistor 104 and the NMOS access transistor 106, and 121 is an active region. A first-layer aluminum wiring 122 connecting the upper contacts 115 and 117 and the gate upper contact 116 is active. The first layer aluminum wiring connecting the region contacts 118, 120 and the gate contact 119, 123 the first layer aluminum wiring connected to the PMOS load transistor 101, 124 the active region contact of the PMOS load transistor 102, and 125 the active This is a first layer aluminum wiring connected to the regional contact 124.

  The first-layer aluminum wiring 121 is a cross-coupled portion that connects the outputs of the PMOS load transistor 101 and the NMOS drive transistor 103 to the gates 112 of the PMOS load transistor 102 and the NMOS drive transistor 104. This is a cross-coupled portion that connects the outputs of the PMOS load transistor 102 and the NMOS drive transistor 104 to the gates 111 of the PMOS load transistor 101 and the NMOS drive transistor 103. In addition, illustration of the through-holes and the aluminum wiring of the second layer or higher is omitted. In the example of the layout shown in FIG. 10, the contacts 115 to 120 and 124 are arranged independently. In this specification, each of the contacts 115 to 120 and 124 arranged independently may be referred to as a normal contact.

  FIG. 11 is a layout diagram showing an SRAM memory cell used in a conventional semiconductor device. FIG. 11 shows an example in which the cell area is reduced using a shared contact with respect to the layout diagram shown in FIG. In FIG. 11, the same reference numerals as those in FIG. 131 is a shared contact in which the gate contact 116 and the active region contact 117 are formed by one contact, and 132 is a shared contact in which the gate contact 119 and the active region contact 118 are formed by one contact. As shown in FIG. 11, since the cell dimension in the gate width direction is shortened, the cell area of the SRAM can be reduced.

  FIG. 12 is a cross-sectional view showing the manufacturing process of the SRAM in the conventional semiconductor device, and corresponds to the cross-sectional view taken along the line A-A ′ shown in FIG. 11. In FIG. 12, 201 is a well portion in a silicon substrate, 202 is an isolation oxide film, 203 is a gate oxide film, 204 is a gate electrode corresponding to the gate 112, 205 is a gate wiring corresponding to the wiring portion of the gate 111, and 206 is a gate. Side wall formed on the side wall of the electrode 204, 207 is a side wall formed on the side wall of the gate wiring 205, 208 is a diffusion layer of source / drain, 209 is a silicide layer on the diffusion layer 208, 210 is a silicide layer on the gate electrode 204 , 211 are silicide layers on the gate wiring 205, and 212 is a silicon nitride film.

  In FIG. 12, reference numeral 213 denotes a contact interlayer film formed of a silicon oxide film, 214 and 215 denote barrier metals formed on the bottom and side walls of the contact, and 216 and 217 denote tungsten plugs (hereinafter referred to as W plugs) formed in the contact holes. 218 and 219 are barrier metals, 220 and 221 are aluminum wirings, and 222 and 223 are anti-reflective coating (ARC) films formed as antireflection films in the photolithography process. The active region contact 124 corresponds to a portion where the barrier metal 214 and the W plug 216 are formed, and the shared contact 132 corresponds to a portion where the barrier metal 215 and the W plug 217 are formed. Corresponds to a portion where the barrier metal 218, the aluminum wiring 220, and the ARC film 222 are formed, and the first layer aluminum wiring 125 corresponds to a portion where the barrier metal 219, the aluminum wiring 221 and the ARC film 223 are formed. Further, the active region contact 124 and the shared contact 132 are formed in the same process, and are not formed through separate photolithography processes, etching processes, and the like. Although not shown in the sectional view, the contacts on the gates 113 and 114 are formed in the same process as the active region contact 124 and the shared contact 132.

  For example, Patent Document 1 and Patent Document 2 disclose the conventional semiconductor devices disclosed above.

Japanese Patent No. 3064999 USP 6,031,271

  Since the conventional semiconductor device is configured as described above, in the system LSI in which DRAM and SRAM are mixedly mounted, the contact interlayer film is thickened to form the DRAM capacitor layer. It becomes difficult to form the shared contact at the same time, and there are problems such as defective junction leakage and increased contact resistance.

  The problems of the prior art will be described in detail. In the manufacturing process of the SRAM in the conventional semiconductor device shown in FIG. 12, the contact interlayer film 213 has a thickness of 0.5 to 0.8 μm, and the active region contact 124 and the shared contact 132 are formed simultaneously. Is possible. On the other hand, in the manufacturing process of a system LSI in which DRAM and SRAM are mounted together, the contact interlayer film 213 has a thickness of 1.0 μm to 3.0 μm in order to form a DRAM capacitor layer. It becomes difficult to form the shared contact 132 at the same time.

  In FIG. 12, the silicon nitride film 212 is etched when the contact 124 and the shared contact 132 on the active region are formed on the contact interlayer film 213 formed of a silicon oxide film by using, for example, a dry etching method. The etching of the contact interlayer film 213 is stopped by a selective etching method using the difference between the two. That is, the silicon nitride film 212 is a stopper layer for the etching process. However, in the case where the silicon nitride film 212 is deposited so as to cover the sidewall 207, the selective ratio to the silicon oxide film is lower than that of the flat part, and the contact interlayer film 213 is thick. In the etching process for forming the shared contact 132, the overetching time becomes long, so that the portion deposited so as to cover the sidewall 207 of the silicon nitride film 212 is almost removed. Further, in the etching process of the silicon nitride film 212 performed after the etching process of the contact interlayer film 213, the side wall (formed of the silicon nitride film) 207 is almost removed.

  Therefore, the W plug 217 and the barrier metal 215 of the shared contact 132 are electrically connected to the sidewall 207 between the silicide layer 209 and the gate wiring 205. This portion of the diffusion layer has a low concentration due to the LDD structure and is not silicided, which causes a problem of defective junction leakage. Further, in the etching process for forming the active region contact 124 and the shared contact 132 in the contact interlayer film 213, when etching is performed under an etching condition that increases the selectivity with respect to the silicon nitride film 212, the active region contact 124 is formed. In addition, the taper angle of the shared contact 132 is reduced from 90 ° and becomes an extreme forward taper. For this reason, when the contact interlayer film 213 is thick, the bottom diameters of the contacts 124 and 132 are reduced, so that the contact resistance is increased. Further, the active region contact 124 and the shared contact 132 are not yet formed. There existed problems, such as the defect which becomes an opening generate | occur | produced.

  The present invention has been made to solve the above-described problems. In a system LSI in which DRAM and SRAM are mixedly mounted, even when the contact interlayer film is thick in order to form a capacitor layer of DRAM, It is an object of the present invention to obtain a semiconductor device capable of simultaneously forming a contact and a shared contact and suppressing a junction leak defect and an increase in contact resistance.

  The semiconductor device according to the present invention is a semiconductor device in which a DRAM and an SRAM are mixedly mounted, and includes a sidewall formed on the gate electrode sidewall of the SRAM and a first diffusion layer surface formed in the same contact hole as the sidewall. A first contact having a first plug for electrically connecting the silicide layer and the second silicide layer on the surface of the gate electrode, and a second plug between the first contact and the first wiring layer And a second contact electrically connecting the first contact and the first wiring layer, and a second silicide layer between the third silicide layer and the second wiring layer on the surface of the SRAM diffusion layer. A third contact having a plug and electrically connecting the third silicide layer and the second wiring layer is provided.

  The semiconductor device according to the present invention is a semiconductor device in which a DRAM and an SRAM are mixedly mounted, and includes a sidewall formed on the gate electrode sidewall of the SRAM and a first diffusion layer surface formed in the same contact hole as the sidewall. A first contact having a first plug for electrically connecting the silicide layer and the second silicide layer on the surface of the gate electrode, and a second plug between the first contact and the first wiring layer And a second contact electrically connecting the first contact and the first wiring layer, and a first plug electrically connecting to the third silicide layer on the surface of the diffusion layer of the SRAM. 4 and a fifth contact having a second plug between the fourth contact and the second wiring layer and electrically connecting the fourth contact and the second wiring layer. thing A.

  In the semiconductor device according to the present invention, the first contact is formed in the same process as the lower contact of the DRAM.

  In the semiconductor device according to the present invention, the first contact or the fourth contact is formed in the same process as the lower contact of the DRAM.

  In the semiconductor device according to the present invention, the second contact or the third contact is formed in the same process as the upper contact of the DRAM.

  In the semiconductor device according to the present invention, the second contact or the fifth contact is formed in the same process as the upper contact of the DRAM.

  In the semiconductor device according to the present invention, the first plug is formed using a metal containing tungsten.

  In the semiconductor device according to the present invention, the second contact or the fifth contact has a first insulating film and a second insulating film stacked on the first insulating film and the first insulating film. A contact opening formed by selective etching with the second insulating film is provided.

  A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device in which a DRAM and an SRAM are mixedly mounted, wherein a step of forming a sidewall on the side wall of the gate electrode, and the surface of the diffusion layer and the gate electrode surface are silicided. A step of forming a first contact interlayer film, a step of forming an opening of a lower contact of the DRAM and an opening of a first contact of the SRAM in the first contact interlayer, and a lower contact of the DRAM Forming a first plug in the opening of the first contact and the opening of the first contact of the SRAM, forming an insulating film for selective etching in the DRAM, forming a capacitor layer in the DRAM, and forming the capacitor in the SRAM Forming a second contact interlayer; opening of upper contact of DRAM and opening of second contact of SRAM And forming a third contact opening in the SRAM, a second plug in the opening in the upper contact in the DRAM, the opening in the second contact in the SRAM, and the opening in the third contact in the SRAM. Forming the process.

  A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device in which a DRAM and an SRAM are mixedly mounted, wherein a step of forming a sidewall on the side wall of the gate electrode, and the surface of the diffusion layer and the gate electrode surface are silicided. A step of forming a first contact interlayer film, an opening of a lower contact of a DRAM, an opening of a first contact of an SRAM, and an opening of a fourth contact of an SRAM in the first contact interlayer Forming a first plug in the opening of the lower contact of the DRAM, the opening of the first contact of the SRAM, and the opening of the fourth contact of the SRAM, and for performing selective etching A step of forming an insulating film, a step of forming a capacitor layer in the DRAM and a second contact interlayer film in the SRAM, and DR Forming an opening of the upper contact of M, an opening of the second contact of the SRAM, and an opening of the fifth contact of the SRAM; an opening of the upper contact of the DRAM; and an opening of the second contact of the SRAM And a step of forming a second plug in the opening of the fifth contact of the SRAM.

  According to the present invention, there is provided a semiconductor device in which a DRAM and an SRAM are mixedly mounted, the sidewall formed on the side wall of the gate electrode of the SRAM, and the first silicide on the surface of the diffusion layer formed in the same contact hole as the sidewall. A first contact having a first plug for electrically connecting the layer and the second silicide layer on the surface of the gate electrode, and a second plug between the first contact and the first wiring layer. A second plug is electrically connected between the second contact for electrically connecting the first contact and the first wiring layer, and the third silicide layer and the second wiring layer on the surface of the SRAM diffusion layer. Since it is configured to include the third contact that electrically connects the third silicide layer and the second wiring layer, it is possible to form a normal contact and a shared contact at the same time. With some, effect that an increase in junction leakage failure and the contact resistance can be suppressed. In addition, since it is possible to form a normal contact and a shared contact at the same time, it is possible to easily reduce the cell area of the logic SRAM.

  According to the present invention, there is provided a semiconductor device in which a DRAM and an SRAM are mixedly mounted, the sidewall formed on the side wall of the gate electrode of the SRAM, and the first silicide on the surface of the diffusion layer formed in the same contact hole as the sidewall. A first contact having a first plug for electrically connecting the layer and the second silicide layer on the surface of the gate electrode, and a second plug between the first contact and the first wiring layer. And a second contact electrically connecting the first contact and the first wiring layer, and a fourth plug having a first plug electrically connected to the third silicide layer on the surface of the SRAM diffusion layer. A contact, and a fifth contact having a second plug between the fourth contact and the second wiring layer and electrically connecting the fourth contact and the second wiring layer. Configured In, together can form regular contact with the shared contact simultaneously, the effect is obtained that an increase in junction leakage failure and the contact resistance can be suppressed. In addition, since it is possible to form a normal contact and a shared contact at the same time, it is possible to easily reduce the cell area of the logic SRAM. Furthermore, the effect that the manufacturing cost can be reduced and the manufacturing period can be shortened can be obtained.

  According to the present invention, since the first contact is formed in the same process as the lower contact of the DRAM, the number of masks used in the photolithography process does not increase, so that the manufacturing cost and the manufacturing process are reduced. The effect of suppressing the increase is obtained.

  According to the present invention, since the first contact or the fourth contact is formed in the same process as the lower contact of the DRAM, the number of masks used in the photolithography process does not increase. And an increase in the number of manufacturing steps can be obtained.

  According to the present invention, since the second contact or the third contact is formed in the same process as the upper contact of the DRAM, the number of masks used in the photolithography process does not increase, so that the manufacturing cost can be increased. And an increase in the number of manufacturing steps can be obtained.

  According to the present invention, since the second contact or the fifth contact is formed in the same process as the upper contact of the DRAM, the number of masks used in the photolithography process does not increase. And an increase in the number of manufacturing steps can be obtained.

  According to the present invention, since the first plug is formed using the metal containing tungsten, there is an effect that the contact resistance can be lowered.

  According to the present invention, the second contact or the fifth contact has the first insulating film and the second contact with respect to the first insulating film and the second insulating film stacked on the first insulating film. Since the contact opening is formed by selectively etching with the insulating film, the aspect ratio of the normal contact is reduced, so that it is possible to easily form the normal contact. It is done. Moreover, the effect that the manufacturing cost can be reduced and the manufacturing period can be shortened can be obtained.

  According to the present invention, there is provided a method of manufacturing a semiconductor device in which DRAM and SRAM are mounted together, the step of forming a sidewall on the side wall of the gate electrode, the step of siliciding the diffusion layer surface and the gate electrode surface, Forming a contact interlayer film of the DRAM, a process of forming an opening of the lower contact of the DRAM and an opening of the first contact of the SRAM in the first contact interlayer film, an opening of the lower contact of the DRAM and the SRAM Forming a first plug in the opening of the first contact, forming an insulating film for selective etching in the DRAM, forming a capacitor layer in the DRAM, and forming a second contact layer in the SRAM Forming a film; an opening in the upper contact of the DRAM; an opening in the second contact of the SRAM; and a third of the SRAM. Forming a contact opening, and forming a second plug in the opening of the upper contact of the DRAM, the opening of the second contact of the SRAM, and the opening of the third contact of the SRAM. With this configuration, it is possible to form a normal contact and a shared contact at the same time, and to obtain an effect of suppressing a junction leak failure and an increase in contact resistance. In addition, since it is possible to form a normal contact and a shared contact at the same time, it is possible to easily reduce the cell area of the logic SRAM.

  According to the present invention, there is provided a method of manufacturing a semiconductor device in which DRAM and SRAM are mounted together, the step of forming a sidewall on the side wall of the gate electrode, the step of siliciding the diffusion layer surface and the gate electrode surface, Forming a contact interlayer film, and forming a lower contact opening of the DRAM, a first contact opening of the SRAM, and an opening of the fourth contact of the SRAM in the first contact interlayer film, Forming a first plug in the opening of the lower contact of the DRAM, the opening of the first contact of the SRAM, and the opening of the fourth contact of the SRAM, and forming an insulating film for performing selective etching; Forming a capacitor layer in the DRAM and forming a second contact interlayer in the SRAM; and an upper contact of the DRAM Forming an opening, an opening of the second contact of the SRAM, and an opening of the fifth contact of the SRAM; an opening of the upper contact of the DRAM; an opening of the second contact of the SRAM; 5 has a step of forming a second plug in the opening of the contact 5, it is possible to form a normal contact and a shared contact at the same time, as well as a junction leak failure and an increase in contact resistance. The effect that it can suppress is acquired. In addition, since it is possible to form a normal contact and a shared contact at the same time, it is possible to easily reduce the cell area of the logic SRAM. Furthermore, the effect that the manufacturing cost can be reduced and the manufacturing period can be shortened can be obtained.

It is sectional drawing which shows the manufacturing process of the semiconductor device by Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing process for demonstrating the manufacturing method of the semiconductor device by Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing process for demonstrating the manufacturing method of the semiconductor device by Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing process for demonstrating the manufacturing method of the semiconductor device by Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing process for demonstrating the manufacturing method of the semiconductor device by Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by Embodiment 2 of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by Embodiment 3 of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by Embodiment 4 of this invention. It is a circuit diagram which shows the memory cell of SRAM used for the conventional semiconductor device. FIG. 14 is a layout diagram showing SRAM memory cells used in a conventional semiconductor device. FIG. 14 is a layout diagram showing SRAM memory cells used in a conventional semiconductor device. It is sectional drawing which shows the manufacturing process of SRAM in the conventional semiconductor device.

An embodiment of the present invention will be described below.
Embodiment 1 FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor device according to Embodiment 1 of the present invention, and is a cross-sectional view showing a manufacturing process of a DRAM memory cell portion (DRAM) and a logic SRAM portion (SRAM). The DRAM memory cell portion and the logic SRAM portion are mixedly mounted on one chip and constitute a system LSI. In FIG. 1, 1 is a well portion in a silicon substrate, 2 is an isolation oxide film, 3 is a gate oxide film of a logic SRAM section, and 4 is a gate oxide film of a DRAM memory cell section. In the method of manufacturing a system LSI in which DRAM and SRAM are mixedly mounted, the gate oxide film 3 of the logic SRAM section is formed with a gate thickness of the DRAM memory cell section in order to achieve both the performance of the DRAM memory cell section and the logic SRAM section. In some cases, the gate oxide films 3 and 4 are formed by a so-called dual oxide process in which the film thickness is smaller than that of the oxide film 4.

  In FIG. 1, 5 is a gate electrode of the logic SRAM section, 6 is a gate wiring (gate electrode) of the logic SRAM section, 7 is a gate electrode of the DRAM memory cell section, and 8 is a side wall of the gate electrode 5 of the logic SRAM section. Side walls to be formed, 9 is a side wall formed on the side wall of the gate wiring 6 of the logic SRAM section, 10 is a side wall formed on the side wall of the gate electrode 7 of the DRAM memory cell section, and 11 is a source of the logic SRAM section. A drain diffusion layer 12 is a source / drain diffusion layer of the DRAM memory cell portion.

  Further, in FIG. 1, the logic SRAM portion uses a silicidation technique, 13 is a silicide layer (first silicide layer) formed on the source / drain diffusion layer 11 of the logic SRAM portion, and 14 is a logic gate. A silicide layer 15 is formed on the gate electrode 5 of the SRAM section, and 15 is a silicide layer (second silicide layer) formed on the gate wiring 6 of the logic SRAM section. For example, a cobalt silicide layer is used as the silicide layer.

  Further, in FIG. 1, 16 is a silicon nitride film formed as an insulating film and a stopper layer for an etching process, 17 is a contact interlayer film (first contact layer) formed of a silicon oxide film, and 18 is a logic SRAM section. The doped polysilicon (first plug) 19 embedded in the lower contact (first contact, contact hole) of the shared contact composed of the upper and lower contacts is the two upper and lower contacts in the DRAM memory cell portion. The doped polysilicon (first plug) embedded in the lower contact (lower contact) of the constructed bit line direct contact, and 20 is the doped polysilicon (first contact) embedded in the storage node direct contact (lower contact). 1 plug), 21 is silicon oxide The contact interlayer film (second contact interlayer film) of the logic SRAM portion formed in step (2), 22 is a silicide layer (third silicide layer) formed on the active region of the logic SRAM portion and the first layer aluminum wiring (first layer). 2 is a barrier metal formed on the side wall of a contact (third contact) that directly connects the second wiring layer), and 23 is a contact (second contact) on the upper part of the shared contact composed of two upper and lower contacts in the logic SRAM section. ) Is a barrier metal formed on the side wall of the upper contact (upper contact) in the bit line direct contact composed of two upper and lower contacts in the DRAM memory cell portion, and 25 is a logic SRAM. Embedded in the contact directly connecting the active region of the part and the first layer aluminum wiring The inserted W plug (second plug) 26 is embedded in the upper contact (second contact) of the shared contact composed of the upper and lower two contacts in the logic SRAM section, and the first layer aluminum wiring (first contact). W plug (second plug) connected to the wiring layer), 27 is a W plug (second plug) embedded in the upper contact of the bit line direct contact composed of two upper and lower contacts in the DRAM memory cell portion. It is.

  1, 28 is a silicon nitride film (insulating film) formed only in the DRAM memory cell portion, 29 is a storage node interlayer film formed of a silicon oxide film, and 30 is formed of doped polysilicon, for example. A storage node electrode, 31 is a capacitor dielectric film formed of, for example, a tantalum oxide film, 32 is a cell plate electrode formed of, for example, a titanium nitride (TiN) film, and 33 is a cell plate electrode 32 formed of a silicon oxide film. This is the upper contact interlayer film. In this specification, the storage node interlayer film 29, the storage node electrode 30, the capacitor dielectric film 31, the cell plate electrode 32, and the contact interlayer film 33 are collectively referred to as a capacitor layer.

  Further, in FIG. 1, 34 is a barrier metal, 35 is an aluminum wiring, and 36 is an ARC film formed as an antireflection film in a photolithography process. The first layer aluminum wiring corresponds to a portion where the barrier metal 34, the aluminum wiring 35, and the ARC film 36 are formed. Further, since the layer above the first layer aluminum wiring is not the essence of the present invention, its description and illustration are omitted.

  Next, a manufacturing method will be described. 2 to 5 are cross-sectional views illustrating manufacturing steps for explaining the method of manufacturing a semiconductor device according to the first embodiment of the present invention. First, the well portion 1 in the silicon substrate is formed by ion implantation, for example, and then the isolation oxide film 2 is selectively formed by LOCOS method or ST method, for example. Next, the gate oxide films 3 and 4 are formed by, for example, a dual oxide process, and then the gate electrodes 5 and 7 and the gate wiring 6 are formed. Next, sidewalls 8, 9, and 10 are formed by depositing and etching a silicon nitride film, and then, for example, cobalt (Co) is sputtered and heat treatment is performed to remove unreacted portions of cobalt and silicon. Thus, a cobalt silicide layer is formed as the silicide layers 13, 14, and 15. Next, the silicon nitride film 16 is deposited by, for example, LP-CVD (Low Pressure-Chemical Vapor Deposition), and then the contact interlayer film 17 is deposited by, for example, CVD. Next, the contact interlayer film 17 is planarized by reflow or CMP. FIG. 2 shows a cross-sectional view in which the manufacturing steps described above are performed. In FIG. 2, the same reference numerals as those in FIG.

  Next, in a photolithography process, a predetermined pattern is formed on the photoresist applied on the contact interlayer film 17, and then the contact interlayer film 17 is processed by etching using, for example, an RIE apparatus. This etching step is a step of selectively etching the silicon oxide film and the silicon nitride film. Further, since the thickness of the contact interlayer film 17 formed of the silicon oxide film is 0.5 to 0.8 μm, A portion of the silicon nitride film 16 deposited so as to cover the sidewalls 9 by etching is not removed when the contact interlayer film 17 is etched. Next, the silicon nitride film 16 is processed by etching using, for example, an RIE apparatus or the like. FIG. 3 shows a cross-sectional view in which the manufacturing steps described above are performed. In FIG. 3, the same reference numerals as those in FIG. 37 is an opening (contact hole) of a lower contact of the shared contact composed of two upper and lower contacts in the logic SRAM portion, and 38 is a lower portion of the bit line direct contact composed of the upper and lower two contacts in the DRAM memory cell portion. Contact openings 39 and 39 are contact openings in the storage node direct contact. The contact on the gate of the NMOS access transistor (not shown) is also formed in the same process.

  Next, doped polysilicon 18 to 20 is embedded in the openings 37 to 39 of each contact by depositing and planarizing doped polysilicon by, for example, LP-CVD. Since the silicide layer 13 and the doped polysilicon 18 are metal-silicon junctions, they become ohmic junctions, and a resistance that does not cause a problem in the SRAM operation can be secured. Next, the silicon nitride film 28 is deposited by, for example, LP-CVD, and then the silicon nitride film 28 in the logic SRAM portion is removed by a photolithography process and an etching process. Next, a storage node interlayer film 29 is formed by depositing a silicon oxide film and performing a predetermined process, and then sequentially stacking and processing the storage node electrode 30, the capacitor dielectric film 31, and the cell plate electrode 32. To form a capacitor. Next, a contact interlayer film 33 on the cell plate electrode 32 is deposited and planarized. In addition, the contact interlayer film 21 in the logic SRAM section includes a storage node interlayer film 29 and a contact interlayer film 33. FIG. 4 shows a cross-sectional view in which the manufacturing steps described above are performed. 4, the same reference numerals as those in FIG. 1 denote the same or corresponding parts, and the description thereof is omitted.

  Next, in a photolithography process, a predetermined pattern is formed on the photoresist applied on the contact interlayer films 21 and 33, and then the silicon oxide film is processed by etching using, for example, an RIE apparatus. The etching process at this time is performed in two steps. First, in the first step, the silicon oxide film is processed under etching conditions that allow selective etching of the doped polysilicon and the silicon nitride film. That is, in the DRAM memory cell portion, the contact interlayer film 33 and the storage node interlayer film 29 are sequentially etched so that the etching stops at the silicon nitride film 28. Further, in the logic SRAM portion, the contact interlayer film 21 is etched so that the etching is stopped by the doped polysilicon 18, and the contact interlayer film 21 and the contact interlayer film 17 are sequentially etched so that the etching is stopped by the silicon nitride film 16. . Next, in the second step, the silicon nitride film is processed under etching conditions that allow selective etching of the doped polysilicon. That is, the silicon nitride film 28 in the DRAM memory cell portion and the silicon nitride film 16 in the logic SRAM portion are etched so that the doped polysilicon 18 is not etched. FIG. 5 shows a cross-sectional view in which the above manufacturing steps have been carried out. In FIG. 5, the same reference numerals as those in FIG. 40 is a contact opening in the contact on the active region of the logic SRAM section, 41 is a contact opening in the upper part of the shared contact composed of two upper and lower contacts in the logic SRAM section, and 42 is an upper and lower contact opening in the DRAM memory cell section. This is an opening of an upper contact in a bit line direct contact constituted by a contact. In the contact opening 41, if the contact opening 37 under the shared contact is formed in advance in consideration of alignment errors and dimensional variations, an increase in contact resistance or the like can be prevented in advance.

  Next, a barrier metal is deposited and processed on the bottom and side walls of each contact 40 to 42 using, for example, sputtering or CVD. Next, tungsten is deposited by, for example, CVD and planarized to fill the W plugs 25 to 27, and then, a barrier metal 34, an aluminum wiring 35, and an ARC film 36 of the first layer aluminum wiring are sequentially stacked and formed. . A cross-sectional view in which the manufacturing steps described above are performed corresponds to FIG. Further, the method for manufacturing the layer above the first layer aluminum wiring is not the essence of the present invention, so the description and illustration thereof are omitted. In this specification, each contact is composed of a contact opening and a plug, and each plug is composed of doped polysilicon or W plug and a barrier metal.

  As described above, according to the first embodiment, first, in the step of forming the lower contact of the bit line direct contact and the storage node direct contact in the DRAM memory cell portion, the lower portion of the shared contact in the logic SRAM portion is formed. The contact is formed at the same time, and further, in the step of forming the contact above the bit line direct contact in the DRAM memory cell portion, the contact above the shared contact in the logic SRAM portion and the contact on the active region are simultaneously formed. Therefore, in a system LSI in which DRAM and SRAM are mixedly mounted, it is possible to simultaneously form an active region contact and a shared contact, and to suppress a junction leak failure and an increase in contact resistance. It says the effect can be obtained.

  According to the first embodiment, in the system LSI in which DRAM and SRAM are mixedly mounted, the active area contact and the shared contact can be formed at the same time. Therefore, the cell area of the logic SRAM section can be easily reduced. The effect that it can reduce is acquired.

  Further, according to the first embodiment, in the system LSI in which DRAM and SRAM are mixedly mounted, the shared contact and the active region contact in the logic SRAM portion are formed simultaneously with the step of forming the contact in the DRAM memory cell portion. Since it did in this way, since the mask used in a photolithography process does not increase, the effect of suppressing an increase in manufacturing cost and a manufacturing process is acquired.

  Embodiment 2. FIG. FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention, and is a cross-sectional view showing the manufacturing process of the DRAM memory cell portion and the logic SRAM portion. In FIG. 6, the same reference numerals as those in FIG. 43 is a doped polysilicon (first plug) embedded in a lower contact (fourth contact) of the upper contact in the active region composed of two upper and lower contacts in the logic SRAM portion, and 44 is a silicon in the logic SRAM portion. A nitride film (first insulating film, insulating film) 45 is a barrier metal formed on the side wall of the upper contact (fifth contact) of the upper contact in the active region composed of two upper and lower contacts in the logic SRAM portion, Reference numeral 46 denotes a W plug (second plug) embedded in the contact above the active region contact. The silicon nitride film 44 is a film deposited in the same process as the silicon nitride film 28. In the second embodiment, the process of removing the silicon nitride film 28 in the logic SRAM portion is omitted.

  Next, a manufacturing method will be described. The manufacturing method of the DRAM memory cell portion in the second embodiment is the same as that in the first embodiment, and thus the description thereof is omitted. In addition, the method of manufacturing the logic SRAM portion will be described only for the portions different from the first embodiment. In the step of etching the contact interlayer film 17 shown in FIG. 3, the contact opening 37 under the shared contact is formed, and at the same time, the contact on the active region in which the doped polysilicon 43 is embedded is formed. Next, doped polysilicon is deposited by, for example, LP-CVD and planarized to bury the doped polysilicon 18 to 20 and 43 in the opening of each contact. Next, silicon nitride films 28 and 44 are deposited by, for example, LP-CVD. Next, a step of forming a capacitor layer in the DRAM memory cell portion and a step of forming a contact interlayer film (second insulating film) 21 in the logic SRAM portion are performed.

  Next, in a photolithography process, a predetermined pattern is formed on the photoresist applied on the contact interlayer films 21 and 33, and then the silicon oxide film is processed by etching using, for example, an RIE apparatus. The etching process at this time is performed in two steps. First, in the first step, the silicon oxide film is processed under etching conditions that allow selective etching of the silicon nitride film. That is, in the logic SRAM portion, the contact interlayer film 21 is etched so that the etching stops at the silicon nitride film 44. Next, in the second step, the silicon nitride film is processed under etching conditions that allow selective etching of the doped polysilicon. That is, the silicon nitride film 44 of the logic SRAM portion is etched so that the doped polysilicon 18 and 43 are not etched. In addition, it is difficult to form a large opening for the contact in the contact on the active region embedded with the doped polysilicon 43 in consideration of alignment error and dimensional variation. In the first step, the contact interlayer film 21 is etched so that the etching stops at the silicon nitride film 44. Therefore, it is not necessary to form a large contact opening, and a borderless stacked contact structure is formed. Is possible. The contact on the gate also has a borderless stacked contact structure similar to the contact on the active region.

  As described above, according to the second embodiment, the same effects as those of the first embodiment are obtained, and first, the contact below the bit line direct contact and the storage node direct contact in the DRAM memory cell portion are formed. In the process, the lower contact of the shared contact in the logic SRAM portion and the lower contact of the active region contact are simultaneously formed, and further, in the step of forming the upper contact of the bit line direct contact in the DRAM memory cell portion, Since the upper contact of the shared contact and the upper contact of the active region contact are simultaneously formed in the SRAM portion, the aspect ratio of the active region contact is small in the etching process for forming the active region contact. Since that, there is an advantage that it is possible to easily form the active region on the contact.

  Further, according to the second embodiment, since the process of removing the silicon nitride film 28 in the logic SRAM portion is omitted, the manufacturing process is reduced as compared with the first embodiment. The effect that reduction and shortening of a manufacturing period can be acquired.

  Embodiment 3 FIG. FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the third embodiment of the present invention, and is a cross-sectional view showing the manufacturing process of the DRAM memory cell portion and the logic SRAM portion. In FIG. 7, the same reference numerals as those in FIG. 47 is a barrier metal formed on the side wall of the lower contact of the shared contact composed of two upper and lower contacts in the logic SRAM section, 48 is a W plug (first plug) embedded in the lower contact of the shared contact, 49 is a silicide layer formed on the source / drain diffusion layer 12 of the DRAM memory cell portion, 50 is a silicide layer formed on the gate electrode 7 of the DRAM memory cell portion, and 51 is an upper and lower contact in the DRAM memory cell portion. The barrier metal formed on the side wall of the lower contact in the bit line direct contact constituted by: 52 is a W plug (first plug) embedded in the lower contact in the bit line direct contact; 53 is the storage node direct contact Formed on the side wall Le, 54 is W plug buried in the storage node direct contact (first plug). Further, unlike the first embodiment, since the storage node direct contact is made of metal, the storage node electrode 30 is not formed of doped polysilicon, but is formed of, for example, a titanium nitride (TiN) film or a ruthenium (Ru) film. . For this reason, the capacitor of the DRAM memory cell portion has an MIM structure.

  Next, a manufacturing method will be described. The method of manufacturing the semiconductor device in the third embodiment will be described only for the parts different from the first embodiment. In the step of forming the silicide layer, the silicide layer is formed only in the logic SRAM portion in the first embodiment, but the silicide layer is formed in the logic SRAM portion and the DRAM memory cell portion in the third embodiment.

  Further, after the manufacturing process shown in FIG. 3 is performed, barrier metals 47, 51, and 53 are deposited and processed on the side walls of the contacts 37 to 39 using, for example, sputtering or CVD. Next, tungsten plugs 48, 52, and 54 are buried by depositing and planarizing tungsten, for example, by CVD. Next, a silicon nitride film 28 is formed in the DRAM memory cell portion, and then a step of forming a capacitor layer of the DRAM memory cell portion and a step of forming the contact interlayer film 21 of the logic SRAM portion are performed.

  Next, in the etching process for forming the contact openings 40 to 42 shown in FIG. 5, the second step processes the silicon nitride film under etching conditions that allow selective etching of tungsten. That is, the silicon nitride film 28 in the DRAM memory cell portion and the silicon nitride film 16 in the logic SRAM portion are etched so that the W plug 48 is not etched. The subsequent manufacturing method is the same as that of the first embodiment.

  As described above, according to the third embodiment, the same effects as those of the first embodiment can be obtained, and the W plugs 52 and 54 are connected to the lower contact of the bit line direct contact and the storage node direct contact in the DRAM memory cell portion. Since the W plug 48 can be formed in the contact below the shared contact in the logic SRAM portion, the effect that the contact resistance can be reduced is obtained.

  Embodiment 4 FIG. FIG. 8 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the fourth embodiment of the present invention, and is a cross-sectional view showing the manufacturing process of the DRAM memory cell portion and the logic SRAM portion. In FIG. 8, the same reference numerals as those in FIGS. 6 and 7 indicate the same or corresponding parts, and the description thereof is omitted. 55 is a barrier metal formed on the side wall of the lower contact of the upper contact in the active region composed of two upper and lower contacts in the logic SRAM portion, and 56 is a W plug embedded in the lower contact of the upper contact in the active region (first Plug).

  Next, a manufacturing method will be described. The method for manufacturing a semiconductor device in the fourth embodiment will be described only for parts different from the first to third embodiments. In the fourth embodiment, the following process is performed in place of the process of embedding doped polysilicon 43 shown in FIG. For example, the barrier metal 55 is deposited and processed using sputtering or CVD. Next, tungsten is deposited by, for example, CVD and planarized to bury the W plug 56. This step is performed simultaneously with the step of forming the barrier metals 47, 51, 53 and the W plugs 48, 52, 54. The subsequent manufacturing method is the same as that of the second embodiment.

  As described above, according to the fourth embodiment, the same effects as those of the first and second embodiments are obtained, and the lower contact of the bit line direct contact and the storage node direct contact in the DRAM memory cell portion are provided. Since the W plugs 52 and 54 are formed, the W plug 56 can be formed in the contact below the active region upper contact in the logic SRAM portion, so that an effect that the contact resistance can be reduced is obtained.

  The embodiment disclosed this time is an example, and the present invention is not limited to this. The present invention is defined by the terms of the claims, rather than the scope described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  DESCRIPTION OF SYMBOLS 1 Well part in silicon substrate, 2 Isolation oxide film, 3, 4 Gate oxide film, 5 Gate electrode, 6 Gate wiring (gate electrode), 7 Gate electrode, 8, 9, 10 Side wall, 11, 12 Diffusion layer, 13 Silicide layer (first silicide layer), 14 silicide layer, 15 silicide layer (second silicide layer), 16 silicon nitride film, 17 contact interlayer film (first contact layer), 18, 19, 20 doped poly Silicon (first plug), 21 contact interlayer film (second contact interlayer film, second insulating film), 22, 23, 24 barrier metal, 25, 26, 27 W plug (second plug), 28 Silicon nitride film (insulating film), 29 storage node interlayer film, 30 storage node electrode, 31 capacitor dielectric film, 32 cell plate Electrode, 33 contact interlayer film, 34 barrier metal, 35 aluminum wiring, 36 ARC film, 37 contact opening (contact hole), 38, 39, 40, 41, 42 contact opening, 43 doped polysilicon (first layer) 1 plug), 44 silicon nitride film (first insulating film, insulating film), 45 barrier metal, 46 W plug (second plug), 47, 51, 53 barrier metal, 48, 52, 54 W plug ( (First plug), 49, 50 silicide layer, 55 barrier metal, 56 W plug (first plug).

Claims (5)

A semiconductor device in which DRAM and SRAM are mounted together,
In a semiconductor substrate having a main surface, a first gate electrode formed in an SRAM formation region in which the SRAM is formed;
A first diffusion layer formed on a surface of the semiconductor substrate so as to be adjacent to the first gate electrode;
A first silicide layer formed on a surface of the first diffusion layer;
A second silicide layer formed on the surface of the first gate electrode;
A second gate electrode formed in a DRAM formation region in which the DRAM is formed in the semiconductor substrate;
A second diffusion layer and a third diffusion layer formed on the surface of the semiconductor substrate so as to sandwich the second gate electrode;
A first interlayer insulating film formed on the semiconductor substrate so as to cover the first gate electrode and the second gate electrode in the SRAM formation region and the DRAM formation region;
A second interlayer insulating film formed on the first interlayer insulating film;
A first wiring layer formed on the second interlayer insulating film;
The first silicide layer is formed so as to penetrate the first interlayer insulating film from the upper surface of the first interlayer insulating film located in the SRAM formation region, and electrically connects the first silicide layer and the second silicide layer. With shared contacts,
A first contact formed so as to penetrate the second interlayer insulating film from an upper surface of the second interlayer insulating film, and electrically connecting the first wiring layer and the shared contact;
A lower contact formed so as to penetrate through the first interlayer insulating film from an upper surface of the first interlayer insulating film located in the DRAM formation region, and electrically connecting the second diffusion layer and the bit line; ,
A storage node contact formed so as to penetrate the first interlayer insulating film from an upper surface of the first interlayer insulating film and electrically connected to the third diffusion layer;
A semiconductor device comprising: a capacitor formed on the first interlayer insulating film and in a region below the upper surface of the second interlayer insulating film and electrically connected to the storage node contact. A fourth diffusion layer formed at a distance from the first diffusion layer in the SRAM formation region;
A third silicide layer formed on the surface of the fourth diffusion layer;
A second contact formed so as to penetrate the first interlayer insulating film and the second interlayer insulating film and electrically connecting the third silicide layer and the first wiring layer;
The second contact is a stacked contact including a first plug formed so as to penetrate the first interlayer insulating film and a second plug formed so as to penetrate the second interlayer insulating film. The semiconductor device according to claim 1. A fourth silicide layer formed on the surface of the second diffusion layer;
A fifth silicide layer formed on the surface of the third diffusion layer;
A sixth silicide layer formed on the surface of the second gate electrode;
Each of the shared contact, the first contact, the lower contact, and the storage node contact is formed of a metal containing tungsten,
The storage node of the capacitor comprises metal;
The lower contact is electrically connected to the fourth silicide layer;
The semiconductor device according to claim 1, wherein the storage node contact is electrically connected to the fifth silicide layer. The second interlayer insulating film is
A first insulating film formed in contact with the surface of the first interlayer insulating film;
A second insulating film laminated on the first insulating film,
The semiconductor device according to claim 1, wherein the first insulating film and the second insulating film have different etching rates with respect to the same etching condition. The first insulating film is a silicon nitride film;
The semiconductor device according to claim 4, wherein the second insulating film is a silicon oxide film.

Images