JP2011049502A - Semiconductor device mounting structure and method of manufacturing semiconductor device - Google Patents

Semiconductor device mounting structure and method of manufacturing semiconductor device Download PDF

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JP2011049502A
JP2011049502A JP2009199005A JP2009199005A JP2011049502A JP 2011049502 A JP2011049502 A JP 2011049502A JP 2009199005 A JP2009199005 A JP 2009199005A JP 2009199005 A JP2009199005 A JP 2009199005A JP 2011049502 A JP2011049502 A JP 2011049502A
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semiconductor device
lsi
electronic component
underfill resin
substrate
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Japanese (ja)
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Kenji Fukuda
研二 福田
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NEC Corp
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NEC Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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Abstract

<P>PROBLEM TO BE SOLVED: To form an underfill material into an appropriate shape. <P>SOLUTION: A platy LSI (electronic component) 4 is mounted to a substrate 1 with bumps 5 therebetween. An underfill resin (underfill material) 3 which is filled between the LSI 4 and the substrate 1 is disposed to be larger than the LSI 4 and has a shape similar to the LSI 4 when it is seen in a plane view. In a filling area of the underfill resin 3, projections 2 are formed that project from the substrate 1. The filling area is located adjacent to corners 4a of the LSI 4 and farthest from the center of the LSI 4. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、アンダーフィル樹脂によって、はんだ付け部分を封止する半導体装置の実装構造および半導体装置の製造方法に関する。   The present invention relates to a mounting structure for a semiconductor device in which a soldered portion is sealed with an underfill resin and a method for manufacturing the semiconductor device.

従来より、電気的接続部分を樹脂封止した構造の半導体装置が使用されている。
例えば、図３（ａ）、（ｂ）に示すような、回路面に低誘電体膜２６を備えるＬＳＩ２４がはんだバンプ２５（図３（ｂ）参照）を介して基板２１に実装されて、アンダーフィル樹脂２３がはんだ付け部分に充填された半導体装置３０が使用されている。アンダーフィル樹脂２３がはんだ付け部に充填されることによって、はんだ付け部分を保護すると共に、はんだバンプ２５がＬＳＩ２４と基板２１との熱膨張差によって生じる熱応力で熱疲労破壊するのを防止している。
また、特許文献１には、センサーチップの表面上にわずかな隙間を残してダム梁を配置し、ダム梁から電極形成領域側を樹脂封止する構造の半導体装置が開示されている。センサーチップの表面とダム梁との間の隙間は、封止用樹脂が流れ込む寸法であると共に、ダム梁とセンサーチップの表面との表面張力によりダム梁より先方へはみ出さない寸法に設置されている。 Conventionally, a semiconductor device having a structure in which an electrical connection portion is sealed with a resin has been used.
For example, as shown in FIGS. 3A and 3B, an LSI 24 having a low dielectric film 26 on the circuit surface is mounted on a substrate 21 via solder bumps 25 (see FIG. A semiconductor device 30 in which a fill resin 23 is filled in a soldered portion is used. By filling the soldering portion with the underfill resin 23, the soldering portion is protected, and the solder bump 25 is prevented from being damaged by thermal fatigue due to the thermal stress generated by the thermal expansion difference between the LSI 24 and the substrate 21. Yes.
Patent Document 1 discloses a semiconductor device having a structure in which a dam beam is disposed on the surface of a sensor chip while leaving a slight gap, and the electrode forming region side is sealed with resin from the dam beam. The gap between the surface of the sensor chip and the dam beam is the dimension that the sealing resin flows in, and the dimension that does not protrude beyond the dam beam due to the surface tension between the dam beam and the surface of the sensor chip. Yes.

特開２００８−２１１１２４号公報JP 2008-2111124 A

しかしながら、従来の半導体装置の実装構造では以下のような問題があった。
図３（ａ）、（ｂ）に示すような半導体装置３０では、アンダーフィル樹脂２３が低誘電体膜２６の側部を覆う構成であるが、製造工程において液状のアンダーフィル樹脂１３をはんだ付け部に充填した後に、加熱により硬化させているため、充填される液状のアンダーフィル樹脂１３の充填量が少ないと、ＬＳＩ１４のコーナー部１４ａにアンダーフィル樹脂１３が十分に行きわたらず、図４（ａ）、（ｂ）に示すように、ＬＳＩ２４のコーナー部２４ａで低誘電体膜２６がアンダーフィル樹脂２３に覆われず露出してしまう。そして、この状態でアンダーフィル樹脂２３を加熱し硬化させると、温度サイクル試験の低温時にアンダーフィル樹脂２３が熱収縮して低誘電体膜２６に応力が集中してしまい、低誘電体膜２６が剥離してしまうことがあった。 However, the conventional semiconductor device mounting structure has the following problems.
In the semiconductor device 30 as shown in FIGS. 3A and 3B, the underfill resin 23 covers the side portion of the low dielectric film 26, but the liquid underfill resin 13 is soldered in the manufacturing process. Since the underfill resin 13 is hardened by heating after filling the portion, if the filling amount of the liquid underfill resin 13 to be filled is small, the underfill resin 13 does not sufficiently reach the corner portion 14a of the LSI 14, and FIG. As shown in a) and (b), the low dielectric film 26 is not covered with the underfill resin 23 and exposed at the corner 24a of the LSI 24. When the underfill resin 23 is heated and cured in this state, the underfill resin 23 is thermally contracted at a low temperature in the temperature cycle test, and stress is concentrated on the low dielectric film 26. It sometimes peeled off.

また、製造工程において、充填される液状のアンダーフィル樹脂２３の充填量が多いとＬＳＩ２４のコーナー部２４ａにアンダーフィル樹脂２３が行きわたるが、図５（ａ）、（ｂ）に示すように、ＬＳＩ２４の外縁部で隣り合うコーナー部２４ａとの中間に位置する中央部２４ｂでアンダーフィル樹脂２３がＬＳＩ２４の上部まで達している。そして、この状態でアンダーフィル樹脂２３を加熱し硬化させると、温度サイクル試験の低温時にアンダーフィル樹脂２３が熱収縮してＬＳＩ２４上部のエッジに応力が集中してしまい、ＬＳＩ２４の側壁にクラックが生じてしまうことがあった。
このように、アンダーフィル樹脂２３の形状が適切でないことにより半導体装置３０の信頼性が低下してしまうという問題があった。
このため、アンダーフィル樹脂の量を厳密に調節する必要があった。 Further, in the manufacturing process, when the filling amount of the liquid underfill resin 23 to be filled is large, the underfill resin 23 reaches the corner portion 24a of the LSI 24. As shown in FIGS. 5A and 5B, The underfill resin 23 reaches the upper part of the LSI 24 at the central portion 24b located in the middle of the corner portion 24a adjacent to the outer edge portion of the LSI 24. If the underfill resin 23 is heated and cured in this state, the underfill resin 23 is thermally contracted at a low temperature in the temperature cycle test, and stress is concentrated on the upper edge of the LSI 24, and a crack is generated on the side wall of the LSI 24. There was a case.
As described above, there is a problem that the reliability of the semiconductor device 30 is lowered because the shape of the underfill resin 23 is not appropriate.
For this reason, it was necessary to strictly adjust the amount of the underfill resin.

本発明は、上述する問題点に鑑みてなされたもので、容易にアンダーフィル材を適切な形状に形成することができる半導体装置の実装構造を提供することを目的とする。   The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a semiconductor device mounting structure in which an underfill material can be easily formed into an appropriate shape.

上記目的を達成するため、本発明に係る半導体装置の実装構造は、板状の電子部品がはんだバンプを介して基板に実装され、前記電子部品と前記基板との間に充填されるアンダーフィル材が平面視にて前記電子部品よりも大きく前記電子部品と相似の形状に配される半導体装置の実装構造であって、前記電子部品の中心から最も離れた位置に相当する前記アンダーフィル材充填領域に、前記基板から突出する突起部を設けたことを特徴とする。
また、本発明に係る半導体装置の製造方法では、前記半導体装置で用いられる前記基板上に前記電子部品をはんだリフローによってはんだ付けする工程と、該はんだ付けされた電子部品と前記基板との間に前記アンダーフィル材を充填する工程とを有することを特長とする。 In order to achieve the above object, a mounting structure of a semiconductor device according to the present invention includes an underfill material in which a plate-like electronic component is mounted on a substrate via solder bumps and is filled between the electronic component and the substrate. Is a mounting structure of a semiconductor device that is larger than the electronic component in a plan view and arranged in a shape similar to the electronic component, and the underfill material filling region corresponding to a position farthest from the center of the electronic component Further, a protrusion protruding from the substrate is provided.
Further, in the method for manufacturing a semiconductor device according to the present invention, the step of soldering the electronic component onto the substrate used in the semiconductor device by solder reflow, and between the soldered electronic component and the substrate And a step of filling the underfill material.

本発明によれば、基板上の電子部品の中心から最も離れた位置に相当するアンダーフィル材充填領域には、基板から突出する突起部が設けられているので、電子部品の外縁部と突起部との間に配されたアンダーフィル材の表面張力により、アンダーフィル材が充填されにくい電子部品の中心から最も離れた位置の電子部品の回路面およびその側部をアンダーフィル材で覆うことができる。そして、電子部品の回路面はアンダーフィル材で覆われているので、温度サイクル試験の低温時にアンダーフィル材の熱収縮により電子部品の回路面にかかる応力で回路面が剥離することを防ぐことができる。
また、表面張力により電子部品の回路面をアンダーフィル材で覆うことができるので、アンダーフィル材を過多に充填する必要がない。そして、アンダーフィル材が過多に充填されないので、温度サイクル試験の低温時にアンダーフィル材の熱収縮により電子部品にかかる応力を低減させることができて、電子部品にクラックが生じることを防ぐことができる。
そして、アンダーフィル材を最適な形状に充填することで、半導体装置の信頼性を高めると共に安定させることができる。 According to the present invention, since the underfill material filling region corresponding to the position farthest from the center of the electronic component on the substrate is provided with the protruding portion protruding from the substrate, the outer edge portion and the protruding portion of the electronic component are provided. The surface of the electronic component located farthest from the center of the electronic component that is difficult to be filled with the underfill material and the side portion thereof can be covered with the underfill material due to the surface tension of the underfill material arranged between . Since the circuit surface of the electronic component is covered with the underfill material, it is possible to prevent the circuit surface from being peeled off due to the stress applied to the circuit surface of the electronic component due to the thermal contraction of the underfill material at the low temperature of the temperature cycle test. it can.
Further, since the circuit surface of the electronic component can be covered with the underfill material by the surface tension, it is not necessary to fill the underfill material excessively. And since the underfill material is not filled excessively, the stress applied to the electronic component due to the thermal contraction of the underfill material can be reduced at the low temperature of the temperature cycle test, and the electronic component can be prevented from cracking. .
Then, by filling the underfill material into an optimum shape, the reliability of the semiconductor device can be improved and stabilized.

（ａ）は本発明の第一の実施の形態による半導体装置の実装構造の一例を示す図、（ｂ）は（ａ）のＡ−Ａ線断面図である。(A) is a figure which shows an example of the mounting structure of the semiconductor device by 1st embodiment of this invention, (b) is the sectional view on the AA line of (a). （ａ）は本発明の第二の実施の形態による半導体装置の実装構造の一例を示す図、（ｂ）は（ａ）のＢ−Ｂ線断面図である。(A) is a figure which shows an example of the mounting structure of the semiconductor device by 2nd embodiment of this invention, (b) is the BB sectional drawing of (a). （ａ）は従来の半導体装置の実装構造の一例を示す図、（ｂ）は（ａ）のＣ−Ｃ線断面図である。(A) is a figure which shows an example of the mounting structure of the conventional semiconductor device, (b) is CC sectional view taken on the line of (a). （ａ）は従来の他の半導体装置の実装構造の一例を示す図、（ｂ）は（ａ）のＤ−Ｄ線断面図である。(A) is a figure which shows an example of the mounting structure of the other conventional semiconductor device, (b) is the DD sectional view taken on the line of (a). （ａ）は従来の更に他の半導体装置の実装構造の一例を示す図、（ｂ）は（ａ）のＥ−Ｅ線断面図である。(A) is a figure which shows an example of the mounting structure of the further another conventional semiconductor device, (b) is the EE sectional view taken on the line of (a). 図５に示す従来の半導体装置と比べてアンダーフィル樹脂が少ない従来の半導体装置に応力のシミュレーションを行いその結果を示す図である。FIG. 6 is a diagram illustrating a result of stress simulation performed on a conventional semiconductor device with less underfill resin compared to the conventional semiconductor device illustrated in FIG. 5. 図５に示す従来の半導体装置に応力のシミュレーションを行いその結果を示す図である。FIG. 6 is a diagram illustrating a result of stress simulation performed on the conventional semiconductor device illustrated in FIG. 5. 図６および図７に示す結果をまとめた図である。It is the figure which put together the result shown in FIG. 6 and FIG.

以下、本発明の第一の実施の形態による半導体装置の実装構造について、図１（ａ）、（ｂ）に基づいて説明する。
図１（ａ）、（ｂ）に示すように、本実施の形態による半導体装置１０は、基板１上にＬＳＩ（電子部品）４がはんだバンプ５（図１（ｂ）参照）によってはんだ付けされているフリップチップ実装構造の半導体装置である。
ＬＳＩ４は、回路面に低誘電体膜６を備えている。この低誘電体膜６と基板１との間のはんだ付け部分はアンダーフィル樹脂（アンダーフィル材）３によって封止されている。アンダーフィル樹脂３は低誘電体膜６の側部６ａも覆っている。 Hereinafter, a semiconductor device mounting structure according to the first embodiment of the present invention will be described with reference to FIGS.
As shown in FIGS. 1A and 1B, in the semiconductor device 10 according to the present embodiment, an LSI (electronic component) 4 is soldered on a substrate 1 by solder bumps 5 (see FIG. 1B). The semiconductor device has a flip chip mounting structure.
The LSI 4 includes a low dielectric film 6 on the circuit surface. The soldered portion between the low dielectric film 6 and the substrate 1 is sealed with an underfill resin (underfill material) 3. The underfill resin 3 also covers the side portion 6 a of the low dielectric film 6.

ＬＳＩ４は平面視略長方形の板状に形成されていて、基板１とＬＳＩ４との間のはんだ付け部分とその周囲にアンダーフィル樹脂３が配設されている。アンダーフィル樹脂３の外形はＬＳＩ４の外形よりも大きい平面視略長方形状となる。
アンダーフィル樹脂３には、エポキシ樹脂やポリイミド樹脂、アクリル樹脂などからなる熱硬化性の接着剤を使用する。
基板１には、ＬＳＩ４の各コーナー部４ａから所定の間隔をあけた位置に基板１から突出する円柱状の突起部２が配設されている。 The LSI 4 is formed in a substantially rectangular plate shape in plan view, and an underfill resin 3 is disposed around and around the soldered portion between the substrate 1 and the LSI 4. The external shape of the underfill resin 3 is substantially rectangular in plan view, which is larger than the external shape of the LSI 4.
For the underfill resin 3, a thermosetting adhesive made of epoxy resin, polyimide resin, acrylic resin, or the like is used.
The substrate 1 is provided with columnar protrusions 2 protruding from the substrate 1 at positions spaced apart from the respective corner portions 4 a of the LSI 4.

突起部２はアンダーフィル樹脂３の外縁部の位置に配設されていて、ＬＳＩ４のコーナー部４ａと突起部２との間には、アンダーフィル樹脂３が充填されている。突起部２は、ＬＳＩ４の外縁部上で隣り合うコーナー部４ａとの中間に位置する中央部４ｂと比べコーナー部４ａと近い位置に配設されている。突起部２は、その高さが充填されるアンダーフィル樹脂３の厚さよりも高くなるように形成されている。   The protrusion 2 is disposed at the position of the outer edge of the underfill resin 3, and the underfill resin 3 is filled between the corner 4 a of the LSI 4 and the protrusion 2. The protruding portion 2 is disposed at a position closer to the corner portion 4a than the central portion 4b located in the middle of the adjacent corner portion 4a on the outer edge portion of the LSI 4. The protrusion 2 is formed so that its height is higher than the thickness of the underfill resin 3 to be filled.

突起部２は、金属端子を有するはんだ付け可能な部材で、はんだ付けによって基板１に形成されてもよい。また、突起部２は、基板１を貫通する孔に基板１の裏面から挿入されて先端部が突出したボルトとしてもよい。また、突起部２は、金属部材でなく、樹脂を含む材料を基板１上に配設して硬化させた樹脂部材としてもよい。
なお、突起部２の形状は円柱に限られることはなく、例えば、三角柱や四角柱などの多角柱や、円錐、円錐台などの他の形状としてもよい。 The protrusion 2 is a solderable member having a metal terminal, and may be formed on the substrate 1 by soldering. Further, the protrusion 2 may be a bolt that is inserted from a back surface of the substrate 1 into a hole penetrating the substrate 1 and has a tip portion protruding. Further, the protruding portion 2 may be a resin member that is not a metal member but a resin-containing material disposed on the substrate 1 and cured.
In addition, the shape of the protrusion part 2 is not restricted to a cylinder, For example, it is good also as other shapes, such as polygonal pillars, such as a triangular prism and a quadratic prism, a cone, and a truncated cone.

次に、本実施の形態による半導体装置の製造方法について説明する。
まず、ＬＳＩ４の回路面である低誘電体膜６の表面にはんだバンプ５を形成し、回路面を基板１側に向けて設置して、はんだリフローによりＬＳＩ４を基板１に実装する。
この基板１へのＬＳＩ４の実装と前後して、突起部２を形成する。突起部２は、金属端子を有する部材としてこれを基板１にはんだ付けによって設置したり、ボルトとして基板１に形成された貫通孔に基板１の裏面からこのボルトを挿入したりして形成する。
また、突起部２は、樹脂を含む材料を基板１上に配設して硬化させて形成してもよい。 Next, a method for manufacturing the semiconductor device according to the present embodiment will be described.
First, the solder bumps 5 are formed on the surface of the low dielectric film 6 that is the circuit surface of the LSI 4, the circuit surface is placed toward the substrate 1, and the LSI 4 is mounted on the substrate 1 by solder reflow.
The protrusion 2 is formed before and after mounting the LSI 4 on the substrate 1. The protrusion 2 is formed as a member having a metal terminal by soldering to the substrate 1 or by inserting the bolt from the back surface of the substrate 1 into a through hole formed in the substrate 1 as a bolt.
The protrusion 2 may be formed by disposing a resin-containing material on the substrate 1 and curing it.

次に、アンダーフィル樹脂３の充填を行う。
アンダーフィル樹脂３は、ＬＳＩ４の周囲から低誘電体膜６と基板１との間のはんだ付け部分に充填する。アンダーフィル樹脂３は、最初は液状で流動性を持つため、ＬＳＩ４と基板１との間に流入する。隣り合うはんだバンプ５間にもアンダーフィル樹脂３を充填する。
そして、ＬＳＩ４と基板１との間にアンダーフィル樹脂３が充填され、アンダーフィル樹脂３がＬＳＩ４のコーナー部４ａの低誘電体膜６の側部６ａと突起部２の側面２ａの下部側とに接触すると、アンダーフィル樹脂３は表面張力により、突起部２の表面を伝って上部に吸いあがるように動き、突起部２の周囲にアンダーフィル樹脂３が集まろうとする。この表面張力により多くのアンダーフィル樹脂３が突起部２側に引っ張られて、ＬＳＩ４のコーナー部４ａに集まり、コーナー部４ａの低誘電体膜６の側部６ａはアンダーフィル樹脂３に覆われることになる。このとき、アンダーフィル樹脂３は低誘電体膜６の側部６ａを覆い、ＬＳＩ４側部の高さ方向の中央付近の高さに供給されることが好ましい。 Next, the underfill resin 3 is filled.
The underfill resin 3 fills a soldered portion between the low dielectric film 6 and the substrate 1 from around the LSI 4. Since the underfill resin 3 is initially liquid and fluid, it flows between the LSI 4 and the substrate 1. Underfill resin 3 is filled between adjacent solder bumps 5.
The underfill resin 3 is filled between the LSI 4 and the substrate 1, and the underfill resin 3 is applied to the side 6 a of the low dielectric film 6 at the corner 4 a of the LSI 4 and the lower side of the side 2 a of the protrusion 2. When contacted, the underfill resin 3 moves so as to be sucked upward along the surface of the protrusion 2 due to surface tension, and the underfill resin 3 tries to gather around the protrusion 2. Due to this surface tension, a large amount of underfill resin 3 is pulled toward the protruding portion 2 side and gathers at the corner portion 4a of the LSI 4, and the side portion 6a of the low dielectric film 6 of the corner portion 4a is covered with the underfill resin 3. become. At this time, the underfill resin 3 preferably covers the side 6a of the low dielectric film 6 and is supplied to a height near the center of the side of the LSI 4 in the height direction.

次に、はんだ付け部分とその周囲に配設された液状のアンダーフィル樹脂３を高温に加熱し硬化させる。アンダーフィル樹脂３が硬化することによって、はんだ付け部分が樹脂封止される。そして、常温となった後に、温度サイクル試験を行い、半導体装置１０の接続信頼性評価を行う。   Next, the soldered portion and the liquid underfill resin 3 disposed around the soldered portion are heated to a high temperature and cured. When the underfill resin 3 is cured, the soldered portion is resin-sealed. Then, after reaching room temperature, a temperature cycle test is performed to evaluate the connection reliability of the semiconductor device 10.

次に、上述した第一の実施の形態による半導体装置の実装構造の作用について説明する。
本実施の形態による半導体装置の実装構造では、突起部２とＬＳＩ４のコーナー部４ａとの表面張力により、ＬＳＩ４の中心から離れていてアンダーフィル樹脂３が行きわたりにくいＬＳＩ４のコーナー部４ａの低誘電体膜６の側部６ａに十分なアンダーフィル樹脂３を供給できることにより、温度サイクル試験の低温時にアンダーフィル樹脂３の熱収縮による応力がＬＳＩ４のコーナー部４ａの低誘電体膜１６に集中することがなく、低誘電体膜６がＬＳＩ４から剥離することを防止できる。
また、アンダーフィル樹脂３は、突起部２とＬＳＩ４のコーナー部４ａとの表面張力によりＬＳＩ４のコーナー部４ａに集まるので、アンダーフィル樹脂３を過多に供給する必要がない。 Next, the operation of the semiconductor device mounting structure according to the first embodiment will be described.
In the semiconductor device mounting structure according to the present embodiment, due to the surface tension between the protrusion 2 and the corner 4a of the LSI 4, the low dielectric of the corner 4a of the LSI 4 that is far from the center of the LSI 4 and the underfill resin 3 is difficult to reach. Since sufficient underfill resin 3 can be supplied to the side portion 6a of the body film 6, stress due to thermal contraction of the underfill resin 3 is concentrated on the low dielectric film 16 at the corner portion 4a of the LSI 4 at a low temperature in the temperature cycle test. Therefore, it is possible to prevent the low dielectric film 6 from peeling from the LSI 4.
Further, since the underfill resin 3 gathers at the corner portion 4a of the LSI 4 due to the surface tension between the protrusion 2 and the corner portion 4a of the LSI 4, it is not necessary to supply the underfill resin 3 excessively.

そして、アンダーフィル樹脂３が過多に供給されないことにより、ＬＳＩ４の中央部４ｂでアンダーフィル樹脂３が上部まで達することがないので、温度サイクル試験の低温時にアンダーフィル樹脂３の熱収縮による応力がＬＳＩ４の上部のエッジに集中することがなく、ＬＳＩ４の側部にクラックが生じることを防止できる。
また、アンダーフィル樹脂３の充填量は、コーナー部４ａの低誘電体膜６の側部６ａを覆うことができる量に設定する必要があるが、厳密にコントロールする必要がないので、製造工程における管理が容易となる。 Since the underfill resin 3 is not supplied excessively, the underfill resin 3 does not reach the upper part at the central portion 4b of the LSI 4, so that the stress due to the thermal contraction of the underfill resin 3 is low when the temperature cycle test is performed at a low temperature. It is possible to prevent the LSI 4 from cracking without concentrating on the upper edge.
In addition, the filling amount of the underfill resin 3 needs to be set to an amount that can cover the side portion 6a of the low dielectric film 6 of the corner portion 4a. Management becomes easy.

第一の実施の形態による半導体装置の実装構造では、アンダーフィル樹脂３を最適な形状に充填できることにより、温度サイクル試験の低温時にＬＳＩ４に作用する応力を軽減することができるので、半導体装置１０の信頼性を高めると共に安定させることができる効果を奏する。   In the mounting structure of the semiconductor device according to the first embodiment, since the underfill resin 3 can be filled into an optimal shape, the stress acting on the LSI 4 at the low temperature of the temperature cycle test can be reduced. There is an effect that the reliability can be enhanced and stabilized.

ここで、図５（ａ）、（ｂ）に示す従来の半導体装置３０のＬＳＩ２４に作用するの応力のシミュレーションを行った。このシミュレーションは、図５（ｂ）の点線で示す形状のアンダーフィル樹脂２３ａを備える半導体装置３０ａと実線で示す形状のアンダーフィル樹脂２３ｂを備える半導体装置３０ｂに行った。
半導体装置３０ａは、半導体装置３０ｂと比べてアンダーフィル樹脂量が多く、ＬＳＩ２４の中央部２４ｂでアンダーフィル樹脂２３はＬＳＩ２４の上部に達している。
半導体装置３０ｂでは、半導体装置３０ａと比べてアンダーフィル樹脂量が少なく、ＬＳＩ２４の中央部２４ｂではアンダーフィル樹脂２３がＬＳＩ２３の上部に達している。 Here, simulation of stress acting on the LSI 24 of the conventional semiconductor device 30 shown in FIGS. 5A and 5B was performed. This simulation was performed on the semiconductor device 30a including the underfill resin 23a having the shape indicated by the dotted line in FIG. 5B and the semiconductor device 30b including the underfill resin 23b having the shape indicated by the solid line.
The semiconductor device 30 a has a larger amount of underfill resin than the semiconductor device 30 b, and the underfill resin 23 reaches the upper portion of the LSI 24 at the central portion 24 b of the LSI 24.
The semiconductor device 30 b has a smaller amount of underfill resin than the semiconductor device 30 a, and the underfill resin 23 reaches the upper portion of the LSI 23 in the central portion 24 b of the LSI 24.

図６乃至図８より、半導体装置３０ａ、半導体装置３０ｂ共に、アンダーフィル樹脂２３ａ２３ｂがＬＳＩ２４の上部まで達しているが、相対的にアンダーフィル樹脂２３が少ない半導体装置３０ａのほうが、相対的にアンダーフィル樹脂２３が多い半導体装置３０ｂよりも、温度サイクル試験の低温時にアンダーフィル樹脂２３の熱収縮によりＬＳＩ２４の上部のエッジにかかる応力を４３％低減できることがわかり、ＬＳＩ２４の側壁にクラックが生じることを防ぐことができる。   6 to 8, in both the semiconductor device 30a and the semiconductor device 30b, the underfill resin 23a23b reaches the upper part of the LSI 24. However, the semiconductor device 30a with relatively less underfill resin 23 has a relatively lower underfill. It can be seen that the stress applied to the upper edge of the LSI 24 can be reduced by 43% due to the thermal contraction of the underfill resin 23 when the temperature cycle test is performed at a low temperature, as compared with the semiconductor device 30b having a large amount of the resin 23. be able to.

また、図３に示すようなＬＳＩ２４のコーナー部２４ａで低誘電体膜２６の側部２６ａがアンダーフィル樹脂２３に覆われている半導体装置３０ｃと、図４に示すようなアンダーフィル樹脂２３が半導体装置３０ｃのアンダーフィル樹脂２３と比べて相対的に少なく、ＬＳＩ２４のコーナー部２４ａで低誘電体膜２６の側部２６ａが露出する半導体装置３０ｄに応力シミュレーションを行った。その結果、図８に示すように、アンダーフィル樹脂２３が少なく低誘電体膜２６の側部２６ａが露出している半導体装置３０ｄでは、温度サイクル試験の低温時にアンダーフィル樹脂２３の熱収縮により低誘電体膜２６にかかる応力が高く、アンダーフィル樹脂２３が低誘電体膜２６の側部２６ａを覆っている半導体装置３０ｃのほうが低誘電体膜２６の剥離を防止することができる。   Further, the semiconductor device 30c in which the side portion 26a of the low dielectric film 26 is covered with the underfill resin 23 at the corner portion 24a of the LSI 24 as shown in FIG. 3, and the underfill resin 23 as shown in FIG. A stress simulation was performed on the semiconductor device 30d in which the side portion 26a of the low dielectric film 26 is exposed at the corner portion 24a of the LSI 24, which is relatively less than the underfill resin 23 of the device 30c. As a result, as shown in FIG. 8, in the semiconductor device 30 d in which the underfill resin 23 is small and the side portion 26 a of the low dielectric film 26 is exposed, the low temperature due to the thermal contraction of the underfill resin 23 at the low temperature of the temperature cycle test. The semiconductor device 30c in which the stress applied to the dielectric film 26 is high and the underfill resin 23 covers the side portion 26a of the low dielectric film 26 can prevent the low dielectric film 26 from peeling off.

次に、他の実施の形態について、添付図面に基づいて説明するが、上述の第一の実施の形態と同一又は同様な部材、部分には同一の符号を用いて説明を省略し、第一の実施の形態と異なる構成について説明する。
図２に示すように、第二の実施の形態による半導体装置の実装構造によれば、半導体装置２０には、ＬＳＩ４の各コーナー部４ａに対して２つの突起部２が設置されている。 Next, other embodiments will be described with reference to the accompanying drawings. However, the same or similar members and parts as those of the above-described first embodiment are denoted by the same reference numerals, and description thereof is omitted. A configuration different from the embodiment will be described.
As shown in FIG. 2, according to the mounting structure of the semiconductor device according to the second embodiment, the semiconductor device 20 is provided with two protrusions 2 for each corner 4 a of the LSI 4.

第二の実施の形態によれば、突起部１２が１つのコーナー部４ａに対して複数設置されていることにより、複数の突起部１２の間にもアンダーフィル樹脂３が毛細管現象により流入し複数の突起部２間でも表面張力が生じるので、第一の実施の形態と比べて表面張力が大きくなりコーナー部４ａへのアンダーフィル樹脂３の流入が大きくなるという効果が得られる。   According to the second embodiment, since a plurality of protrusions 12 are provided for one corner 4a, the underfill resin 3 flows between the plurality of protrusions 12 due to capillary action. Since surface tension is also generated between the protrusions 2, the surface tension is increased as compared with the first embodiment, and the inflow of the underfill resin 3 to the corner portion 4 a is obtained.

以上、本発明による半導体装置の実装構造の実施の形態について説明したが、本発明は上記の実施の形態に限定されるものではなく、その趣旨を逸脱しない範囲で適宜変更可能である。
例えば、上述した実施の形態では、ＬＳＩ４は回路面に低誘電体膜６を備えているが、その他の誘電体を備えるＬＳＩとしてもよい。
また、例えば、上記の実施の形態ではＬＳＩ４は平面視略長方形であるが、それ以外の平面視多角形でもよく、また、ＬＳＩが多角形とこの多角形から突出する凸部とからなる場合には、この凸部に近接して突起部２を設けてもよい。
また、例えば、上記の実施の形態では、アンダーフィル樹脂３ではんだ付け部分を封止しているが、アンダーフィル樹脂３以外のアンダーフィル材を使用してもよい。
また、例えば、上記の第二の実施の形態では、ＬＳＩ４の各コーナー部４ａに対して突起部１２が２つずつ配設されているが、３つ以上としてもよい。 Although the embodiments of the semiconductor device mounting structure according to the present invention have been described above, the present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the scope of the present invention.
For example, in the embodiment described above, the LSI 4 includes the low dielectric film 6 on the circuit surface, but may be an LSI including other dielectrics.
Further, for example, in the above-described embodiment, the LSI 4 is substantially rectangular in plan view, but may be other polygons in plan view, or when the LSI includes a polygon and a convex portion protruding from the polygon. May be provided with a protrusion 2 in the vicinity of the protrusion.
For example, in the above embodiment, the soldered portion is sealed with the underfill resin 3, but an underfill material other than the underfill resin 3 may be used.
Further, for example, in the second embodiment described above, two protrusions 12 are provided for each corner 4a of the LSI 4, but three or more may be provided.

１ 基板
２、１２ 突起部
３ アンダーフィル樹脂（アンダーフィル材）
４ ＬＳＩ（電子部品）
４ａ コーナー部
５ はんだバンプ
１０、２０ 半導体装置 1 Substrate 2, 12 Protrusion 3 Underfill resin (underfill material)
4 LSI (electronic parts)
4a Corner 5 Solder bump 10, 20 Semiconductor device

Claims (5)

板状の電子部品がはんだバンプを介して基板に実装され、前記電子部品と前記基板との間に充填されるアンダーフィル材が平面視にて前記電子部品よりも大きく前記電子部品と略相似の形状に配される半導体装置の実装構造であって、
前記電子部品の中心から最も離れた位置に相当する前記アンダーフィル材充填領域に、前記基板から突出する突起部を設けたことを特徴とする半導体装置の実装構造。 A plate-shaped electronic component is mounted on a substrate via a solder bump, and an underfill material filled between the electronic component and the substrate is larger than the electronic component in a plan view and substantially similar to the electronic component. A mounting structure of a semiconductor device arranged in a shape,
A mounting structure of a semiconductor device, wherein a protrusion protruding from the substrate is provided in the underfill material filling region corresponding to a position farthest from the center of the electronic component. 前記電子部品の中心から最も離れた位置に相当する前記アンダーフィル材充填領域には、前記アンダーフィル充填領域を挟むあるいは囲むように前記突起部が複数設けられていることを特徴とする請求項１に記載の半導体装置の実装構造。   2. The underfill material filling region corresponding to a position farthest from the center of the electronic component is provided with a plurality of projections so as to sandwich or surround the underfill filling region. 2. A mounting structure of the semiconductor device according to 1. 前記電子部品は平面視多角形の板状であると共に、前記アンダーフィル材充填領域は平面視にて前記電子部品と略相似の多角形であって、前記突起部は前記アンダーフィル材充填領域の前記多角形の頂点に各々設けられていることを特徴とする請求項１または２に記載の半導体装置の実装構造。   The electronic component has a plate shape with a polygonal shape in a plan view, and the underfill material filling region is a polygon that is substantially similar to the electronic component in a plan view, and the protruding portion is a portion of the underfill material filling region. The semiconductor device mounting structure according to claim 1, wherein the semiconductor device mounting structure is provided at each vertex of the polygon. 前記アンダーフィル材は樹脂を含む材料で形成されていることを特徴とする請求項１乃至３のいずれかに記載の半導体装置の実装構造。   The semiconductor device mounting structure according to claim 1, wherein the underfill material is formed of a material containing a resin. 請求項１で用いられる前記基板上に前記電子部品をはんだリフローによってはんだ付けする工程と、
該はんだ付けされた電子部品と前記基板との間に前記アンダーフィル材を充填する工程とを有することを特長とする半導体装置の製造方法。 Soldering the electronic component on the substrate used in claim 1 by solder reflow;
And a step of filling the underfill material between the soldered electronic component and the substrate.
JP2009199005A 2009-08-28 2009-08-28 Semiconductor device mounting structure and method of manufacturing semiconductor device Pending JP2011049502A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013062472A (en) * 2011-09-15 2013-04-04 Toppan Printing Co Ltd Semiconductor package and manufacturing method of the same
WO2014103133A1 (en) 2012-12-28 2014-07-03 富士電機株式会社 Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013062472A (en) * 2011-09-15 2013-04-04 Toppan Printing Co Ltd Semiconductor package and manufacturing method of the same
WO2014103133A1 (en) 2012-12-28 2014-07-03 富士電機株式会社 Semiconductor device
US9852968B2 (en) 2012-12-28 2017-12-26 Fuji Electric Co., Ltd. Semiconductor device including a sealing region

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