JP2011018832A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device allowing a Cu wire to be mounted on a Cu wiring layer.SOLUTION: The semiconductor device includes: a protective layer 6 formed on a silicon substrate 1; a Cu wiring layer 9 formed on the protective layer 6 and electrically connected to a semiconductor element formed on the silicon substrate 1; a resin film 10 covering the Cu wiring layer 9 and formed on the protective layer 6; a pad electrode 12 connected to the Cu wiring layer 9 through an opening region 11 formed on the resin film 10; and a Cu wire 14 wire-bonded onto the pad electrode 12, wherein an alloy layer 13 is arranged between the Cu wire 14 and the Cu wiring layer 9.

Description

  The present invention relates to a semiconductor device in which an alloy layer is formed between a copper wiring layer and a pad electrode to improve the bonding strength between the copper wire and the pad electrode, and a method for manufacturing the same.

  As an example of a conventional method for manufacturing a semiconductor device, a manufacturing method shown in FIGS. 11A to 11D is known. 11A to 11D are cross-sectional views illustrating a conventional method for manufacturing a semiconductor device.

  First, as shown in FIG. 11A, an interlayer insulating film 32 such as a silicon oxide film is formed on the upper surface of the silicon substrate 31 by, eg, CVD. Next, for example, a trench 33 is formed in the interlayer insulating film 32 by a damascene method, and the inside of the trench 33 is buried with a barrier metal film 34 and a Cu wiring layer 35.

  Next, as shown in FIG. 11B, a barrier metal film 36 is formed on the entire surface of the interlayer insulating film 32 by, eg, sputtering. Then, the barrier metal film 36 is selectively processed so as to cover the upper surface of the Cu wiring layer 35 in the groove 33.

  Next, as shown in FIG. 11C, an SiN film 37 is formed on the entire surface of the interlayer insulating film 32, and an opening 38 is formed in the SiN film 37 so that the barrier metal film 36 is exposed.

  Next, as shown in FIG. 11D, an Al film is deposited on the entire surface of the SiN film 37 so as to fill the opening 38. Then, the Al film is selectively processed to form an Al pad 39 on the Cu wiring layer 35 (see, for example, Patent Document 1).

JP 2002-353221 A (page 3-4, Fig. 1-4)

  In the conventional method of manufacturing a semiconductor device, Cu in the Cu wiring layer 35 diffuses into the Al pad 39 and the entire Al pad 39 is alloyed, whereby the hardness of the Al pad 39 is increased and the fine metal wire is formed into the Al pad 39. In order to prevent the wire bonding from becoming impossible, a barrier metal film 36 is disposed between the Cu wiring layer 35 and the Al pad 39. When the barrier metal film 36 is formed, the barrier metal film 36 is deposited on the entire surface of the silicon substrate 31 (semiconductor wafer), and then etched to form a desired shape.

  At this time, there is a problem that warpage occurs due to a difference in film characteristics between the silicon substrate 31 (semiconductor wafer) and the barrier metal film 36.

  Further, as described above, the barrier metal film 36 is formed in order to prevent Cu from diffusing into the Al pad 39. For this reason, a process of depositing the barrier metal film 36 and performing an etching process is required, which increases the manufacturing cost and the material cost.

  Further, when a gold wire is used as the metal wire connected to the Al pad 39, the gold wire has a higher material cost than the copper wire, and there is a problem of raising the cost cost. Moreover, since the allowable current density of the gold wire is smaller than that of the copper wire, it is necessary to increase the diameter of the gold wire in a semiconductor element that handles a large current, resulting in an extra material cost.

  In view of the above circumstances, the semiconductor device of the present invention includes an insulating layer formed on a semiconductor layer, a semiconductor element formed on the insulating layer, and formed on the semiconductor layer. A copper wiring layer that is electrically connected, a resin film that covers the copper wiring layer and is formed on the insulating layer, and a pad that is connected to the copper wiring layer through an opening region formed in the resin film An electrode and a copper wire wire-bonded on the pad electrode, and a part of the pad electrode becomes an alloy layer from a boundary with the copper wiring layer, and the copper wire is formed on the pad on the alloy layer. It is connected to the other part of the electrode.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device comprising: forming a semiconductor element in a semiconductor layer; forming an insulating layer on the semiconductor layer; and forming a copper wiring layer electrically connected to the semiconductor element on the insulating layer. Forming a resin film on the insulating layer so as to cover the copper wiring layer, and forming an opening region so that the copper wiring layer is exposed on the resin film; and the opening region Forming a pad electrode electrically connected to the copper wiring layer through a baking process, and forming a part of the pad electrode as an alloy layer from the boundary of the copper wiring layer; and And a step of wire bonding a copper wire to the other part of the pad electrode.

  In the present invention, a part of the pad electrode is an alloy layer, the other part of the pad electrode is maintained as an Al film or an Al alloy film, and a Cu wire is connected to the part, thereby joining the pad electrode and the Cu wire. Strength is improved.

  Moreover, in this invention, Cu wire can be connected on Cu wiring layer by forming a pad electrode on Cu wiring layer. In addition, it is possible to cope with a product with a large current specification while reducing the material cost as compared with the case of using a conventional Au wire.

  In the present invention, a part of the pad electrode is made an alloy layer by baking, and the step of depositing the barrier metal film is omitted, so that the manufacturing cost can be suppressed while improving the yield.

It is sectional drawing explaining the semiconductor device in embodiment of this invention. 1 is a cross-sectional analysis view illustrating a semiconductor device in an embodiment of the present invention. 1A and 1B are a cross-sectional view and a plan view illustrating a semiconductor device in an embodiment of the present invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in other embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in conventional embodiment.

  A semiconductor device according to an embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a cross-sectional view illustrating a semiconductor device. 2A to 2C are cross-sectional analysis diagrams illustrating the pad electrode. FIG. 3A is a cross-sectional view illustrating the structure of the pad electrode and its periphery. FIG. 3B is a plan view illustrating the structure of the pad electrode and its periphery.

  As shown in FIG. 1, an insulating layer 2 for insulation processing is formed on a silicon substrate 1. As the insulating layer 2, for example, at least one layer such as a silicon oxide film, a NSG (Nondoped Silicate Glass) film, a BPSG (Boron Phospho Silicate Glass) film, or the like is selected. The silicon substrate 1 may be a single crystal substrate or an epitaxial layer formed on the single crystal substrate. The silicon substrate 1 may be a compound semiconductor substrate.

  A wiring layer 3 is formed on the insulating layer 2 and is electrically connected to a semiconductor element formed on the silicon substrate 1. The wiring layer 3 has a three-layer structure, and a metal film is formed on the barrier metal film, and an antireflection film is formed on the metal film. The barrier metal film is made of a refractory metal such as titanium (Ti) or titanium nitride (TiN). The metal film is made of an alloy film mainly composed of Al, such as an aluminum (Al) film, an aluminum-copper (Al-Cu) film, or an aluminum-silicon-copper (Al-Si-Cu) film. The antireflection film is made of a refractory metal such as TiN or titanium tungsten (TiW). And the film thickness of the wiring layer 3 is 0.4-3.0 micrometers, for example.

  The protective layer 6 is formed on the insulating layer 2 including the wiring layer 3. The protective layer 6 is formed by the planarizing film 4 and the silicon nitride film 5 formed on the planarizing film 4. The planarizing film 4 is formed by stacking, for example, a TEOS oxide film, an SOG (Spin On Glass) film, and a TEOS oxide film. The silicon nitride film 5 prevents moisture from entering the semiconductor element and prevents corrosion of the wiring layer 3 and the like. An opening region 7 is formed in the protective layer 6 on the wiring layer 3.

  A plating metal layer 8 is arranged in a pattern on the protective layer 6 through the opening region 7. The plating metal layer 8 is also disposed in the opening region 7 and is directly connected to the wiring layer 3 in the opening region 7.

  The plating metal layer 8 has a laminated structure of a barrier metal film and a Cu seed film, for example. As the barrier metal film, for example, a chromium (Cr) layer, a Ti layer, a TiW layer, or the like is used. The Cu seed film is used as a seed for forming the plating layer.

  The Cu wiring layer 9 is formed on the upper surface of the plating metal layer 8 by, for example, electrolytic plating. The film thickness of the Cu wiring layer 9 is, for example, 8.0 to 10.0 μm.

  A resin film 10 is formed on the upper surface of the protective layer 6 including the Cu wiring layer 9. The resin film 10 is made of, for example, a polybenzoxazole (PBO) film or a polyimide resin film, and is applied by a spin coating method. The PBO film is a photosensitive resin, and is a film having characteristics such as high heat resistance, stress relaxation characteristics, and low dielectric properties.

  The film thickness of the resin film 10 is, for example, about 10.0 to 15.0 μm, and the resin film 10 completely covers the Cu wiring layer 9. An opening region 11 is formed in the resin film 10 on the Cu wiring layer 9. A part of the Cu wiring layer 9 is exposed from the opening region 11.

  The pad electrode 12 is arranged in a pattern on the Cu wiring layer 9 through the opening region 11. The pad electrode 12 is directly connected to the Cu wiring layer 9 in the opening region 11. The pad electrode 12 is made of an Al film or an Al alloy film such as the aforementioned Al—Cu film or Al—Si—Cu film, and has a thickness of about 1.0 μm. Although details will be described later, in the pad electrode 12, an alloy layer 13 is formed from a boundary region with the Cu wiring layer 9, and as illustrated, an Al film or the like constituting the pad electrode 12 is formed on the upper surface of the alloy layer 13. Exists. With this structure, the Cu wire 14 is connected to the Al film portion of the pad electrode 12, and the bonding strength is also maintained. The film thickness of the pad electrode 12 can be arbitrarily changed depending on the application to be used, and is adjusted, for example, in the range of 1.0 to 3.5 μm.

  The Cu wire 14 is made of, for example, copper having a diameter of 33 to 50 μm and 99.9 to 99.99 wt%. As illustrated, the Cu wire 14 is wire bonded onto the pad electrode 12. By using the Cu wire 14, the material property is lower than that of the Au wire and the unit price is lower than that of the Au wire. Therefore, the material cost is reduced as compared with the case of using the Au wire. In addition, the design of the diameter of the Cu wire 14 can be arbitrarily changed according to the intended use.

  Next, FIGS. 2A to 2C are cross-sectional views for analyzing an alloy layer formed by baking between the Cu plating layer and the Al film. 2A is a cross-sectional analysis diagram before baking, FIG. 2B is a cross-sectional analysis after baking at 300 ° C., and FIG. 2C is 350 ° C. It is a cross-sectional analysis figure after performing a baking process in FIG. In all cross-sectional analysis diagrams, a carbon layer deposited in the analysis apparatus exists on the outermost surface. In the following cases, description will be made on the Al film, but the same applies to the case of an Al alloy film.

  First, as shown in FIG. 2 (A), the region above the alternate long and short dash line and indicated by the + mark 01 is a carbon layer deposited at the time of analysis. A region between the alternate long and short dash line and indicated by + mark 02 is an Al film and corresponds to the Al film portion of the pad electrode 12 shown in FIG. A region below the two-dot chain line and indicated by + mark 03 is a Cu plating layer and corresponds to the Cu wiring layer 9 shown in FIG.

  In this case, since the Al film is deposited on the upper surface of the Cu plating layer and the baking process is not performed, the Al film maintains the thickness of 1.0 μm at the time of deposition. However, although not shown in the drawing, as described above in the problem column, when heat is applied in the subsequent process, Cu in the Cu plating layer diffuses into the Al film, and Al and Cu in the Al film are dispersed. The metal reacts to become an alloy layer, and the film quality becomes harder than the Al film. That is, the entire pad electrode 12 becomes the alloy layer 13 containing Al and Cu, and the film quality becomes hard, so that the Cu wire 14 (see FIG. 1) cannot be wire-bonded to the pad electrode 12.

  Next, as shown in FIG. 2 (B), the area above the dotted line and indicated by the + mark 01 is a carbon layer deposited at the time of analysis. A region between the dotted line and the alternate long and short dash line and indicated by + mark 02 is an Al film and corresponds to the Al film portion of the pad electrode 12 shown in FIG. A region between the one-dot chain line and the two-dot chain line and indicated by + mark 03 is an alloy layer and corresponds to the alloy layer 13 portion of the pad electrode 12 shown in FIG. A region below the two-dot chain line and indicated by a + mark 04 is a Cu plating layer and corresponds to the Cu wiring layer 9 shown in FIG.

  In this case, by performing the baking process at 300 ° C., for example, a part of the Al film becomes the above-described alloy layer from the boundary between the Cu plating layer and the Al film. On the other hand, since the Al film exists above the alloy layer, the film quality on the surface side of the Al film maintains the softness capable of wire bonding. That is, the surface side of the pad electrode 12 maintains the state of the Al film, and the Cu wire 14 (see FIG. 1) can be wire-bonded. Furthermore, by having the above-described alloy layer 13 in the pad electrode 12, it is possible to prevent Cu in the Cu wiring layer 9 from diffusing into the pad electrode 12 even when heat is applied in a later process. Here, in this embodiment, for example, baking is performed at 300 ° C. for about 20 minutes, but it is preferably performed within a range of 270 ° C. to 330 ° C. In addition, what is necessary is just to be baked within the range in which the pad electrode 12 is not completely alloyed.

  Next, as shown in FIG. 2 (C), the region above the alternate long and short dash line and indicated by + mark 01 is a carbon layer deposited at the time of analysis. A region between the one-dot chain line and the two-dot chain line and indicated by + mark 02 is an alloy layer, and corresponds to the alloy layer 13 portion of the pad electrode 12 shown in FIG. A region below the two-dot chain line and indicated by + mark 03 is a Cu plating layer and corresponds to the Cu wiring layer 9 shown in FIG.

  In this case, by performing baking at 350 ° C., all the Al films become the alloy layers described above. That is, the entire pad electrode 12 becomes the alloy layer 13 by the baking process, and the film quality becomes hard, so that the Cu wire 14 (see FIG. 1) cannot be wire-bonded.

  As described above, the manufacturing conditions such as the baking temperature are adjusted, and a part of the pad electrode 12 is used as the alloy layer 13 so that an Al film region exists on the surface side of the pad electrode 12. Although this structure will be described in detail in the method of manufacturing a semiconductor device, it is not necessary to form a barrier metal film on the upper surface of the Al film constituting the pad electrode 12, and silicon is formed by film stress at the time of sputtering formation of the barrier metal film. The peripheral area of the substrate 1 (semiconductor wafer) is not warped. Therefore, it is possible to reduce the occurrence of cracks in the resin film 10, reduce the appearance defects, and improve the yield.

  Next, FIG. 3A illustrates a cross-sectional view in the direction of the line AA illustrated in FIG. As shown in the figure, a Cu wire 14 is wire-bonded on the pad electrode 12 in the opening region 11. The pad electrode 12 is provided in order to improve the bonding strength with the Cu wire 14, and the film thickness is, for example, about 1.0 μm. At this time, as described above, a part of the pad electrode 12 becomes the alloy layer 13, and the Al film region of the pad electrode 12 exists on the upper surface of the alloy layer 13. Due to the load during wire bonding, the Cu ball 15 of the Cu wire 14 slightly bites into the Al film of the pad electrode 12, and splash 16 is generated around the Cu ball 15. However, since the thickness of the Al film portion of the pad electrode 12 is thin, the splash 16 is slightly generated between the pad electrode 12 on the side surface of the opening region 11 and the Cu ball 15. With this structure, the splash 16 does not contact and short-circuit between adjacent pad electrodes 12.

  Note that the wire bonding load can be adjusted by reducing the size of the Cu ball 15 to suppress the generation of the splash 16 as much as possible. Further, the film thickness of the pad electrode 12 may be such that the Al film remains between the Cu ball 15 and the alloy layer 13 after wire bonding in order to improve the bonding strength with the Cu wire 14 described above.

  Next, as shown in FIG. 3B, a resin film 10 is disposed on the upper surface of the Cu wiring layer 9 indicated by a dotted line. The alternate long and short dash line indicates the opening region 11, the solid line inside the alternate long and short dash line indicates the Cu ball 15, and the solid line outside the alternate long and short dash line indicates the pad electrode 12. In FIG. 3B, the splash 16 (see FIG. 3A) is not shown.

  First, the above-described resin film 10 disposed on the lower surface of the pad electrode 12 is a film that is liable to generate cracks due to the stress of the metal film when the metal film is formed on the film by sputtering. It is desirable to prevent the occurrence of However, in the present invention, the pad electrode 12 made of an Al film or an Al alloy film needs to be disposed on the upper surface of the resin film 10. Furthermore, as described above, a part of the pad electrode 12 becomes the alloy layer 13, and a part of the alloy layer 13 is also formed in a region in contact with the resin layer 10. Therefore, in the present invention, the shape of the pad electrode 12 described above is formed in a round shape such as a circle or an ellipse, for example. And the pad electrode 12 becomes a structure which does not have an acute angle shape in the outer peripheral surface, and suppresses that a crack generate | occur | produces in the resin film 10 from an acute angle location.

  Similarly, the opening region 11 is also formed in a round shape such as a circle or an ellipse, for example. Further, as shown in FIG. 3A, the side surface of the opening region 11 has a gentle slope so as to spread outward. In addition, the pad electrode 12 is formed in the opening region 11, but an acute angle portion is not disposed in the shape of the opening region 11 located at the boundary between the pad electrode 12 and the resin film 10. As a result, as described above, the generation of cracks in the resin film 10 is suppressed.

  Next, in order to reduce the resistance value of the Cu wiring layer 9, the thickness of the Cu wiring layer 9 is increased as described above. Therefore, when the pad electrode 12 which is a thin film is formed on the Cu wiring layer 9, a step due to the Cu wiring layer 9 becomes a problem.

  Specifically, the pad electrode 12 is formed by depositing an Al film or an Al alloy film on the entire surface of the silicon substrate 1 and then patterning by etching using a resist film as a mask. At this time, when an insulating film made of a silicon nitride film or the like is formed on the silicon substrate 1 including the Cu wiring layer 9 described above, the side wall of the Cu wiring layer 9 cannot be filled with the insulating film. Then, depending on the insulating layer, an Al film or an Al alloy film is deposited on the insulating film in a state where the step due to the side wall of the Cu wiring layer 9 is not eliminated. On the other hand, the resist film is completely removed after patterning the Al film or the Al alloy film, but the resist film that should be originally removed due to the step of the Cu wiring layer 9 is not removed on the side wall of the Cu wiring layer 9. Will remain. As a result, the remaining resist film is covered, and a residue of the Al film or the Al alloy film is generated on the side wall of the Cu wiring layer 9, resulting in a patterning failure.

  Therefore, in the present invention, for example, by setting the film thickness of the resin film 10 made of a PBO film to, for example, about 10.0 μm to 15.0 μm, the step of the Cu wiring layer 9 is greatly reduced, and the above-described patterning is performed. Defects are suppressed. A region indicated by a circle 17 in FIG. 3A corresponds to the upper surface of the dotted line in FIG. As shown in the figure, the step of the Cu wiring layer 9 is substantially eliminated by using the resin film 10, and the surface of the resin film 10 is substantially flattened.

  In this embodiment, the case where the Cu wiring layer 9 is formed on the wiring layer 3 composed of an Al film or an Al alloy film has been described. However, the present invention is not limited to this case. For example, the wiring pattern may be formed only by the Cu wiring layer without having the Al wiring layer on the silicon substrate 1. In addition, various modifications can be made without departing from the scope of the present invention.

  Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 4 to 9 are cross-sectional views illustrating a method for manufacturing a semiconductor device in the present embodiment. In the present embodiment, the same reference numerals are assigned to the same constituent members in order to describe the manufacturing method of the structure shown in FIG.

  First, as shown in FIG. 4, a silicon substrate (semiconductor wafer) 1 is prepared, and an insulating layer 2 is formed on the silicon substrate 1. In the silicon substrate 1 (including an epitaxial layer when an epitaxial layer is formed), a semiconductor element is formed by a diffusion region. As the insulating layer 2, at least one layer such as a silicon oxide film, an NSG film, and a BPSG film is selected.

  Next, the wiring layer 3 is formed on the insulating layer 2. Specifically, a barrier metal film, a metal film, and an antireflection film are laminated on the silicon substrate 1 by, for example, a sputtering method. Thereafter, using the photolithography technique and the etching technique, the barrier metal film, the metal film, and the antireflection film are selectively removed to form the wiring layer 3.

  Next, the protective layer 6 is formed on the upper surface of the insulating layer 2 including the upper surface of the wiring layer 3. As the protective layer 6, for example, a planarizing film 4 made of a TEOS oxide film, an SOG film, and a TEOS oxide film, and a silicon nitride film 5 are laminated to about 3000 to 10,000 mm. Thereafter, the silicon nitride film 5 and the planarizing film 4 are selectively removed by using a photolithography technique and an etching technique, and an opening region 7 is formed.

  Next, as shown in FIG. 5, a plating metal layer 8 composed of a barrier metal film 21 and a Cu seed layer 22 is deposited on the upper surface of the protective layer 6 by, for example, sputtering. The plating metal layer 8 is electrically connected to the wiring layer 3 through the opening region 7. Thereafter, in order to form the Cu wiring layer 9 (see FIG. 6), a photoresist layer 23 is formed in a portion excluding the formation region of the Cu wiring layer 9.

  Next, as shown in FIG. 6, after forming the Cu wiring layer 9 by electrolytic plating, the photoresist layer 23 (see FIG. 5) is removed. Thereafter, using the Cu wiring layer 9 as a mask, the plating metal layer 8 is selectively removed by wet etching.

  As described above, the Cu wiring layer 9 is formed on the upper surfaces of the barrier metal film 21 and the Cu seed layer 22 (see FIG. 5) as the plating metal layer 8 by the electrolytic plating method. Therefore, compared with the case where the Cu wiring layer is formed by the sputtering method, it is easy to finely process the wiring pattern, and it is easy to realize miniaturization of the semiconductor element. Furthermore, by using the electrolytic plating method, the thickness of the Cu wiring layer 9 can be easily increased, and the resistance value of the Cu wiring layer 9 can be reduced.

  Next, as shown in FIG. 7, the resin film 10 is formed on the upper surface of the insulating layer 2 including the Cu wiring layer 9 by, for example, spin coating. As a material, a PBO film, a photosensitive polyimide resin film, or the like is used. Then, the resin film 10 is selectively removed using a photolithography technique and an etching technique, and the opening region 11 is formed.

  At this time, by using the resin film 10 as a film covering the upper surface of the Cu wiring layer 9, the step due to the Cu wiring layer 9 can be easily eliminated, and the surface of the resin film 10 can be flattened. Then, by forming the opening region 11 by wet etching, the side surface of the opening region 11 has a gentle inclination.

  Next, as shown in FIG. 8, after the oxide film on the surface of the Cu wiring layer 9 exposed from the opening region 11 is removed by the reverse sputtering method, the Al film 24 is formed on the upper surface of the resin film 10 by the sputtering method. Thereafter, a photoresist layer 25 is selectively formed so as to cover the upper surface of the formation region of the pad electrode 12 (see FIG. 9).

  Finally, as shown in FIG. 9, for example, the Al film 24 is selectively removed by dry etching, the pad electrode 12 is formed, and the photoresist layer 25 (see FIG. 8) is removed. Then, an alloy layer 13 is formed from the boundary between the Cu wiring layer 9 and the pad electrode 12 by performing, for example, a baking process at 300 ° C. on the silicon substrate 1 (semiconductor wafer). The alloy layer 13 is formed by the diffusion of Cu in the Cu wiring layer 9 to the pad electrode 12 and the metal reaction of Al and Cu, mainly the contact surface between the Cu wiring layer 9 and the pad electrode 12 and It is formed in the vicinity area. In addition, it can prevent that the whole pad electrode 12 becomes the alloy layer 13 by making baking process temperature into about 300 degreeC. Depending on the film thickness of the alloy layer 13, the bake treatment temperature can be arbitrarily changed. Thereafter, back grinding is performed from the back side of the silicon substrate 1, the film thickness of the silicon substrate 1 is adjusted, and the silicon substrate 1 (semiconductor wafer) is divided into individual semiconductor chips. The separated semiconductor chip is die-bonded on a substrate such as a lead frame, and a Cu wire 14 is wire-bonded to the pad electrode 12 of the semiconductor chip.

  As described above, when the pad electrode 12 is formed on the Cu wiring layer 9, the alloy layer 13 is formed by baking without forming a barrier metal film between the Cu wiring layer 9 and the pad electrode 12. Here, in the conventional technique, a barrier metal film is disposed on the lower surface of the pad electrode 12 in order to improve the bonding strength between the Cu wiring layer 9 and the pad electrode 12 and to prevent diffusion of Cu. In the same manner as the Al film 24, the barrier metal film is first formed on the entire surface of the silicon substrate 1 (semiconductor wafer) by sputtering. Then, the outer peripheral region of the silicon substrate 1 (semiconductor wafer) is warped due to the film stress at the time of forming the barrier metal film by sputtering, and a crack is generated in the resin film 10, which leads to an appearance defect. Therefore, in the present invention, only the Al film 24 is deposited on the Cu wiring layer 9 to reduce the amount of warpage of the outer peripheral region of the silicon substrate 1 (semiconductor wafer). On the other hand, by forming an alloy layer 13 between the Cu wiring layer 9 and the pad electrode 12 by baking, the bonding strength between the Cu wiring layer 9 and the pad electrode 12 is improved and Cu is diffused into the pad electrode 12. Also prevent.

  Further, the step of the Cu wiring layer 9 is eliminated and the surface of the resin film 10 is substantially planarized, so that the Al film 24 is easily deposited with a uniform film thickness. Then, when the Al film 24 is etched, all of the photoresist layer 25 (see FIG. 8) that should be removed is completely removed, and a patterning defect such as generation of a residue of the Al film 24 on the sidewall of the Cu wiring layer 9 can be prevented. . Moreover, since the pad electrode 12 aims at improving the bonding strength with the Cu wire 14, the film thickness should just have about 1.0 micrometer, for example. As a result, the Al film 24 can be processed by dry etching.

  In the present embodiment, the case where the Al film 24 is processed by dry etching has been described. However, the present invention is not limited to this case. For example, when the Al film 24 is deposited to have a thickness of, for example, about 3.0 μm, the Al film 24 is processed by wet etching in order to further alleviate the impact when wire bonding the Cu wire 14 to the upper surface of the pad electrode 12. Workability is better than dry etching. In addition, various modifications can be made without departing from the scope of the present invention.

  In the above description, the embodiment in which the Cu wire 14 is formed on the Cu wiring layer 9 in place of the conventional Au wire has been described. However, in the following description, a stud bump system made of Cu is used in place of the Cu wire 14. The described embodiment will be described with reference to FIG. In addition, about the structure similar to 1st Embodiment mentioned above, the overlapping description is abbreviate | omitted by using the same code | symbol.

  In FIG. 10, the configuration greatly different from the first embodiment is that a stud bump 26 is formed on the Cu wiring layer 9 via the pad electrode 12. The stud bump 26 is formed by cutting a wire after bonding a Cu wire. More specifically, the height of the stud bump 26 can be arbitrarily set by cutting a wire, then performing wire bonding on the wire, and further repeating the step of cutting the wire a plurality of times. Thus, by forming the stud bump 26 on the pad electrode 12, flip chip mounting becomes possible.

  In consideration of impact mitigation when mounting the above-described semiconductor device on which the stud bumps 26 are formed on the circuit board, a PBO film, a photosensitive polyimide resin film, etc. are formed under the Cu wiring layer 9 by spin coating. It is preferable to form a resin film 27 made of

DESCRIPTION OF SYMBOLS 1 Silicon substrate 3 Wiring layer 9 Cu wiring layer 10 Resin film 11 Opening region 12 Pad electrode 13 Alloy layer 14 Cu wire

Claims (8)

An insulating layer formed on the semiconductor layer;
A copper wiring layer formed on the insulating layer and electrically connected to a semiconductor element formed on the semiconductor layer;
A resin film that covers the copper wiring layer and is formed on the insulating layer;
A pad electrode connected to the copper wiring layer through an opening region formed in the resin film;
A copper wire wire-bonded on the pad electrode;
A part of the pad electrode becomes an alloy layer from a boundary with the copper wiring layer, and the copper wire is connected to another part of the pad electrode on the alloy layer. 2. The pad electrode is made of an aluminum film or an aluminum alloy film, and the alloy layer is a metal reaction film including copper constituting the copper wiring layer and aluminum constituting the pad electrode. A semiconductor device according to 1. 3. The semiconductor device according to claim 2, wherein the other part of the pad electrode is an aluminum film or an aluminum alloy film of the pad electrode on the alloy layer. 4. The semiconductor device according to claim 1, wherein the resin film is made of a polybenzoxazole film or a polyimide resin film. 5. Forming a semiconductor element on the semiconductor layer, forming an insulating layer on the semiconductor layer, and forming a copper wiring layer electrically connected to the semiconductor element on the insulating layer;
Forming a resin film on the insulating layer so as to cover the copper wiring layer, and then forming an opening region so that the copper wiring layer is exposed on the resin film;
Forming a pad electrode that is electrically connected to the copper wiring layer through the opening region and then performing a baking process, and forming a part of the pad electrode from the boundary of the copper wiring layer as an alloy layer;
And a step of wire bonding a copper wire to another part of the pad electrode on the alloy layer. The pad electrode is made of an aluminum film or an aluminum alloy film, and in the baking process, copper constituting the copper wiring layer is diffused into the pad electrode, and the alloy includes the copper and aluminum constituting the pad electrode. 6. The method of manufacturing a semiconductor device according to claim 5, wherein a layer is formed. The method for manufacturing a semiconductor device according to claim 6, wherein the baking process is performed at a temperature at which another portion of the alloy layer maintains the state of the aluminum film or the aluminum alloy film. The method for manufacturing a semiconductor device according to claim 5, wherein a polybenzoxazole film or a polyimide resin film is used as the resin film.