JP2010282422A - Data storage device and data transfer control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data storage device allowing effective improvement of performance by controlling order of data transfer requests. <P>SOLUTION: In this data storage device 10 performing data transfer control accompanying command processing of NCQ (native command queuing) specifications, the order of the data transfer requests are rearranged based on a priority condition of the command processing notified from a host system 20. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a data storage device, and more particularly to a data transfer control technique for an interface.

  2. Description of the Related Art In recent years, in a data storage device (hereinafter sometimes collectively referred to as a drive) such as a hard disk drive (simply referred to as a disk drive) or a solid state drive (SSD), a host system (host controller) As an interface, a serial ATA (SATA: Serial AT Attachment) standard interface (hereinafter sometimes referred to as a SATA interface) is employed. Here, the host system is, for example, a personal computer or a digital television receiver.

  For example, the disk drive writes data on the disk or reads data from the disk by executing a command such as a write command or a read command transferred from the host system via the SATA interface.

  The serial ATA standard defines a command queuing specification called NCQ (native command queuing). The NCQ is a specification that realizes a function that can arbitrarily determine the execution order of a plurality of commands stored (queued) in a command buffer on the drive side.

  Further, in the serial ATA standard, as a specification for performing data transfer control accompanying the execution of NCQ specification commands, the drive side sets up a FIS (Frame Information Structure) defined when making a data transfer request to the host system.・ Issues a frame. This data transfer request is referred to as a DMA setup FIS request. The frame is a unit (data structure) for performing data communication with the serial ATA interface.

  Here, for data transfer between the drive and the host system, data transfer from the host system side such as transfer of write data accompanying execution of a write command, and host such as transfer of read data accompanying execution of a read command are performed. There is data transfer to the system side.

  In such a data transfer control method, a technique for improving the performance on the drive side by controlling the timing of command completion notification to the host system has been proposed (see, for example, Patent Document 1).

JP 2005-215729 A

  Data transfer control technology is related to improving the efficiency of command processing, and is an important technology for improving drive-side performance. The above prior art methods alone are insufficient to effectively improve the drive side performance.

  Therefore, an object of the present invention is to provide a data storage device that can effectively improve performance by controlling the order of data transfer requests.

  A data storage device according to an aspect of the present invention includes an interface unit for transferring commands and data to and from a host system, and when executing a data transfer request accompanying command processing via the interface unit, And a control unit that rearranges the order of the data transfer requests based on the priority condition of the command processing.

  According to the present invention, it is possible to effectively improve the performance of the data storage device by controlling the order of data transfer requests.

The block diagram which shows the principal part of the disk drive regarding embodiment of this invention. The flowchart for demonstrating the outline of the data transfer control regarding this embodiment. The figure for demonstrating an example of the command queue regarding this embodiment. The figure for demonstrating an example of the data transfer request | requirement table regarding this embodiment. The figure for demonstrating an example of the data transfer request | requirement table regarding this embodiment. The figure for demonstrating an example of the data transfer request | requirement table regarding this embodiment. The figure for demonstrating an example of the data transfer request | requirement table regarding this embodiment. 6 is a timing chart for explaining a procedure of data transfer control according to the embodiment. The flowchart for demonstrating the procedure of the data transfer control method regarding this embodiment. The figure for demonstrating the specific example to which the data transfer control method regarding other embodiment is applied. The figure for demonstrating the specific example to which the data transfer control method regarding other embodiment is applied. The figure for demonstrating the specific example to which the data transfer control method regarding other embodiment is applied. The figure for demonstrating the specific example to which the data transfer control method regarding other embodiment is applied. The figure for demonstrating the specific example to which the data transfer control method regarding other embodiment is applied. The block diagram which shows the principal part of SSD applied to the data storage device of this embodiment.

  Embodiments of the present invention will be described below with reference to the drawings.

[Disk Drive Configuration]
FIG. 1 is a block diagram showing a main part of a disk drive 10 as a data storage device according to this embodiment.

  As shown in FIG. 1, the disk drive 10 includes a hard disk controller (HDC, hereinafter simply referred to as a disk controller) 11, a memory 12, a microprocessor (CPU) 13, and a head disk assembly (HDA) 14. Have.

  The HDA 14 includes a disk 140 that is a data recording medium, magnetically records data on the disk 140, and reproduces data from the disk 140. The HDA 14 includes a mechanism for driving the disk 140 and the head, and a circuit group such as a head amplifier and a read / write channel. The data surface on the disk 140 is composed of a large number of tracks (cylinders), and each track is divided into a plurality of data recording areas called sectors (access units for read / write operations). Each sector is assigned a logical block address (LBA). A target sector for write access or read access is specified by the host system 20 by LBA (n).

  The disk controller 11 is connected to the host system 20 via the SATA bus 100 of the serial ATA (SATA) interface standard, and executes NCQ (native command queuing) specification command and data (read data or write data) transfer control. A host interface module. The disk controller 11 also has a disk interface module that controls transfer of read data or write data between the read / write channels of the HDA 14.

  The memory 12 includes an NCQ specification command buffer 120 and a data buffer 121. The command buffer 120 is a queue buffer for queuing a plurality of commands continuously transferred from the host system 20. The data buffer 121 includes a write buffer area for storing write data transferred from the host system 20 and a read buffer area for storing read data for transfer to the host system 20.

  The CPU 13 is a main control device of the drive 10 and executes control of the HDA 14 and command processing. The control of the HDA 14 includes control of read and write operations on the disk 140 and head servo control. Furthermore, as will be described later, the CPU 13 executes processing of a data transfer request (DMA setup FIS request) accompanying execution of a command with the host system 20.

[Data transfer control]
The outline of data transfer control in the disk drive 10 of this embodiment will be described below with reference to FIG.

  The disk controller 11 continuously receives commands (read / write commands) transferred from the host system 20 via the SATA bus 100 (block 200). The disk controller 11 sequentially stores (queues) the received commands in the command buffer 120 (block 201).

  Here, the CPU 13 executes command processing according to the NCQ specification. That is, the CPU 13 sets the execution order of a plurality of commands queued in the command buffer 120 and executes them at an arbitrary timing. Specifically, the CPU 13 registers a plurality of commands queued in the command buffer 120 in a reordering table secured in the memory 12, and starts the commands in an order that can be processed at high speed.

  The CPU 13 executes a data transfer request (DMA setup FIS request) accompanying the execution of the command to the host system 20 via the SATA bus 100 (block 202). At this time, the data transfer request (DMA setup FIS request) is registered in the data transfer request table (queue buffer) secured in the memory 12.

  In response to the data transfer request, the host system 20 transfers the write data to the HDC 11 in the case of a write command, and receives the read data transferred from the HDC 11 in the case of a read command (block 203). Such a series of operations is repeated until execution of a plurality of commands stored in the command buffer 120 is completed (block 204).

  Further, the data transfer control of the present embodiment will be specifically described with reference to the timing charts of FIGS. 3 to 7 and 8 and the flowchart of FIG.

  As shown in FIG. 8, the host system 20 notifies the drive 10 of the priority condition of the order of data transfer requests (DMA setup FIS request) (800). Here, the host system 20 notifies the priority of the read data transfer accompanying the read command processing, for example, as the priority condition. The disk controller 11 notifies the host system 20 of an acknowledgment response (801). Next, the host system 20 issues a read / write command group of NCQ specifications at a time (802).

  Here, the processing of the disk drive 10 will be described with reference to the flowchart of FIG.

  As shown in FIG. 3, the disk controller 11 queues the command group transferred from the host system 20 in the command buffer 120. In the NCQ specification, up to 32 commands can be controlled simultaneously, and a tag number (Tag No.) from 0 to 31 is added to each command issued from the host system 20.

  In the table shown in FIG. 3, “LBA” is a logical block address that designates a sector to be accessed. “Block” is the number of blocks of data to be transferred. “Command” indicates the type of command. Here, there are two types, a read command (Read) and a write command (Write).

  As shown in FIG. 9, the CPU 13 sequentially executes the commands queued in the command buffer 120 (YES in block 900). At this time, in the case of a write command, if the write buffer area of the data buffer 121 is empty, the CPU 13 queues a write data transfer request (DMA setup FIS request) in the data transfer request table and resets the command. It registers in the ordering table (YES in block 901, YES in 902, 903, 904).

  In the present embodiment, the queue of the read data transfer request (DMA setup FIS request) in the data transfer request table is stored when read data to be transferred by the read operation to the disk 140 is prepared in the read buffer area of the data buffer 121. It is assumed that In this case, in the case of a read command, the CPU 13 only registers the command in the reordering table (NO in block 901, 904).

  In the present embodiment, when two or more requests are set in the queue of the data transfer request table, the CPU 13 executes the request order rearrangement process of the data transfer request table as follows (block 905). YES, 906).

  In the present embodiment, as described above, it is assumed that the host system 20 notifies the priority of read data transfer as a priority condition. In this case, when the read data to be transferred is not prepared in the read buffer area of the data buffer 121, the CPU 13 stores a write command (300, 302 in FIG. 3) in the data transfer request table as shown in FIG. Register only the data transfer request associated with.

  As shown in FIG. 8, the disk controller 11 sends a write data transfer request (DMA setup FIS request) accompanying the execution of the write command (300) of the first request in the data transfer request table shown in FIG. (803). In response to the data transfer request, the host system 20 transfers write data necessary for processing the write command (300) to the disk drive 10 (804). At this time, it is assumed that an elapsed time of, for example, 20 ms is required until transfer of write data from the host system 20 to the disk controller 11 is completed.

  Assume that the read data associated with the read command (301, 303) shown in FIG. 3 is ready in the read buffer area of the data buffer 121 during the transfer of the write data having the highest request order. As shown in FIG. 5, the CPU 13 registers the data transfer request of the read command (301, 303) in the data transfer request table. After completion of the write data transfer, the data transfer request table is in a state as shown in FIG.

  Based on the priority of the read data transfer from the host system 20, the CPU 13 executes a rearrangement process for the order of requests in the data transfer request table shown in FIG. 6 (see block 906). Next, the disk controller 11 sends a read data transfer request (DMA setup FIS request) accompanying the execution of the read command (301) to the host system 20 in accordance with the first rank in the request order of the data transfer request table shown in FIG. (805). In response to the data transfer request, the disk controller 11 transfers the read data accompanying the processing of the read command (301) to the host system 20 (806).

  Further, in accordance with the second rank of the request order of the data transfer request table shown in FIG. 7, the disk controller 11 sends a read data transfer request (DMA setup FIS request) to the host system 20 when the read command (303) is executed. Execute (807). In response to the data transfer request, the disk controller 11 transfers the read data accompanying the processing of the read command (303) to the host system 20 (808).

  When the read data transfer, which is a priority condition from the host system 20, is completed, the disk controller 11 performs a write data transfer request (DMA setup) associated with the execution of the write command (302) in accordance with the third request rank in the data transfer request table. FIS request) is executed to the host system 20 (809). In response to the data transfer request, the host system 20 transfers write data required for processing the write command (302) to the disk drive 10 (810).

  As described above, the disk drive 10 gives priority to the read data transfer accompanying the read command process based on the condition giving priority to the read data transfer accompanying the read command process as the priority condition notified from the host system 20. In addition, processing for rearranging the order of the data transfer requests in the data transfer request table is executed. However, if the preparation for the read data transfer is not completed, a write data transfer request accompanying the write command processing is executed in advance, and a process for rearranging the order of the data transfer requests is executed after the preparation is completed.

  By controlling the order of data transfer requests in accordance with requests from the host system 20 by such a data transfer control method, the command processing efficiency of the disk drive 10 is improved, and as a result, the performance on the drive 10 side is improved. It becomes possible to make it.

[Other Embodiments]
10 to 14 are diagrams for explaining a data transfer control method according to another embodiment.

  FIG. 10 is a diagram showing an example of a command group transferred from the host system 20 and registered in the reordering table. FIG. 11 is a diagram showing a data transfer request table in which data transfer requests (DMA setup FIS requests) accompanying processing of the command group are registered. That is, the CPU 13 starts processing of the read command with the tag number 0 in the table shown in FIG. 10 and, for example, tag numbers 1, 2, 4 to 6 on the condition that the write buffer area of the data buffer 121 is sufficiently free. Register the DMA setup FIS request with the write command in the queue.

  FIGS. 12A to 12E are diagrams each showing a result of executing a request order rearrangement process in the data transfer request table based on a request from the host system 20 or a preset command process priority condition. It is.

  First, as described above, under the condition that priority is given to read data transfer, the CPU 13 executes the rearrangement process of the data transfer request table as shown in FIG. Here, since the read data transfer is not ready, only the write data transfer request accompanying the write command is registered in the data transfer request table. Note that if the host system 20 processes the read command in preference to the write command, the next command processing can be determined earlier, and the performance is improved.

  Next, under the condition that priority is given to a command having a small number of transfer blocks, the CPU 13 executes a data transfer request table rearrangement process as shown in FIG. In this case, in the disk drive 10, the number of commands that can be processed per unit time increases. Therefore, the host system 20 can issue a number of new commands.

  On the other hand, under the condition that priority is given to a command having a large number of transfer blocks, the CPU 13 executes a data transfer request table rearrangement process as shown in FIG. In the write command process, when the write data transfer from the host system 20 is completed, the disk drive 10 writes the write data in the write buffer area onto the disk 1401. At this time, the write buffer area can be emptied by the larger number of transfer blocks.

  Further, under the condition that priority is given to the sequential command, the CPU 13 executes the rearrangement process of the data transfer request table as shown in FIG. In this case, when a sequential disk access request requested by a certain process on the host system 20 is divided before issuing a command to the disk drive 10, the host system 20 can quickly determine the next command processing.

  Further, under the condition that priority is given to a command having a long time elapsed since the command issuance from the host system 20, the CPU 13 executes a rearrangement process of the data transfer request table as shown in FIG. However, here, the state of the data transfer request table is the same as the state shown in FIG. In this case, a timeout on the host system 20 side can be prevented, and a decrease in overall performance can be avoided.

  FIG. 13 is a diagram showing a data transfer request table in which, for example, two read commands (tag numbers 3 and 7) are registered after the data transfer request is processed. In such a state, a specific example of the processing for rearranging the request order of the data transfer request table will be described with reference to FIGS.

  Under the condition that priority is given to the read data transfer, the CPU 13 executes the rearrangement process of the data transfer request table as shown in FIG. That is, the data transfer request table is rearranged so that the data transfer request order of the two read commands (tag numbers 3 and 7) is first and second. Similarly to the above, under the condition that priority is given to a command with a small number of transfer blocks, the CPU 13 executes a data transfer request table rearrangement process as shown in FIG. On the other hand, under the condition that priority is given to a command having a large number of transfer blocks, the CPU 13 executes a data transfer request table rearrangement process as shown in FIG. Further, under the condition that priority is given to the sequential command, the CPU 13 executes the rearrangement process of the data transfer request table as shown in FIG. Furthermore, under the condition that priority is given to a command having a long time elapsed since the command issuance from the host system 20, the CPU 13 executes a rearrangement process of the data transfer request table as shown in FIG. It should be noted that the same effect as described above can also be obtained in such rearrangement processing of the data transfer request table.

[Configuration of SSD]
In this embodiment, the case where the disk drive 10 is applied as a data storage device has been described. However, the present invention is not limited to this, and the present invention can also be applied to a solid state drive (SSD) 30 as shown in FIG.

  The SSD 30 is a data storage device that uses a flash memory 32 as a data recording medium, and includes a controller 31 connected to the host system 20 via the SATA bus 100. The controller 31 has functions corresponding to the disk controller 11 and the CPU 13 of the disk drive 10 shown in FIG. 1, and executes NCQ specification command processing, data transfer request order rearrangement processing, and the like related to this embodiment.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

10 ... disk drive, 11 ... hard disk controller (HDC),
12 ... Memory, 13 ... Microprocessor (CPU),
14 ... head disk assembly (HDA), 20 ... host system,
30 ... Solid state drive (SSD), 31 ... Controller,
32 ... Flash memory, 100 ... Serial ATA bus,
120: command buffer, 121: data buffer, 140: disk.

Claims (11)

Interface means for transferring commands and data to and from the host system;
Control means for rearranging the order of the data transfer requests based on a priority condition of the command processing when a data transfer request associated with command processing is executed via the interface means; Storage device.   The priority condition is a condition for preferentially executing a read command, and a condition for giving priority to the order of data transfer requests for transferring read data to the host system. Item 4. The data storage device according to Item 1.   2. The data storage device according to claim 1, wherein the priority condition is a condition for preferentially executing a command having a relatively small transfer data amount.   The data storage device according to claim 1, wherein the priority condition is a condition for preferentially executing a command having a relatively large transfer data amount.   The data storage device according to claim 1, wherein the priority condition is a condition for preferentially executing a sequential access command.   2. The data storage device according to claim 1, wherein the priority condition is a condition for preferentially executing a command having a long time elapsed since the issuance of the host system. The control means includes
The data according to any one of claims 1 to 6, wherein the order of the data transfer requests is rearranged based on the priority condition notified from the host system via the interface unit. Storage device. The control means includes
8. The data transfer request is queued according to completion of execution preparation of the command, and the queue order of the data transfer request is changed based on the priority condition. A data storage device according to item.   9. The data storage device according to claim 1, wherein the interface means is configured to execute data transfer control based on a serial ATA interface standard. Serial interface means included in the data storage device for transferring commands and data to and from the host system;
Control means for rearranging the order of the data transfer requests based on a priority condition of the command processing when a data transfer request associated with command processing is executed via the serial interface means; Transfer control device. A data transfer control method for controlling command and data transfer through a serial interface connecting a data storage device and a host system,
A process of receiving a command transferred from the host system via the serial interface;
And a process for rearranging the order of the data transfer requests based on a priority condition of the command processing when executing a data transfer request associated with the command processing.

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