JP2010277300A - Power saving control device for multiprocessor system, and mobile terminal - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To effectively reduce power consumption while securing real time performance without assuming that a processor load is set to a low load state according to the lapse of a time in a multiprocessor system in which both performance securing/performance non-securing tasks coexist. <P>SOLUTION: This multiprocessor system equipped with a plurality of processors for performing the distributed processing of a plurality of tasks includes an assignment control means E1 for controlling the assignment of each performance securing task to each processor so that the number of use processors can be minimized on the basis of a relative relationship between each of processing performance value Φi of each performance securing task Ti and each of processing capability values Wj of a processor Pj in consideration of a real time performance time τi required by each performance securing task; and an operation state control means E2 for applying a power saving state to the operating states of non-use processors to which the assignment of the performance securing tasks has been canceled as the result of the assignment control means. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a power-saving control apparatus in a multiprocessor system including a plurality of processors that perform distributed processing of a plurality of tasks, and in which a performance guarantee task and a performance non-guarantement task coexist. The present invention relates to a technique for effectively reducing power consumption. The present invention also relates to a mobile terminal such as a digital still camera having the same function as described above. Real-time property refers to the ability to complete a predetermined task within a predetermined time. The technique of the present invention is preferably applied particularly to an information processing apparatus adopting a multiprocessor system.

  Since a multiprocessor system is composed of a plurality of processors, it consumes more power than a single processor system composed of a single processor. In a multiprocessor system, distributed processing is performed by a plurality of processors, so that the processing efficiency of the entire system is high, but it is not necessary to perform distributed processing using all the processors in a low load state. Operating all processors in a low load state consumes more power than necessary for the system. Therefore, conventionally, a technique for reducing power consumption in a low load state has been proposed.

  For example, in the power saving control system described in Patent Document 1, in a multiprocessor system including two or more processors (CPUs), a state monitoring unit that constantly detects the operating state of the system and the state monitoring unit detect When the operating state of the system changes beyond a predetermined boundary condition (threshold value), it is constituted by state control means for performing state transition control for a designated processor. Here, state transition control refers to mutual switching between power saving control that changes the processor operating state from the normal operating state to the standby state and return control that changes the processor operating state from the standby state to the normal operating state. Is to do. In addition, the system operation state includes a normal operation state and an operation standby state regarding the operation state of the processor. Alternatively, there are a waiting state for input from the keyboard and a low load state. In this document, a system state monitoring unit is described as corresponding to the state monitoring unit, and a system state control unit is described as corresponding to the state control unit. Further, the system operating state exceeding a predetermined boundary condition means that a value representing a current load state of a bus that relays signals exchanged between system components exceeds a predetermined threshold value. . Alternatively, the value representing the current load state of application execution in the entire system exceeds a predetermined threshold value. Alternatively, the value indicating the scheduling state for distributing the task for realizing the function of the application to each processor exceeds a predetermined threshold value.

  In this prior art, the operating state of the system, that is, the time-varying element value (bus load state, application execution load state, scheduling state) is constantly monitored to determine whether or not a predetermined threshold value is exceeded. When the element value that changes automatically falls below the threshold value, the operation state of the processor is changed from the normal operation state to the operation standby state. Further, when the element value that changes with time exceeds a threshold value, the operation state of the processor is changed from the operation standby state to the normal operation state. Specifically, the operating state of each processor is monitored, and if the load on a specific processor continues to be low due to waiting for key input, etc., the optimum clock can be obtained by switching the clock supplied to the processor to a low frequency. Maintain operation with power consumption.

The feature of this prior art is that
(A) It is based on “element values that change with time in the system” such as a bus load state, an application execution load state, and a scheduling state, and
(B) Control of the operating state of the processor to be controlled (switching between power saving control for switching from the normal operating state to the standby state for operation and return control for switching from the standby state to the normal operating state) is also performed over time. Transition,
That's what it means. In other words, it is important that both the monitoring target and the control target are accompanied by temporal changes.

JP-A-8-6681 (paragraphs [0013], [0014], [0018], [0020], [0029], [0071], [0075])

  In the power saving control system of the above-mentioned Patent Document 1, element values that change with time such as a bus load state, an application execution load state, and a scheduling state, which are operating states of the system, are used as judgment criteria. Therefore, it is necessary to constantly monitor the element value changing with time. Further, the operation state of the processor is controlled to be switched between the power saving control and the return control according to the determination result, and this control itself also changes with time. That is, a temporal circulation occurs in which a temporal change in the monitoring target results in a temporal change in the control target, and further, a temporal change in the control target induces a temporal change in the monitoring target. Such constant monitoring and control with temporal circulation results in a decrease in processing speed of the multiprocessor system.

  In addition, since the control for reducing the frequency of the supply clock to the processor is based on the condition that the processor load is in a low load state, the frequency of the supply clock cannot be reduced unless the processor load is in a low load state. This is an obstacle to effective power consumption reduction.

  The present invention was created in view of such circumstances, and in a multiprocessor system in which performance assurance tasks and performance non-guaranteed tasks are mixed, element values that change over time are constantly monitored, Real-time performance (predetermined tasks are completed within a predetermined time without requiring the operating state to be under constant control and without assuming that the processor load becomes low over time. An object of the present invention is to provide a power saving control apparatus capable of effectively reducing power consumption while guaranteeing that the restriction that must be satisfied is satisfied.

(1) A power saving control device in a multiprocessor system according to the present invention includes:
In a multiprocessor system that has multiple processors that distribute and process multiple tasks, and that includes both performance guarantee tasks and non-performance guarantee tasks,
There is a correlation between each processing performance value Φi of each performance assurance task Ti to be assigned to each processor and each processing performance value Wj of the processor Pj taking into account the real-time performance time τi required by each performance assurance task Ti. Based on allocation control means for controlling allocation of each performance assurance task to each processor so that the number of processors used is minimized,
As a result of the assignment by the assignment control means, an operation state control means for applying a power saving state to the operation state of the unused processor for which the assignment of the performance guarantee task has been eliminated is provided.

  As an attribute of each performance guarantee task Ti (i = 1, 2,... N), there is a processing performance value Φi (i = 1, 2,... N) representing the size (number of instructions) of the task. The time required to complete execution of a certain performance guarantee task Ti is the real-time performance time τi (i = 1, 2,... N). On the other hand, each processor Pj (j = 1, 2,... M) has a processor processing capacity value Wj (j = 1, 2,... M) that takes into account the real-time performance time τi required by the performance guarantee task Ti assigned thereto. ) The processing capability value Wj is the total processing amount of tasks that the processor Pj can process within the real-time performance time τi.

  Based on the correlation between the processing performance value Φi of the performance guarantee task Ti and the processing capacity value Wj of the processor taking into account the real-time performance time τi, the allocation control means is configured to minimize the number of processors used. The allocation of the guaranteed task Ti to each processor Pj is controlled. In any given processor allocation state, if a certain processor has the capacity (allowance for processing power) that it is possible to change (move) the allocation of a performance assurance task that has already been allocated to another processor, the allocation of that performance assurance task Make a change. This is reassignment of the performance guarantee task. If such reassignment of performance assurance tasks is advanced as much as possible, unused processors whose performance assurance task assignments have been resolved will appear, and the number of such unused processors will increase. The operation state control means applies the power saving state to the operation state of the unused processor for which the assignment of the performance guarantee task is eliminated. Even if a performance non-guaranteed task is assigned to a processor to which the power saving state is applied, it is a performance non-guaranteed, and therefore there is no problem in performance guarantee even in the power saving state.

  Here, as in the case of the prior art, if it is not necessary to constantly monitor an element value that changes over time (processor load), the comparison result between the element value and the threshold value changes over time. There is no need for continuous control of the operating state.

  Thus, according to the power saving control device having the above configuration, in a multiprocessor system in which a performance guarantee task and a performance non-guarantement task coexist, it is a precondition that the processor load becomes a low load state as time passes Therefore, it is possible to effectively reduce power consumption while ensuring real-time performance.

  (2) In the configuration of (1), the allocation control unit determines whether or not the performance guarantee task can be reassigned to another processor, and performs the reassignment when it is possible. There is an aspect of being configured. According to this configuration, it is possible to reliably minimize the number of processors used by reassigning performance guarantee tasks that can be reassigned without omission.

  (3) In the configuration of (2), the allocation control unit compares the processing performance value Φi of the performance assurance task Ti to be determined with the remaining performance Mj of another processor Pj, and determines the performance assurance task to be determined There is a mode in which when the processing performance value Φi of Ti is equal to or less than the remaining capacity Mj of the other processor Pj, the performance guarantee task to be determined is reassigned to another processor having remaining capacity. When a performance guarantee task Ti is already assigned to a certain processor, the remaining performance Mj of the other processor is examined when determining whether or not the performance guarantee task Ti can be reassigned to another processor. That is, when the processing performance value Φi of the performance guarantee task Ti to be judged is smaller than or equal to the remaining performance Mj of the other processor, it is judged that the reallocation is possible and the performance guarantee task Ti is reallocated to the other processor. To do.

  (4) In the configurations of (1) to (3), the processing capability value Wj of the processor Pj multiplies the processing capability qj per unit time of the processor Pj by the real-time performance time τi of the performance assurance task Ti. There is a mode that it is. That is, Wj = qj × τi. Thus, the processing capability value Wj of the processor Pj can be made to take into account the real-time performance time τi required by the performance guarantee task Ti.

  (5) In the configurations of (3) and (4) above, the remaining performance Mj of the processor Pj is calculated from the processing capability value Wj of the processor Pj taking into account the real-time performance time τi of the performance guarantee task Ti. Is a value obtained by subtracting the sum ΣΦi of the processing performance values Φi of the performance guarantee tasks Ti that have already been assigned. That is, Mj = Wj−ΣΦi. By adopting such an operation, it is possible to satisfactorily achieve the effect of reducing power consumption while guaranteeing real-time performance.

  (6) In the configurations of (1) to (5), there is an aspect in which the allocation control means is configured to minimize the movement of the performance guarantee task between the processors for the reallocation. According to this configuration, it is possible to improve the efficiency of the reallocation itself.

  (7) In the configurations of (2) to (6), the allocation control means minimizes contention between processors of resources used by the performance assurance task when the performance assurance task is reassigned to another processor. There is an aspect in which reassignment is performed with priority given to being limited. According to this configuration, since contention among resources is minimized, the total task distribution processing of the multiprocessor system can be efficiently advanced.

  (8) In the configurations of (2) to (6), the allocation control means is configured to preallocate performance guarantee task groups that need to be processed in sequence to the same processor. There is an aspect of being. According to this configuration, the number of times the performance guarantee task for sequential processing is dispatched is minimized, and the total task distribution processing of the multiprocessor system can be efficiently advanced. Dispatch refers to assigning processors to a plurality of tasks processed by an operating system (OS) according to priority (also called scheduling).

  (9) In the configurations of (1) to (8), the allocation control unit performs the reallocation between the processors of the performance non-guaranteed task after the reallocation of the performance guaranteed task. There is an aspect in which the processor to which the performance assurance task has been reassigned is configured to be reassigned in a state where the reassignment of the performance non-guaranteed task is prohibited. For task reassignment to minimize the number of processors used, priority is given to reassignment of performance assurance tasks, and if this is completed, it will proceed to reassignment of performance non-guaranteed tasks. The performance non-guaranteed tasks can be reassigned while keeping the total task distributed processing efficiency of the system as high as possible.

  (10) In the configurations of (1) to (9), the operation state control means is configured to change the operation mode of the unused processor in which the allocation of the performance guarantee task is canceled. is there.

  (11) Further, in the configuration of the above (10), the mode of changing the operation mode of the unused processor in which the allocation of the performance guarantee task has been canceled is to stop the clock supply to the unused processor. is there.

  (12) In the configurations of (1) to (9), the operation state control means is configured to change the operation mode of the processor in use for which the performance guarantee task assignment is determined. .

  (13) Further, in the configuration of (12) above, changing the operation mode of the used processor for which the assignment of the performance guarantee task has been determined means changing the state of the used processor from the low power consumption state to the normal operation state. Alternatively, there is a mode in which the normal operation state is changed to the high-speed operation state.

  (14) In the configurations of (1) to (13), the operation state control means is configured to dynamically change the allocation of the memory to the processor.

  (15) Further, in the configuration of (14), there is an aspect in which dynamically changing the allocation of the memory to the processor is to reallocate the memory allocated to the unused processor to the used processor. . If the memory allocated to the unused processor for which the performance assurance task assignment has been resolved is reassigned to the used processor for which the performance assurance task assignment has been determined, the total task distribution processing of the multiprocessor system will be more efficient. It is possible to proceed.

  (16) In the configurations of (1) to (15), the operation state control means is configured to change the snoop mode of a cache having a snooping function. The snooping function is a function that monitors whether the memory contents do not match the cache contents by DMA (Direct Memory Access) from a peripheral device, and discards the cache contents if necessary.

  (17) Further, in the configuration of (16), there is an aspect in which changing the snoop mode of the cache having the snooping function is stopping the snoop mode of the cache of the unused processor. By stopping the snoop mode of the unused processor cache, it is possible to increase the efficiency of the total task distribution processing of the multiprocessor system.

  (18) In the above configurations (1) to (17), the operation state control unit may replace the unused processor whose allocation of the performance guarantee task has been eliminated as a result of the allocation by the allocation control unit, or There is an aspect in which the operation state of the peripheral device is changed together with the unused processor. In addition to simply controlling unused processors to a power-saving state, by controlling peripheral devices to a power-saving state instead of or together with unused processors, the total task distribution processing of a multiprocessor system can be reduced. The efficiency can be further increased.

  (19) A mobile terminal according to the present invention is a mobile terminal equipped with a power saving control device in the multiprocessor system according to any one of (1) to (18).

  (20) The configuration of (19) includes a normal operation mode that operates in a normal operation state and a low power consumption mode that operates in a low power consumption state, and the allocation control unit and the operation state control unit include the low power consumption mode. There is a mode that it is configured to be activated only in the case of the power mode.

  (21) In the configuration of (20), there is an aspect in which the normal operation mode and the low power consumption mode are configured to be settable by a user. If comprised in this way, the use according to a use condition can be performed and usability will improve.

  (22) In addition, in the configuration of (20), there is an aspect in which the normal operation mode and the low power consumption mode are configured to switch when the remaining power amount of the battery becomes equal to or less than a certain level. As a result, under a situation where the remaining amount of battery power is large, the high-speed processing operation can be maintained in a full capacity state, and it is possible to operate in the low power consumption mode only when the remaining power amount of the battery decreases.

  According to the present invention, in a multiprocessor system in which performance assurance tasks and performance non-guaranteed tasks coexist, the performance assurance tasks to the processors can be executed with a minimum number of processors while maintaining real-time performance. The power-saving state is applied to the operating state of the unused processor whose performance assurance task has been unassigned by performing allocation control, so it is a prerequisite that the processor load becomes a low-load state over time Therefore, power consumption can be effectively reduced while guaranteeing real-time performance.

The block diagram which shows the structure of the power saving control apparatus in the multiprocessor system of Embodiment 1 of this invention Functional explanatory drawing showing the function of the principal part of the power-saving control device in Embodiment 1 of the present invention The figure which shows the structure of the task management information of the power saving control apparatus in Embodiment 1 of this invention The figure which shows the specific content of the task management information before reallocation of the power saving control apparatus in Embodiment 1 of this invention The figure which shows an example of the MIPS value of the processor of the power saving control apparatus in Embodiment 1 of this invention Explanatory drawing of the remaining performance of the processor of the power saving control device in Embodiment 1 of the present invention Operation explanatory diagram of the power saving control device in Embodiment 1 of the present invention The figure which shows the specific content of the task management information after reallocation of the power saving control apparatus in Embodiment 1 of this invention The flowchart which shows operation | movement of the power saving control apparatus in Embodiment 1 of this invention. The figure which shows the structure of the task management information of the power saving control apparatus in Embodiment 2 of this invention The figure which shows the specific content of the task management information before reallocation of the power saving control apparatus in Embodiment 2 of this invention Operation explanatory diagram of the power saving control device in Embodiment 2 of the present invention The figure which shows the specific content of the task management information after reallocation of the power saving control apparatus in Embodiment 2 of this invention The flowchart which shows operation | movement of the power saving control apparatus in Embodiment 2 of this invention. Block diagram showing a schematic configuration of a digital still camera according to Embodiment 3 of the present invention. Functional explanatory drawing showing the function of the principal part of the digital still camera in Embodiment 3 of the present invention

  Embodiments of a power saving control device in a multiprocessor system according to the present invention will be described below in detail with reference to the drawings. In the following, the same or corresponding elements are denoted by the same reference symbols throughout all the drawings, and redundant description thereof is omitted.

(Embodiment 1)
FIG. 1 is a block diagram showing the configuration of a power saving control device in a multiprocessor system in which performance guarantee tasks and non-performance guarantee tasks are mixed according to the first embodiment of the present invention. In FIG. 1, 1 is a CPU (Central Processing Unit), 2 is a ROM (Read Only Memory), 3 is a RAM (Random Access Memory), 4 is a clock controller, 5 is a peripheral device, and P1 to P4 are first through first. These processors are connected to each other via a bus 6. The peripheral device 5 includes a plurality of tasks, and here, includes the first to eighth tasks T1 to T8. α indicates a performance guarantee task that is a task for performing performance guarantee, and β indicates a performance non-guaranteed task that is a task for which performance is not guaranteed. In this example, the first to fifth tasks T1 to T5 correspond to the performance guarantee task α, and the sixth to eighth tasks T6 to T8 correspond to the performance non-guaranteed task β. A multiprocessor system generally performs a distributed processing of a plurality of tasks Ti (i = 1, 2,... N) by a plurality of processors Pj (j = 1, 2,... M). In an example here, the integer n is n = 8 and the integer m is m = 4. Reference numeral 10 denotes an operating system (OS) generated by the functional combination of the CPU 1, the ROM 2, and the RAM 3. The operating system 10 includes at least an allocation control unit E1 and an operation state control unit E2.

  The assignment control means E1 is configured to control assignment so that the number of processors used is minimized when assigning a plurality of tasks to a plurality of processors (details will be described later).

  The operation state control means E2 is configured to apply the power saving state to the operation state of the unused processor in which the assignment of the performance guarantee task Ti is eliminated as a result of the assignment by the assignment control means E1. The application of the power saving state is performed through the control of the clock frequency in the clock control unit 4.

  As an attribute of each performance guarantee task Ti (i = 1, 2,... N), there is a processing performance value Φi (i = 1, 2,... N) representing the size (number of instructions) of the task (FIGS. 3, 4). FIG. 6). It is assumed that each performance guarantee task Ti is desired to be completed within a certain time τi (i = 1, 2,... N). The time τi is the real-time performance time. On the other hand, each processor Pj (j = 1, 2,... M) has a processing capability qj (j = 1, 2,... M) that represents the amount of processing that can be executed per unit time (FIGS. 5, 6). reference). The processing capability qi is often represented by a MIPS value.

The processing capability value Wj, which is the processing amount that can be executed by the processor Pj having the processing capability qj per unit time within the real-time performance time τi, is:
Wj = qj × τi
(A specific example will be described later).

  The allocation control means E1 controls the allocation of each performance assurance task Ti to each processor Pj, the processing performance value Φi (i = 1, 2,... N) of each performance assurance task Ti, and the real-time performance time. Based on the correlation with each of the processing capability values Wj (more specifically, the surplus performance Mj) (j = 1, 2,... m) of the processor Pj taking into account τi (i = 1, 2,... n), It is configured to control so that the number of processors used is minimized.

  The operation state control unit E2 is configured to apply the power saving state to the operation state of the unused processor in which the assignment of the performance guarantee task Ti is canceled as a result of the assignment by the assignment control unit E1. When the power saving state is applied, the clock controller 4 is configured to respond by changing the clock frequency.

  FIG. 2 is a function explanatory diagram showing functions of main parts of the power saving control device according to the first embodiment. The operating system 10 operates on the first to fourth processors P1 to P4, assigns the first to eighth tasks T1 to T8 to the processors P1 to P4, and the operating states of the processors P1 to P4. And control.

  The assignment control means E1 in the operating system 10 assigns the first to eighth tasks T1 to T8 to the first to fourth processors P1 to P4 according to a predetermined algorithm as the previous stage assignment process. Now, as shown in FIG. 2, the assignment control means E1 assigns the first task T1 and the fifth task T5 to the first processor P1, and assigns the second task T2 and the sixth task T6 to the first task. Assigned to the second processor P2, the third task T3 and the seventh task T7 are assigned to the third processor P3, and the fourth task T4 and the eighth task T8 are assigned to the fourth processor P4. And The first to fifth tasks T1 to T5 are performance guarantee tasks α for which real-time performance is required, and the sixth to eighth tasks T6 to T8 are performance non-guaranteed tasks β for which real-time performance is not required. To do.

  The performance guarantee tasks T1 to T5 are allocated and assigned to the four processors P1 to P4. In this pre-assignment state, the assignment control means E1 determines whether or not there are tasks and processors that can be reassigned from the currently assigned processor to other processors among the performance guarantee tasks T1 to T5. The allocation control means E1 includes the processing performance values Φ1 to Φ5 of the performance assurance tasks T1 to T5 allocated to the processors P1 to P4 and the performance assurance tasks T1 to T5 allocated to the processors P1 to P4. Whether the performance guarantee tasks T1 to T5 can be reassigned to other processors based on the correlations with the processing capability values W1 to W4 of the processors taking into account the real-time performance times τ1 to τ5 required by the It is determined whether or not (more details will be described later).

  FIG. 3 shows the structure of the task management information 20 held by each of the tasks T1 to T8. The task management information 20 includes real-time flag information a1 indicating whether or not the processing requires real-time performance, real-time performance information a2 indicating performance necessary for guaranteeing real-time performance, and processing performance indicating actual processing performance. Information a3.

  As for the real-time flag information a1, “1” is set to indicate that the process requires real-time performance, and “0” is set to indicate that the process does not require real-time performance.

  The real-time performance information a2 represents the time required for processing when the task Ti (i = 1, 2,... N) must be completed within a certain time. Specifically, it corresponds to the real-time performance time τi (i = 1, 2,... N), and in this operation example, the unit is ms (millisecond).

  The processing performance information a3 is a load amount (processing amount) of the task Ti, specifically corresponds to the processing performance value Φi (i = 1, 2,... N), and is represented by KI (Kilo This corresponds to the number of instructions in units of “Instructions: 1000 instructions”.

  For each task Ti (i = 1, 2,... N), the operating system 10 is based on the respective real-time flag information a1, and is a performance guarantee task α that requires real-time performance or a performance non-guaranteed task that does not require real-time performance. It is determined whether it is β, and the performance assurance task α in the determination result is sent to the processor Pj (j = 1, 2... m) while guaranteeing the real-time performance based on the real-time performance information a2 and the processing performance information a3. Among the allocation methods, the allocation method is determined so that the number of processors used is minimized, and the performance guarantee task α is allocated to an appropriate processor according to the allocation method of the determination result. This assignment includes reassignment. Here, two processes are performed: a process for determining whether the performance guarantee task α is a performance non-guaranteed task β and a process for assigning a performance guarantee task in a state where the number of processors used is minimized. The processing is performed by the allocation control means E1 in the operating system 10.

  Hereinafter, a method in which the operating system 10 performs reallocation to a processor while guaranteeing real-time performance will be described.

  FIG. 4 shows the specific contents of the task management information 20 for the first to eighth tasks T1 to T8, and FIG. 5 shows the processing capability qj (j per unit time of the first to fourth processors P1 to P4. = 1, 2... 4) shows an example of the MIPS value.

  The first task T1 assigned to the first processor P1 corresponds to a performance guarantee task α that requires real-time performance. Looking at the task management information 20 of the first task T1, the real-time flag information a1 is “1”. The real-time performance time τ1 that is real-time performance information a2 is 10 ms, and the processing performance value Φ1 that is processing performance information a3 is 50 KI (Kilo Instructions) (τ1 = 10 ms, Φ1 = 50 KI). Similarly, the fifth task T5 assigned to the first processor P1 also corresponds to the performance guarantee task α, and the real-time flag information a1 is “1”. The real-time performance time τ5 is also 10 ms, and the processing performance value Φ5 is 10 KI (τ5 = 10 ms, Φ5 = 10 KI).

  The second task T2 assigned to the second processor P2 corresponds to the performance guarantee task α, and the real-time flag information a1 is “1”. The real-time performance time τ2 is 12 ms, and the processing performance value Φ2 is 60 KI (τ2 = 12 ms, Φ2 = 60 KI). Similarly, the sixth task T6 assigned to the second processor P2 corresponds to a performance non-guaranteed task β for which real-time performance is not required, and the real-time flag information a1 is “0”. Further, the real-time performance time τ6 is 0 ms, and the processing performance value Φ6 is 0 KI (τ6 = 0 ms, Φ6 = 0 KI).

  The third task T3 assigned to the third processor P3 corresponds to the performance guarantee task α, and the real-time flag information a1 is “1”. The real-time performance time τ3 is 12 ms, and the processing performance value Φ3 is 50 KI (τ3 = 12 ms, Φ3 = 50 KI). Similarly, the seventh task T7 assigned to the third processor P3 corresponds to the performance non-guaranteed task β, and the real-time flag information a1 is “0”. The real-time performance time τ7 is 0 ms, and the processing performance value Φ7 is 0 KI (τ7 = 0 ms, Φ7 = 0 KI).

  The fourth task T4 assigned to the fourth processor P4 corresponds to the performance guarantee task α, and the real-time flag information a1 is “1”. The real-time performance time τ4 is 10 ms, and the processing performance value Φ4 is 40 KI (τ4 = 10 ms, Φ4 = 40 KI). Similarly, the eighth task T8 assigned to the fourth processor P4 corresponds to the performance non-guaranteed task β, and the real-time flag information a1 is “0”. The real-time performance time τ8 is 0 ms, and the processing performance value Φ8 is 0 KI (τ8 = 0 ms, Φ8 = 0 KI).

  Referring to FIG. 5, the MIPS value of the processing capacity q1 per unit time of the first processor P1 is 10 MIPS, and similarly, the processing capacities q2, q3 of the second to fourth processors P2, P3, and P4 per unit time. All of the MIPS values of q4 are 10 MIPS (q1 = q2 = q3 = q4 = 10MIPS). MIPS (Million Instructions Per Second) is a unit representing the processing capacity of a computer, and 1 MIPS is a processing capacity for executing 1 million instructions per second.

  The allocation control means E1 in the operating system 10 refers to the real-time performance information a2 and the processing performance information a3, determines that it is necessary to execute 50 KI processing within 10 ms for the first task T1, and the second For task T2, it is determined that 60 KI processing needs to be executed within 12 ms, for third task T3 it is determined that 50 KI processing needs to be executed within 12 ms, and for fourth task T4 Determines that it is necessary to execute 40 KI processing within 10 ms, and determines that it is necessary to execute 10 KI processing within 10 ms for the fifth task T5.

  Furthermore, the assignment control means E1 determines that each of the first to fifth tasks T1 to T5 whose real-time flag information a1 is “1” should be the target of task reassignment to the processor. Reassignment of tasks to the processors is performed by the processing performance values Φ1 to Φ5 of the individual tasks T1 to T5 and the remaining performance Mj (j = 1, 2,...) Of the individual processors Pj (j = 1, 2,. Based on the comparison with 4).

  Here, the remaining performance Mj (j = 1, 2,... M) of the processor Pj will be described with reference to FIG.

The processing capability value Wj of the processor Pj taking into account the real-time performance time τi of the task Ti (Ta, Tb) is obtained by multiplying the processing capability qj per unit time of the processor Pj by the real-time performance time τi.
Wj = qj × τi
It is. This processing capability value Wj corresponds to a rectangular area (total area) surrounded by a thick line in the figure. The horizontal width of the rectangle represents the processing capability qj of the processor Pj per unit time, and the vertical axis direction is the time axis direction. In this way, the factor in the time axis direction is taken into consideration, which is a point for comparison with the prior art.

Processing corresponding to the real-time performance time τ1 of the first processor P1, where q1 is the processing capacity per unit time of the first processor P1, and τ1 is the real-time performance time of the performance guarantee task T1 assigned to the first processor P1 The ability value W1 is
W1 = q1 × τ1
It becomes.

Processing corresponding to the real-time performance time τ2 of the second processor P2, where q2 is the processing capacity per unit time of the second processor P2, and τ2 is the real-time performance time of the performance guarantee task T2 assigned to the second processor P2. The ability value W2 is
W2 = q2 × τ2
It becomes.

Processing corresponding to the real-time performance time τ3 of the third processor P3, where q3 is the processing capacity per unit time of the third processor P3 and τ3 is the real-time performance time of the performance guarantee task T3 assigned to the third processor P3 The ability value W3 is
W3 = q3 × τ3
It becomes.

Processing corresponding to the real-time performance time τ4 of the fourth processor P4, where q4 is the processing capacity per unit time of the fourth processor P4 and τ4 is the real-time performance time of the performance guarantee task T4 assigned to the fourth processor P4 The ability value W4 is
W4 = q4 × τ4
It becomes. In the four processors P1 to P4 in the multiprocessor system, the processing capabilities q1 to q4 per unit time are generally equal to each other (q1 = q2 = q3 = q4).

In the example of FIG. 4, the processing capability value W1 of the first processor P1 is obtained by multiplying the processing capability q1 = 10 MIPS per unit time by the real-time performance time τ1 = 10 ms.
W1 = 10 MIPS × 10 ms = 100 KI
(Refer to the leftmost block in FIG. 7A).

In FIG. 6, assuming that the performance assurance tasks assigned to the processor Pj are Ta and Tb, the processing performance value of the task Ta is Φa, and the processing performance value of the task Tb is Φb, the processing of the currently assigned performance assurance tasks Ta and Tb The total performance value ΣΦi is
ΣΦi = Φa + Φb
It becomes. The total processing performance value ΣΦi of the first processor P1 corresponds to the filled portion inside the bold rectangle in FIG. In the example of FIG.
ΣΦi = Φ1 + Φ5 = 50 KI + 10 KI = 60 KI
(Refer to the leftmost block in FIG. 7A).

In FIG. 6, the remaining performance Mj of the processor Pj is determined from the processing capability value Wj (= qj × τi) of the processor Pj taking into consideration the real-time performance time τi of the task Ti (Ta, Tb). The processing performance value sum ΣΦi is subtracted.
Mj = Wj−ΣΦi
= Qj × τi−ΣΦi
= Qj × τi− (Φa + Φb)
It becomes. In other words, the surplus performance Mj is obtained by multiplying the processing capability qj (MIPS value) per unit time of the processor Pj by the value of the real-time performance time τi of the task to be determined, based on the task assigned to the processor Pj. Addition result (total processing performance value ΣΦ
i) is subtracted (remaining power performance Mj = qj × τi−ΣΦi). The remaining capacity Mj is
In FIG. 6, this corresponds to the white portion inside the bold rectangle.

The allocation control means E1 first searches for a processor that has the minimum surplus performance Mj (= qj × τi−ΣΦi).

Here, with respect to the examples of FIGS. 4 and 5, the remaining capacity performances M1 to M4 of the first to fourth processors P1 to P4 are obtained. The calculation formula is
M1 = W1- (Φ1 + Φ5) = q1 × τ1- (Φ1 + Φ5)
M2 = W2- (Φ2 + Φ6) = q2 × τ2-Φ2
M3 = W3- (Φ3 + Φ7) = q3 × τ3-Φ3
M4 = W4- (Φ4 + Φ8) = q4 × τ4-Φ4
It becomes.

Hereinafter, a specific operation example will be described with reference to FIG. FIG. 7 is an operation explanatory diagram of the power saving control device according to the first embodiment. In FIG. 7, the vertical widths of the first processor P1 and the fourth processor P4 are equal to each other, and the vertical widths of the second processor P2 and the third processor P3 are equal to each other. The vertical axis width is different between the time (time = 10 ms) and the latter (real time performance time = 12 ms). Substituting specific numerical values into a series of expressions for the above-described remaining capacity Mj, the remaining capacity M1 of the first processor P1 is
M1 = q1 × τ1- (Φ1 + Φ5)
= [(10 MIPS × 10 ms) − (50 KI + 10 KI)]
= 100KI-60KI = 40KI
(See the bottom row in FIG. 4 and the leftmost block in FIG. 7A).

The remaining capacity M2 of the second processor P2 is
M2 = [(10 MIPS × 12 ms) − (60 KI + 0 KI)] = 60 KI
The remaining capacity M3 of the third processor P3 is
M3 = [(10 MIPS × 12 ms) − (50 KI + 0 KI)] = 70 KI
The remaining capacity M4 of the fourth processor P4 is
M4 = [(10 MIPS × 10 ms) − (40 KI + 0 KI)] = 60 KI
It becomes.

  Thus, the remaining performances M1 to M4 of the four processors P1 to P4 are obtained.

  Here, the allocation control means E1 searches for a processor having the minimum value of the remaining capacity Mj. Among the remaining power performances M1 to M4 (40 KI, 60 KI, 70 KI, 60 KI) of the first to fourth processors P1 to P4, the minimum remaining power performance is the remaining power performance M1 of the first processor P1 = 40 KI. In other words, the processor having the minimum surplus performance is the first processor P1.

  Next, the allocation control means E1 searches for the possibility of reassignment. That is, the tasks assigned to the second, third, and fourth processors P2, P3, and P4 other than the first processor P1 corresponding to the minimum surplus performance M1 = 40 KI are the second task T2, the third task Task T3 and fourth task T4. With respect to these three tasks T2, T3, and T4, whether there is a task that can be reassigned to the first processor P1 is searched based on the remaining performance M1 = 40 KI of the first processor P1.

  Since the second task T2 has a processing performance value Φ2 of 60 KI and is larger than the surplus performance M1 of the first processor P1 = 40 KI, it cannot be reassigned to the first processor P1.

  The third task T3 has a processing performance value Φ3 of 50 KI and is still larger than the remaining capacity M1 = 40 KI of the first processor P1, and therefore cannot be reassigned to the first processor P1.

  The fourth task T4 has a processing performance value Φ4 of 40 KI and falls within the size range of the surplus performance M1 of the first processor P1 = 40 KI. Therefore, it can be reassigned to the first processor P1. .

  Therefore, as indicated by the arrows from FIG. 7A to FIG. 7B, the fourth task T4 that has been assigned to the fourth processor P4 so far is reassigned (moved) to the first processor P1. To do. As a result of this reassignment, the surplus performance M1 of the first processor P1 becomes 0 KI, and the processor assignment of the fourth processor P4 is canceled.

With the above,
The remaining capacity M1 of the first processor P1 is M1 = 0 KI (full allocation)
The remaining capacity M2 of the second processor P2 is M2 = 60 KI (no change)
The remaining capacity M3 of the third processor P3 is M3 = 70 KI (no change)
The remaining capacity M4 of the fourth processor P4 is M4 = 100 KI (assignment cancellation)
It becomes.

  As a result, the next processor with the smallest surplus performance is the second processor P2 with 60 KI. Hereinafter, a description will be given with reference to FIG.

  The task assigned to other than the second processor P2 corresponding to the minimum remaining power performance M2 = 60 KI is the third task T3. Whether or not this task T3 is a reassignable task is searched based on the remaining performance M2 = 60 KI of the second processor P2.

  Since the third task T3 has a processing performance value Φ3 of 50 KI and falls within the size range of the remaining performance M2 of the second processor P2 = 60 KI, it can be reassigned to the second processor P2. .

  Therefore, as indicated by the arrows from FIG. 7B to FIG. 7C, the third task T3 that has been assigned to the third processor P3 so far is reassigned (moved) to the second processor P2. To do. As a result of this reassignment, the remaining capacity M2 of the second processor P2 becomes 10 KI, and the processor assignment of the third processor P3 is canceled.

With the above,
The remaining capacity M1 of the first processor P1 is M1 = 0 KI (full allocation)
The remaining capacity M2 of the second processor P2 is M2 = 10 KI (decrease)
The remaining capacity M3 of the third processor P3 is M3 = 120 KI (assignment cancellation)
The remaining capacity M4 of the fourth processor P4 is M4 = 100 KI (assignment cancellation)
It becomes.

  When reassigned as described above, the first task T1, the fifth task T5, and the fourth task T4 are assigned to the first processor P1, and the second task T2 and the sixth task T4 are assigned to the second processor P2. The task T6 and the third task T3 are assigned, the seventh processor T3 is assigned to the third processor P3, and the eighth task T8 is assigned to the fourth processor P4. If attention is paid only to the performance guarantee tasks T1 to T5 and the performance non-guarantee tasks T6 to T8 are ignored, the first task T1, the fifth task T5, and the fourth task T4 are allocated to the first processor P1, A second task T2 and a third task T3 are assigned to the second processor P2, and no assignment is made to the third processor P3 and the fourth processor P4. As a result, there are no more reassignable performance assurance tasks.

  When the above assignment control means E1 completes the assignment and reassignment of tasks to processors, the operation state control means E2 is activated next, and the third processor P3 and the fourth processor 4 in which the performance guarantee task assignment is canceled The power saving state is applied to the operation state of the processor P4. Here, the operation state control means E2 controls the clock controller 4 to stop the supply of clocks to the third processor P3 and the fourth processor P4. Since the performance guarantee task α is not assigned to the third processor P3 and the fourth processor P4, there is no problem in stopping the supply of the clock.

  FIG. 8 shows the result of task reassignment (movement) starting from the state of FIG. 4 as described above. The first to fifth tasks T1 to T5 in which the real-time flag information a1 is “1” are aggregated into the first processor P1 and the second processor P2, and an allocation that minimizes the number of processors used is performed. It has been realized.

  FIG. 9 is a flowchart showing the operation of the power saving control apparatus according to the first embodiment. The operation will be described below according to this flowchart.

  First, in step S1, the allocation control means E1 of the operating system 10 searches for a processor having a minimum surplus performance Mj. More details are as follows.

The remaining performance Mj is obtained as a difference between the processing capability value Wj and the processing performance value sum ΣΦi (Mj
= Wj-ΣΦi). The processing capability value Wj is obtained by multiplying the processing capability qj per unit time of the processor Pj by the real-time performance time τi (Wj = qj × τi). That is, the remaining capacity performance Mj is
Mj = qj × τi−ΣΦi
Ask according to. In step S1, a processor having a minimum value of the surplus performance Mj is searched.

  Next, in step S2, a search is made as to whether there is a task (task A) that can be reassigned while the performance is guaranteed to the processor searched in step S1 among the tasks assigned to another processor. In the above operation example, the task T4 assigned to the fourth processor P4 corresponds.

  Step S3 is a process of branching according to whether or not a reassignable task (task A) exists in the result searched in step S2. If it is determined that there is a reassignable task (task A), the process branches to step S4. If it is determined that there is no reassignable task (task A), the process branches to step S5.

  In step S4, the reassignable task (task A) is moved to the processor searched in step S1, and the process proceeds to step S2 again.

  When the loop of steps S2, S3, and S4 is repeated, the process of searching for a reassignable task for the processor obtained in step S1 is completed, and the process proceeds from step S3 to step S5.

  In step S5, it is determined whether or not there is a processor task that has not been reassigned. If it is determined that there is a processor task that has not yet been reassigned, the processor task that has not yet been reassigned is re-stepped. The same steps are repeated from S1.

  If it is determined in step S5 that there are no unassigned processor tasks, the process proceeds to step S6. In step S6, the operation state control means E2 reduces power consumption by stopping the clock supply via the clock control unit 4 for the unused processor whose real-time flag information a1 is assigned with the task “1”. To do.

  As described above, in the power saving control device according to the first embodiment, the real-time performance time τi (i = 1) required by the performance guarantee task Ti allocated to each processor Pj (j = 1, 2,... M). , 2... N) is used as the element value taking into account the processor Pj's processing capability value Wj, and the allocation control means E1 processes the processing performance value Φi (i = 1) of each performance assurance task Ti to be allocated to each processor Pj. , 2... N) and the processing capability values Wj (j = 1, 2,... M) of the processor Pj, so that each performance assurance task is minimized so that the number of processors used is minimized. It is configured to control allocation of Ti to each processor Pj. More specifically, the processing performance value Φi of the performance assurance task Ti to be determined is compared with the remaining performance Mj of the other processor Pj, and the processing performance value Φi of the performance assurance task Ti to be determined is the remaining performance Mj of the other processor Pj. The performance guarantee task to be determined is reassigned to another processor having a surplus at the following time. The operation state control unit E2 is configured to apply the power saving state to the operation state of the unused processor in which the assignment of the performance guarantee task Ti is canceled as a result of the assignment by the assignment control unit E1. As a result, according to the power saving control device of the first embodiment, in a multiprocessor system in which a performance guarantee task and a performance non-guarantement task are mixed, a temporally changing element value is constantly monitored, While guaranteeing real-time performance without always keeping the processor operating state under control and without assuming that the processor load becomes low over time as in the prior art Power consumption can be effectively reduced.

  Instead of stopping the clock supply to the unused processor whose performance assurance task assignment has been eliminated, the frequency may be lowered (low clock mode) (* 1).

  In addition, the processor operating mode may be changed, and the processor clock supply may be changed from the low clock mode to the high clock mode for the operating mode of the used processor for which the performance guarantee task assignment has been confirmed. The power state may be changed to the normal operation state (* 2).

  Note that the memory allocated to the unused processor for which the allocation of the performance guarantee task is eliminated may be reassigned to the used processor to which the performance assurance task is allocated. Alternatively, the cache mode of the unused processor in which the performance guarantee task assignment is canceled may be changed. For example, in a cache having a snooping function, it is monitored whether the memory contents do not match the cache contents by DMA or the like from a peripheral device, and if it does not match, the cache contents are discarded. Yes. Therefore, the snoop mode of the cache is stopped for the unused processor for which the performance guarantee task assignment has been eliminated. By stopping the snoop mode, the total task distribution processing efficiency of the multiprocessor system can be increased (* 3).

  In the first embodiment, the performance non-guaranteed task is determined based on the real-time flag information a1. For example, a task whose real-time performance information a2 or processing performance information a3 has a value of “0” is regarded as a performance non-guaranteed task. It may be judged (* 4).

In the first embodiment, in step S1, the remaining capacity Mj (= qj × τi−ΣΦi
) Is searched for, but priority may be given to the processor having the maximum surplus performance Mj, or the search may be simply performed in ascending or descending order of the processor numbers (* 5).

  9 includes a loop process (S2 → S3 → S4 → S2..., S1 → S2 → S3 → S5 → S1...), The loop processing time may be long. is there. Therefore, it may be configured to separately perform a process of determining whether to execute the steps of the flowchart shown in FIG. 9 (that is, determining whether to shift the process to “start” in FIG. 9). (* 6).

  In the first embodiment, the allocation control means E1 and the operation state control means E2 are configured with an operating system 10 that is a functional combination of the CPU 1, the ROM 2, and the RAM 3, but a dedicated DSP is used instead of the operating system 10. (Digital Signal Processor) may be used (* 7).

(Embodiment 2)
The second embodiment of the present invention is configured to reallocate a performance guarantee task to a processor on the condition that there is no contention for resources used by the performance guarantee task.

  For the configuration of the power saving control device in the multiprocessor system of the second embodiment, FIG. 1 in the case of the first embodiment is used.

  FIG. 10 shows the structure of the task management information 20 held by each of the tasks T1 to T8 in the case of the second embodiment. In addition to the real-time flag information a1, the real-time performance information a2, and the processing performance information a3 in FIG. 3 in the case of the first embodiment, the task management information 20 includes used resource information a4 indicating resources used by each task. keeping.

  FIG. 11 shows the specific contents of the task management information 20 for the first to eighth tasks T1 to T8 in the case of the second embodiment. As for the MIPS value, which is the processing capability qj (j = 1, 2,..., 4) per unit time of the first to fourth processors P1 to P4, FIG.

  In FIG. 11, the difference from FIG. 4 in the case of the first embodiment is the real-time performance time τi. In the case of the first embodiment (FIG. 4), the real-time performance times τ1 and τ4 of the first and fourth processors P1 and P4 are equal to 10 ms, and the real-time performance of the second and third processors P2 and P3. Times τ2 and τ3 are equally 12 ms. There is a difference between τ1, τ4 and τ2, τ3. On the other hand, in the second embodiment, the real-time performance times τ1 to τ5 of all the performance guarantee tasks αT1 to T5 are equal to each other and are all 10 ms.

  FIG. 12A corresponds to FIG. In comparison with FIG. 4, the real-time flag information a1 is the same, and the real-time performance time τi and the processing performance value Φi are the same in the first task T1, the fourth task T4, and the fifth task T5. It is. The second task T2 and the third task T3 are different. That is, in the second task T2, the real-time performance time τ2 is 10 ms, and the processing performance value Φ2 is 40 KI (τ2 = 10 ms, Φ2 = 40 KI). In the third task T3, the real-time performance time τ3 is 10 ms, and the processing performance value Φ3 is 30 KI (τ3 = 10 ms, Φ3 = 30 KI).

  In the second embodiment, the allocation control means E1 of the operating system 10 refers to the used resource information a4, determines that the first task T1 uses the resource A and the resource B, and the second task T2 C and resource D are determined to be used, the third task T3 is determined to use resource A and resource C, the fourth task T4 is determined to use resource B and resource D, and the fifth task T5 is It is determined that the resource E is used.

The remaining performance Mj (= qj × τi−ΣΦi) is the same as that in the first embodiment. That is, the remaining capacity of the first processor P1 is M1 = 40 KI, the remaining capacity of the second processor P2 is M2 = 60 KI, the remaining capacity of the third processor P3 is M3 = 70 KI, and the remaining capacity of the fourth processor P4 is M4 = 60 KI. Again, it is the first processor P1 that has the minimum surplus performance.

  The allocation control means E1 searches for the possibility of reassignment. That is, the tasks assigned to the second, third, and fourth processors P2, P3, and P4 other than the first processor P1 corresponding to the minimum surplus performance M1 = 40KI are the second task T2, the third task Task T3 and fourth task T4, but for these three tasks T2, T3, and T4, there are tasks that do not compete with resources A, B, and E used by the first processor P1, which is the comparison criterion Search if you want to. The resources used by the third processor P3 are A and C, and the resource A competes. The resources used by the fourth processor P4 are B and D, and the resource B competes. On the other hand, the resources used by the second processor P2 are C and D, and do not compete with the resources A, B, and E used by the first processor P1. Therefore, the second processor P2 having no resource contention is selected as a reassignment candidate.

  Therefore, as shown by the arrows from FIG. 12A to FIG. 12B, the second task T2 that has been assigned to the second processor P2 until then is reassigned (moved) to the first processor P1. To do. As a result of this reassignment, the remaining capacity M1 of the first processor P1 becomes 0 KI, and the processor assignment of the second processor P2 is canceled.

With the above,
The remaining capacity M1 of the first processor P1 is M1 = 0 KI (full allocation)
The remaining performance M2 of the second processor P2 is M2 = 100 KI (assignment cancellation)
The remaining capacity M3 of the third processor P3 is M3 = 70 KI (no change)
The remaining capacity M4 of the fourth processor P4 is M4 = 60 KI (no change)
It becomes.

  As a result, the next processor with the smallest surplus performance is the fourth processor P4 with 60 KI. Hereinafter, a description will be given with reference to FIG.

  The task assigned to other than the fourth processor P4 corresponding to the minimum remaining power performance M4 = 60 KI is the third task T3. The task T3 is searched for whether or not it is a reassignable task on the basis of the remaining capacity M4 = 60 KI of the fourth processor P4.

  Since the third task T3 has a processing performance value Φ3 of 30 KI and falls within the size range of the remaining performance M4 of the fourth processor P4 = 60 KI, it can be reassigned to the fourth processor P4. . The resources used by the fourth task T4 of the fourth processor P4 are the resource B and the resource D, and the resource A and the resource C used by the third task T3 do not compete.

  Therefore, as indicated by the arrows from FIG. 12B to FIG. 12C, the third task T3 that has been assigned to the third processor P3 so far is reassigned (moved) to the fourth processor P4. To do. As a result of this reassignment, the remaining capacity M4 of the fourth processor P4 becomes 30 KI, and the processor assignment of the third processor P3 is canceled.

With the above,
The remaining capacity M1 of the first processor P1 is M1 = 0 KI (full allocation)
The remaining performance M2 of the second processor P2 is M2 = 100 KI (assignment cancellation)
The remaining capacity M3 of the third processor P3 is M3 = 100 KI (assignment cancellation)
The remaining capacity M4 of the fourth processor P4 is M4 = 30 KI (decrease)
It becomes.

  In the above reassignment, when focusing only on the performance guarantee tasks T1 to T5, the first processor T1, the fifth task T5, and the second task T2 are assigned to the first processor P1, and the fourth processor P4. Are assigned the fourth task T4 and the third task T3, and the second processor P2 and the third processor P3 are not assigned. As a result, there are no more reassignable performance assurance tasks.

  When the above assignment control means E1 completes the process of assigning and reassigning tasks to processors, the operation state control means E2 is activated next, and the second processor P2 and the third processor 3 in which the performance guarantee task assignment is canceled The power saving state is applied to the operating state of the processor P3. Here, the operation state control means E2 controls the clock control unit 4 to stop the supply of clocks to the second processor P2 and the third processor P3. Since the performance guarantee task α is not allocated to the second processor P2 and the third processor P3, there is no problem in stopping the supply of the clock.

  FIG. 13 shows the result of task reassignment (movement) starting from the state shown in FIG. 11 as described above. The first to fifth tasks T1 to T5 in which the real-time flag information a1 is “1” are aggregated into the first processor P1 and the fourth processor P4, and an allocation that minimizes the number of processors used is performed. It has been realized.

  FIG. 14 is a flowchart showing the operation of the power saving control apparatus according to the second embodiment. The operation will be described below according to this flowchart. In contrast to FIG. 9 in the case of the first embodiment, step S12 is different from step S2, and the other steps are the same.

First, in step S11, the allocation control means E1 of the operating system 10 searches for a processor having a minimum surplus performance Mj (= qj × τi−ΣΦi).

  Next, in step S12, among the tasks assigned to another processor, among the tasks that can be reassigned while the performance guarantee is possible to the processor searched in step S11, there is no contention of resources to be used ( Search for task B). In the above operation example, the task T2 assigned to the second processor P2 corresponds.

  Step S13 is a process of branching according to whether or not a reassignable task (task B) having no resource conflict exists in the result searched in step S12. If it is determined that there is a reassignable task (task B) without resource conflict, the process branches to step S14. If it is determined that there is no reassignable task (task B) without resource conflict, the process branches to step S15. .

  In step S14, the reassignable task (task B) having no resource conflict is moved to the processor searched in step S11, and the process proceeds to step S12 again.

  When the loop of steps S12, S13, and S14 is repeated, the process of searching for a reassignable task for the processor obtained in step S11 is completed, and the process proceeds from step S13 to step S15.

  In step S15, it is determined whether or not there is a processor task that has not been reassigned. If it is determined that there is a processor task that has not yet been reassigned, the step is performed again for the processor task that has not been reassigned. The same steps are repeated from S11.

  If it is determined in step S15 that there are no unassigned processor tasks, the process proceeds to step S16. In step S16, the operation state control means E2 reduces the power consumption by stopping the clock supply via the clock control unit 4 for the unused processor whose real-time flag information a1 is assigned with the task “1”. To do.

  As described above, according to the second embodiment, resource contention between processors is minimized, so that efficient task processing can be performed.

  In the second embodiment, reallocation is performed so as to minimize contention between processors for resources used by the performance assurance task. Instead, the following embodiment is also effective. .

  That is, a performance guarantee task group that needs to be processed in sequence in the performance guarantee task is reassigned to the same processor as much as possible. With this configuration, the number of dispatches can be minimized.

  In addition, a performance non-guaranteed task is not assigned to a processor to which a performance assurance task is reassigned. With this configuration, the movement of non-guaranteed tasks between processors can be minimized.

  Note that the notes (* 1) to (* 7) in the first embodiment also correspond to the second embodiment.

(Embodiment 3)
The third embodiment of the present invention exemplifies a form in which the power saving control device according to the first and second embodiments is used in a digital still camera (mobile terminal).

  FIG. 15 is a block diagram showing a functional configuration of a digital still camera according to Embodiment 3 of the present invention, and FIG. 16 is a functional explanatory diagram showing functions of a main part of the digital still camera.

  The digital still camera 30 according to the third embodiment includes a CPU 40, a key operation unit 51, a timer unit 52, a camera unit 53, an audio unit 54, and a USB (Universal Serial Bus) interface unit 55. Has been. The key operation unit 51 includes a key determination task T1 and a key execution task T5 that control the key operation unit 51. The timer unit 52 includes a timer task T2 that controls the task. The camera unit 53 includes a camera task T3 that controls the task. The unit 54 includes an audio task T4 that controls this, and the USB interface unit 55 includes USB tasks T6 to T8 that control this. Tasks T1 to T5 correspond to the performance guarantee task α, and tasks T6 to T8 correspond to the performance non-guaranteed task β.

  The CPU 40 includes a multiprocessor system. The multiprocessor system includes a plurality of (here, four) processors, that is, first to fourth processors P1 to P4. The CPU 40 controls the entire digital still camera 30 while processing a plurality of tasks in parallel. Specifically, the CPU 40 reads and executes an operating system program (OS) and various application programs in response to various instruction signals input from the key operation unit 51, and performs a timer unit 52, a camera unit 53, and an audio unit. 54 and the USB interface unit 55 are controlled.

  The operation sequence in the CPU 40 of the digital still camera configured as described above is essentially the same as the operation of the power saving control device according to the first or second embodiment, and thus the description thereof is omitted.

  According to the digital still camera of the third embodiment, it is possible to reduce power consumption and to increase the battery life.

  In addition, as a function of the digital still camera, low power consumption can be achieved by switching between a normal power consumption mode that operates without particularly reducing power consumption and a low power consumption mode that operates with less power consumption. When the power mode is set, the reassignment as in the third embodiment may be performed.

  Further, the transition to the low power consumption mode may be a function that can be set by the user, or the transition to the low power consumption mode may be automatically performed when specific conditions are met.

  Note that the notes (* 1) to (* 7) in the first embodiment also correspond to the third embodiment.

  Other mobile terminals to which this embodiment is applied are battery-powered portable devices that can be carried around. Specifically, cellular phones, PHS (Personal Handy-phone System), PDA (Personal Digital) Assistant), portable game consoles, and other notebook computers. For tasks that run on mobile terminals, call functions, mail functions, Internet functions, game functions, TV phone functions, TV viewing functions, TV recording functions, photo shooting functions, video shooting functions, music playback functions, and various other functions Application.

  In the above embodiments, the case where the present invention is applied to the CPU of a multiprocessor system and a digital still camera has been described. However, the present invention is not limited to these embodiments. The present invention can be realized as an integrated circuit including the multiprocessor system, or as a program that causes a computer to function as the multiprocessor. These programs may be distributed via a recording medium such as a CD-ROM or a communication medium such as the Internet.

  The power saving control device in a multiprocessor system in which performance guarantee tasks and performance non-guaranteed tasks coexist according to the present invention is useful as a technique for effectively reducing power consumption while guaranteeing real-time performance. It is also excellent as a mobile terminal such as a digital still camera.

E1 Allocation control means E2 Operation state control means P1-P4 Processor T1-T8 Task a1 Real-time flag information a2 Real-time performance information a3 Processing performance information a4 Used resource information α Performance assurance task β Performance non-guaranteed task 1 CPU
2 ROM
3 RAM
4 Clock control means 5 Peripheral device 6 Bus 10 Operating system (OS)
20 Task management information 30 Digital still camera 40 CPU
51 Key operation section 52 Timer section 53 Camera section 54 Audio section 55 USB interface section

Claims (22)

In a multiprocessor system that has multiple processors that distribute and process multiple tasks, and that includes both performance guarantee tasks and non-performance guarantee tasks,
The number of processors used based on the correlation between the processing performance value of each performance assurance task to be assigned to each processor and the processing capacity value of the processor taking into account the real-time performance time required by each performance assurance task Assignment control means for controlling the assignment of each performance assurance task to each processor,
A power saving control apparatus in a multiprocessor system, comprising: an operation state control means for applying a power saving state to an operation state of an unused processor whose assignment of the performance guarantee task has been eliminated as a result of assignment by the assignment control means.   2. The allocation control unit according to claim 1, wherein the allocation control unit is configured to determine whether or not the performance guarantee task can be reassigned to another processor, and to perform the reassignment when it is possible. A power-saving control device in a multiprocessor system.   The allocation control means compares the processing performance value of the performance assurance task to be determined with the remaining performance of another processor, and when the processing performance value of the performance assurance task to be determined is equal to or less than the remaining performance of another processor 3. The power saving control device in a multiprocessor system according to claim 2, wherein the performance guarantee task to be determined is reassigned to another processor having a surplus capacity.   4. The multiprocessor system according to claim 1, wherein the processing capacity value of the processor is obtained by multiplying the processing capacity per unit time of the processor by the real-time performance time of the performance guarantee task. Power-saving control device.   The surplus performance of the processor is obtained by subtracting the sum of the processing performance values of the performance assurance tasks already assigned to the processor from the processing capacity value of the processor taking into account the real-time performance time of the performance assurance task. A power saving control device in a multiprocessor system according to claim 3 or 5.   The power saving in the multiprocessor system according to any one of claims 1 to 5, wherein the allocation control unit is configured to minimize the movement of the performance guarantee task for the reallocation between processors. Control device.   The allocation control unit is configured to perform the reassignment with priority given to minimizing contention between processors of resources used by the performance guarantee task when the performance guarantee task is reassigned to another processor. The power saving control device in the multiprocessor system according to any one of claims 2 to 6.   The multi-assignment according to any one of claims 2 to 6, wherein the assignment control unit is configured to pre-assign a performance guarantee task group that needs to be processed in a sequential manner to the same processor. A power saving control device in a processor system.   The assignment control means, when reassigning the performance non-guaranteed task between processors after reassigning the performance guarantee task, to the processor on which the performance guarantee task has been reassigned 9. The power saving control apparatus in a multiprocessor system according to claim 1, wherein reassignment is performed in a state in which reassignment of the performance non-guaranteed task is prohibited.   The multiprocessor system according to any one of claims 1 to 9, wherein the operation state control means is configured to change an operation mode of an unused processor in which assignment of a performance guarantee task has been canceled. Power control device.   11. The power saving control device in a multiprocessor system according to claim 10, wherein changing the operation mode of the unused processor for which the assignment of the performance guarantee task has been canceled is stopping the clock supply to the unused processor.   The power saving in the multiprocessor system according to any one of claims 1 to 9, wherein the operation state control means is configured to change an operation mode of a processor in use for which assignment of a performance guarantee task is fixed. Control device.   Changing the operating mode of the processor in use for which the assignment of the performance guarantee task is fixed means changing the state of the processor to be used from the low power consumption state to the normal operation state or from the normal operation state to the high speed operation state. The power saving control device in the multiprocessor system according to claim 12, wherein   The power-saving control device in a multiprocessor system according to any one of claims 1 to 13, wherein the operation state control means is configured to dynamically change allocation of a memory to a processor.   15. The power saving control apparatus in a multiprocessor system according to claim 14, wherein dynamically changing the allocation of the memory to the processor is to reallocate the memory allocated to the unused processor to the used processor.   The power saving control device in a multiprocessor system according to any one of claims 1 to 15, wherein the operation state control means is configured to change a snoop mode of a cache having a snooping function.   17. The power saving control device in a multiprocessor system according to claim 16, wherein changing the snoop mode of the cache having the snooping function is to stop the cache snoop mode of the unused processor.   The operation state control unit changes the operation state of the peripheral device in place of or together with the unused processor in which the allocation of the performance guarantee task is canceled as a result of the allocation by the allocation control unit. The power saving control device in the multiprocessor system according to any one of claims 1 to 17, wherein the power saving control device is configured.   A mobile terminal equipped with the power saving control device in the multiprocessor system according to any one of claims 1 to 18.   A normal operation mode that operates in a normal operation state and a low power consumption mode that operates in a low power consumption state are provided, and the allocation control unit and the operation state control unit are activated only in the case of the low power consumption mode. The mobile terminal according to claim 19, which is configured.   The mobile terminal according to claim 20, wherein a user can set the normal operation mode and the low power consumption mode.   The mobile terminal according to claim 20, wherein the normal operation mode and the low power consumption mode are configured to be switched when the remaining power amount of the battery becomes equal to or less than a certain level.

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