JP2010276783A - Active matrix type display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an active matrix type display for achieving good display, and also, reducing power consumption. <P>SOLUTION: The active matrix type display includes a plurality of pixel parts PX arranged in matrix, and a plurality of high-potential power supply lines PVDD having potential different from one another. Each of the pixel parts includes: a display element 16, one electrode of which is connected to a low-potential power supply line; and a plurality of pixel circuits 18 for driving the display element. Each of the pixel circuits of the pixel parts includes: a drive transistor DRT; an output switch BCT having a second terminal which is connected to one of the high-potential power supply lines; a pixel switch SST; and a holding capacitance C. With respect to each of the pixel circuits, each pixel part has a writing period for writing a gradation image voltage signal in the driving transistor, and a plurality of light emission periods divided in accordance with a control signal changing stepwise, for allowing the display elements to selectively emit light in accordance with the written gradation image voltage signals. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an active matrix display device, and more particularly to an active matrix display device that performs signal writing using a digital voltage signal.

  In recent years, the demand for flat display devices typified by liquid crystal display devices has been rapidly increased by taking advantage of the features of thinness, light weight, and low power consumption. In particular, an active matrix display device in which a pixel switch having a function of electrically separating an on pixel and an off pixel and holding a video signal to the on pixel is provided in each pixel has crosstalk between adjacent pixels. Since a good display quality without any problem can be obtained, it has come to be used for various displays including portable information devices.

  As such a flat-type active matrix display device, an organic electroluminescence (EL) display device using a self-luminous element has attracted attention, and research and development has been actively conducted. This organic EL display device does not require a backlight that obstructs the reduction in thickness and weight, is suitable for moving image reproduction because of its high-speed response, and further has a feature that it can be used even in cold regions because the luminance does not decrease at low temperatures. .

  In general, an organic EL display device includes a plurality of display pixels arranged in a plurality of rows and a plurality of columns and constituting a display screen, a plurality of scanning lines extending along each row of display pixels, and a column of display pixels. A plurality of extended video signal lines, a scanning line driving circuit for driving each scanning line, a signal line driving circuit for driving each video signal line, and the like are provided. Each display pixel includes an organic EL element that is a self-light emitting element and a pixel circuit that supplies a drive current to the organic EL element, and performs a display operation by controlling the light emission luminance of the organic EL element. Each pixel circuit includes a driving transistor or the like that is connected in series between the organic EL element and the power supply line, and controls the amount of current that flows through the organic EL element based on a video signal.

  For supplying image information to the pixel circuit, a method using a current signal (for example, Patent Document 1) and a method using a voltage signal (for example, Patent Document 2) are known.

US Pat. No. 6,373,454 B1 US Pat. No. 6,229,506 B1

  In any of the current signal type and voltage signal type organic EL display devices as described above, according to variations in characteristics of drive transistors formed by thin film transistors (hereinafter referred to as TFTs), in particular, variations in mobility. There is a problem that display unevenness is visually recognized. Further, since the drive transistor operates in a saturation region, there is a problem that the TFT applied voltage required for the light emission operation increases, and the power consumption of the drive transistor increases.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide an active matrix display device capable of realizing good display and reducing power consumption.

  In order to achieve the above object, an active matrix display device according to an aspect of the present invention includes a plurality of video signal lines arranged in parallel and a plurality of first scans extending in a direction intersecting the video signal lines. Line, second scanning line, and third scanning line, a plurality of high potential power supply lines set to different potentials, a low potential power supply line, and the first scanning line and the third scanning line are turned on and off. A scanning line driving circuit that outputs a control signal whose potential changes stepwise to the second scanning line, and a signal line that outputs a video voltage signal of a plurality of gradations to the video signal line A plurality of pixel portions each having a driving circuit, a display element having one electrode connected to the low-potential power line, and a plurality of pixel circuits for driving the display element, arranged in a matrix; , Multiple images of each pixel The circuit includes a driving transistor having a second terminal connected to the other electrode of the display element, a second terminal connected to the first terminal of the driving transistor, and a second terminal connected to the plurality of high potential power lines. An output switch connected to one of the plurality of high potential power lines, a gate connected to the third scanning line, a second terminal connected to the video signal line, and a first terminal connected to the gate of the driving transistor. A pixel switch having a gate connected to the first scan line, a storage capacitor having one electrode connected to the gate of the drive transistor and the other electrode connected to the second scan line. Each pixel unit includes a writing period for writing a grayscale video voltage signal from the video signal line to the drive transistor via the pixel switch for each of a plurality of pixel circuits, and the stage. A plurality of light emission periods that are divided into a plurality according to a control signal that changes in a row and each causes the display element to selectively emit light according to the written gradation video voltage signal. A pixel portion.

  An active matrix display device according to another aspect of the present invention includes a plurality of video signal lines provided in parallel, and a plurality of first scanning lines and second scanning lines respectively extending in a direction intersecting with the video signal lines. A line, a third scanning line, a high-potential power line, a low-potential power line, an on-off potential control signal to the first scanning line and the third scanning line, and a second scanning line, A scanning line driving circuit that outputs a control signal whose potential changes stepwise, and a video voltage signal of a plurality of gradations are output to the video signal line, and a different potential is applied to the high potential power line for each of a plurality of subframes. A plurality of pixel portions each having a signal line driving circuit to be supplied, a display element having one electrode connected to the low-potential power supply line, and a pixel circuit for driving the display element. And the picture The circuit includes a driving transistor having a first terminal connected to the second voltage power source and a second terminal connected to the other electrode of the display element, and a connection between the control terminal of the driving transistor and the second scanning line. A storage capacitor, a pixel switch having a first terminal connected to the control terminal of the driving transistor, a second terminal connected to the video signal line, and a control terminal connected to the first scanning line, and a control terminal Connected to the third scanning line and connected between the second voltage power source and the display element, and an output switch for controlling light emission and non-light emission of the display element, and each pixel unit Has a sub-frame period in which the operation leading to light emission is divided into a plurality of sub-frame periods, and each sub-frame period is written to write a grayscale video voltage signal from the video signal line to the drive transistor via the pixel switch. And a plurality of light emission periods that are divided into a plurality according to the control signal that changes stepwise, and that selectively cause the display element to emit light according to the written gradation video voltage signal. A plurality of pixel portions.

  According to the aspect of the present invention, an active matrix display device capable of realizing good display and reducing power consumption can be obtained.

FIG. 1 is a plan view schematically showing an organic EL display device according to the first embodiment of the present invention. FIG. 2 is a plan view showing an equivalent circuit of display pixels in the organic EL display device. FIG. 3 is a timing chart of supply signals in the scanning line driving circuit of the organic EL display device. FIG. 4 is a diagram showing a relationship between transistor characteristics of a driving transistor and a video signal potential to be written in the organic EL display device. FIG. 5 is a plan view showing an equivalent circuit of a display pixel for explaining a display operation of the organic EL display device. FIG. 6 is another timing chart of the supply signal in the scanning line driving circuit of the organic EL display device. FIG. 7 is a diagram showing the relationship between the write signal potential and the gradation in each display pixel. FIG. 8 is a plan view showing an equivalent circuit of a display pixel in the organic EL display device according to the second embodiment of the present invention. FIG. 9 is a plan view schematically showing an organic EL display device according to the third embodiment of the present invention. FIG. 10 is a plan view showing an equivalent circuit of a display pixel in the organic EL display device according to the third embodiment. FIG. 11 is a timing chart of supply signals during normal display in the scanning line driving circuit of the organic EL display device according to the third embodiment. FIG. 12 is a plan view showing an equivalent circuit of a display pixel for explaining a display operation of the organic EL display device according to the third embodiment. FIG. 13 is another timing chart of the supply signal at the time of normal display in the scanning line driving circuit of the organic EL display device according to the third embodiment. FIG. 14 is a diagram showing a relationship between a write signal potential and a gradation in each display pixel. FIG. 15 is a plan view showing an equivalent circuit of display pixels in an organic EL display device according to a modification of the present invention.

Hereinafter, an organic EL display device will be described in detail as an embodiment of the present invention with reference to the drawings.
(First embodiment)
FIG. 1 shows an organic EL panel 10 of the organic EL display device according to the first embodiment, and FIG. 2 shows an equivalent circuit of display pixels in the organic EL display device.
As shown in FIG. 1, the organic EL display device is configured as, for example, an active matrix display device of two or more types, and includes an organic EL panel 10 and a controller 13 that controls the organic EL panel.

  As shown in FIG. 1, an organic EL panel 10 includes an insulating substrate 8 having light transmissivity, such as a glass plate, and m × n display pixels PX arranged in a matrix on the insulating substrate to form a display region 11. The first scanning line SG (1 to m), the second scanning line Cs (1 to m), which are connected for each row of display pixels and provided independently for each m, and five for each row. A third scanning line BG (1 to m) provided and n video signal lines X (1 to n) connected to each column of the display pixels PX are provided. As will be described later, each display pixel PX has one display element, and each third scanning line BG (1 to m) includes a plurality of scanning lines for each display pixel PX, and each video signal line. X (1 to n) includes a plurality of video signal lines for each display pixel PX.

  The organic EL panel 10 sequentially scans the first, second, and third scanning lines SG (1 to m), Cs (1 to m), and BG (1 to m) for each row of the display pixels PX. Drive circuits 14a and 14b and a signal line drive circuit 15 for driving a plurality of video signal lines X (1 to n) are provided. The scanning line driving circuits 14 a and 14 b and the signal line driving circuit 15 are integrally formed on the insulating substrate 8 outside the display area 11 and constitute a control unit together with the controller 13.

  As shown in FIG. 2, each display pixel PX functioning as a pixel unit includes one display element having a photoactive layer between opposing electrodes, and five pixel circuits 18 a that respectively supply drive current to the display element. 18b, 18c, 18d, and 18e. The display element is, for example, a self-luminous element. In this embodiment, the organic EL element 16 including at least an organic light-emitting layer is used as a photoactive layer. Each display pixel PX is composed of five sub-regions 1, 2, 3, 4, and 5 that are arranged in the row direction, and one pixel circuit is provided in each sub-region.

  The pixel circuits 18a, 18b, 18c, 18d, and 18e are voltage signal type pixel circuits that control light emission of the organic EL element 16 in accordance with a video signal that is a voltage signal. The pixel circuits SST (1-5), drive A transistor DRT (1-5), a holding capacitor C (1-5) as a capacitor, and an output switch BCT (1-5) for controlling on / off of the organic EL element 16 are provided.

  Since the five pixel circuits 18a, 18b, 18c, 18d, and 18e have the same configuration, the pixel circuit 18a in the sub region 1 will be described as a representative. Here, the pixel switch SST1, the drive transistor DRT1, and the output switch BCT1 are formed of thin film transistors of the same conductivity type, for example, a P-channel type. In the present embodiment, the thin film transistors constituting the drive transistors and the switches are all formed in the same process and the same layer structure, and are top gate thin film transistors using polysilicon as a semiconductor layer.

  Each of the pixel switch SST1, the driving transistor DRT1, and the BCT1 has a first terminal, a second terminal, and a control terminal. In the present embodiment, the first terminal, the second terminal, and the control terminal are used as a source, The drain and gate are used.

  In the pixel circuit 18a, the output switch BCT1, the drive transistor DRT1, and the organic EL element 16 are connected in series in this order between the high potential voltage power supply line PVDD1 and the low potential reference voltage power supply line PVSS. The drive transistor DRT1 outputs a drive current having a current amount corresponding to the video signal to the organic EL element 16. The source of the output switch BCT1 is connected to the voltage power supply line PVDD1. The source of the driving transistor DRT1 is connected to the drain of the output switch BCT1, and the drain is connected to one electrode of the organic EL element 16, for example, the anode. The cathode of the organic EL element 16 is connected to the reference voltage power line PVSS.

  The voltage power supply line PVDD1 and the reference voltage power supply line PVSS are set to, for example, potentials of + 5V and −3V, respectively. The voltage power supply line PVDD1 and the reference voltage power supply line PVSS are connected to the signal line drive circuit 15 and supplied with a power supply voltage from the signal line drive circuit.

  The storage capacitor C1 is connected between the gate of the drive transistor DRT1 and the second scanning line Cs1. The holding capacitor C1 holds the gate potential of the driving transistor DRT1, and at the same time changes the gate potential of the driving transistor DRT1 in accordance with the potential change of the second scanning line Cs1 that changes for each of the divided light emission periods. It plays a role of controlling on / off of DRT1.

  The pixel switch SST1 is connected between the corresponding video signal line X1a and the gate of the driving transistor DRT1, and the gate is connected to the corresponding first scanning line SG (1 to m). The pixel switch SST1 controls connection / disconnection between the pixel circuit 18a and the video signal line X1a in response to the control signal Sa (1-m) supplied from the first scanning line SG (1-m), A video voltage signal corresponding to the gradation is written from the corresponding video signal line X1a to the gate potential of the drive transistor DRT1.

  The gate of the output switch BCT1 is connected to the third scanning line BG (1 to m). The output switch BCT1 is ON / OFF controlled in response to a control signal Sc (1 to m) supplied from the third scanning line BG (1 to m), and connects and disconnects the drive transistor DRT1 and the organic EL element 16. Control.

  As described above, each video signal line X (1 to n) is provided with five video signal lines X1 (a to e) for one display pixel PX, and each sub-region 1, 2, 3 is provided. 4 and 5 are connected to the pixel circuit 18. Further, these video signal lines X (a to e) are connected to voltage supply units V <b> 1 to V <b> 5 provided in the signal line driving circuit 15. The five pixel circuits of each display pixel PX are driven by a common first scanning line SG (1-m) and a common second scanning line SG (1-m).

  The third scanning line BG (1 to m) has five scanning lines BG1 (a to e) for each display pixel PX, and is connected to the gates of the output switches BCT1 to BCT1 of the pixel circuits 18a to 18e. . Further, for each display pixel PX, five voltage power supply lines PVDD1 to PVDD5 are provided and connected to the sources of the output switches BCT1 to BCT5 of the pixel circuits 18a to 18e, respectively. The voltage power supply lines PVDD1 to PVDD5 have different potentials, and are set to potentials of +5, +5.2, +5.4, +5.6, and +5.8 V, for example.

  On the other hand, the controller 13 shown in FIG. 1 is formed on a printed circuit board disposed outside the organic EL panel 10 and controls the scanning line driving circuits 14 a and 14 b and the signal line driving circuit 15. The controller 13 receives a digital video signal and a synchronization signal supplied from the outside, and generates a vertical scanning control signal for controlling the vertical scanning timing and a horizontal scanning control signal for controlling the horizontal scanning timing based on the synchronizing signal. The controller 13 supplies the vertical scanning control signal and the horizontal scanning control signal to the scanning line driving circuit and the signal line driving circuit, respectively, and sends the digital video signal to the signal line driving circuit in synchronization with the horizontal and vertical scanning timings. Supply.

  The signal line driving circuit 15 converts the video signal sequentially obtained in each horizontal scanning period into an analog format under the control of the horizontal scanning control signal to obtain a signal wiring voltage, and in parallel with the plurality of video signal lines X (1 to n). Supply. In the signal line driving circuit 15, voltage supply units V1 to V5 functioning as voltage sources output a plurality of gradation voltage signals Vsig corresponding to the image signal to the image signal lines X (1 to n).

The scanning line drive circuits 14a and 14b include a shift register, an output buffer, and the like, sequentially transfer a horizontal scanning start pulse supplied from the outside to the next stage, and pass through the output buffer to the first, second, and third scanning lines. Supply control signals Sa (1-m), Sb (1-m), Sc (1-m) (a-e) to SG (1-m), Cs (1-m), BG (1-m) To do.
Next, the operation of the organic EL display device configured as described above will be described. In driving the organic EL display device, the display pixels Px are sequentially selected for each row, the gradation voltage signal writing operation is performed in the selection period of the display pixels Px, and the light emission operation is performed in the non-selection period. 3 shows a timing chart of the output signals of the scanning line driving circuits 14a and 14b. FIG. 4 shows a relationship between the potential of the control signal Sb (1 to m) and the transistor characteristics of the driving transistor DRT (1 to 4). FIG. 5 shows the operation of the pixel circuit in one sub-region of the display pixel PX.

  For example, the scanning line driving circuits 14a and 14b generate a pulse having a width of one horizontal scanning period (Tw-Starta) corresponding to each horizontal scanning period from a start signal (STV1, STV2) and a clock (CKV1, CKV2). The pulses are output as control signals Sa (1 to m), Sb (1 to m), and Sc (1 to m) (a to e).

Taking the 10-bit gradation as an example, the operation of each pixel circuit in one sub-region of the display pixel PX will be described. The operation of the display pixel PX in one vertical cycle (V) is divided into 1) a writing period, 2) a first light emitting period, 3) a second light emitting period, and 4) a third light emitting period.
1) In the writing period, as shown in FIGS. 3 and 5A, the control signal Sa (1 to m) of the display pixel PX becomes an ON potential (low level) for turning on the pixel switch SST, and the pixel switch SST Is turned on (conducting state). In the writing period, the gradation video voltage signal Vsig is output from the voltage supply unit V of the signal line driving circuit 15 to the video signal lines X (1 to n), and is written in the storage capacitor C via the pixel switch SST. As a result, the gate potential Vg of the drive transistor DRT becomes Vsig.

  As the voltage signal Vsig, a plurality of, for example, four signal line potentials (set potentials) V1, V2, V3, and V4 are digitally written according to the gradation. At this time, the signal line potential is set so as to satisfy the relationship of V1 <V2 <V3 <V4. In the case of having a plurality of, for example, n light emission periods, (n + 1) set potentials are used as the signal line potential. The signal line potentials V1, V2, V3, and V4 are set so that their values change in an arithmetic progression, and the difference (tolerance) ΔVsig between the potentials is set to a constant value, for example, 5v. Yes.

As shown in FIG. 4, V1 is set to a value at which the driving transistor DRT operates in its linear region and is turned on, and V2, V3, and V4 are respectively set to values at which the driving transistor DRT is turned off. Yes.
When the drive transistor DRT is composed of an Nch type transistor, the value of the voltage signal Vsig is set in the reverse relationship, that is, V1>V2>V3> V4.

  Next, as shown in FIGS. 3 and 5B, the control signal Sa (1 to m) is turned off (high level), and the pixel switch SST is turned off. Thereby, the video voltage signal writing operation is completed. At the same time or subsequently, the control signals Sc (1 to m) (a to e) are turned on (low level), the output switches BCT (1 to 5) are turned on, and the first light emission operation is performed. Be started.

  2) In the first light emission period, the drive transistor DRT outputs a drive current Ie having a corresponding amount of current according to the gate control voltage Vg = Vsig written in the storage capacitor C. This drive current Ie is supplied to the organic EL element 16. Thereby, the organic EL element 16 emits light with a luminance corresponding to the drive current Ie, and performs a light emission operation.

  In the present embodiment, the output switch BCT is turned on / off in the first light emission period, thereby setting a predetermined light emission period in which the organic EL element 16 actually emits light. A non-emission period that is not performed is set. However, when the peak processing is unnecessary, the output switch BCT is always maintained in the on state (see, for example, FIG. 6).

  In the first light emission period, the drive transistor DRT is turned on only when the written voltage signal Vsig is V1, and a current flows through the organic EL element 16 to emit light. When the written voltage signals are V2, V3, and V4, the drive transistor DRT is maintained in the off state, and the organic EL element does not emit light.

  3) In the second light emission period, as shown in FIGS. 3 and 5C, the potential of the control signal Sb1 supplied from the second scanning line Cs changes to the negative side by ΔVsig. Accordingly, the gate potential Vg of the drive transistor DRT also changes by ΔVsig (Vg = Vsig−ΔVsig). Therefore, when the initial write signal line potential Vsig is V1, the gate potential is Vg = V1−ΔVsig, and the drive transistor DRT is continuously maintained in the ON state. Even when the initial write signal line potential Vsig is V2, the gate potential is Vg = V2−ΔVsig = V1, and the driving transistor DRT is turned on. Thereby, a current flows through the organic EL element 16 through the driving transistor DRT, and the organic EL element is maintained in a light emitting state.

  When the initial write signal line potential Vsig is V3 and V4, the gate potential of the drive transistor DRT is V2 and V3 even after being lowered by ΔVsig, and the drive transistor DRT is maintained in the off state, and the organic EL element emits light. Is not done.

  Also in the second light emission period, a predetermined light emission period for actually emitting light from the organic EL element 16 is set by controlling the output switch BCT to be turned on and off, and non-light emission in which no light emission is performed following this light emission period. A period has been set. However, when the peak processing is unnecessary, the output switch BCT is always maintained in the on state (see, for example, FIG. 6).

  4) In the third light emission period, as shown in FIGS. 3 and 5D, the potential of the control signal supplied from the second scanning line Cs further changes to the negative side by ΔVsig. Along with this, the gate potential Vg of the driving transistor DRT also changes by ΔVsig (Vg = Vsig−2ΔVsig). Therefore, when the initial write signal line potential Vsig is V1 or V2, the drive transistor DRT is continuously maintained in the on state. Thereby, a current flows through the organic EL element 16 through the driving transistor DRT, and the organic EL element is maintained in a light emitting state.

  Even when the initial write signal line potential Vsig is V3, the gate potential is Vg = V3−2ΔVsig = V1, and the drive transistor DRT is turned on. As a result, a current flows to the organic EL element 16 through the driving transistor DRT, and the organic EL element emits light.

  When the initial write signal line potential Vsig is V4, the gate potential of the drive transistor DRT is V2 even after being lowered by 2ΔVsig, the drive transistor DRT is maintained in the off state, and the organic EL element does not emit light. .

Also in the third light emission period, a predetermined light emission period for actually emitting light from the organic EL element 16 is set by controlling the output switch BCT to be turned on and off, and non-light emission in which no light emission is performed following this light emission period. A period has been set. However, when the peak processing is unnecessary, the output switch BCT is always maintained in the on state (see, for example, FIG. 6).
In the first, second, and third light emission periods, the lengths of the non-light emission periods existing between the light emission periods are all set equal.

  The organic EL element 16 maintains the light emission state after the elapse of one vertical cycle (V) until the control signal Sa becomes the ON potential again. In the present embodiment, the first, second, and third light emission periods are set to equal periods. As described above, the control signal potential supplied from the second scanning line CS (1 to m) to the holding capacitors C1 to C4 changes in an arithmetic progression, and the tolerances thereof are the signal line potentials V1, V2, and V3. , V4 is set equal to the tolerance.

  In each display pixel PX, the same operation as described above is performed for each of the pixel circuits 18a to 18e provided in the five sub-regions 1, 2, 3, 4, and 5. Summarizing these operations, as shown in FIG. 7, when the signal line potential written through the video signal line X (1 to m) is V1, it is driven during the first, second, and third light emission periods. The transistor DRT is turned on, a current flows through the organic EL element, and the light emitting state is maintained. When the potential of the write voltage signal is V2, the drive transistor DRT is turned off in the first light emission period, the organic EL element 16 does not emit light, and the drive transistor DRT is turned on in the second and third light emission periods, and the organic EL element is turned on. A current flows and the light emission state is maintained.

  When the potential of the write voltage signal is V3, the drive transistor DRT is turned off in the first and second light emission periods, the organic EL element 16 does not emit light, and the drive transistor DRT is turned on in the third light emission period, and the organic EL element is turned on. A current flows and the light emission state is maintained. When the potential of the write voltage signal is V4, the drive transistor DRT is turned off during the first, second, and third light emission periods, and the organic EL element 16 does not emit light.

  As a result, if the light-emitting current when the signal line potential to be written is V1, the V2 is 2, the V3 is 1, the V4 is 0, and the gradation expression for 2 bits is performed in one sub-region. Can do.

  For example, in the case of 10-bit gradation expression, a region in one display pixel PX is divided into five sub-regions 1, 2, 3, 4, 5 and voltages connected to the pixel circuits 18a to 18e in these sub-regions. The potentials of the power supply lines PVDD1 to PVDD5 are set to +5, +5.2, +5.4, +5.6, and + 5.8V, respectively. In this case, the gradation 0, 1, 2, 3 in the pixel circuit 18a in the subregion 1, the gradation 0, 4, 8, 12, in the pixel circuit 18b in the subregion 2, and the gradation in the pixel circuit 18c in the subregion 3. The pixel circuits 18d in 0, 16, 32, 48, and sub-region 4 can express gradations 0, 64, 128, and 192, and the pixel circuit 18e in sub-region 5 can express gradations 0, 256, 512, and 768. Therefore, by combining these five sub-regions 1 to 5, it is possible to express 1024 gradations with 10 bits for each display pixel PX.

  According to the organic EL display device configured as described above and the driving method thereof, the driving transistor of the pixel circuit is driven in its linear region, and is operated as an on / off switch. Display unevenness can be reduced without being affected by variations in mobility and threshold. At the same time, the applied voltage of the drive transistor required during the light emission operation is small, and the power consumption of the drive transistor can be greatly reduced. In addition, a frame memory for storing a video signal of one entire frame, which is used in a display device of a digital signal driving system, is used to perform gradation expression by combining time-division driving and sub-region division driving. There is no need to provide it, and the manufacturing cost can be reduced, and at the same time, the bit can be increased. Further, as compared with the case of only light emission area division driving, the number of sub-region divisions of the display pixel can be significantly reduced, and the configuration can be simplified. Thus, an active matrix display device capable of realizing good display and greatly reducing power consumption can be provided.

Further, according to the first embodiment, in the first, second, and third light emission periods, the light emission period in which light is actually emitted can be controlled, and the light emission luminance during normal display and the peak luminance display can be controlled. It is possible to provide a luminance difference between the emission luminances and improve the contrast.
In the present embodiment, the pixel switch SST and the output switch BCT may be formed with either P-channel or N-channel polarity.

(Second Embodiment)
In the first embodiment described above, the output switches BCT1-5 of the pixel circuits 18a-18e are provided between the drive transistor DRT and the high-potential voltage power supply line PVDD. 8 may be provided between the driving transistor DRT and the organic EL display element. In the present embodiment, the pixel switch SST and the output switch BCT may be formed with either P-channel or N-channel polarity.

(Third embodiment)
Next, an organic EL display device according to a third embodiment will be described.
In the first embodiment, each display pixel has a plurality of, for example, five pixel circuits, and five voltage power supply lines PVDD1 to 5 having different potentials are provided for each display pixel. According to the third embodiment, there is one pixel circuit for each display pixel, and one voltage power supply line PVDD for each display pixel, and a plurality of, for example, five different potentials are applied to this voltage power supply line with a time difference. It is configured to supply.

  Specifically, as shown in FIG. 9, the organic EL display device is configured as, for example, an active matrix display device of two or more types, and includes an organic EL panel 10 and a controller 13 that controls the organic EL panel.

  The organic EL panel 10 includes a light-transmitting insulating substrate 8 such as a glass plate, m × n display pixels PX arranged in a matrix on the insulating substrate and constituting a display region 11, and each display pixel row. The first scanning line SG (1 to m) and the second scanning line Cs (1 to m), which are connected and provided independently by m, are each connected to each column of the display pixels PX. Video signal lines X (1 to n) are provided. As will be described later, each display pixel PX has a plurality of display elements, and each video signal line X (1 to n) has a plurality of video signal lines corresponding to the number of display elements in each display pixel PX. Contains.

  The organic EL panel 10 includes scanning line driving circuits 14a and 14b that sequentially drive the first and second scanning lines SG (1 to m) and Cs (1 to m) for each row of the display pixels PX, and a plurality of video signal lines. A signal line driving circuit 15 for driving X (1 to n) is provided. The scanning line driving circuits 14 a and 14 b and the signal line driving circuit 15 are integrally formed on the insulating substrate 8 outside the display area 11 and constitute a control unit together with the controller 13.

  FIG. 2 shows an equivalent circuit of the display pixel PX. Each display pixel PX that functions as a pixel portion includes one display element having a photoactive layer between opposing electrodes, and a pixel circuit 18 that supplies a drive current to each display element. The display element is, for example, a self-luminous element. In this embodiment, the organic EL element 16 including at least an organic light-emitting layer is used as a photoactive layer.

  The pixel circuit 18 is a voltage signal type pixel circuit that controls light emission of an organic EL element in accordance with a video signal composed of a voltage signal, and includes a pixel switch SST, a drive transistor DRT, a holding capacitor C as a capacitor, and an organic EL element. 16 is provided with an output switch BCT for controlling on / off of 16.

  Here, the pixel switch SST, the drive transistor DRT, and the output switch BCT are configured by the same conductivity type, for example, a P-channel type thin film transistor. In the present embodiment, the thin film transistors constituting the drive transistors and the switches are all formed in the same process and the same layer structure, and are top gate thin film transistors using polysilicon as a semiconductor layer.

  Each of the pixel switch SST, the drive transistor DRT, and the BCT has a first terminal, a second terminal, and a control terminal. In the present embodiment, the first terminal, the second terminal, and the control terminal are the source, The drain and gate are used.

  In the pixel circuit 18, the output switch BCT, the drive transistor DRT, and the organic EL element 16 are connected in series between the high potential voltage power supply line PVDD and the low potential reference voltage power supply line PVSS in this order. The drive transistor DRT outputs a drive current having a current amount corresponding to the video signal to the organic EL element 16. The source of the output switch BCT is connected to the voltage power supply line PVDD. The source of the drive transistor DRT is connected to the drain of the output switch BCT, and the drain is connected to one electrode, for example, the anode of the organic EL element 16. The cathode of the organic EL element 16 is connected to the reference voltage power line PVSS.

  The voltage power supply line PVDD and the reference voltage power supply line PVSS are connected to the signal line drive circuit 15 and supplied with a power supply voltage from the signal line drive circuit. The reference voltage power line PVSS is set to a potential of −3V, for example. As will be described later, the voltage power supply line PVDD is set to different potentials for each frame by the signal line driving circuit 15, for example, five types of potentials +5, +5.2, +5.4, +5.6, and + 5.8V. Is done.

  The storage capacitor C is connected between the gate of the driving transistor DRT and the second scanning line Cs (1 to m). The holding capacitor C holds the gate potential of the driving transistor DRT, and at the same time, changes the gate potential of the driving transistor DRT according to the potential change of the second scanning line Cs (1 to m) that changes for each of the divided light emission periods. It is changed and plays a role of controlling on / off of the driving transistor DRT.

  The pixel switch SST is connected between the corresponding video signal line X (1-n) and the gate of the driving transistor DRT, and the gate is connected to the corresponding first scanning line SG (1-m). The pixel switch SST is connected to the pixel circuit 18 and the video signal line X (1 to n) in response to the control signal Sa (1 to m) supplied from the first scanning line SG (1 to m). The connection is controlled, and the video voltage signal corresponding to the gradation is written from the corresponding video signal line X (1 to n) to the gate of the drive transistor DRT.

  On the other hand, the controller 13 shown in FIG. 1 is formed on a printed circuit board disposed outside the organic EL panel 10 and controls the scanning line driving circuits 14 a and 14 b and the signal line driving circuit 15. The controller 13 receives a digital video signal and a synchronization signal supplied from the outside, and generates a vertical scanning control signal for controlling the vertical scanning timing and a horizontal scanning control signal for controlling the horizontal scanning timing based on the synchronizing signal. The controller 13 supplies the vertical scanning control signal and the horizontal scanning control signal to the scanning line driving circuits 14a and 14b and the signal line driving circuit 15, respectively, and outputs a digital video signal in synchronization with the horizontal and vertical scanning timings. This is supplied to the line drive circuit 15.

  The signal line driving circuit 15 converts the video signals sequentially obtained in each horizontal scanning period into the analog format under the control of the horizontal scanning control signal into a voltage signal and supplies it in parallel to the plurality of video signal lines X (1 to n). To do. In the signal line driving circuit 15, the voltage supply unit V that functions as a voltage source outputs a gradation voltage signal Vsig having a plurality of gradations corresponding to the video signal to the video signal lines X (1 to n). In addition, the signal line driver circuit 15 sets the voltage power supply line PVDD to five types of potentials +5, +5.2, +5.4, +5.6, and +5.8 V for each subframe period.

  The scanning line driving circuits 14a and 14b include a shift register, an output buffer, and the like, sequentially transfer a horizontal scanning start pulse supplied from the outside to the next stage, and control signals Sa, A control signal Sb is supplied.

  Next, the operation of the organic EL display device configured as described above will be described. In driving the organic EL display device, the display pixels Px are sequentially selected for each row, the gradation voltage signal writing operation is performed in the selection period of the display pixels Px, and the light emission operation is performed in the non-selection period. FIG. 11 shows a timing chart of output signals of the scanning line drive circuits 14a and 14b, and FIG. 12 shows an operation of the display pixel PX.

  For example, the scanning line driving circuits 14a and 14b generate a pulse having a width of one horizontal scanning period (Tw-Starta) corresponding to each horizontal scanning period from a start signal (STV1, STV2) and a clock (CKV1, CKV2). The pulse is output as a control signal Sa (1 to m).

Taking the 10-bit gradation as an example, the operation of the display pixel PX will be described. As shown in FIG. 11, one horizontal period (V) is divided into five subframe (SF) periods 1 to 5, and each subframe period is divided into 1) a writing period, 2) a first light emission period, and 3) a first. It is divided into 2 light emission periods and 4) third light emission periods.
The operation during the i-th subframe period will be described. When the subframe is switched, the potential of the voltage power supply line PVDD is set from PVDDi-1 to PVDDi, and the operation is started.

  1) In the writing period, as shown in FIGS. 11 and 12A, the control signal Sa (1 to m) of the display pixel PX becomes an ON potential (low level) for turning on the pixel switch SST, and the pixel switch SST Is turned on (conducting state). In the writing period, the gradation video voltage signal Vsig is output from the voltage supply unit V of the signal line driving circuit 15 to the video signal lines X (1 to n), and is written in the storage capacitor C via the pixel switch SST. As a result, the gate potential Vg of the drive transistor DRT becomes Vsig.

  As the voltage signal Vsig, a plurality of, for example, four signal line potentials (setting potentials) Vi1, Vi2, Vi3, Vi4 are digitally written according to the gradation. At this time, the signal line potential is set so as to satisfy the relationship of Vi1 <Vi2 <Vi3 <Vi4. Further, the signal line potentials Vi1, Vi2, Vi3, Vi4 are set so that their values change in an arithmetic progression, and the difference (tolerance) ΔVsig between the potentials is set to a constant value, for example, 5v. Yes.

As in the case shown in FIG. 4, Vi1 is set to a value at which the drive transistor DRT operates in its linear region and is turned on, and Vi2, Vi3, and Vi4 are respectively set to values at which the drive transistor DRT is turned off. Is set.
When the drive transistor DRT is composed of an Nch type transistor, the value of the voltage signal Vsig is set in the reverse relationship, that is, Vi1>Vi2>Vi3> Vi4.

  Next, as shown in FIGS. 11 and 12B, the control signal Sa (1 to m) is turned off (high level), and the pixel switch SST is turned off. Thereby, the video voltage signal writing operation is completed. At the same time or subsequently, the control signal Sc (1 to m) is turned on (low level), the output switch BCT is turned on, and the first light emission operation is started.

  2) In the first light emission period, the drive transistor DRT outputs a drive current Ie having a corresponding amount of current according to the gate control voltage Vg = Vsig written in the storage capacitor C. This drive current Ie is supplied to the organic EL element 16. Thereby, the organic EL element 16 emits light with a luminance corresponding to the drive current Ie, and performs a light emission operation.

  In the present embodiment, in the first light emission period, a predetermined light emission period in which the organic EL element 16 actually emits light is set by ON / OFF control of the output switch BCT. When peak processing is required, a non-light emission period in which light emission is not performed is set following this light emission period (see, for example, FIG. 13). In the first light emission period, the drive transistor DRT is turned on only when the written voltage signal Vsig is Vi1, and a current flows through the organic EL element 16 to emit light. When the written voltage signal is Vi2, Vi3, or Vi4, the drive transistor DRT is maintained in the off state, and the organic EL element does not emit light.

  3) In the second light emission period, as shown in FIGS. 11 and 12C, the potential of the control signal Sb1 supplied from the second scanning line Cs changes to the negative side by ΔVsig. Accordingly, the gate potential Vg of the drive transistor DRT also changes by ΔVsig (Vg = Vsig−ΔVsig). Therefore, when the initial write signal line potential Vsig is V1, the gate potential is Vg = V1−ΔVsig, the drive transistor DRT is continuously kept on, and the gate potential is also maintained when the initial write signal line potential Vsig is V2. Vg = V2−ΔVsig = V1, and the driving transistor DRT is turned on. Thereby, a current flows through the organic EL element 16 through the driving transistor DRT, and the organic EL element is maintained in a light emitting state.

  When the initial write signal line potential Vsig is V3 and V4, the gate potential of the drive transistor DRT is V2 and V3 even after being lowered by ΔVsig, and the drive transistor DRT is maintained in the off state, and the organic EL element emits light. Is not done.

  4) In the third light emission period, as shown in FIGS. 11 and 12D, the potential of the control signal supplied from the second scanning line Cs further changes to the negative side by ΔVsig. Along with this, the gate potential Vg of the driving transistor DRT also changes by ΔVsig (Vg = Vsig−2ΔVsig). Therefore, when the initial write signal line potential Vsig is V1 or V2, the drive transistor DRT is continuously maintained in the on state. Thereby, a current flows through the organic EL element 16 through the driving transistor DRT, and the organic EL element is maintained in a light emitting state.

  Even when the initial write signal line potential Vsig is V3, the gate potential is Vg = V3−2ΔVsig = V1, and the drive transistor DRT is turned on. As a result, a current flows to the organic EL element 16 through the driving transistor DRT, and the organic EL element emits light.

When the initial write signal line potential Vsig is V4, the gate potential of the drive transistor DRT is V2 even after being lowered by 2ΔVsig, the drive transistor DRT is maintained in the off state, and the organic EL element does not emit light. .
In the first, second, and third light emission periods, the output switch BCT is maintained in the on state. When peak processing is required, a non-light emission period in which light emission is not performed is set following this light emission period (see, for example, FIG. 13). In the present embodiment, the first, second, and third light emission periods are set to equal periods. As described above, the control signal potential supplied from the second scanning line SC (1 to m) to the holding capacitors C1 to C4 changes in an arithmetic progression, and the tolerances thereof are the signal line potentials Vi1, Vi2, Vi3. , Vi4 is set equal to the tolerance.

In each display pixel PX, the light emission operation similar to the above is sequentially performed for the five subframes SF1 to SF5. At this time, for the subframes SF1 to SF5, the potential of the voltage power supply line PVDD is sequentially changed to PVDD1 to 5 and output.
The organic EL element 16 maintains the light emission state after the elapse of one vertical cycle (V) until the control signal Sa becomes the ON potential again.

  Summarizing these operations, as shown in FIG. 14, when the signal line potential written through the video signal line X (1 to m) is V1, it is driven during the first, second, and third light emission periods. The transistor DRT is turned on, a current flows through the organic EL element, and the light emitting state is maintained. When the potential of the write voltage signal is V2, the drive transistor DRT is turned off in the first light emission period, the organic EL element 16 does not emit light, and the drive transistor DRT is turned on in the second and third light emission periods, and the organic EL element is turned on. A current flows and the light emission state is maintained.

  When the potential of the write voltage signal is V3, the drive transistor DRT is turned off in the first and second light emission periods, the organic EL element 16 does not emit light, and the drive transistor DRT is turned on in the third light emission period, and the organic EL element is turned on. A current flows and the light emission state is maintained. When the potential of the write voltage signal is V4, the drive transistor DRT is turned off during the first, second, and third light emission periods, and the organic EL element 16 does not emit light.

  As a result, if the light-emitting current when the signal line potential to be written is V1, the V2 is 2, the V3 is 1, the V4 is 0, and the gradation expression for 2 bits is performed in one sub-region. Can do. For example, in the case of 10-bit gradation expression, one vertical period (V) is divided into five subframes SF, and the potentials of the voltage power supply lines PVDD1 to PVDD1 during operation in these subframes are +5, +5.2, It is set to +5.4, +5.6, and + 5.8V, respectively. In this case, gradations 0, 1, 2, and 3 in subframe 1SF, gradations 0, 4, 8, and 12 in subframe 2SF, gradations 0, 16, 32, and 48 in subframe 3SF, and gradations in subframe 4SF. In the keys 0, 64, 128, and 192 and the subframe 5SF, gradations 0, 256, 512, and 768 can be expressed. Therefore, by combining these five sub-frames, it is possible to express 1024 gradations with 10 bits for each display pixel PX.

  According to the organic EL display device configured as described above and the driving method thereof, the driving transistor of the pixel circuit is driven in its linear region, and is operated as an on / off switch. Display unevenness can be reduced without being affected by variations in mobility and threshold. At the same time, the applied voltage of the drive transistor required during the light emission operation is small, and the power consumption of the drive transistor can be greatly reduced. In addition, a frame memory for storing a video signal of one entire frame, which is used in a display device of a digital signal driving system, is used to perform gradation expression by combining time-division driving and sub-region division driving. There is no need to provide it, and the manufacturing cost can be reduced, and at the same time, the number of bits can be increased.

  Furthermore, according to the third embodiment, the number of elements constituting the pixel circuit in each display pixel can be reduced, and as a result, a high-definition display device of 300 PPI or more can be realized. Further, as compared with the case of only the light emission area division drive, the number of divisions of the display pixels can be greatly reduced, and the configuration can be simplified. As a result, it is possible to provide a high-definition active matrix display device that can realize good display and can significantly reduce power consumption.

(Fourth embodiment)
In the third embodiment described above, the output switch BCT of each pixel circuit is provided between the drive transistor DRT and the high-potential voltage power supply line PVDD. However, the present invention is not limited to this, and the fourth switch shown in FIG. As in the embodiment, it may be provided between the drive transistor DRT and the organic EL element 16.

  The present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

  For example, the number of sub-regions in the display pixel PX is not limited to five, and may be six or more or four or less. The potentials of the voltage power supply lines PVDD1 to PVDD5 are not limited to the above-described embodiments, and can be appropriately changed according to the number of gradations. In the light emission period, the gate potential of the drive transistor DRT is changed in two steps. However, it may be changed in one step or three or more steps. Furthermore, the plurality of light emission periods are not limited to the same period, but can be set to different periods. Each display pixel may be provided with a plurality of display elements having different light emission areas or the same light emission areas, and may be used in combination with light emission area division driving.

  The semiconductor layer of the thin film transistor is not limited to polysilicon but can be composed of amorphous silicon. Further, the dimensions of the transistor and the switch are not limited to the above-described embodiments, and can be changed as necessary. The self-luminous elements constituting the display pixels are not limited to organic EL elements, and various display elements capable of self-luminance are applicable.

1, 2, 3, 4 ... sub-region, 8 ... insulating substrate, 10 ... organic EL panel,
DESCRIPTION OF SYMBOLS 11 ... Display area, 13 ... Controller, 14a, 14b ... Scanning line drive circuit,
DESCRIPTION OF SYMBOLS 15 ... Signal line drive circuit, 16 ... Organic EL element, 18 ... Pixel circuit, V ... Voltage supply part,
SST: pixel switch, DRT: drive transistor, BCT: output switch,
X ... video signal line, SG ... first scanning line, Cs ... second scanning line, BG ... third scanning line

Claims (7)

A plurality of video signal lines arranged in parallel;
A plurality of first scanning lines, second scanning lines, and third scanning lines, each extending in a direction crossing the video signal line;
A plurality of high-potential power lines having different potentials;
A low-potential power line;
A scanning line driving circuit that outputs a control signal of an on / off potential to the first scanning line and the third scanning line, and outputs a control signal whose potential changes stepwise to the second scanning line;
A signal line driving circuit for outputting a video voltage signal of a plurality of gradations to the video signal line;
A plurality of pixel portions, each having one electrode having a display element connected to the low-potential power line and a plurality of pixel circuits for driving the display element, arranged in a matrix, each pixel portion A plurality of pixel circuits, wherein the second terminal is connected to the other electrode of the display element and the second terminal is connected to the first terminal of the drive transistor with respect to the plurality of high-potential power lines. An output switch having a second terminal connected to one of the plurality of high potential power lines, a gate connected to the third scanning line, a second terminal connected to the video signal line, and a first terminal connected to the video signal line A pixel switch connected to the gate of the drive transistor, the gate connected to the first scan line, and one electrode connected to the gate of the drive transistor and the other electrode connected to the second scan line Capacity, Each pixel unit has a writing period in which a gradation video voltage signal is written from the video signal line to the drive transistor via the pixel switch for each of a plurality of pixel circuits, and changes in stages. A plurality of pixel units each having a plurality of light emission periods that are divided into a plurality of times according to a control signal to be emitted and selectively cause the display element to emit light according to the written gradation video voltage signal. ,
An active matrix display device comprising: A plurality of video signal lines arranged in parallel;
A plurality of first scanning lines, second scanning lines, and third scanning lines, each extending in a direction crossing the video signal line;
A plurality of high-potential power lines having different potentials;
A low-potential power line;
A scanning line driving circuit that outputs a control signal of an on / off potential to the first scanning line and the third scanning line, and outputs a control signal whose potential changes stepwise to the second scanning line;
A signal line driving circuit for outputting a video voltage signal of a plurality of gradations to the video signal line;
A plurality of pixel portions, each having one electrode having a display element connected to the low-potential power line and a plurality of pixel circuits for driving the display element, arranged in a matrix, each pixel portion The plurality of pixel circuits have an output switch in which a second terminal is connected to the other electrode of the display element, a gate is connected to the third scanning line, and a second terminal is connected to the plurality of high potential power supply lines. A driving transistor connected to a first terminal of the output switch, a second terminal connected to one of the plurality of high potential power supply lines, a second terminal connected to the video signal line, and a first terminal connected to the video signal line A pixel switch connected to the gate of the drive transistor, the gate connected to the first scan line, and one electrode connected to the gate of the drive transistor and the other electrode connected to the second scan line Capacity and Each pixel unit has a writing period for writing a grayscale video voltage signal from the video signal line to the driving transistor via each pixel switch for each of a plurality of pixel circuits, and stepwise. A plurality of pixel portions that are divided into a plurality according to a changing control signal and each has a plurality of light emission periods for selectively causing the display element to emit light according to the written gradation video voltage signal. When,
An active matrix display device comprising: A plurality of video signal lines arranged in parallel;
A plurality of first scanning lines, second scanning lines, and third scanning lines, each extending in a direction crossing the video signal line;
A high-potential power line and a low-potential power line;
A scanning line driving circuit that outputs a control signal of an on / off potential to the first scanning line and the third scanning line, and outputs a control signal whose potential changes stepwise to the second scanning line;
A signal line driving circuit that outputs video voltage signals of a plurality of gradations to the video signal line and supplies different potentials to the high potential power line for each of a plurality of subframes;
A plurality of pixel portions each having one electrode having a display element connected to the low-potential power line and a pixel circuit for driving the display element and arranged in a matrix, wherein the pixel circuit includes: A driving transistor having a first terminal connected to a second voltage power source and a second terminal connected to the other electrode of the display element, and a holding connected between a control terminal of the driving transistor and the second scanning line A capacitor, a pixel switch having a first terminal connected to the control terminal of the driving transistor, a second terminal connected to the video signal line, a control terminal connected to the first scanning line, and a control terminal connected to the first scanning line An output switch that is connected to three scanning lines and connected between the second voltage power source and the display element and controls light emission and non-light emission of the display element, and each pixel unit emits light Multiple actions leading to Each subframe period includes a writing period in which a grayscale video voltage signal is written from the video signal line to the driving transistor via the pixel switch, and the stepwise change control. A plurality of pixel units each having a plurality of light emission periods that are divided into a plurality according to signals and selectively cause the display element to emit light according to the written gradation video voltage signal,
An active matrix display device comprising:   The control signal output from the scanning line driving circuit to the second scanning line has a plurality of set potentials whose potential changes stepwise, and has a different set voltage for each of the divided light emission periods. Item 4. The active matrix display device according to any one of Items 1 to 3.   When the video voltage signal output from the signal line driver circuit to the video signal line has a plurality of digitally set potentials, and each pixel portion has a light emission period divided into X, 5. The active matrix display device according to claim 4, wherein (X + 1) types of different set voltages are provided.   4. The active matrix display device according to claim 3, wherein the output switch of each pixel circuit has a first terminal connected to the drive transistor and a second terminal connected to the display element.   4. The active matrix according to claim 3, wherein the output switch of each pixel circuit has a first terminal connected to the second voltage power source and a second terminal connected to the first terminal of the drive transistor. Type display device.

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