JP2010272853A - Creating method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To integrate a semiconductor device having n-channel type transistors to p-channel type transistors, to improve performance of the semiconductor device, and to reduce cost of the semiconductor device having a large area, in a creating method of the semiconductor device. <P>SOLUTION: The creating method of the semiconductor device includes a process wherein accelerated ions are radiated onto its single-crystal silicon substrate having a plane within ±15° from a ä211} plane as its surface, and thereby, a brittle region is formed in its single-crystal silicon substrate. Also, the creating method includes a process wherein the single-crystal silicon substrate and a base substrate are bonded to each other via an insulating layer, a process wherein the single-crystal silicon substrate is separated in the brittle region, and a single-crystal silicon layer having the plane within ±15° from the ä211} plane as its surface is formed on the base substrate and a process wherein by using the single-crystal silicon layer, the n-channel type and p-channel type transistors having their channel length directions within ± 15° from a <111> axis are formed. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

The present invention relates to a method for manufacturing a semiconductor device.

Instead of a silicon wafer produced by thinly slicing a single crystal semiconductor ingot, a semiconductor substrate called a silicon-on-insulator (hereinafter also referred to as “SOI”) having a thin single crystal semiconductor layer provided on an insulating surface was used. Integrated circuits have been developed. An integrated circuit using an SOI substrate has attracted attention as an element that reduces the parasitic capacitance between the drain of the transistor and the substrate and improves the performance of the semiconductor integrated circuit.

As a method for manufacturing an SOI substrate, a hydrogen ion implantation separation method is known (for example, see Patent Document 1). In the hydrogen ion implantation separation method, an embrittled region is formed at a predetermined depth from the surface by implanting hydrogen ions into a silicon wafer, and a thin silicon layer is formed on another silicon wafer by separating in the embrittled region. It is a method of joining.

By the way, in CMOS technology, NMOS and PMOS are mainly formed using a silicon wafer having a plane orientation called (100) plane. This (100) plane shows a high mobility for electrons and is therefore a crystal plane suitable for NMOS, but has a low hole mobility and cannot be said to be a crystal plane suitable for PMOS.

Therefore, in order to achieve both the electron mobility of NMOS and the hole mobility of PMOS, a PMOS formed using a silicon wafer having a (110) plane and a silicon wafer having the (110) plane are provided. In addition, a semiconductor device including an NMOS formed in a silicon layer having a (100) plane has been proposed (see, for example, Patent Document 2).

Japanese Patent Application Laid-Open No. 2000-124092 JP 2006-229047 A

As described above, as a method for making both the hole mobility of the p-channel transistor and the electron mobility of the n-channel transistor compatible, the p-channel transistor and the n-channel transistor each have an optimum surface as the surface. There is a method of forming using a semiconductor layer. However, in this case, since it is necessary to use two types of semiconductor substrates having different plane orientations, it becomes difficult to provide a p-channel transistor and an n-channel transistor adjacent to each other, and integration cannot be achieved. In the case where a semiconductor device is formed by bonding two semiconductor substrates together, the size of the semiconductor device is limited to the size of the semiconductor substrate, which is disadvantageous for increasing the area. Furthermore, since it is necessary to use two types of semiconductor substrates having different plane orientations, it is difficult to reduce the cost.

An object of one embodiment of the disclosed invention is to integrate a semiconductor device including an n-channel transistor and a p-channel transistor. Another object of one embodiment of the disclosed invention is to improve the performance of a semiconductor device. Another object of one embodiment of the disclosed invention is to provide a large-area semiconductor device at low cost.

One embodiment of the disclosed invention is a single crystal silicon whose surface is a plane within ± 15 ° from the {211} plane (that is, a plane in the range of −15 ° to + 15 ° with respect to the {211} plane). In the embrittlement region, a step of irradiating the substrate with accelerated ions to form an embrittlement region in the single crystal silicon substrate, a step of bonding the single crystal silicon substrate and the base substrate through an insulating layer, Separating the single crystal silicon substrate, forming a single crystal silicon layer having a surface within ± 15 ° from the {211} plane on the base substrate; and using the single crystal silicon layer, the channel length direction is < And a step of forming an n-channel transistor and a p-channel transistor within ± 15 ° from the 111> axis.

In the above, the insulating layer is preferably formed by oxidizing a single crystal silicon substrate in an atmosphere containing chlorine.

In the above, a CMOS circuit is preferably formed using an n-channel transistor and a p-channel transistor. In the above, the channel length of the n-channel transistor and the channel length of the p-channel transistor are preferably formed to be approximately the same. Here, the same level means a range of ± 20% from the average value of the channel lengths of the n-channel transistor and the p-channel transistor. A single crystal silicon layer is preferably formed as the single crystal semiconductor layer.

In the present specification, a plane within ± 15 ° from the {211} plane means a plane having an angle of 15 ° or less between a direction perpendicular to the target plane and the <211> axis. In the present specification, the direction within ± 15 ° from the <111> axis refers to a direction in which an angle formed between the target direction and the <111> axis is 15 ° or less.

In this specification, a single crystal refers to a crystal in which the direction of the crystal axis is the same in any part of the sample when attention is paid to a crystal axis. That is, in this specification, even if crystal defects and dangling bonds are included, those in which the directions of the crystal axes are aligned as described above are called single crystals.

Further, the structure of the transistor described in this specification can take various forms and is not limited to a specific structure. For example, a multi-gate structure having two or more gate electrodes can be applied. When the multi-gate structure is employed, the channel regions are connected in series, so that a plurality of transistors are connected in series. With the multi-gate structure, off-state current can be reduced and the breakdown voltage of the transistor can be improved (reliability improvement). Alternatively, with the multi-gate structure, even when the drain-source voltage changes, the drain-source current does not change much when operating in the saturation region, and the slope of the voltage / current characteristics can be flattened. By using the characteristic that the slope of the voltage / current characteristic is flat, an ideal current source circuit and an active load having a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with good characteristics can be realized.

As another example, a structure in which gate electrodes are arranged above and below a channel can be applied. By employing a structure in which gate electrodes are arranged above and below the channel, the channel region increases, so that the current value can be increased. Alternatively, a structure in which gate electrodes are provided above and below a channel facilitates the formation of a depletion layer, so that the S value can be improved. Note that a structure in which a plurality of transistors are connected in parallel is obtained by using a structure in which gate electrodes are arranged above and below a channel.

A structure in which the gate electrode is arranged above the channel region, a structure in which the gate electrode is arranged under the channel region, a normal stagger structure, an inverted stagger structure, a structure in which the channel region is divided into a plurality of regions, and a channel region A structure connected in parallel or a configuration in which channel regions are connected in series can also be applied. Further, a structure in which a source electrode or a drain electrode overlaps with a channel region (or part of it) can be used. With the structure where the source electrode and the drain electrode overlap with the channel region (or part thereof), unstable operation due to accumulation of electric charge in part of the channel region can be prevented. Alternatively, a structure provided with an LDD region can be applied. By providing the LDD region, off-state current can be reduced or the breakdown voltage of the transistor can be improved (reliability improvement). Alternatively, by providing an LDD region, when operating in the saturation region, even if the drain-source voltage changes, the drain-source current does not change so much and the slope of the voltage-current characteristic is flat. be able to.

In the present specification, silicon oxynitride has a composition containing more oxygen than nitrogen, and preferably Rutherford Backscattering Spectroscopy (RBS) and Hydrogen Forward Scattering ( When measured using HFS (Hydrogen Forward Scattering), the concentration ranges from 50 to 70 atomic% for oxygen, 0.5 to 15 atomic% for nitrogen, 25 to 35 atomic% for silicon, and 0.1 to 10 for hydrogen. It is included in the atomic% range. Further, silicon nitride oxide has a composition containing more nitrogen than oxygen, and preferably has a concentration range of 5 to 30 atomic% when measured using RBS and HFS. Nitrogen is contained in the range of 20 to 55 atomic%, silicon is contained in the range of 25 to 35 atomic%, and hydrogen is contained in the range of 10 to 30 atomic%. However, when the total number of atoms constituting silicon oxynitride or silicon nitride oxide is 100 atomic%, the content ratio of nitrogen, oxygen, silicon, and hydrogen is included in the above range.

A semiconductor device in this specification refers to all devices that can function by utilizing semiconductor characteristics, and a display device, a semiconductor circuit, and an electronic device are all included in the semiconductor device.

In this specification, a display device includes a light-emitting device and a liquid crystal display device. The light emitting device includes a light emitting element, and the liquid crystal display device includes a liquid crystal element. The light emitting element includes, in its category, an element whose luminance is controlled by current or voltage, and specifically includes an inorganic EL (Electro Luminescence) element, an organic EL element, and the like.

According to one embodiment of the disclosed invention, a semiconductor device can be integrated by forming a channel layer using a crystal plane and a crystal axis which are suitable for an n-channel transistor and a p-channel transistor. Alternatively, according to another embodiment of the disclosed invention, the performance of a semiconductor device can be improved. Alternatively, according to another embodiment of the disclosed invention, a large-area semiconductor device can be provided at low cost.

It is a figure which shows an example of the manufacturing method of a semiconductor substrate. It is a figure which shows an example of the single crystal semiconductor substrate to apply. FIG. 6 illustrates an example of a method for manufacturing a semiconductor device. It is a figure which shows an example of the manufacturing method of a semiconductor substrate. FIG. 6 illustrates an example of a method for manufacturing a semiconductor device. It is a figure which shows an example of the manufacturing method of a semiconductor substrate. It is a figure which shows an example of the manufacturing method of a semiconductor substrate. It is a figure which shows an example of the manufacturing method of a semiconductor substrate. It is a figure which shows an example of the manufacturing method of a semiconductor substrate. It is a block diagram which shows the structure of a microprocessor. It is a block diagram which shows the structure of RFCPU. (A) It is a top view of the pixel of a liquid crystal display device. (B) It is sectional drawing of FIG. 12 (A) by a JK cut line. (A) It is a top view of the pixel of an electroluminescent display apparatus. (B) It is sectional drawing of FIG. 13 (A) by a JK cut line. It is a figure which shows an electronic device. It is a figure which shows an electronic device. It is a figure which shows the calculation result of a crystal structure.

Hereinafter, embodiments will be described in detail with reference to the drawings. Note that the disclosed invention is not limited to the description of the embodiments described below, and it is obvious to those skilled in the art that modes and details can be variously changed without departing from the spirit of the invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. In addition, configurations according to different embodiments can be implemented in appropriate combination. In the structure of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment 1)
In this embodiment, an example of a method for manufacturing a semiconductor substrate having a semiconductor layer over an insulating surface and a method for manufacturing a semiconductor device using the semiconductor substrate will be described with reference to drawings.

<Method for Manufacturing Semiconductor Substrate>
First, a method for manufacturing a semiconductor substrate will be described with reference to FIGS.

First, the base substrate 300 is prepared, and the insulating layer 302 is formed over the base substrate 300 (see FIG. 1A).

As the base substrate 300, a glass substrate, a polycrystalline silicon substrate, or the like can be used. A glass substrate having a strain point of 580 ° C. or higher (preferably 600 ° C. or higher) is preferably used. The glass substrate is preferably an alkali-free glass substrate. For the alkali-free glass substrate, glass materials such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass are used, for example.

In addition, as the base substrate 300, a ceramic substrate, a substrate made of an insulator such as a quartz substrate or a sapphire substrate, a substrate made of a single crystal semiconductor such as silicon, a substrate made of a conductor such as metal or stainless steel, or the like may be used. it can.

There is no particular limitation on the formation method of the insulating layer 302; for example, a sputtering method, a CVD method, or the like can be used. Since the insulating layer 302 is a layer having a surface for bonding (a bonding layer), the insulating layer 302 is preferably formed so that the surface has high flatness. The insulating layer 302 can be formed using one or more materials selected from silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, and the like. . For example, when the insulating layer 302 is formed using silicon oxide, the insulating layer 302 having extremely excellent flatness can be obtained by forming the insulating layer 302 using an organic silane gas by a chemical vapor deposition method. Note that the insulating layer 302 may have a single-layer structure or a stacked structure.

Further, in the case where there is no particular problem in bonding and the insulating layer 302 is not necessary, the insulating layer 302 may be omitted.

Next, a single crystal semiconductor substrate 310 is prepared (see FIG. 1B). As the single crystal semiconductor substrate 310, for example, a single crystal silicon substrate can be used. In addition, as the single crystal semiconductor substrate 310, a single crystal semiconductor substrate made of a Group 14 element such as germanium, silicon germanium, or silicon carbide can be used. There is no limitation on the size of the single crystal semiconductor substrate 310; for example, a semiconductor substrate having a diameter of 8 inches (200 mm), 12 inches (300 mm), 18 inches (450 mm), or the like can be used.

In this embodiment, the case where a single crystal silicon substrate having a surface within ± 15 ° from the {211} plane is used as the single crystal semiconductor substrate 310 is described. As an example, a circular single crystal silicon substrate with a surface orientation of {211} and a notch formed in the <111> axis direction can be used (see FIG. 2A). Further, a circular semiconductor substrate may be processed into a rectangular shape. When processed into a rectangular shape, a laser marker can be formed over the single crystal semiconductor substrate 310 so that the <111> axial direction can be determined (see FIG. 2B). Besides {211} plane, for example, {311} plane, {321} plane, {322} plane, {421} plane, {432} plane, {433} plane, {521} plane, {522} plane , {531} plane, {532} plane, {533} plane, {542} plane, {543} plane, {544} plane, {632} plane, {643} plane, {653} plane, {654} plane , {655} plane, and the like can be used.

Next, an insulating layer 312 is formed on the surface of the single crystal semiconductor substrate 310 and an embrittlement region 314 is formed in the single crystal semiconductor substrate 310 (see FIG. 1C).

A method for forming the insulating layer 312 is not particularly limited, and for example, a thermal oxidation method, a sputtering method, a CVD method, or the like can be used. The insulating layer 312 can be formed using one or more materials selected from silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, and the like. . For example, in the case of forming the insulating layer 312 using silicon oxide, the single crystal semiconductor substrate 310 can be formed by heat treatment in an oxidizing atmosphere (eg, an oxygen atmosphere). Alternatively, silicon oxide may be formed by chemical vapor deposition using an organosilane gas. Note that the insulating layer 312 may have a single-layer structure or a stacked structure.

In the case where the insulating layer 312 is formed using thermal oxidation treatment, halogen (fluorine, chlorine, or the like) can be added to the oxidizing atmosphere. For example, the insulating layer 312 containing chlorine atoms can be formed by performing thermal oxidation treatment (hydrochloric acid oxidation treatment) on the single crystal semiconductor substrate 310 in an oxidizing atmosphere into which chlorine (Cl) gas is introduced. As an example, the treatment can be performed at a temperature of 900 ° C. to 1150 ° C. in an oxidizing atmosphere containing hydrogen chloride (HCl) at a ratio of 0.5 to 10% by volume (preferably 3% by volume) with respect to oxygen. . The treatment time is 0.1 to 6 hours, preferably 0.5 to 1 hour, and the thickness of the insulating layer 312 to be formed can be 10 to 1000 nm (preferably 50 to 300 nm).

Inclusion of chlorine atoms in the insulating layer 312 has an effect of collecting heavy metals (for example, Fe, Cr, Ni, Mo, and the like) that are impurities and preventing the single crystal semiconductor substrate 310 from being contaminated. In addition, inclusion of halogen such as chlorine in the insulating layer 312 by hydrochloric acid oxidation or the like is effective for removing contamination when the semiconductor substrate is not sufficiently cleaned or when the semiconductor substrate is repeatedly reused. . Further, by forming an insulating layer 312 containing a halogen such as chlorine over the single crystal semiconductor substrate 310, Na or the like contained in the glass when the single crystal semiconductor substrate 310 is bonded to the base substrate 300 formed of a glass substrate. It functions as a film that neutralizes impurities.

Further, the halogen atoms contained in the insulating layer 312 are not limited to chlorine atoms. The insulating layer 312 may contain fluorine atoms. In order to oxidize the surface of the single crystal semiconductor substrate 310 with fluorine, a method in which the surface of the single crystal semiconductor substrate 310 is immersed in an HF solution and then thermally oxidized in an oxidizing atmosphere, or NF ₃ is added to the oxidizing atmosphere to perform simple oxidation. A method of thermally oxidizing the crystalline semiconductor substrate 310 can be used.

The embrittlement region 314 can be formed by adding ions to the single crystal semiconductor substrate 310. For example, the embrittled region 314 is formed in a region having a predetermined depth from the surface of the single crystal semiconductor substrate 310 by irradiation with an ion beam including ions accelerated by an electric field. The depth at which the embrittled region 314 is formed can be controlled by the acceleration energy of the ion beam and the incident angle of the ion beam. That is, the embrittlement region 314 is formed in a region having a depth that is approximately the same as the average penetration depth of ions.

In addition, it is preferable that the depth at which the embrittlement region 314 is formed be uniform over the entire surface of the single crystal semiconductor substrate 310. Accordingly, separation can be performed on a crystal plane equivalent to the surface of the single crystal semiconductor substrate 310 (a plane within ± 15 ° from the {211} plane). That is, the plane orientation of the surface of the single crystal semiconductor layer formed by separation of the single crystal semiconductor substrate 310 can be within ± 15 ° from the {211} plane.

The depth at which the embrittlement region 314 is formed can be 50 nm to 1 μm, preferably 50 nm to 300 nm from the surface of the single crystal semiconductor substrate 310.

When ions are added to the single crystal semiconductor substrate 310, an ion implantation apparatus or an ion doping apparatus can be used. The ion implantation apparatus excites a source gas to generate ion species, mass-separates the generated ion species, and irradiates an object with an ion species having a predetermined mass. The ion doping apparatus excites a process gas to generate ion species, and irradiates the object to be processed without mass separation of the generated ion species. Note that an ion doping apparatus including a mass separation apparatus can perform ion irradiation with mass separation in the same manner as the ion implantation apparatus.

The step of forming the embrittlement region 314 when using an ion doping apparatus can be performed under the following conditions, for example.
・ Acceleration voltage: 10 kV to 100 kV (preferably 30 kV to 80 kV)
・ Dose amount 1 × 10 ¹⁶ / cm ² or more and 4 × 10 ¹⁶ / cm ² or less ・ Beam current density ² μA / cm ² or more (preferably 5 μA / cm ² or more, more preferably 10 μA / cm ² or more)

In the case of using an ion doping apparatus, a gas containing hydrogen can be used as a source gas. By using the gas, H ⁺ , H ₂ ⁺ , and H ₃ ⁺ can be generated as ionic species. When hydrogen gas is used as a source gas, it is preferable to irradiate a large amount of H ₃ ⁺ . Specifically, it is preferable that 70% or more of H ₃ ⁺ ions are included in the ion beam with respect to the total amount of H ⁺ , H ₂ ⁺ , and H ₃ ⁺ . Moreover, it is more preferable that the ratio of H ₃ ⁺ ions is 80% or more. By increasing the ratio of H ₃ ^{+ in} this manner, the embrittlement region 314 can contain hydrogen at a concentration of 1 × 10 ²⁰ atoms / cm ³ or more. Thereby, separation in the embrittled region 314 is facilitated. In addition, by irradiating a large amount of H ₃ ⁺ ions, the embrittled region 314 can be formed in a shorter time than when H ⁺ and H ₂ ⁺ are irradiated. Further, by using H ₃ ⁺ , the average penetration depth of ions can be reduced, so that the embrittled region 314 can be formed in a shallow region.

When using an ion implantation apparatus, it is preferable to irradiate H ₃ ⁺ ions by mass separation. Of course, H ⁺ or H ₂ ⁺ may be irradiated.

As a source gas in the ion irradiation process, in addition to a gas containing hydrogen, a rare gas such as helium or argon, a halogen gas typified by fluorine gas or chlorine gas, or a halogen compound gas such as fluorine compound gas (for example, BF ₃ ) One or more kinds of gases selected from the above can be used. When helium is used as the source gas, an ion beam having a high ratio of He ⁺ ions can be generated by not performing mass separation. By using such an ion beam, the embrittled region 314 can be efficiently formed.

Further, the embrittlement region 314 can be formed by performing ion irradiation in a plurality of times. In this case, ion irradiation may be performed with different source gases, or the same source gas may be used. For example, after ion irradiation is performed using a rare gas (for example, helium) as a source gas, ion irradiation can be performed using a gas containing hydrogen as a source gas. Alternatively, ion irradiation can be performed first using a halogen gas or a halogen compound gas, and then ion irradiation can be performed using a gas containing hydrogen.

Note that the embrittlement region 314 may be formed before the insulating layer 312 is provided or after the insulating layer 312 is provided. From the viewpoint of reducing damage to the surface of the single crystal semiconductor substrate 310 due to the addition of ions, the embrittlement region 314 is preferably formed after the insulating layer 312 is formed.

Next, the base substrate 300 and the single crystal semiconductor substrate 310 are attached to each other (see FIG. 1D). Specifically, the base substrate 300 and the single crystal semiconductor substrate 310 are attached to each other with the insulating layer 302 and the insulating layer 312 which are bonding layers interposed therebetween. Note that the surfaces of the insulating layer 302 and the insulating layer 312 to be bonded are preferably cleaned by a method such as ultrasonic cleaning. After the surface of the insulating layer 302 and the surface of the insulating layer 312 are brought into contact with each other, pressure treatment is performed, so that the base substrate 300 and the single crystal semiconductor substrate 310 are bonded to each other. As a bonding mechanism, a mechanism involving Van der Waals force, a mechanism involving hydrogen bonding, and the like are considered.

Note that before the base substrate 300 and the single crystal semiconductor substrate 310 are bonded to each other, surface treatment is preferably performed on the surfaces related to the bonding. By performing the surface treatment, the bonding strength at the bonding interface between the base substrate 300 and the single crystal semiconductor substrate 310 can be improved.

Examples of the surface treatment include wet treatment, dry treatment, or a combination of wet treatment and dry treatment. Further, different wet treatments can be combined, or different dry treatments can be combined.

Examples of the wet treatment include ozone treatment using ozone water (ozone water cleaning), megasonic cleaning, or two-fluid cleaning (a method of spraying functional water such as pure water or hydrogenated water together with a carrier gas such as nitrogen). It is done. Examples of the dry treatment include ultraviolet treatment, ozone treatment, plasma treatment, bias application plasma treatment, and radical treatment. By performing the surface treatment as described above on the object to be processed, the effect of improving the hydrophilicity and cleanliness of the surface of the object to be processed is obtained. As a result, the bonding strength between the substrates can be improved.

The wet treatment is effective for removing macro dust adhering to the surface of the object to be treated. The dry treatment is effective for removing or decomposing micro dust such as organic substances adhering to the surface of the object to be treated. Here, the surface of the object to be treated is cleaned and hydrophilized by performing a dry treatment such as an ultraviolet ray treatment on the object to be treated, and then performing a wet process such as washing, and further, the watermark on the surface of the object to be treated is removed. Since generation | occurrence | production can be suppressed, it is preferable.

Further, it is preferable to perform a surface treatment using oxygen in an active state such as ozone or singlet oxygen as the dry treatment. Organic substances attached to the surface of the object to be processed can be effectively removed or decomposed by oxygen in an active state such as ozone or singlet oxygen. In addition, by combining oxygen in an active state such as ozone or singlet oxygen with treatment with light having a wavelength of less than 200 nm among ultraviolet rays, organic substances attached to the surface of the object to be processed can be more effectively removed. it can. This will be specifically described below.

For example, the surface treatment of the object to be processed is performed by irradiating ultraviolet rays in an atmosphere containing oxygen. In an atmosphere containing oxygen, irradiation with light having a wavelength of less than 200 nm and light having a wavelength of 200 nm or more of ultraviolet rays can generate ozone and singlet oxygen. Further, by irradiating light including a wavelength of less than 180 nm among ultraviolet rays, ozone can be generated and singlet oxygen can be generated.

An example of a reaction that occurs by irradiation with light having a wavelength of less than 200 nm and light having a wavelength of 200 nm or more in an atmosphere containing oxygen is shown.
O ₂ + hν (λ ₁ nm) → O ( ³ P) + O ( ³ P) (1)
O ( ³ P) + O ₂ → O ₃ (2)
O ₃ + hν (λ ₂ nm) → O ( ¹ D) + O ₂ (3)

In the reaction formula (1), irradiation with light (hν) containing a wavelength (λ ₁ nm) of less than 200 nm in an atmosphere containing oxygen (O ₂ ) results in a ground state oxygen atom (O ( ³ P)). Produces. Next, in the reaction formula (2), the oxygen atom (O ( ³ P)) in the ground state reacts with oxygen (O ₂ ) to generate ozone (O ₃ ). Then, in reaction formula (3), irradiation with light including a wavelength (λ ₂ nm) of 200 nm or more is performed in an atmosphere including the generated ozone (O ₃ ), whereby singlet oxygen O ( ¹ D) is generated. In an atmosphere containing oxygen, ozone is generated by irradiating light having a wavelength of less than 200 nm among ultraviolet rays, and singlet oxygen is generated by decomposing ozone by irradiating light having a wavelength of 200 nm or more. To do. The surface treatment as described above can be performed, for example, by irradiation with a low-pressure mercury lamp (λ ₁ = 185 nm, λ ₂ = 254 nm) in an atmosphere containing oxygen.

An example of a reaction that occurs by irradiation with light having a wavelength of less than 180 nm in an atmosphere containing oxygen is shown.
O ₂ + hν (λ ₃ nm) → O ( ¹ D) + O ( ³ P) (4)
O ( ³ P) + O ₂ → O ₃ (5)
O ₃ + hν (λ ₃ nm) → O ( ¹ D) + O ₂ (6)

In the reaction formula (4), singlet oxygen O ( ¹ D) and a ground state in an excited state are irradiated with light including a wavelength (λ ₃ nm) of less than 180 nm in an atmosphere including oxygen (O ₂ ). Of oxygen atoms (O ( ³ P)). Next, in reaction formula (5), oxygen atoms (O ( ³ P)) in the ground state and oxygen (O ₂ ) react to generate ozone (O ₃ ). In reaction formula (6), singlet oxygen and oxygen in an excited state are generated by irradiation with light having a wavelength of less than 180 nm (λ ₃ nm) in an atmosphere including the generated ozone (O ₃ ). The In an atmosphere containing oxygen, ozone is generated by irradiating light having a wavelength of less than 180 nm among ultraviolet rays, and ozone or oxygen is decomposed to generate singlet oxygen. The surface treatment as described above can be performed, for example, by irradiation with a Xe excimer UV lamp in an atmosphere containing oxygen.

Chemical bonds such as organic substances adhering to the surface of the object to be processed are cut by light having a wavelength of less than 200 nm, and organic substances adhering to the surface of the object to be processed or organic substances having broken chemical bonds are oxidatively decomposed by ozone or singlet oxygen. Can be removed. By performing the surface treatment as described above, the hydrophilicity and cleanliness of the surface of the object to be processed can be further improved, and bonding can be performed satisfactorily.

Further, heat treatment is performed after the base substrate 300 and the single crystal semiconductor substrate 310 are bonded to each other so that the bonding is strong. The heating temperature at this time needs to be a temperature at which separation in the embrittled region 314 does not proceed. For example, it is less than 400 ° C., preferably 300 ° C. or less. The heat treatment time is not particularly limited, and an appropriate condition may be set from the relationship between the treatment time and the bonding strength. For example, heat treatment can be performed at 200 ° C. for 2 hours. Note that it is also possible to locally heat only the region by irradiating the region to be bonded with microwaves or the like. When there is no problem in the bonding strength, the heat treatment may be omitted.

Next, the single crystal semiconductor substrate 310 is separated in the embrittlement region 314 (see FIG. 1E). The single crystal semiconductor substrate 310 is preferably separated by heat treatment. The heat treatment temperature can be based on the heat resistant temperature of the base substrate 300. For example, in the case where a glass substrate is used as the base substrate 300, the temperature of the heat treatment is preferably 400 ° C. or higher and 750 ° C. or lower. However, this does not apply as long as the heat resistance of the glass substrate permits. Note that in this embodiment, heat treatment is performed at 600 ° C. for 2 hours.

By performing the heat treatment as described above, a volume change of minute holes formed in the embrittled region 314 occurs, and a crack occurs in the embrittled region 314. As a result, the single crystal semiconductor substrate 310 can be separated along the embrittled region 314. Accordingly, the single crystal semiconductor layer 316 separated from the single crystal semiconductor substrate 310 remains over the base substrate 300. In addition, since the interface related to bonding is heated by this heat treatment, a covalent bond is formed at the interface, and the bonding can be further strengthened.

Here, since the single crystal semiconductor substrate 310 has a surface within ± 15 ° from the {211} plane as a surface for bonding, the single crystal semiconductor substrate 310 is separated in an embrittlement region 314 substantially parallel to the surface. Thus, the single crystal semiconductor layer 316 having a surface within ± 15 ° from the {211} surface can be formed.

Note that defects (due to a separation step or an ion irradiation step) exist on the surface (particularly the upper surface) of the single crystal semiconductor layer 316 formed as described above, and the flatness thereof is sometimes impaired. is there. Therefore, treatment for reducing defects in the single crystal semiconductor layer 316 or treatment for improving planarity of the surface of the single crystal semiconductor layer 316 is preferably performed.

In this embodiment, reduction in defects and improvement in planarity of the single crystal semiconductor layer 316 can be achieved by, for example, irradiating the single crystal semiconductor layer 316 with laser light. By irradiating the single crystal semiconductor layer 316 with laser light, the single crystal semiconductor layer 316 is melted, and a single crystal semiconductor layer with improved surface flatness is obtained by subsequent cooling and solidification.

Further, a thinning process for reducing the thickness of the single crystal semiconductor layer may be performed. For the thinning of the semiconductor layer, an etching process in which one or both of a dry etching process and a wet etching process are combined may be applied. For example, if the semiconductor layer is made of silicon, by a dry etching process using SF ₆ and 0 ₂ in the process gas, it is possible to thin the semiconductor layer.

Through the above steps, the island-shaped single crystal semiconductor layer 316 whose top surface is within ± 15 ° from the {211} plane can be formed over the base substrate 300 (see FIG. 1F).

Note that in this embodiment, reduction of defects and improvement in flatness are realized using laser light; however, one embodiment of the disclosed invention is not limited thereto. Other methods such as heat treatment may be used to reduce defects and improve flatness. Further, if the defect reduction process is unnecessary, only the flatness improving process such as an etching process may be applied.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing a semiconductor device including an n-type transistor and a p-type transistor using the single crystal semiconductor layer 316 provided over the base substrate 300 will be described with reference to FIGS. . 3 is a schematic plan view, FIG. 4 is a schematic cross-sectional view taken along line AB in FIG. 3, and FIG. 5 is a schematic cross-sectional view taken along line CD in FIG.

First, the semiconductor substrate obtained in the manufacturing process of FIG. 1 is prepared (see FIGS. 3A, 4A, and 5A).

Next, the single crystal semiconductor layer 316 is etched to form island-shaped single crystal semiconductor layers 320a and 320b (see FIGS. 3B, 4B, and 5B). .

In this case, the single crystal semiconductor layer 320a and the single crystal semiconductor layer 320b are formed so that the channel length direction of a transistor to be formed later is within ± 15 ° from the <111> axis. Here, as an example, a case where the single crystal semiconductor layer 320a and the single crystal semiconductor layer 320b are formed in a rectangular shape and the long axis of the rectangular shape is parallel to the <111> axis direction is shown. Note that the shapes of the single crystal semiconductor layer 320a and the single crystal semiconductor layer 320b are not limited to rectangular shapes.

Further, before the single crystal semiconductor layer 316 is etched, an impurity element such as boron, aluminum, or gallium or an impurity element such as phosphorus or arsenic is added to the single crystal semiconductor layer 316 in order to control the threshold voltage of the TFT. Can be added. For example, an impurity element is added to a region where an n-channel TFT is formed, and an impurity element is added to a region where a p-channel TFT is formed.

Next, after the insulating layer 322 is formed so as to cover the single crystal semiconductor layer 320a and the single crystal semiconductor layer 320b, the conductive layer 324a and the single crystal semiconductor layer 320b which overlap with the single crystal semiconductor layer 320a are formed over the insulating layer 322. Overlapping conductive layers 324b are formed (see FIGS. 4C and 5C).

A method for forming the insulating layer 322 is not particularly limited, and for example, a sputtering method, a CVD method, or the like can be used. The insulating layer 322 can be formed using one or more materials selected from silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, and the like. The insulating layer 322 may have a single-layer structure or a stacked structure.

Alternatively, the insulating layer 322 may be formed by oxidizing or nitriding the surfaces of the single crystal semiconductor layer 320a and the single crystal semiconductor layer 320b by performing plasma treatment.

The plasma treatment can be performed using, for example, a mixed gas of a rare gas such as helium, argon, krypton, or xenon and a gas such as oxygen, nitrogen oxide, ammonia, nitrogen, or hydrogen. In this case, high-density plasma can be generated at a low electron temperature by exciting the plasma by introducing a microwave. The surfaces of the single crystal semiconductor layer 320a and the single crystal semiconductor layer 320b are caused by oxygen radicals (which may include OH radicals) or nitrogen radicals (which may include NH radicals) generated by such high-density plasma. By oxidizing or nitriding, an insulating layer having a thickness of 1 nm to 20 nm, preferably 2 nm to 10 nm can be formed.

Since oxidation or nitridation of the single crystal semiconductor layer 320a and the single crystal semiconductor layer 320b by the plasma treatment described above is a solid-phase reaction, the interface state density between the insulating layer 322, the single crystal semiconductor layer 320a, and the single crystal semiconductor layer 320b is increased. Can be lowered. In addition, when the single crystal semiconductor layer 320a and the single crystal semiconductor layer 320b are directly oxidized or nitrided by plasma treatment, variation in thickness of the formed insulating layer can be suppressed.

The insulating layer 322 formed by the above-described method functions as a gate insulating layer of a transistor using the single crystal semiconductor layer 320a as a channel layer or a transistor using the single crystal semiconductor layer 320b as a channel layer.

The conductive layers 324a and 324b are formed of tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium (Nb), or the like. It can be formed using a material. Alternatively, the conductive layer 324a and the conductive layer 324b may be formed using an alloy material containing any of these metals as a main component, or may be formed using a compound containing these metals. Alternatively, the conductive layer 324a and the conductive layer 324b may be formed using a semiconductor material such as polycrystalline silicon doped with an impurity element imparting conductivity to a semiconductor. The conductive layers 324a and 324b can be formed by a CVD method, a sputtering method, or the like. The conductive layers 324a and 324b may have a single-layer structure or a stacked structure.

The conductive layer 324a formed by the above method functions as a gate electrode of a transistor using the single crystal semiconductor layer 320a as a channel layer, and the conductive layer 324b functions as a gate electrode of a transistor using the single crystal semiconductor layer 320b as a channel layer. .

Next, an impurity element is added to the single crystal semiconductor layer 320a and the single crystal semiconductor layer 320b, whereby an n-type impurity region 326a and an impurity region 326b are formed in the single crystal semiconductor layer 320a, and p is added to the single crystal semiconductor layer 320b. A type impurity region 328a and an impurity region 328b are formed (see FIGS. 3C and 4D).

The impurity region 326a and the impurity region 326b function as a source region or a drain region of a transistor using the single crystal semiconductor layer 320a as a channel layer, and the impurity region 328a and the impurity region 328b are transistors using the single crystal semiconductor layer 320b as a channel layer. Functions as a source region or a drain region.

As the impurity element, an impurity element imparting p-type conductivity such as boron, aluminum, or gallium, or an impurity element imparting n-type conductivity such as phosphorus or arsenic may be added.

Next, after an insulating layer 332 is formed so as to cover the conductive layer 324a, the conductive layer 324b, and the insulating layer 322, the conductive layer 334a, the impurity region 326b, and the A conductive layer 334b electrically connected to the impurity region 328a and a conductive layer 334c electrically connected to the impurity region 328b are formed (see FIGS. 3D, 4E, and 5D).

The insulating layer 332 can be formed using an inorganic insulating material such as silicon oxide or silicon oxynitride, or an organic insulating material such as polyimide or acrylic. The insulating layer 332 may have a single-layer structure or a stacked structure in which a plurality of insulating layers are stacked.

As the conductive layer 334a, the conductive layer 334b, and the conductive layer 334c, aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), Nd (Neodymium), a metal containing an element selected from scandium (Sc), an alloy containing the above element as a component, or a material made of a nitride containing the above element as a component, or a single layer or a stacked layer. can do. These materials can be formed using a sputtering method, a vacuum deposition method, or the like.

Through the above steps, an n-type transistor 330a using the single crystal semiconductor layer 320a as a channel layer and a p-type transistor 330b using the single crystal semiconductor layer 320b as a channel layer can be formed.

In the transistor structure described in this embodiment, the n-channel transistor 330a and the p-channel transistor 330b have channel length directions within ± 15 ° from the <111> axis, preferably ± from the <111> axis. It is preferable to form within 10 °, more preferably within ± 5 ° from the <111> axis. By setting the channel length direction to such a direction, a difference in mobility between the n-channel transistor and the p-channel transistor can be reduced. As a result, the channel layers (channel length L and channel width W) constituting the n-channel transistor and the p-channel transistor can be made to have the same level, which is caused by the difference in capacitance. Variations in signals can be suppressed.

Note that although the case where a CMOS circuit is formed using the n-type transistor 330a and the p-type transistor 330b is described in this embodiment mode, the present invention is not limited thereto. The structures of the transistors 330a and 330b described in this embodiment can take various forms and are not limited to the structures illustrated in the drawings.

<Advantage of using {211} plane>
Next, the advantage that the upper surface of the channel layer of the transistor is the {211} plane will be described based on simulation.

First, the structure of silicon when the crystal plane and the crystal axis were changed was confirmed by computer simulation using CASTEP (manufactured by Accelrys Co., Ltd.) which is first principle calculation software.

The structure of the {211} plane viewed from the <111> axis direction is shown in FIG. 16A, the structure of the {110} plane viewed from the <110> axis direction is shown in FIG. 16B, and the {211} plane FIG. 16C shows the structure of the structure viewed from the <110> axis direction.

Next, the relationship between the transistor mobility μ and the crystal planes and crystal axes will be considered.

The mobility μ of the transistor is expressed by equation (7).

Here, τ is a relaxation time, and m is an effective mass. Note that equation (7) is an equation that holds in an isotropic case.

When the equation (7) is expanded to the case where μ and τ are anisotropic, the equation (8) is obtained.

As can be seen from the equation (8), μ and 1 / m are tensors. Originally, τ also has direction dependency, but for the sake of simplicity, the calculation was performed assuming that it is isotropic. Specifically, the direction dependency of 1 / m was calculated, and the silicon crystal plane and the channel direction in which the mobility of the n-type carrier and the p-type carrier were approximately the same were obtained. As a result, it was found that the mobility of the n-type carrier and the p-type carrier is approximately the same in the <111> axis direction of the {211} plane.

As described above, in the <111> axis direction of the {211} plane, the mobility of the n-type carrier and the p-type carrier is approximately the same, and thus an n-channel transistor and a p-channel transistor are formed using this. The size of the channel layer (channel length L, channel width W) of the transistor can be made approximately the same. Thereby, the dispersion | variation in the signal resulting from the difference in electrostatic capacitance can be suppressed.

Further, the semiconductor layer can be integrated by forming a channel layer using a crystal plane and a crystal axis which are suitable for an n-channel transistor and a p-channel transistor.

<Modification>
Although FIG. 1 illustrates the case where one base substrate 300 and one single crystal semiconductor substrate 310 are bonded to each other, this embodiment is not limited thereto. A plurality of single crystal semiconductor substrates may be attached to one base substrate 300. Hereinafter, a case where a plurality of semiconductor substrates are bonded to the base substrate 300 will be described with reference to FIGS.

First, the base substrate 300 is prepared, and the insulating layer 302 is formed over the base substrate 300 (see FIG. 6A). Here, the case where silicon nitride or silicon nitride oxide is used for the insulating layer 302 is shown.

Next, a plurality of (here, three) single crystal semiconductor substrates 310 provided with an insulating layer 312 on the surface and provided with an embrittlement region 314 at a predetermined depth are prepared (see FIG. 6B). The plurality of single crystal semiconductor substrates 310 are attached to the base substrate 300 (see FIG. 6C). Here, bonding is performed through an insulating layer 312 formed over the single crystal semiconductor substrate 310 and an insulating layer 302 formed over the base substrate 300.

Next, heat treatment is performed to separate the single crystal semiconductor substrate 310 in the embrittled region 314, whereby a plurality of single crystal semiconductor layers 316 are provided over the base substrate 300 with the insulating layers 312 interposed therebetween (FIG. 6D). reference).

In this manner, when a plurality of semiconductor substrates are bonded to one base substrate, the insulating layer 302 functioning as a barrier layer is formed on the base substrate 300 having a large size, so that the base substrate 300 is provided. Intrusion of impurities into the single crystal semiconductor layer 316 from gaps between the plurality of single crystal semiconductor layers 316 can be effectively suppressed.

Note that in this embodiment, the contents described in each drawing can be combined with or replaced with the contents described in another embodiment as appropriate.

(Embodiment 2)
In this embodiment, a method for manufacturing a single crystal silicon substrate is described below with reference to drawings.

FIG. 7A illustrates a single crystal silicon ingot 601 that is a base of a single crystal silicon substrate. As the single crystal silicon ingot 601, for example, a crystal obtained by growing in the <111> axial direction using a seed crystal in the <111> axial direction by the Czochralski method (CZ method) can be used. In addition, a crystal grown in the <100> axial direction using a seed crystal in the <100> axial direction or a crystal grown in the <110> axial direction using a seed crystal in the <110> axial direction is used. Also good.

Next, the single crystal silicon ingot 601 is cut and peripherally ground. Specifically, for example, the single crystal silicon ingot 601 is cut to a predetermined length so that the shoulder portion 602 and the tail portion 603 of the single crystal silicon ingot 601 are removed. Further, the outer periphery is ground so as to have a predetermined diameter. Thus, a cylindrical single crystal silicon ingot 604 is obtained (see FIG. 7B). The cutting can be performed using a band saw or the like. Moreover, said grinding can be performed by rotating the wheel provided with the diamond grindstone at high speed, and making it contact with the ingot surface.

Next, an orientation flat (orientation flat) or notch is provided as an index indicating the crystal orientation. Since orientation flats and notches are important indicators of the crystal orientation axis, they are formed using a precision three-dimensional cylindrical grinder after precise measurement of crystal axes using X-rays. Here, a notch is provided in the <111> axial direction. Of course, a notch may be provided in a direction perpendicular to the <111> axis.

Next, the notched single crystal silicon ingot 604 is 19.47 ° ± 15 °, preferably 19.47 ° ± 10 °, more preferably 19.47 ° ± with respect to the {111} plane. By slicing at an inclination angle of 5 °, a single crystal silicon substrate 605 having a surface within ± 15 ° from the {211} plane as a surface is formed (see FIGS. 7C1 and 7C2). Here, FIG. 7C1 is a perspective view of the single crystal silicon substrate 605, and FIG. 7C2 is a plan view of the single crystal silicon substrate 605. FIG. The slicing is performed using an outer peripheral saw or inner peripheral saw that is a single-wafer cutting method, a multi-wire saw that is a batch cutting method, or the like. From the cutting accuracy, it is preferable to use an inner peripheral saw for a diameter of 200 mm or less and a multi-wire saw for a diameter of 200 mm or more.

When an ingot grown in the <100> axis direction is used, it is 35.26 ° ± 15 °, preferably 35.26 ° ± 10 °, more preferably 35.35 with respect to the {100} plane. By slicing at an inclination angle of 26 ° ± 5 °, a single crystal silicon substrate having a surface within ± 15 ° from the {211} plane as a surface can be obtained. When an ingot grown in the <110> axial direction is used, it is 30.00 ° ± 15 °, preferably 30.00 ° ± 10 °, more preferably 30.30 with respect to the {110} plane. By slicing at an inclination angle of 00 ° ± 5 °, a single crystal silicon substrate having a surface within ± 15 ° from the {211} plane as a surface can be obtained.

Since the single crystal silicon substrate 605 formed in this manner is obtained by slicing a cylindrical single crystal silicon ingot 604 obliquely with respect to the {111} plane, the outer shape of the single crystal silicon substrate 605 is elliptical. It has become. Since the outer shape of the single crystal silicon substrate 605 remains elliptical and is difficult to handle in a later process, it is preferable to form the single crystal silicon substrate 606 by rounding the outer shape of the single crystal silicon substrate 605 by peripheral grinding or the like (see FIG. 7 (D1)). 7D1 is a perspective view of the single crystal silicon substrate 606, and FIG. 7D2 is a plan view of the single crystal silicon substrate 606. FIG. The rounding can be performed together with chamfering. By rounding the outer shape of the single crystal silicon substrate, the ease of handling in the subsequent process can be improved.

FIG. 7E illustrates an upper surface of the single crystal silicon substrate 607 which is provided with orientation flat instead of the notch and then rounded. Even in this case, it is desirable to provide the orientation flat in the <111> axial direction or a direction perpendicular thereto.

Note that, when the above-described cylindrical single crystal silicon ingot is cut, if the inclination angle from the {111} plane is increased, the removal amount of the shoulder portion and the tail portion is increased, leading to loss of the single crystal silicon material. Further, when the cylindrical single crystal silicon ingot is sliced, the ellipticity of the sliced single crystal silicon substrate 605 increases as the inclination angle from the {111} plane increases. When the ellipticity of the single crystal silicon substrate 605 is increased, the amount of grinding by the outer periphery grinding must be increased during rounding, and in this case as well, the loss of the single crystal silicon material results.

In order to reduce the loss of the single crystal silicon material as described above, for example, a single crystal silicon ingot 611 grown in the <211> axial direction using a seed crystal in the <211> axial direction may be used (see FIG. 8 (A)).

Also in this case, the single crystal silicon ingot 611 is cut and peripherally ground to form the single crystal silicon ingot 614 (see FIG. 8B), and then an orientation flat or notch is provided. For the details of the cutting process, the peripheral grinding process, the orientation flat or the notching, the above description can be referred to.

The slicing is performed within ± 15 °, preferably within ± 10 °, more preferably ± 5 ° from the {211} plane of the single crystal silicon ingot 614 provided with a notch. Thus, a single crystal silicon substrate 615 having a surface within ± 15 ° from the {211} plane is formed (see FIGS. 8C, 8D1, and 8D2). 8D1 is a perspective view of the single crystal silicon substrate 615, and FIG. 8D2 is a plan view of the single crystal silicon substrate 615. FIG.

As described above, when the single crystal silicon substrate is formed by the method shown in FIG. 8, the tilt angle can be made smaller than in the case where the single crystal silicon substrate is formed by the method shown in FIG. For this reason, there is an advantage that loss of the single crystal silicon material due to the tilt angle can be reduced.

Note that although the single crystal silicon substrate formed as described above is circular, it may be processed into a rectangle or a polygon. For example, as shown in FIG. 9, from a circular single crystal silicon substrate 621 (see FIG. 9A) to a rectangular single crystal silicon substrate 622 (see FIG. 9B), a polygonal single crystal silicon substrate 623. (See FIG. 9C) can be cut out.

Note that FIG. 9B illustrates the case where a rectangular single crystal silicon substrate 622 that is inscribed in the circular single crystal silicon substrate 621 and has the largest area is cut out. Here, the internal angle of the corner (vertex) of the single crystal silicon substrate 622 is approximately 90 degrees. FIG. 9C illustrates the case where a single crystal silicon substrate 623 having a longer distance between opposite sides than the single crystal silicon substrate 622 is cut out. In this case, the internal angle of the corner (vertex) of the single crystal silicon substrate 623 is not 90 degrees, and the single crystal silicon substrate 623 is not a rectangle but a polygon.

Note that the above description is for the case where a circular single crystal silicon substrate is processed into a rectangular shape or a polygonal shape; however, one embodiment of the disclosed invention is not limited thereto. For example, in the process according to FIG. 7, an elliptical single crystal silicon substrate may be rectangularized without being rounded.

After the above steps, the single crystal silicon substrate processed into a predetermined shape can be manufactured by lapping, etching, donor killer treatment, mirror polishing, cleaning, and the like.

(Embodiment 3)
In this embodiment mode, specific modes of a semiconductor device will be described with reference to the drawings.

First, a microprocessor will be described as an example of a semiconductor device. FIG. 10 is a block diagram illustrating a configuration example of the microprocessor 500.

The microprocessor 500 includes an arithmetic circuit 501 (also referred to as Arithmetic logic unit. ALU), an arithmetic circuit controller 502 (ALU Controller), an instruction analyzer 503 (Instruction Decoder), an interrupt controller 504 (Interrupt Controller), and a timing controller. 505 (Timing Controller), a register 506 (Register), a register controller 507 (Register Controller), a bus interface 508 (Bus I / F), a read-only memory 509, and a memory interface 510.

An instruction input to the microprocessor 500 via the bus interface 508 is input to the instruction analysis unit 503 and decoded, and then to the arithmetic circuit control unit 502, the interrupt control unit 504, the register control unit 507, and the timing control unit 505. Entered. The arithmetic circuit control unit 502, the interrupt control unit 504, the register control unit 507, and the timing control unit 505 perform various controls based on the decoded instruction.

The arithmetic circuit control unit 502 generates a signal for controlling the operation of the arithmetic circuit 501. The interrupt control unit 504 is a circuit that processes an interrupt request from an external input / output device or a peripheral circuit while the microprocessor 500 is executing a program. And processing an interrupt request. The register control unit 507 generates an address of the register 506 and reads and writes the register 506 in accordance with the state of the microprocessor 500. The timing control unit 505 generates a signal that controls the operation timing of the arithmetic circuit 501, the arithmetic circuit control unit 502, the instruction analysis unit 503, the interrupt control unit 504, and the register control unit 507. For example, the timing control unit 505 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1. As shown in FIG. 10, the internal clock signal CLK2 is input to another circuit.

Next, an example of a semiconductor device having a function of performing transmission / reception of data without contact and an arithmetic function will be described. FIG. 11 is a block diagram illustrating a configuration example of such a semiconductor device. The semiconductor device illustrated in FIG. 11 can be referred to as a computer that operates by transmitting and receiving signals to and from an external device by wireless communication (hereinafter referred to as “RFCPU”).

As illustrated in FIG. 11, the RFCPU 511 includes an analog circuit unit 512 and a digital circuit unit 513. The analog circuit unit 512 includes a resonance circuit 514 having a resonance capacity, a rectifier circuit 515, a constant voltage circuit 516, a reset circuit 517, an oscillation circuit 518, a demodulation circuit 519, a modulation circuit 520, and a power management circuit 530. Yes. The digital circuit unit 513 includes an RF interface 521, a control register 522, a clock controller 523, a CPU interface 524, a central processing unit 525, a random access memory 526, and a read only memory 527.

The outline of the operation of the RFCPU 511 is as follows. A signal received by the antenna 528 generates an induced electromotive force by the resonance circuit 514. The induced electromotive force is charged in the capacitor unit 529 through the rectifier circuit 515. Capacitance portion 529 is preferably formed of a capacitor such as a ceramic capacitor or an electric double layer capacitor. The capacitor portion 529 does not need to be integrated on the substrate constituting the RFCPU 511, and can be incorporated into the RFCPU 511 as another component.

The reset circuit 517 generates a signal that resets and initializes the digital circuit portion 513. For example, a signal that rises after a rise in the power supply voltage is generated as a reset signal. The oscillation circuit 518 changes the frequency and duty ratio of the clock signal in accordance with the control signal generated by the constant voltage circuit 516. The demodulation circuit 519 is a circuit that demodulates the received signal, and the modulation circuit 520 is a circuit that modulates data to be transmitted.

For example, the demodulation circuit 519 is formed of a low-pass filter, and binarizes an amplitude modulation (ASK) reception signal based on the amplitude fluctuation. In addition, in order to transmit transmission data by changing the amplitude of an amplitude modulation (ASK) transmission signal, the modulation circuit 520 changes the amplitude of the communication signal by changing the resonance point of the resonance circuit 514.

The clock controller 523 generates a control signal for changing the frequency and duty ratio of the clock signal in accordance with the power supply voltage or the current consumption in the central processing unit 525. The power supply management circuit 530 monitors the power supply voltage.

A signal input from the antenna 528 to the RFCPU 511 is demodulated by the demodulation circuit 519 and then decomposed into a control command and data by the RF interface 521. The control command is stored in the control register 522. The control command includes reading of data stored in the read-only memory 527, writing of data to the random access memory 526, an arithmetic instruction to the central processing unit 525, and the like.

The central processing unit 525 accesses the read only memory 527, the random access memory 526, and the control register 522 via the CPU interface 524. The CPU interface 524 has a function of generating an access signal for any of the read-only memory 527, the random access memory 526, and the control register 522 from the address requested by the central processing unit 525.

As a calculation method of the central processing unit 525, a method in which an OS (operating system) is stored in the read-only memory 527 and a program is read and executed together with activation can be employed. Further, it is also possible to adopt a method in which an arithmetic circuit is configured by a dedicated circuit and arithmetic processing is processed in hardware. In the system using both hardware and software, a system in which a part of arithmetic processing is performed by a dedicated arithmetic circuit and the remaining arithmetic operations are processed by the central processing unit 525 using a program can be applied.

Next, the display device will be described with reference to FIGS.

FIG. 12 is a diagram for explaining a liquid crystal display device. 12A is a plan view of a pixel of the liquid crystal display device, and FIG. 12B is a cross-sectional view of FIG. 12A taken along the line JK.

As shown in FIG. 12A, a pixel includes a single crystal semiconductor layer 820, a scan line 822 that intersects with the single crystal semiconductor layer 820, a signal line 823 that intersects with the scan line 822, a pixel electrode 824, a pixel An electrode 828 that electrically connects the electrode 824 and the single crystal semiconductor layer 820 is provided. The single crystal semiconductor layer 820 is a single crystal semiconductor layer whose upper surface is a plane within ± 15 ° from the {211} plane described in Embodiment 1, and forms a TFT 825 of a pixel.

As shown in FIG. 12B, a single crystal semiconductor layer 820 is stacked over the base substrate 300 with the insulating layer 302 and the insulating layer 312 interposed therebetween. As the base substrate 300, a glass substrate can be used. A single crystal semiconductor layer 820 of the TFT 825 is a film formed by element isolation of a single crystal semiconductor layer by etching. In the single crystal semiconductor layer 820, a channel formation region 840 and an n-type high concentration impurity region 841 to which an impurity element is added are formed. A gate electrode of the TFT 825 is included in the scanning line 822, and one of the source electrode and the drain electrode is included in the signal line 823.

A signal line 823, a pixel electrode 824, and an electrode 828 are provided over the interlayer insulating film 827. A columnar spacer 829 is formed on the interlayer insulating film 827. An alignment film 830 is formed to cover the signal line 823, the pixel electrode 824, the electrode 828, and the columnar spacer 829. The counter substrate 832 is provided with a counter electrode 833 and an alignment film 834 that covers the counter electrode. The columnar spacer 829 is formed to maintain a gap between the base substrate 300 and the counter substrate 832. A liquid crystal layer 835 is formed in a gap formed by the columnar spacer 829. A connection portion between the signal line 823 and the electrode 828 and the high-concentration impurity region 841 has a step in the interlayer insulating film 827 due to the formation of the contact hole. For this reason, columnar spacers 829 are formed at the stepped portions to prevent liquid crystal alignment disorder.

Next, an electroluminescent display device (hereinafter referred to as an EL display device) will be described with reference to FIG. 13A is a plan view of a pixel of the EL display device, and FIG. 13B is a cross-sectional view of FIG. 13A taken along the line JK.

As shown in FIG. 13A, the pixel includes a selection transistor 401 made of TFT, a display control transistor 402, a scanning line 405, a signal line 406, a current supply line 407, and a pixel electrode 408. Each pixel is provided with a light-emitting element having a structure in which a layer (EL layer) formed including an electroluminescent material is sandwiched between a pair of electrodes. One electrode of the light emitting element is a pixel electrode 408. In the single crystal semiconductor layer 403, a channel formation region, a source region, and a drain region of the selection transistor 401 are formed. In the single crystal semiconductor layer 404, a channel formation region, a source region, and a drain region of the display control transistor 402 are formed. The single crystal semiconductor layers 403 and 404 are layers formed from a single crystal semiconductor layer provided over a base substrate.

In the selection transistor 401, the gate electrode is included in the scanning line 405, one of the source electrode and the drain electrode is included in the signal line 406, and the other is formed as the electrode 411. In the display control transistor 402, the gate electrode 412 is electrically connected to the electrode 411, one of the source electrode and the drain electrode is formed as an electrode 413 electrically connected to the pixel electrode 408, and the other is supplied with current. Included in line 407.

The display control transistor 402 is a p-channel TFT. As shown in FIG. 13B, a channel formation region 451 and a p-type high concentration impurity region 452 are formed in the single crystal semiconductor layer 404. Note that the semiconductor substrate used in this embodiment is the semiconductor substrate manufactured in Embodiment 1.

An interlayer insulating film 427 is formed to cover the gate electrode 412 of the display control transistor 402. Over the interlayer insulating film 427, a signal line 406, a current supply line 407, electrodes 411, 413, and the like are formed. Further, a pixel electrode 408 that is electrically connected to the electrode 413 is formed over the interlayer insulating film 427. The peripheral portion of the pixel electrode 408 is surrounded by an insulating partition layer 428. An EL layer 429 is formed over the pixel electrode 408, and a counter electrode 430 is formed over the EL layer 429. A counter substrate 431 is provided as a reinforcing plate, and the counter substrate 431 is fixed to the base substrate 300 by a resin layer 432.

There are two methods for controlling the gradation of an EL display device: a current driving method in which the luminance of a light-emitting element is controlled by current, and a voltage driving method in which the luminance is controlled by voltage. When the difference in values is large, it is difficult to adopt, and for this purpose, a correction circuit for correcting variation in characteristics is required. Since an EL display is manufactured by a manufacturing method including a manufacturing process of the semiconductor device according to Embodiment 1, characteristics of the selection transistor 401 and the display control transistor 402 are eliminated from pixel to pixel, and thus a current driving method is employed. can do.

In other words, various electrical devices can be manufactured by using the semiconductor device according to Embodiment 1. Electrical equipment includes video cameras, digital cameras, navigation systems, sound playback devices (car audio, audio components, etc.), computers, game machines, personal digital assistants (mobile computers, mobile phones, portable game machines, electronic books, etc.) An image reproduction apparatus provided with a recording medium (specifically, an apparatus provided with a display device capable of reproducing audio data stored in a recording medium such as a DVD (digital versatile disc) and displaying the stored image data) Examples of these are shown in FIGS.

FIG. 14A illustrates a display device, which includes a housing 901, a support base 902, a display portion 903, a speaker portion 904, a video input terminal 905, and the like. This display device is manufactured using the transistor formed by the manufacturing method described in Embodiment 1 for a driver IC, the display portion 903, or the like. The display device includes a liquid crystal display device, a light-emitting display device, and the like, and all information display devices such as a computer, a television receiver, and an advertisement display are included depending on the application. Specifically, a display, a head mounted display, a reflective projector, and the like can be given.

FIG. 14B illustrates a computer, which includes a housing 911, a display portion 912, a keyboard 913, an external connection port 914, a pointing device 915, and the like. The transistor according to Embodiment 1 can be applied not only to the pixel portion of the display portion 912 but also to a semiconductor device such as a driver IC for display, a CPU in the main body, and a memory.

FIG. 14C illustrates a mobile phone, which is a typical example of a portable information processing terminal. This mobile phone includes a housing 921, a display portion 922, operation keys 923, and the like. A transistor manufactured using the semiconductor substrate according to Embodiment 1 can be used not only for the pixel portion or the sensor portion 924 of the display portion 922 but also for a display driver IC, a memory, an audio processing circuit, and the like. The sensor unit 924 includes an optical sensor element. The brightness of the display unit 922 is controlled in accordance with the illuminance obtained by the sensor unit 924, and the operation key 923 is illuminated in accordance with the illuminance obtained by the sensor unit 924. By suppressing, the power consumption of the mobile phone can be suppressed.

The semiconductor substrate according to Embodiment 1 may be used for electronic devices such as the above-described mobile phones, PDAs (Personal Digital Assistants), digital cameras, small game machines, and portable sound reproduction devices. it can. For example, it is possible to form functional circuits such as a CPU, a memory, and a sensor, and to apply to a pixel portion of these electronic devices and a display driver IC.

14D and 14E are digital cameras. Note that FIG. 14E illustrates the back side of FIG. This digital camera includes a housing 931, a display portion 932, a lens 933, operation keys 934, a shutter button 935, and the like. The transistor according to Embodiment 1 can be used for a pixel portion of the display portion 932, a driver IC that drives the display portion 932, a memory, or the like.

FIG. 14F illustrates a digital video camera. This digital video camera includes a main body 941, a display portion 942, a housing 943, an external connection port 944, a remote control receiving portion 945, an image receiving portion 946, a battery 947, an audio input portion 948, operation keys 949, an eyepiece portion 950, and the like. . The transistor according to Embodiment 1 can be used for a pixel portion of the display portion 942, a driver IC that controls the display portion 942, a memory, a digital input processing device, or the like.

In addition, the present invention can be used for a navigation system, an audio reproducing device, an image reproducing device provided with a recording medium, and the like. The transistor according to Embodiment 1 can be used for a pixel portion of the display portion, a driver IC that controls the display portion, a memory, a digital input processing device, a sensor portion, or the like.

FIG. 15 illustrates an example of a mobile phone to which one embodiment of the present invention is applied. FIG. 15A is a front view, FIG. 15B is a rear view, and FIG. FIG. The mobile phone illustrated in FIG. 15 includes a housing 701 and a housing 702. The mobile phone shown in FIG. 15 is a so-called smartphone that has both functions of a mobile phone and a portable information terminal, has a built-in computer, and can perform various data processing in addition to voice calls.

A cellular phone shown in FIG. 15 includes a housing 701 and a housing 702. The housing 701 includes a display portion 703, a speaker 704, a microphone 705, operation keys 706, a pointing device 707, a front camera lens 708, an external connection terminal jack 709, an earphone terminal 710, and the like. 711, an external memory slot 712, a rear camera 713, a light 714, and the like. The antenna is built in the housing 701.

In addition to the above structure, the cellular phone illustrated in FIG. 15 may incorporate a non-contact IC chip, a small recording device, or the like.

The overlapping housing 701 and housing 702 (shown in FIG. 15A) can be slid, and are expanded as illustrated in FIG. 15C. A display panel or a display device to which the display device manufacturing method illustrated in FIGS. 12 or 13 is applied can be incorporated in the display portion 703. Since the display portion 703 and the front camera lens 708 are provided on the same surface, they can be used as a videophone. Further, by using the display portion 703 as a viewfinder, still images and moving images can be taken with the rear camera 713 and the light 714.

By using the speaker 704 and the microphone 705, the cellular phone illustrated in FIG. 15 can be used as an audio recording device (recording device) or an audio reproducing device. In addition, operation keys 706 can be used to perform incoming / outgoing calls, simple information input operations such as e-mail, scroll operation of a screen displayed on the display unit, cursor movement operation for selecting information displayed on the display unit, and the like. Is possible.

In addition, it is convenient to use the keyboard 711 when there is a lot of information to be handled, such as creation of a document or use as a portable information terminal. Further, by sliding the overlapping housings 701 and 702 (FIG. 15A), they can be developed as shown in FIG. 15C. When used as a portable information terminal, the mouse can be operated smoothly by using the keyboard 711 and the pointing device 707. The external connection terminal jack 709 can be connected to an AC adapter and various cables such as a USB cable, and charging and data communication with a personal computer or the like are possible. In addition, a large amount of data can be stored and moved by inserting a recording medium into the external memory slot 712.

The rear surface of the housing 702 (FIG. 15B) is provided with a rear camera 713 and a light 714, and a still image and a moving image can be taken using the display portion 703 as a viewfinder.

Further, in addition to the above functional configuration, an infrared communication function, a USB port, a TV one-segment reception function, a non-contact IC chip, an earphone jack, or the like may be provided.

The electronic device described with reference to FIGS. 15A and 15B can be manufactured using the above-described method for manufacturing a transistor and a display device.

300 base substrate 302 insulating layer 310 single crystal semiconductor substrate 312 insulating layer 314 embrittled region 316 single crystal semiconductor layer 320a single crystal semiconductor layer 320b single crystal semiconductor layer 322 insulating layer 324a conductive layer 324b conductive layer 326a impurity region 326b impurity region 328a impurity Region 328b Impurity region 330a Transistor 330b Transistor 332 Insulating layer 334a Conductive layer 334b Conductive layer 334c Conductive layer 401 Selection transistor 402 Display control transistor 403 Single crystal semiconductor layer 404 Single crystal semiconductor layer 405 Scan line 406 Signal line 407 Current supply line 408 Pixel electrode 411 Electrode 412 Gate electrode 413 Electrode 427 Interlayer insulating film 428 Partition layer 429 EL layer 430 Counter electrode 431 Counter substrate 432 Resin layer 451 Channel formation region 452 High concentration Impurity region 500 Microprocessor 501 Arithmetic circuit 502 Arithmetic circuit control unit 503 Instruction analysis unit 504 Control unit 505 Timing control unit 506 Register 507 Register control unit 508 Bus interface 509 Dedicated memory 510 Memory interface 511 RFCPU
512 Analog circuit unit 513 Digital circuit unit 514 Resonant circuit 515 Rectifier circuit 516 Constant voltage circuit 517 Reset circuit 518 Oscillator circuit 519 Demodulator circuit 520 Modulator circuit 521 RF interface 522 Control register 523 Clock controller 524 CPU interface 525 Central processing unit 526 Random access memory 527 Dedicated memory 528 Antenna 529 Capacitance unit 530 Power management circuit 601 Single crystal silicon ingot 602 Shoulder 603 Tail 604 Single crystal silicon ingot 605 Single crystal silicon substrate 606 Single crystal silicon substrate 607 Single crystal silicon substrate 611 Single crystal silicon ingot 614 Single crystal Silicon ingot 615 Single crystal silicon substrate 621 Single crystal silicon substrate 622 Single crystal silicon substrate 623 Single Crystal silicon substrate 701 Case 702 Case 703 Display unit 704 Speaker 705 Microphone 706 Operation key 707 Pointing device 708 Front camera lens 709 External connection terminal jack 710 Earphone terminal 711 Keyboard 712 External memory slot 713 Back camera 714 Light 820 Single crystal semiconductor Layer 822 Scan line 823 Signal line 824 Pixel electrode 825 TFT
827 Interlayer insulating film 828 Electrode 829 Columnar spacer 830 Alignment film 832 Counter substrate 833 Counter electrode 834 Alignment film 835 Liquid crystal layer 840 Channel formation region 841 High-concentration impurity region 901 Housing 902 Support base 903 Display portion 904 Speaker portion 905 Video input terminal 911 Case 912 Display unit 913 Keyboard 914 External connection port 915 Pointing device 921 Case 922 Display unit 923 Operation key 924 Sensor unit 931 Case 932 Display unit 933 Lens 934 Operation key 935 Shutter button 941 Main body 942 Display unit 943 Case 944 External Connection port 945 Remote control receiver 946 Image receiver 947 Battery 948 Audio input 949 Operation key 950 Eyepiece

Claims (6)

Irradiating a single crystal silicon substrate having a surface within ± 15 ° from the {211} plane with accelerated ions to form an embrittled region in the single crystal silicon substrate;
Bonding the single crystal silicon substrate and the base substrate through an insulating layer;
Separating the single crystal silicon substrate in the embrittlement region, and forming a single crystal silicon layer having a surface within ± 15 ° from the {211} plane on the base substrate;
Forming a n-channel transistor and a p-channel transistor having a channel length direction within ± 15 ° from the <111> axis using the single crystal silicon layer. In claim 1,
A method for manufacturing a semiconductor device, wherein the insulating layer is formed by oxidizing the single crystal silicon substrate in an atmosphere containing chlorine. In claim 1 or claim 2,
A method for manufacturing a semiconductor device in which a channel length direction of the n-channel transistor and a channel length direction of the p-channel transistor are parallel to each other. In any one of Claims 1 thru | or 3,
A method for manufacturing a semiconductor device, in which a CMOS circuit is formed using the n-channel transistor and the p-channel transistor. In any one of Claims 1 thru | or 4,
A method for manufacturing a semiconductor device, in which a glass substrate, a polysilicon substrate, or a single crystal silicon substrate is used as the base substrate. In any one of Claims 1 thru | or 5,
A method for manufacturing a semiconductor device, wherein a substrate having an orientation flat or a notch in a <111> axis direction or a direction perpendicular to a <111> axis is used as the single crystal silicon substrate.

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