JP2010250564A - Sensing device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress an increase in device scale while reducing fixed pattern noise. <P>SOLUTION: A sensing device 10 includes a plurality of detection circuits P, a driving circuit 20, a plurality of holding parts 30, a plurality of amplification parts U, a control part 50, a line memory 46, and a differential circuit 48. In a first read period Te in each unit period T, a first signal generated in each amplification part U is supplied to the line memory 46. In a second read period Tf in each unit period T, a difference between a second signal generated in each amplification part U and the first signal read out from the line memory 46 is calculated. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a sensing device and an electronic device that output a signal corresponding to a state of a detection element.

  Conventionally, a display device having a function of detecting that an object such as a finger or a pen has approached the screen is known. For example, the display device disclosed in Patent Document 1 converts data indicating the amount of light received by each of a plurality of optical sensors incorporated in a display screen into a sensing image, and a sensing image at an arbitrary time, and 1 more than that. Whether or not the object has approached the screen is detected based on the difference data from the frame or the sensing image two frames before.

JP 2006-244446 A

By the way, in the technique of Patent Document 1, the optical sensor is controlled using a TFT (Thin Film Transistor). Since TFTs have large variations in characteristics compared to CMOS, it is desirable to reduce fixed pattern noise caused by variations in TFT characteristics in optical sensors using TFTs. According to the technique of Patent Document 1, it is possible to remove fixed pattern noise by taking the difference between sensing images in two frames, but this requires a frame memory. Therefore, there has been a problem that the scale of the apparatus is increased.
In view of the above circumstances, an object of the present invention is to solve the problem of suppressing an increase in apparatus scale while reducing fixed pattern noise.

  In order to solve the above problems, the sensing device according to the present invention is arranged corresponding to the intersection of the plurality of control lines and the plurality of signal lines, and each of the detection signals corresponds to the state of the detection element. A plurality of detection circuits that generate a signal, a drive circuit that sequentially outputs a drive signal for driving the detection circuit corresponding to the control line, and a plurality of signal lines, And a plurality of holding units that hold detection signals generated by a detection circuit corresponding to the control line from which the drive signal is output, and a plurality of holding units that are provided in one-to-one correspondence. Amplifying the detection signal held in the corresponding holding unit and outputting the first signal, and reading out the second signal corresponding to the characteristics of the amplifying unit for each of the plurality of amplifying units Is controlled to be in a possible state, the second And a control unit to output the items, a memory for storing a first signal corresponding to the number of the plurality of amplifier unit, a second signal, a differential circuit for calculating a difference between the first signal read from the memory.

More specifically, the amplification unit includes a source follower amplifier including a current amplification transistor, and the control unit controls the amplification unit so that the threshold voltage of the current amplification transistor is reflected in the second signal. Each amplification unit includes a constant current source, a constant current source, and a second power source arranged between a first power supply line to which a first potential is supplied and a second power supply line to which a second potential is supplied. A current amplifying transistor disposed between the line and a first switching element disposed between a gate and a drain of the current amplifying transistor, between the constant current source of each amplifying unit and the current amplifying transistor. Between the output terminal and the output line, a plurality of amplification units and a plurality of second switching elements corresponding to the one-to-one are arranged. All the first switching elements of the amplifying unit are turned off, and each second switching element is sequentially turned on. In the second reading period in which the second signal is read out after the first reading period, The first switching element of the amplifier As well as the on state Te and sequentially turned on each of the second switching element.
When the first potential is higher than the second potential, the current amplification transistor is configured as a P-channel type, and when the first potential is lower than the second potential, the current amplification transistor is configured as an N-channel type. Is preferred.

  According to the above aspect, by taking the difference between the first signal for one row and the second signal reflecting the threshold voltage of the current amplification transistor of each amplification unit, the characteristics of the current amplification transistor of each amplification unit are obtained. Can be compensated for. In this aspect, since the difference is taken in units of rows, the capacity of the memory is sufficient to hold the first signal for one row. That is, according to this aspect, there is an advantage that the fixed pattern noise caused by the variation in the characteristics of the current amplifying transistors of the respective amplifying units can be removed and the increase in the scale of the apparatus can be suppressed.

  Moreover, as an aspect of the sensing device according to the present invention, each amplifying unit includes a constant current disposed between a first power supply line to which a first potential is supplied and a second power supply line to which a second potential is supplied. A first current amplifier disposed between a power source, a current amplification transistor disposed between the constant current source and the second power supply line, a third power supply line to which a third potential is supplied, and a gate of the current amplification transistor. A plurality of second switching units corresponding to the plurality of amplification units on a one-to-one basis between the output terminal between the constant current source of each amplification unit and the current amplification transistor and the output line. In the first read period in which the first signal is read, the control unit turns off all the first switching elements of each amplification unit and sequentially turns on the second switching elements to perform the first reading. After the period, the second signal In the second reading period that begins seen, as well as all turned on the first switching element of each amplification unit, to sequentially turn on the respective second switching element.

  In this aspect, by setting the third potential supplied to the third power supply line to a predetermined value, it is possible to give a predetermined offset to the second signal read in the second reading period. Thereby, the difference which is an output signal can be set to a desired value.

  As another aspect of the sensing device according to the present invention, a plurality of control devices are arranged corresponding to intersections of a plurality of control lines and a plurality of signal lines, and each generates a plurality of detection signals according to the state of the detection element. A detection circuit, a drive circuit that sequentially outputs a drive signal for driving the detection circuit corresponding to the control line, and a plurality of signal lines are provided in a one-to-one correspondence with the plurality of control lines. A plurality of holding units that hold detection signals generated by a detection circuit corresponding to the control line to which the drive signal is output, and a plurality of holding units that are provided in a one-to-one correspondence with the holding units. A plurality of amplifying units that amplify the detection signal held in step 1 and output the first signal, and a state in which the second signal corresponding to the characteristics of the amplifying unit can be read out for each of the plurality of amplifying units Control to output the second signal. And a control unit, a memory for storing a second signal corresponding to the number of the plurality of amplifier unit, a first signal, and a differential circuit for calculating a difference between the second signal read from memory.

  More specifically, the amplification unit includes a source follower amplifier including a current amplification transistor, and the control unit controls the amplification unit so that the threshold voltage of the current amplification transistor is reflected in the second signal. Each amplification unit includes a constant current source, a constant current source, and a second power source arranged between a first power supply line to which a first potential is supplied and a second power supply line to which a second potential is supplied. A current amplifying transistor disposed between the line and a first switching element disposed between a gate and a drain of the current amplifying transistor, between the constant current source of each amplifying unit and the current amplifying transistor. Between the output terminal and the output line, a plurality of amplification units and a plurality of second switching elements corresponding to the one-to-one correspondence are arranged. All the first switching elements of the amplifying unit are turned on, and each second switching element is sequentially turned on, and each amplification is performed in a first read period after the second read period and reading the first signal. All first switching elements While the OFF state, and sequentially turned on each of the second switching element.

  In this aspect, first, the second signal corresponding to the threshold voltage of the current amplification transistor of each amplifier is read and stored in the memory, and then the first signal of each row, the second signal read from the memory, and The difference is calculated. According to this aspect, in order to read the second signal after reading the first signal for one row, all the first switching elements of each amplification unit are turned on and the second switching elements are sequentially turned on. There is no need to control the state to be in a state, and it is only necessary to read the second signal from the memory. Therefore, there are advantages that the control process can be simplified and the second signal can be read quickly.

  Each amplification unit includes a constant current source, a constant current source, and a second power source arranged between a first power supply line to which a first potential is supplied and a second power supply line to which a second potential is supplied. A current amplifying transistor disposed between the line, a third power supply line to which a third potential is supplied, and a first switching element disposed between a gate and a drain of the current amplifying transistor, Between the output terminal between the constant current source of the amplification unit and the current amplification transistor and the output line, a plurality of amplification units and a plurality of second switching elements corresponding to the one-to-one are arranged, and the control unit In the second readout period for reading out the second signal, all the first switching elements of the amplifiers are turned on, and the second switching elements are sequentially turned on, which is a period after the second readout period. In the first reading period for reading the first signal, A first switching element having a width portion while all turned off, it may be a mode that sequentially turns on the respective second switching element. According to this aspect, the difference as the output signal can be set to a desired value by setting the third potential supplied to the third power supply line to a predetermined value.

  Furthermore, the sensing circuit according to the present invention can be used in various electronic devices. Examples of this type of device include a fingerprint sensor, a vein sensor, a touch panel, and a contact image sensor.

1 is a block diagram illustrating a configuration of a sensing device according to a first embodiment of the present invention. It is a figure which shows the structure of the photon detection circuit which concerns on the same embodiment. It is a figure which shows the specific waveform of each signal utilized for operation | movement of the sensing apparatus which concerns on the same embodiment. It is a figure which shows operation | movement of the photon detection circuit in a reset period. It is a figure which shows operation | movement of the photon detection circuit in a sensing period. It is a figure which shows operation | movement of the photon detection circuit in a read-out period. It is a block diagram which shows the structure of the sensing apparatus which concerns on 2nd Embodiment of this invention. It is a figure which shows the specific waveform of each signal utilized for operation | movement of the sensing apparatus which concerns on 3rd Embodiment of this invention. It is a figure which shows the structure of the amplification part which concerns on the modification of this invention. It is a figure which shows the structure of the amplification part which concerns on the modification of this invention.

<A: First Embodiment>
FIG. 1 is a block diagram showing a configuration of a sensing device 10 according to the first embodiment of the present invention. As illustrated in FIG. 1, the sensing device 10 includes a plurality of detection circuits P, a drive circuit 20, a plurality of holding units 30, an output unit 40, and a control unit 50. The plurality of detection circuits P are arranged in the detection region 100. More specifically, it is as follows. The detection region 100 is provided with m control lines 70 extending in the X direction and n signal lines 80 extending in the Y direction orthogonal to the X direction (m and n are natural numbers of 2 or more). ). Each detection circuit P is arranged at a position corresponding to the intersection of the control line 70 and the signal line 80. Therefore, these detection circuits P are arranged in a matrix of m rows × n columns.

  The drive circuit 20 shown in FIG. 1 sequentially outputs a reset signal RES and a selection signal SEL for driving each detection circuit P to each control line 70 based on the signal VSYNC supplied from the control unit 50. As shown in FIG. 2, the control line 70 includes a reset line 72 and a selection line 74 each extending in the X direction. The reset signal RES [i] is supplied to the reset line 72 of the control line 70 of the i-th row (1 ≦ i ≦ m), and the selection signal SEL [i] is supplied to the selection line 74 of the control line 70 of the i-th row. It is supplied.

  FIG. 3 is a diagram illustrating a specific waveform of each signal used for the operation of the sensing device 10. As shown in FIG. 3, in each unit period T in one vertical scanning period 1V, the reset signals RES [1] to RES [m] and the selection signals SEL [1] to SEL [m] are sequentially set to the active level (high level). Level).

  As shown in FIG. 3, the driving period Td is set within each unit period T. Each drive period Td includes a reset period Tr, a sensing period Ts, and a readout period T0. In the reset period Tr of the drive period Td within the unit period T of the i-th row, the reset signal RES [i] is set to a high level. In the sensing period Ts after the reset period Tr, the reset signal RES [i] and the selection signal SEL [i] are set to a low level. In the readout period To after the sensing period Ts, the selection signal SEL [i] is set to a high level. The same applies to the other rows.

  FIG. 2 is a circuit diagram showing a detailed configuration of the detection circuit P. In FIG. 2, one detection circuit P belonging to the i-th row is shown. The detection circuit P includes an N-channel reset transistor 61, an N-channel amplification transistor 62, an N-channel selection transistor 63, and a light-receiving element that outputs a light-receiving signal having a magnitude corresponding to the amount of received light (for example, a photosensor). Diode) Q. The cathode of the light receiving element Q is connected to a fixed potential.

  As shown in FIG. 2, the reset transistor 61 is interposed between the power supply line 90 to which the power supply potential VEL is supplied and the gate of the amplification transistor 62. The gate of the reset transistor 61 is connected to the reset line 72. The amplification transistor 62 is interposed between the power supply line 90 and the selection transistor 63. The anode of the light receiving element Q is connected to the gate of the amplification transistor 62. As shown in FIG. 2, the selection transistor 63 is interposed between the amplification transistor 62 and the signal line 80. The gate of the selection transistor 63 is connected to the selection line 74.

  Next, the operation of the detection circuit P will be described. Here, the specific operation of the detection circuit P in the first row will be described with reference to FIGS. As shown in FIG. 3, in the reset period Tr, the reset signal RES [1] is set to a high level, so that the reset transistor 61 is turned on. As a result, as shown in FIG. 4, the potential VA of the gate of the amplification transistor 62 is set (reset) to the power supply potential VEL.

  As shown in FIG. 3, in the sensing period Ts, the reset signal RES [1] and the selection signal SEL [1] transition to a low level, so that the reset transistor 61 and the selection transistor 63 are off as shown in FIG. Transition to the state. At this time, the potential VA of the gate of the amplification transistor 62 is set to a value corresponding to the photoconductive current Ip of the light receiving element Q. The photoconductive current Ip of the light receiving element Q is determined according to the amount of light incident on the light receiving element Q.

  As shown in FIG. 3, during the readout period To, the selection signal SEL [1] transitions to a high level, so that the selection transistor 63 is turned on as shown in FIG. At this time, the detection current It having a magnitude corresponding to the potential VA of the gate of the amplification transistor 62 flows through the signal line 80.

  When an object such as a finger approaches or comes into contact with the detection area 100 while casting a shadow in the sensing period Ts, the amount of light received by the light receiving element Q provided corresponding to the shadowed area changes, and the photoconductivity of the light receiving element Q is changed. The current Ip changes. Accordingly, the potential VA of the gate of the amplification transistor 62 also changes. In the reading period To, a detection current It corresponding to the amount of received light is output to the signal line 80.

  Returning to FIG. 1 again, the description will be continued. As shown in FIG. 1, in this embodiment, a holding unit 30 is provided for each signal line 80. Each of the multiple (n) holding units 30 is a means for holding a detection signal (detection current It) output to the corresponding signal line 80. Each holding unit 30 includes capacitive elements C1 and C2, and a switch K interposed between the signal line 80 corresponding to the holding unit 30 and the capacitive elements C1 and C2. One electrode of the capacitive element C2 is connected on a path from the switch K to the capacitive element C1, and the other electrode is grounded. This is because the potential is determined when the switch K transitions to the off state. The switch K is controlled to be turned on / off according to the sampling signal SHG supplied from the control unit 50. A sampling signal SHG is commonly supplied to the switches K of the holding units 30. Therefore, when the sampling signal SHG transitions to the active level, the switches K of the holding units 30 are turned on simultaneously.

  The output unit 40 illustrated in FIG. 1 is a unit that generates an output signal corresponding to the detected current It held by each holding unit 30. The output unit 40 includes a plurality (n) of amplifying units U, a shift register 42, an AD converter 44, a switching unit CH, A memory 46 and a difference circuit 48 are included.

  Each amplification unit U is configured by a source follower amplifier including a current amplification transistor Ap. More specifically, it is as follows. Each amplifying unit U is arranged between the high-potential power supply line 102 to which the power supply potential VDD is supplied and the low-potential power supply line 104 to which the ground potential GND (<VDD) is supplied. Each amplification unit U includes a constant current source S, a P-channel type current amplification transistor Ap, and a first switching element SW1 configured by an N-channel type transistor. The constant current source S is connected in series with the current amplification transistor Ap. The current amplification transistor Ap is disposed between the constant current source S and the lower power supply line 104. The capacitive element C1 of the holding unit 30 corresponding to the amplification unit U is connected to the gate of the current amplification transistor Ap.

  The first switching element SW1 is disposed between the gate and drain of the current amplification transistor Ap. The first switching element SW <b> 1 is controlled to be turned on / off according to a control signal AMPG supplied from the control unit 50. A control signal AMPG is commonly supplied to the first switching element SW1 of each amplification unit U. Therefore, when the control signal AMPG transitions to the active level, the first switching elements SW1 of the amplification units U are turned on all at once.

  Between each output unit D between the constant current source S and the current amplification transistor Ap in each amplification unit U and the output line 106 connected to the AD converter 44, there is a one-to-one correspondence with n amplification units U. N second switching elements SW2 are provided. Each of the n second switching elements SW <b> 2 is controlled to be turned on / off according to the operation signal G supplied from the shift register 42. The shift register 42 outputs the operation signals G [1] to G [n] to the second switching elements SW2 based on the signal HSYNC supplied from the control unit 50.

  The output destination of the AD converter 44 is selected as one of the line memory 46 and the difference circuit 48 by the switching unit CH. The switching unit CH selects the output destination of the AD converter 44 according to the switching signal Sh supplied from the control unit 50. The switching signal Sh is a signal that designates the output destination of the AD converter 44. For example, when the line memory 46 is designated as the output destination of the AD converter 44, the switching unit 44 makes the output terminal T1 of the AD converter 44 and the input terminal T2 of the line memory 46 conductive. On the other hand, when the difference circuit 48 is designated as the output destination of the AD converter 44, the switching unit 44 makes the output terminal T1 of the AD converter 44 and the input terminal T3 of the difference circuit 48 conductive. The difference circuit 48 calculates the difference between the data supplied from the AD converter 44 and the data read from the line memory 46, and outputs the difference as an output signal.

  Next, operations of the holding unit 30 and the output unit 40 will be described with reference to FIGS. 1 and 3. As shown in FIG. 3, each unit period T is divided into a driving period Td, a first reading period Te after the driving period Td, and a second reading period Tf after the first reading period Te. Here, a specific operation in the unit period T in the first row will be described as an example.

  In the reset period Tr and the sensing period Ts within the drive period Td, the control unit 50 sets the sampling signal SHG to an inactive level (low level). Therefore, the switch K of each holding unit 30 is turned off, and each signal line 80 and the capacitive elements C1 and C2 of each holding unit 30 are in a non-conductive state. In the readout period To within the drive period Td, the control unit 50 sets the sampling signal SHG to an active level (high level). Therefore, the switch K of each holding unit 30 is turned on, and each signal line 80 and the capacitive elements C1 and C2 of each holding unit 30 are in a conductive state. Therefore, the detection current It output to each signal line 80 in the readout period To (detection current It generated by the n detection circuits P corresponding to the control line 70 in the first row) is in the on state. It is supplied to the capacitive elements C1 and C2 via the switch K. Further, since the control signal AMPG is set to an inactive level (low level), the first switching element SW1 of each amplification unit U is turned off.

  At this time, the potential of the output terminal D of each amplification unit U is set to a value corresponding to the detection current It held in the holding unit 30 (capacitance elements C1 and C2) corresponding to the amplification unit U. Explaining the amplification unit U in the j-th column (1 ≦ j ≦ n) as an example, the current amplification transistor Ap of the amplification unit U is a current obtained by amplifying the detection current It held in the corresponding holding unit 30. Is generated. At this time, the potential of the gate of the current amplification transistor Ap is set to the potential Vg corresponding to the detection current It. If the threshold voltage of the current amplification transistor Ap is Vth, the potential of the output terminal D (the current amplification transistor Ap of the current amplification transistor Ap). Source potential) is set to Vg + Vth. The same applies to other amplification units U.

  In the first readout period Te after the drive period Td, each amplifier unit U sequentially outputs a first signal corresponding to the detected current It held in the holding unit 30 corresponding to the amplifier unit U to the output line 106. To be controlled. More specifically, it is as follows. In the first reading period Te, the control unit 50 sets the sampling signal SHG to a low level. Therefore, each signal line 80 and the capacitive elements C1 and C2 of each holding unit 30 are in a non-conductive state, but the detection current It output to each signal line 80 in the reading period To is the capacitance of each holding unit 30. Held in elements C1 and C2. In addition, the control unit 50 maintains the control signal AMPG at a low level, and sequentially shifts the operation signals G [1] to G [n] to an active level (high level). Therefore, each of the n second switching elements SW2 is sequentially turned on. As a result, the potential (analog value) at the output terminal D of each amplifier unit U is sequentially output to the output line 106 via the corresponding second switching element SW2, and converted into digital data d by the AD converter 44. . At this time, the potential output from the output terminal D of each amplification unit U is a value corresponding to the detection current It held in the holding unit 30 corresponding to the amplification unit U, and this is referred to as a “first signal”. Call.

  In the first reading period Te, the line memory 46 is designated as the output destination of the AD converter 44. As a result, the digital data d output from the AD converter 44 is supplied to the line memory 46. The serial digital data d held in the line memory 46 is a set of n data (data corresponding to the first signal) indicating the amount of light received by each detection circuit P within the unit period T in the first row. Yes, it can be regarded as sensing data in the first row.

  In the second readout period Tf after the first readout period Te, each amplification unit U is controlled so as to sequentially output the second signal corresponding to the characteristics of the amplification unit U to the output line 106. More specifically, it is as follows. In the second read period Tf, the control unit 50 maintains the sampling signal SHG at a low level, while setting the control signal AMPG at a high level. Therefore, the first switching element SW1 of each amplification unit U is turned on, and the current amplification transistor Ap is diode-connected. As a result, the gate of the current amplification transistor Ap of each amplification unit U is electrically connected to the lower power supply line 104 to which the ground potential GND is supplied, so that the charge held in the holding unit 30 corresponding to the amplification unit U is low. Discharge to the side power supply line 104. At this time, the potential of the output terminal D of each amplification unit U is set to a value corresponding to the threshold voltage Vth of the current amplification transistor Ap of the amplification unit U. The j-th column amplification unit U will be described as an example. Since the potential of the gate of the current amplification transistor Ap of the amplification unit U is set to the ground potential GND, the potential of the output terminal D of the amplification unit U ( The potential of the source of the current amplification transistor Ap) is set to GND + Vth. In the present embodiment, since the ground potential GND is 0 V, the potential of the output terminal D of the amplifying unit U is set to Vth. The same applies to other amplification units U.

  In the second read period Tf, the control unit 50 sequentially shifts the operation signals G [1] to G [n] to a high level. Therefore, each of the n second switching elements SW2 is sequentially turned on. As a result, the potential at the output terminal D of each amplifier unit U is sequentially output to the output line 106 via the corresponding second switching element SW2, and converted into digital data d by the AD converter 44. At this time, the potential output from the output terminal D of each amplification unit U is a value reflecting the threshold voltage Vth of the current amplification transistor Ap of the amplification unit U, and this is referred to as a “second signal”.

In the second readout period Tf, the difference circuit 48 is designated as the output destination of the AD converter 44. As a result, the digital data d output from the AD converter 44 is supplied to the difference circuit 48. The serial digital data d supplied to the difference circuit 48 is a set of n data (data corresponding to the second signal) reflecting the threshold voltage Vth of the current amplification transistor Ap of each amplifier unit U. The difference circuit 48 calculates a difference between the data corresponding to the second signal supplied from the AD converter 44 and the data corresponding to the first signal read from the line memory 46, and uses the difference as an output signal. Output. For example, the amplification unit U in the j-th column will be described as an example. The difference circuit 48 includes the data corresponding to the second signal Vth of the amplification unit U and the amplification unit U read from the line memory 46. The difference from the data corresponding to one signal (VG + Vth) is calculated. The difference between the two is expressed by the following equation (1).
(VG + Vth) −Vth = VG (1)

  As understood from the above formula (1), the difference obtained by the difference circuit 48 is determined only by the potential VG determined according to the detection current It held in the holding unit 30 corresponding to the amplification unit U. And does not depend on the threshold voltage Vth of the current amplification transistor Ap. Therefore, according to the present embodiment, there is an advantage that the fixed pattern noise caused by the variation in the threshold voltage Vth for each amplification unit U can be suppressed. In this embodiment, since the difference is taken in units of rows, the capacity of the line memory 46 is sufficient to hold the sensing data for one row. That is, according to the present embodiment, there is an advantage that fixed pattern noise caused by variation in characteristics of each amplification unit U can be removed and an increase in the scale of the apparatus can be suppressed.

<B: Second Embodiment>
FIG. 7 is a block diagram showing a configuration of a sensing device according to the second embodiment of the present invention. In the second embodiment, the first switching element SW1 of each amplification unit U includes the gate of the current amplification transistor Ap and the offset power supply line 108 to which the potential VEE (GND <VEE <VDD in this embodiment) is supplied. It differs from 1st Embodiment by the point arrange | positioned between. Since the other configuration is the same as that of the first embodiment, the description of the overlapping parts is omitted.

In the second readout period Tf in each unit period T, when the control signal AMPG is set to a high level, the gate of the current amplification transistor Ap of each amplification unit U is conducted to the offset power line 108. The j-th column amplification unit U will be described as an example. At this time, the second signal generated by the amplification unit U (the potential of the source of the current amplification transistor Ap of the amplification unit U) is set to VEE + Vth. Is done. That is, an offset corresponding to the potential VEE supplied to the offset power supply line 108 can be given to the second signal. Then, the difference obtained by the difference circuit 48 is expressed by the following equation (2).
(VG + Vth) − (VEE + Vth) = VG−VEE (2)

  In the second embodiment, the difference (output signal) obtained by the difference circuit 48 can be set to a desired value by setting the value of the potential VEE to a predetermined value. For example, when the amount of light received by the light receiving element Q in the detection circuit P is zero (that is, in a completely dark state), the value of the potential VEE can be set so that the difference is also zero.

<C: Third Embodiment>
Next, a sensing device according to a third embodiment of the present invention will be described. In each of the above-described embodiments, the second signal generated by each amplification unit U is read for each second reading period Tf in each unit period T, and then the second signal and the first signal read from the line memory 46 are read. The difference from one signal (sensing data for one row) was calculated. Here, the value of the second signal generated in each amplification unit U is the same for each second readout period Tf in each unit period T. Focusing on this, in the third embodiment, first, the second signal generated by each amplification unit U is read out and stored in the line memory 46, and each amplification unit U is thereafter stored in each unit period T. Is different from each of the above-described embodiments in that the difference between the first signal (sensing data for one row) generated in step S1 and the second signal read from the line memory 46 is calculated. The configuration of the sensing device according to the third embodiment is the same as that of the first embodiment described above, as shown in FIG.

  FIG. 8 is a diagram illustrating specific waveforms of signals used for the operation of the sensing device according to the third embodiment. As shown in FIG. 8, one vertical scanning period V is divided into a second readout period Tf and unit periods T for m rows after the second readout period Tf. Each unit period T is divided into a driving period Td and a first reading period Te.

  In the second read period Tf, the control unit 50 sets the control signal AMPG to a high level. Therefore, the first switching element SW1 of each amplification unit U is turned on, and each current amplification transistor Ap is diode-connected. Thereby, the potential of the output terminal D of each amplification unit U is set to a value reflecting the threshold voltage Vth of the current amplification transistor Ap of the amplification unit U. That is, each amplification unit U generates a second signal. Further, in the second readout period Tf, the control unit 50 sequentially shifts the operation signals G [1] to G [n] to a high level, so that the second signal generated by each amplification unit U corresponds to the corresponding second signal. The signals are sequentially output to the output line 106 via the two switching elements SW2. The second signal output to the output line 106 is converted into digital data d by the AD converter 44. In the third embodiment, since the line memory 46 is designated as the output destination of the AD converter 44 in the second readout period Tf, the line memory 46 stores data corresponding to the second signal.

  Since the operation of the sensing device in the driving period Td within each unit period T is the same as that in each of the above-described embodiments, detailed description thereof is omitted. In the first readout period Te in each unit period T, the control unit 50 sets the sampling signal SHG and the control signal AMPG to the low level and sequentially shifts the operation signals G [1] to G [n] to the high level. Therefore, the first signal generated by each amplification unit U is sequentially output to the output line 106 via the corresponding second switching element SW2, and converted into digital data d by the AD converter 44. In the third embodiment, since the difference circuit 46 is designated as the output destination of the AD converter 44 in the first reading period Te, data corresponding to the first signal is supplied to the difference circuit 46. Then, the difference circuit 46 calculates the difference between the data corresponding to the first signal and the data corresponding to the second signal read from the line memory 46.

  As described above, in the third embodiment, first, the second signal reflecting the threshold voltage Vth of the current amplifying transistor Ap of each amplifier unit U is read out and stored in the line memory 46, and thereafter In each unit period T, the difference between the first signal for one row and the second signal read from the line memory 46 is calculated. In each of the above-described embodiments, in order to read the second signal after reading the first signal for one row in each unit period T, all the first switching elements SW1 of each amplification unit U are turned on. The second switching element SW2 needs to be controlled so as to be sequentially turned on, whereas in the third embodiment, the second signal only needs to be read from the line memory 46, so that the control process is simplified. In addition, there is an advantage that the second signal can be read quickly.

<D: Modification>
The present invention is not limited to the above-described embodiments, and for example, the following modifications are possible. Also, two or more of the modifications shown below can be combined.

(1) Modification 1
In each of the embodiments described above, each detection circuit P includes the light receiving element Q that outputs a light reception signal having a magnitude corresponding to the amount of received light. However, the present invention is not limited to this, and the detection element included in each detection circuit P. The type of is arbitrary. For example, each detection circuit P may have a contact detection capacitive element for detecting the approach or contact of an object. In short, each detection circuit P only needs to have a detection element such as the light receiving element Q and generate a detection signal corresponding to the state of the detection element.

(2) Modification 2
In the second embodiment described above, the potential VEE supplied to the offset power supply line 108 is a constant potential. However, the present invention is not limited to this, and the value of the potential VEE can be changed by an external power supply circuit (not shown). It can also be set as the aspect controlled.

(3) Modification 3
In the above-described third embodiment, the configuration of the first embodiment is employed as the configuration of the sensing device, but the configuration of the second embodiment (see FIG. 7) is not limited to this, and may be employed. It is.

(4) Modification 4
In the first embodiment described above, the current amplifying transistor Ap of each amplifying unit U is configured as a P-channel type. However, the present invention is not limited thereto. For example, as illustrated in FIG. Ap can also be configured as an N-channel type. In the embodiment shown in FIG. 9, the current amplification transistor Ap is disposed between the high-potential power supply line 102 and the constant current source S. Even in this embodiment, the potential of the output terminal D of each amplification unit U is set to a value corresponding to the potential of the gate of the current amplification transistor Ap of the amplification unit U.
In the second embodiment described above, the current amplifying transistor Ap of each amplifier unit U is configured as a P-channel type. However, the present invention is not limited to this. For example, as illustrated in FIG. The amplification transistor Ap can also be configured as an N-channel type.

<E: Electronic equipment>
The sensing device according to the present invention can be used for various electronic devices. Examples of this type of electronic device include a fingerprint sensor, a vein sensor, a touch panel, and a contact image sensor.

DESCRIPTION OF SYMBOLS 10 ... Sensing device, 20 ... Drive circuit, 30 ... Holding part, 40 ... Output part, 42 ... Shift register, 44 ... AD converter, 46 ... Line memory, 48 ... Difference circuit, 50 Control unit, 70 Control line, 80 Signal line, 100 Detection area, 102 High power line, 104 Low power line, 106 Output line, 108 Offset Power line, CH ...... switching unit, C1, C2 ... capacitance element, D ... output terminal, P ... detection circuit, It ... detection current, T ... unit period, Td ... drive period, Te ... First reading period, Tf... Second reading period, SHG... Sampling signal, AMPG... Control signal, G... Operation signal, Sh.

Claims (9)

A plurality of detection circuits arranged corresponding to the intersections of the plurality of control lines and the plurality of signal lines, each generating a detection signal corresponding to the state of the detection element;
A driving circuit for sequentially outputting a driving signal for driving the detection circuit corresponding to the control line to each of the plurality of control lines;
A plurality of holding units that are provided in one-to-one correspondence with the plurality of signal lines, and that hold the detection signals generated by the detection circuit corresponding to the control lines from which the drive signals are output;
A plurality of amplifying units provided in a one-to-one correspondence with the plurality of holding units, amplifying the detection signals held in the corresponding holding units and outputting a first signal;
For each of the plurality of amplifying units, a control unit that outputs the second signal by controlling the second signal according to the characteristics of the amplifying unit so that the second signal can be read;
A memory for storing the first signals as many as the plurality of amplifying units;
A difference circuit that calculates a difference between the second signal and the first signal read from the memory;
Sensing device. The amplifying unit includes a source follower amplifier including a current amplifying transistor,
The control unit controls the amplification unit such that a threshold voltage of the current amplification transistor is reflected in the second signal;
The sensing device according to claim 1. Each of the amplification units is
A constant current source disposed between a first power supply line to which a first potential is supplied and a second power supply line to which a second potential is supplied;
The current amplification transistor disposed between the constant current source and the second power supply line;
A first switching element disposed between the gate and drain of the current amplification transistor,
Between the output terminal between the constant current source and the current amplification transistor in each amplification section and an output line, a plurality of second switching elements corresponding to the amplification sections in a one-to-one manner are arranged. And
The controller is
In the first read period for reading the first signal, all the first switching elements of the amplifiers are turned off, and the second switching elements are sequentially turned on.
In a second read period after the first read period and reading the second signal, all the first switching elements of the amplifiers are turned on, and the second switching elements are turned on. Turn on sequentially,
The sensing device according to claim 2. Each of the amplification units is
A constant current source disposed between a first power supply line to which a first potential is supplied and a second power supply line to which a second potential is supplied;
The current amplification transistor disposed between the constant current source and the second power supply line;
A third power supply line to which a third potential is supplied, and a first switching element disposed between the gate of the current amplification transistor,
Between the output terminal between the constant current source and the current amplification transistor in each amplification section and an output line, a plurality of second switching elements corresponding to the amplification sections in a one-to-one manner are arranged. And
The controller is
In the first read period for reading the first signal, all the first switching elements of the amplifiers are turned off, and the second switching elements are sequentially turned on.
In a second read period after the first read period and reading the second signal, all the first switching elements of the amplifiers are turned on, and the second switching elements are turned on. Turn on sequentially,
The sensing device according to claim 2. A plurality of detection circuits arranged corresponding to the intersections of the plurality of control lines and the plurality of signal lines, each generating a detection signal corresponding to the state of the detection element;
A driving circuit for sequentially outputting a driving signal for driving the detection circuit corresponding to the control line to each of the plurality of control lines;
A plurality of holding units that are provided in one-to-one correspondence with the plurality of signal lines, and that hold the detection signals generated by the detection circuit corresponding to the control lines from which the drive signals are output;
A plurality of amplifying units provided in a one-to-one correspondence with the plurality of holding units, amplifying the detection signals held in the corresponding holding units and outputting a first signal;
For each of the plurality of amplifying units, a control unit that outputs the second signal by controlling the second signal according to the characteristics of the amplifying unit so that the second signal can be read;
A memory for storing the second signals by the number of the plurality of amplifying units;
A difference circuit that calculates a difference between the first signal and the second signal read from the memory;
Sensing device. The amplifying unit includes a source follower amplifier including a current amplifying transistor,
The control unit controls the amplification unit such that a threshold voltage of the current amplification transistor is reflected in the second signal;
The sensing device according to claim 5. Each of the amplification units is
A constant current source disposed between a first power supply line to which a first potential is supplied and a second power supply line to which a second potential is supplied;
The current amplification transistor disposed between the constant current source and the second power supply line;
A first switching element disposed between the gate and drain of the current amplification transistor,
Between the output terminal between the constant current source and the current amplification transistor in each amplification section and an output line, a plurality of second switching elements corresponding to the amplification sections in a one-to-one manner are arranged. And
The controller is
In the second reading period for reading the second signal, all the first switching elements of the amplifiers are turned on, and the second switching elements are sequentially turned on.
In a first readout period after the second readout period and reading out the first signal, all the first switching elements of the amplifiers are turned off and the second switching elements are sequentially turned on. Turn on,
The sensing device according to claim 5 or 6. Each of the amplification units is
A constant current source disposed between a first power supply line to which a first potential is supplied and a second power supply line to which a second potential is supplied;
The current amplification transistor disposed between the constant current source and the second power supply line;
A third power supply line to which a third potential is supplied, and a first switching element disposed between the gate of the current amplification transistor,
Between the output terminal between the constant current source and the current amplification transistor in each amplification section and an output line, a plurality of second switching elements corresponding to the amplification sections in a one-to-one manner are arranged. And
The controller is
In the second reading period for reading the second signal, all the first switching elements of the amplifiers are turned on, and the second switching elements are sequentially turned on.
In a first readout period after the second readout period and reading out the first signal, all the first switching elements of the amplifiers are turned off and the second switching elements are sequentially turned on. Turn on,
The sensing device according to claim 5 or 6. The electronic device which comprises the sensing apparatus in any one of Claims 1-8.

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