JP2010226303A - Phase comparison device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a digital signal accurately indicating whether a phase is a leading or lagging phase without using a charge pump or an A/D converter even if an output pulse of a high-speed Bang-Bang type phase comparator circuit has distortion and/or defect. <P>SOLUTION: There are provided a Bang-Bang type phase comparator circuit 10 and a phase comparison result discriminator circuit 20 for receiving a leading phase output pulse and a lagging phase output pulse of the phase comparator circuit to discriminate lagging and leading phases. The phase comparison result discriminator circuit 20 includes a first counter circuit 21 that counts a clock signal after being reset by the leading phase output pulse of the phase comparator circuit 10 and outputs a signal indicating the lagging phase when reaching a predetermined count value, a second counter circuit 22 that counts the clock signal after being reset by the lagging phase output pulse of the phase comparator circuit 10 and outputs a signal indicating the leading phase when reaching the predetermined count value, and a discriminator circuit 23 that receives a signal indicating the lagging phase and a signal indicating the leading phase to output a leading/lagging phase discrimination signal. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention inputs a phase advance signal indicating a phase advance and a phase delay signal indicating a phase lag output from a Bang-Bang type phase comparison circuit, identifies the phase advance and the phase lag, and digitalizes the identification result. The present invention relates to a phase comparison device that outputs a signal.

  The phase comparison circuit that detects whether the phase is the leading phase, the slow phase, or the synchronization, rather than comparing the phases of the clock signals or the phase of the data signal and the clock signal, is a general purpose It is called Bang-Bang type. The simplest configuration includes the one described in Non-Patent Document 1.

  FIG. 6 schematically shows an output signal of the Bang-Bang type phase comparison circuit. When the phase is advanced, only the pulse of the advanced phase output UP1, only when the phase is delayed, only the pulse of the delayed phase output DW1, and when the phase is synchronized, the advanced phase output is shown. Both pulses of UP1 and delayed phase output DW1 are output, and when the phase difference is small, both pulses of advanced phase output UP1 and delayed phase output DW1 are output at a frequency corresponding to the phase difference.

  In general, such a Bang-Bang type phase comparison circuit 10 performs the current outflow operation and the current inflow operation of the charge pump 30 using the output from the output, as shown in FIG. By passing through a low-pass filter (loop filter) in the pump 40, an output voltage Vc that becomes a constant voltage only at the time of synchronization is obtained and input to the voltage controlled oscillation circuit 50. The oscillation output is input to the phase comparison circuit 10. It is used for a PLL circuit to be fed back (for example, see Non-Patent Document 2). The features of such a Bang-Bang type phase comparison circuit 10 include that the circuit configuration is simple and that it is possible to reduce the size and power consumption even when high-speed operation is required.

  However, in the conventional technique, there are some problems in taking out the phase comparison result of the Bang-Bang type phase comparison circuit 10 as a digital signal and using it for logic control. When the above-described charge pump is used, a conversion circuit for A / D converting the output is required, and the circuit area is increased. Further, the output of the A / D conversion circuit is also different from the output of the original phase comparison circuit that detects only the leading and lagging phases. Although the output pulse itself of the Bang-Bang type phase comparison circuit 10 may be handled as a digital signal, the pulse output at the time of high-speed operation is often distorted or lost, so that it is easy to cause a malfunction.

  The object of the present invention is to advance or retard the phase without using a charge pump or an A / D converter even if the output pulse of a Bang-Bang type phase comparison circuit operating at high speed is distorted or missing. It is an object of the present invention to provide a phase comparison device capable of obtaining a digital signal that accurately represents which one is.

  In order to achieve the above object, a phase comparison apparatus according to a first aspect of the present invention includes a Bang-Bang type phase comparison circuit, and a phase-shift output pulse and a phase-shift output pulse of the phase comparison circuit as inputs. A phase comparison apparatus comprising a phase comparison result identification circuit for identifying a phase advance, wherein the phase comparison result identification circuit performs a phase discrimination by measuring a non-pulse period of the phase advance output pulse, Advancing phase discrimination is performed by measuring a non-pulse period of the delayed output pulse, and an advancing / delaying phase identification signal is output.

  According to a second aspect of the present invention, in the phase comparison device according to the first aspect, the phase comparison result identification circuit counts a clock signal after being reset by a phase advance output pulse of the phase comparison circuit and performs a predetermined count. A first counter circuit that outputs a signal indicating a delayed phase when the value is reached, and the clock signal is counted after being reset by a delayed output pulse of the phase comparison circuit, and the phase is advanced when a predetermined count value is reached. A second counter circuit that outputs a signal; and an identification circuit that inputs a signal indicating the delayed phase and a signal indicating the advanced phase and outputs an identification signal of the advanced phase / delayed phase.

  According to a third aspect of the present invention, in the phase comparison device according to the second aspect, when the one input of the phase comparison circuit is a data signal, the predetermined count value is the maximum number of consecutive same signs of the data signal. It is set according to.

  According to a fourth aspect of the present invention, in the phase comparison device according to the second or third aspect, the phase-advanced output pulse of the phase comparison circuit is divided by N and the first counter circuit of the phase comparison result identification circuit is divided into N. A first frequency dividing circuit to be input, and a second frequency dividing circuit for frequency-dividing the delayed output pulse of the phase comparison circuit by N and inputting it to the second counter circuit of the phase comparison result identification circuit, and The clock signal is replaced with a clock signal divided by N.

  According to a fifth aspect of the present invention, in the phase comparison device according to any one of the second to fourth aspects, each time the discrimination circuit discriminates the fast phase / late phase, the fast phase or the slow phase is determined. The digital signal which shows these is output.

  According to a sixth aspect of the present invention, in the phase comparison device according to any one of the second to fifth aspects, the identification circuit indicates that the identification has been performed each time the phase advance / late phase is identified. A signal is output.

  According to the present invention, the phase difference is determined by measuring the non-pulse period of the phase advance output pulse output from the phase comparison circuit, and the phase advance is determined by measuring the no pulse period of the phase delay output pulse. In other words, since the pulse-free period is measured instead of the presence of a pulse, a charge pump or an A / D converter is used even when the output pulse of a Bang-Bang type phase comparison circuit operating at high speed is distorted or missing. Therefore, it is possible to obtain a digital signal that accurately represents whether the phase is advanced or delayed.

It is a block diagram which shows the structure of the phase comparison apparatus of 1st Example of this invention. It is a timing chart of operation | movement of the phase comparison apparatus of FIG. It is a block diagram which shows the structure of the phase comparison apparatus of the 2nd Example of this invention. FIG. 4 is a partial timing chart of the operation of the phase comparison device of FIG. 3. It is a timing chart of operation | movement of the phase comparison apparatus of FIG. It is a wave form diagram which shows the output signal of a Bang-Bang type phase comparison circuit. It is a circuit diagram which shows an example of the usage method of the conventional Bang-Bang type | mold phase comparison circuit. It is a wave form diagram which shows the input / output signal at the time of phase advance of a Bang-Bang type | mold phase comparison circuit.

  As shown in FIG. 8, in the Bang-Bang type phase comparison circuit that compares the phase difference between the data signal Data and the clock signal Clock1, the phase comparison with the rising timing of the clock signal Clock1 is performed every time the data signal Data rises and falls. If the phase is advanced, the pulse signal of the advanced phase output UP1 is output every time the data signal Data rises and falls, and the pulse signal of the delayed phase output DW1 is not output. Therefore, the interval between the output pulses is equal to the number of consecutive identical signs of the data signal.

  As shown in FIG. 6, there is no state in which no pulse is output to both the advanced phase output UP1 and the delayed phase output DW1, and therefore, the maximum number of consecutive same signs is X, and the delayed phase output DW1 is at least X bit time or longer. In the non-pulse state where no pulse is observed, as shown in FIG. 8, it can be determined that the data signal Data is in a phase advance state with respect to the clock signal Clock1. Conversely, if the no-pulse period of the phase advance output UP1 is sufficiently long, it can be determined that the phase is in the late phase, and otherwise it is determined that the phase is in the synchronized state. Further, in the case of comparison between clock signals, since the maximum number of consecutive identical codes is 1, it is possible to identify more easily. The present invention is based on such knowledge.

<First embodiment>
FIG. 1 shows a phase comparison apparatus according to a first embodiment of the present invention. FIG. 2 shows a timing chart in this embodiment. The phase comparison apparatus according to the present embodiment includes the Bang-Bang type phase comparison circuit 10 described above and a phase comparison result identification circuit 20 connected to the subsequent stage. The phase comparison circuit 10 receives the data signal Data and the clock signal Clock1 and outputs a phase advance output UP1 and a phase advance output DW1. The phase comparison result identification circuit 20 includes a first counter circuit 21 to which the pulse signal of the phase advance output UP1 from the phase comparison circuit 10 is input and a second signal to which the pulse signal of the slow phase output DW1 from the phase comparison circuit 10 is input. A counter circuit 22 and an identification circuit 23 that receives the outputs from the first and second counter circuits 21 and 22 and identifies the phase advance / late phase are provided.

  The first counter circuit 21 and the second counter circuit 22 receive a clock signal Clock having the same frequency as that of the clock signal Clock input to the phase comparison circuit 10, and count each time the clock signal Clock rises. The circuit 21 is reset when the pulse signal of the advanced phase output UP1 is input from the phase comparison circuit 10, and the second counter circuit 21 is reset when the pulse signal of the delayed phase output DW1 is input from the phase comparison circuit 10.

  Further, the first counter circuit 21 and the second counter circuit 22 determine that the above-described no-pulse state is present when the count number exceeds the count number Y sufficiently larger than the maximum consecutive same sign number X of the data signal Data. The first counter circuit 21 shows a signal DW2 indicating that the phase is delayed and a signal Gate1 indicating that the phase has been identified, and the second counter circuit 22 indicates that the signal is differentiated from the signal UP2 that indicates the phase advanced state. Gate2 is output to the identification circuit 23, respectively. The first counter circuit 21 and the second counter circuit 22 are also reset when the count number reaches a count number Z greater than Y.

  In the time chart of FIG. 2, as the first counter circuit 21 and the second counter circuit 22, a 4-bit counter that simply takes a value from 0 to 15 (the output of each bit of the first counter circuit 21 is D0 to D3, The output of the second counter circuit 22 uses U0 to U3). When the count number is 13 to 15, the pulses of the signals Gate1 and Gate2 are output. When the count number is 14, the advanced phase output UP2 and the delayed phase output DW2 An example is shown in which a pulse is output and reset when the count exceeds 15.

  When the signals Gate1 and Gate2 indicating that identification is performed from the first counter circuit 21 and the second counter circuit 22 are input, the identification circuit 23 performs identification regardless of which counter circuit is input. The signal Gate3 indicating that this is output. Further, the identification circuit 23 becomes “H” when the pulse of the advanced phase output UP2 is inputted from the first counter circuit 21, and “L” when the pulse of the delayed phase output DW2 is inputted from the second counter circuit 32. The identification signal UP / DW which becomes “is output.

  Therefore, each time the signal Gate3 having a pulse width corresponding to the difference between the counter number Y and the counter number Z rises or falls, by referring to the logic of the identification signal UP / DW, the leading and lagging phases are converted into digital signals. And can be used for logic control or the like.

  Here, if there are errors in the pulses of the advanced phase output UP1 and the delayed phase output DW1 from the phase comparison circuit 10, there are two cases. One is a case where a pulse should not be output originally, and the other is a case where a pulse to be output is not output. In the former case, in the phase comparison result identification circuit 20, only the first counter 21 or the second counter 22 is reset, and the identification of the leading phase and the lagging phase is delayed, but the phase comparison result identification circuit 20 is erroneously identified. There is no. On the other hand, in the latter case, for example, depending on the position of the missing pulse, the pulse interval of the advanced phase output UP1 and the delayed phase output DW1 may be larger than the maximum continuous same sign number X. Accordingly, the counter number Y described above needs to be set sufficiently larger than the maximum continuous same sign number X.

<Second embodiment>
FIG. 3 shows a phase comparison apparatus according to a second embodiment in which the above problem is reduced. In FIG. 3, first and second frequency dividing circuits 31 and 32 are inserted between the output side of the phase comparison circuit 10 and the input side of the phase comparison result identification circuit 20. The clock signal Clock 2 input to the phase comparison result identification circuit 20 is divided by the same frequency division ratio N as the frequency division ratio N by the frequency dividing circuits 31 and 32 with respect to the clock signal Clock 1 input to the phase comparison circuit 10. Clock signal. The first counter circuit 21 and the second counter circuit 22 in the phase comparison result identification circuit 20 are reset each time the outputs of the frequency dividing circuits 31 and 32 rise.

  FIG. 4 is a timing chart (partial) of the phase comparison circuit output and the frequency divider circuit output when the frequency divider circuits 31 and 32 use the 64 frequency divider circuit. As shown in FIG. 4, the number of pulses of the phase advance output UP <b> 1 of the phase comparison circuit 10 of the frequency division output (Div64) of the first frequency division circuit 31 changes every 64. When the maximum number of consecutive same signs of the data signal Data is X, when the pulse of the phase advance output UP1 is output from the phase comparison circuit 10, the maximum number of consecutive same signs of the output of the first frequency dividing circuit 31 is 64 × X. It becomes. Even if there is one missing pulse, the maximum number of consecutive identical codes increases only to 65 × X, and it is unlikely that the data is actually biased to that extent. Accordingly, it is not necessary to make the counter number Y as large as possible, and the first counter circuit 21 and the second counter circuit 22 can be made small and simple.

  FIG. 5 shows a timing chart when the output div64_1 of the frequency dividing circuit 31 and the output Div64_2 of the frequency dividing circuit 32 are input to the phase comparison result identification circuit 20 described above. In this case, when the clock signal Clock2 frequency-divided by 64 is input as in the case where the phase advance output UP1 and the phase delay output DW1 are directly input to the phase comparison result identification circuit 20, the operation is the same as the timing chart of FIG.

10: Bang-Bang type phase comparison circuit 20: Phase comparison result identification circuit, 21: First counter circuit, 22: Second counter circuit, 23: Identification circuit 31: First frequency divider circuit, 32: Second frequency divider Circuit 40: charge pump, 50: voltage controlled oscillation circuit

J.D.H.Alexander, “Clock Recovery from Random Binary Signals”, IEEE Electrons Letters, Vol. 11, pp.541-542, 1975 M. Ramezani, C. Andre, T. Salama, "A 10Gb / s CDR with a half-rate bang-bang phase detector", pp. II-181-II-184, vol.2, ISCAS 2003

Claims (6)

A phase comparison device comprising a Bang-Bang type phase comparison circuit and a phase comparison result identification circuit for inputting a phase advance output pulse and a phase advance output pulse of the phase comparison circuit and identifying phase lag / phase advance. And
The phase comparison result identification circuit determines a phase delay by measuring a no-pulse period of the phase-advanced output pulse, performs a phase-advance determination by measuring a pulse-free period of the phase-lag output pulse, / A phase comparison device that outputs an identification signal of a late phase. The phase comparison apparatus according to claim 1,
The phase comparison result identification circuit is configured to count a clock signal after being reset by a phase advance output pulse of the phase comparison circuit and to output a signal indicating a delay phase when reaching a predetermined count value; A second counter circuit that counts the clock signal after being reset by the delayed output pulse of the phase comparison circuit and outputs a signal indicating a phase advance when a predetermined count value is reached; A phase comparison apparatus comprising: an identification circuit that inputs a signal indicating a phase and outputs an identification signal of a leading / delaying phase. The phase comparison device according to claim 2,
The predetermined count value is set in accordance with the maximum number of consecutive same signs of the data signal when one input of the phase comparison circuit is a data signal. In the phase comparison apparatus according to claim 2 or 3,
A first frequency dividing circuit for dividing the phase advance output pulse of the phase comparison circuit by N and inputting it to the first counter circuit of the phase comparison result identification circuit; and a phase delay output pulse of the phase comparison circuit for N. A phase dividing device comprising: a second frequency dividing circuit for frequency division and inputting to the second counter circuit of the phase comparison result identification circuit; and the clock signal is replaced with a clock signal obtained by frequency division by N . In the phase comparison apparatus according to any one of claims 2 to 4,
The phase comparison device is characterized in that the identification circuit outputs a digital signal indicating either the leading phase or the retarding phase each time the leading phase / late phase is identified. The phase comparison device according to any one of claims 2 to 5,
The identification circuit outputs a signal indicating that the identification is performed every time the identification of the leading phase / slow phase is performed.

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