JP2010211885A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently test connection of many terminals by using minimum circuits and wiring for the test. <P>SOLUTION: A semiconductor device receives multiple data through a plurality of input terminals and selects one piece of the data in synchronization with a clock signal to supply it to a common bus. The semiconductor device outputs the data of common bus from a first output terminal among a plurality of output terminals and outputs inverted data obtained by inverting the data of common bus, from a second output terminal adjacent to the first output terminal among the plurality of output terminals. Thus, the semiconductor device is manufactured in such a manner that the data output from the first output terminal and the inverted data output from the second output terminal are checked. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  In general, for system products with semiconductor chips mounted on a substrate, a non-defective chip is mounted on the substrate, and then a connection test between the semiconductor chip and the substrate, or a connection test between multiple semiconductor chips connected on the substrate is performed. There is a need to. For example, a semiconductor chip has a test circuit disposed between an input terminal and an output terminal. The connection test is performed by outputting a test pattern supplied to an input terminal from an output terminal via a test circuit and comparing it with an expected value (see, for example, Patent Documents 1-4).

JP 2004-317221 A JP-T-2001-520780 JP 2004-61272 A JP 2000-236069 A

  Circuits and wiring for connection tests need to be minimized in order to prevent an increase in chip size. Also, in order to shorten the test time, it is necessary to detect many terminal connection failures with a small number of test cycles.

  An object of the present invention is to efficiently perform a connection test of many terminals while minimizing a test circuit and wiring.

  The semiconductor device receives a plurality of data via a plurality of input terminals, selects one data from the plurality of data in synchronization with a clock signal, and supplies the selected data to a common bus. The semiconductor device outputs the data of the common bus from the first output terminal of the plurality of output terminals, and the inverted data obtained by inverting the data of the common bus is adjacent to the first output terminal of the plurality of output terminals. Output from 2 output terminals. The semiconductor device is manufactured by checking data output from the first output terminal and inverted data from the second output terminal.

  By selectively supplying data to the common bus and outputting the data supplied to the common bus and its inverted data from the first and second output terminals, the number of test circuits and wiring is minimized, and fewer tests are performed. Many terminal connection tests can be performed in a cycle.

1 illustrates an example of a semiconductor device according to an embodiment. 2 shows an example of a chip layout of the semiconductor device shown in FIG. 2 shows an example of the test input circuit shown in FIG. An example of the test output circuit shown in FIG. 1 is shown. 4 illustrates an example of the register illustrated in FIG. 3. 4 illustrates an example of the register illustrated in FIG. 3. An example of the register reset circuit shown in FIG. 3 is shown. An example of the test data selection unit shown in FIG. 3 is shown. 5 shows an example of the data selection unit shown in FIG. 2 shows an example of a system in which the semiconductor memory shown in FIG. 1 is mounted. 11 shows an example of a manufacturing method of the system shown in FIG. 12 illustrates an example of a test system that performs the interconnection test illustrated in FIG. 11. 13 shows an example in which an interconnection test is performed by the test system shown in FIG. 13 shows another example in which an interconnection test is performed by the test system shown in FIG. 13 shows another example in which an interconnection test is performed by the test system shown in FIG. The example of the semiconductor device in another embodiment is shown. 17 shows an example of a system in which the semiconductor memory shown in FIG. 16 is mounted. 18 shows an example in which an interconnection test of the system shown in FIG. 17 is performed. The example of the semiconductor device in another embodiment is shown. 20 shows an example of the test input circuit and test output circuit shown in FIG. 21 shows an example of the input data selection unit, data latch, and output data selection unit shown in FIG. 20 shows an example of the data output buffer and data input buffer shown in FIG. 20 shows an example in which an interconnection test of a system in which the semiconductor memory shown in FIG. 19 is mounted is performed. The example of the data selection part of the semiconductor device in another embodiment is shown.

  Hereinafter, embodiments will be described with reference to the drawings. In the figure, a plurality of signal lines indicated by bold lines are shown. A part of the block to which the thick line is connected has a plurality of circuits. The same reference numerals as the signal names are used for signal lines through which signals are transmitted. A signal with “Z” at the end indicates positive logic. The signal with “X” at the end and the signal with “/” at the beginning indicate negative logic. Double square marks in the figure indicate external terminals. The external terminal is, for example, a pad on a semiconductor chip or a lead of a package in which the semiconductor chip is stored. For the signal supplied via the external terminal, the same symbol as the terminal name is used.

  FIG. 1 shows an example of a semiconductor device according to an embodiment. For example, the semiconductor device is a semiconductor memory MEM such as SDRAM. The semiconductor memory MEM operates in synchronization with the clock signal CLK, but may operate asynchronously with the clock signal CLK. The semiconductor memory MEM may be formed as a single memory chip or may be formed as a semiconductor memory device enclosed in a package.

  The semiconductor memory MEM includes a clock buffer 10, a clock enable latch 12, an address buffer 14, an address latch 16, a command buffer 18, a command decoder 20, a test input circuit 22, a test output circuit 24, a data output buffer 26, a data input buffer 28, A burst controller 30, an address controller 32, a mode register 34, a core controller 36, a bus controller 38, and a memory core 40 are provided.

  Clock buffer 10 receives clock signal CLK and clock enable signal CKE, and outputs the received signals as internal clock signal ICLK and internal clock enable signal ICKE. The internal clock signal ICLK is supplied to a circuit that operates in synchronization with the clock.

  The clock enable latch 12 latches the logic level of the internal clock enable signal CKE in synchronization with the rising edge of the internal clock signal ICLK, and outputs a latch clock enable signal LCKE having the latched level. During a period when the latch clock enable signal LCKE is at a high level, the operation mode of the semiconductor memory MEM is set to the normal operation mode, and the semiconductor memory MEM performs a write operation, a read operation, a refresh operation, and the like according to an external command. During the period when the latch clock enable signal LCKE is at a low level, the semiconductor memory MEM is set to the power down mode. For example, in the power down mode, operations other than the clock buffer 10 and the clock enable latch 12 are prohibited in order to reduce power consumption.

  The address buffer 14 receives, for example, a 23-bit address signal A0-22 while the chip select signal CSZ is activated to a high level, and outputs the received signal as the internal address signal IA0-22. In this example, the column address signal and the row address signal are simultaneously supplied to the address terminal A0-8 and the address terminal A9-22. That is, the semiconductor memory MEM is an address non-multiplex type. Note that the column address signal and the row address signal may be supplied to a common address terminal in a time-sharing manner.

  The address latch 16 latches the logic level of the internal address signal IA0-22 in synchronization with the clock signal ICLK, and outputs a latch address signal LA0-22 having the latched level.

  The command buffer 18 receives the command signal CMD and outputs the received signal as an internal command signal ICMD. For example, the command signal CMD includes a chip select signal / CS, a row address strobe signal / RAS, a column address strobe signal / CAS, and a write enable signal / WE. Internal command signal ICMD includes a chip select signal CSZ, a row address strobe signal RASZ, a column address strobe signal CASZ, and a write enable signal WEZ. The command decoder 20 receives the internal command signal ICMD, decodes the received signal, and outputs an operation control signal for operating the memory core 40 or a setting signal for setting the mode register 34.

  The test input circuit 22 activates the test signal TESZ to a high level according to the address signal IA0-22 and the command signal ICMD in order to perform an interconnection test described later. As the test signal TESZ is activated, the operation mode of the semiconductor memory MEM shifts from the normal operation mode to the test mode. The test input circuit 22 activates the test output enable signal TESOEZ to a high level according to the address signal IA0-22 and the command signal ICMD in order to enable the data output buffer 26 during the test mode.

  The test input circuit 22 sequentially selects one of the address signals IA0-10, 12-22, the internal command signal ICMD, the clock signal ICLK, and the clock enable signal ICKE as test data, and sets the logic level of the selected signal. Inverted and output to the test data bus TBUSX as inverted test data. Signal selection is performed in synchronization with a clock signal supplied to the external address terminal A11, as shown in FIGS. The test data bus TBUSX is a test data bus common to the input terminals IA0-10, 12-22, CLK, CKE, CMD and the data terminals DQ0-15. Note that the test data bus TBUSX is set to negative logic in accordance with the data bus CDBX, but may be set to positive logic when the data bus CDBX is positive logic.

  The test output circuit 24 outputs 16-bit read data transferred from the memory core 40 via the data bus CDBX to a corresponding bit of the data output bus DOUTX during the normal operation mode. The logic of the read data on the data bus CDBX and the data output bus DOUTX is opposite to the logic of the read data output from the data terminals DQ0-15. The test output circuit 24 outputs common test data transferred via the test data bus TBUSX to all bits of the data output bus DOUTX during the test mode. The test output circuit 24 sets the output enable signal OEZ to a high level during the high level period of the test output enable signal TESOEZ or the output enable signal OE0Z.

  The data output buffer 26 outputs read data and test data to the data terminals DQ0-15 during the high level period of the output enable signal OEZ. The data output buffer 26 inverts the logic of the read data transferred via the data output bus DOUTX during the read operation in the normal operation mode, and outputs it to the data terminals DQ0-15. The data output buffer 26 simultaneously outputs common test data transferred via the data output bus DOUTX to the data terminals DQ0-15 during the test mode. At this time, the logic level of the test data on the test data bus TBUSX is output to the even-numbered data terminals DQ0, 2,. The level obtained by inverting the logic of the test data on the test data bus TBUSX is output to odd-numbered data terminals DQ1, 3,. As shown in FIG. 2, the data terminals DQ0-15 are arranged on the semiconductor memory chip MEM in the order of bit numbers. For this reason, during the test mode, test data whose logic levels are inverted from each other is output from two adjacent data terminals DQ.

  The data input buffer 28 receives write data supplied to the data terminals DQ0-15 in synchronization with the write enable signal WR0Z. During a write operation in the normal operation mode, the data input buffer 28 receives write data supplied via the data terminals DQ0-15, inverts the logic level, and transmits the inverted write data to the data bus CDBX (data input bus DINX). ) To the memory core 40.

  The burst controller 30 outputs a control signal for controlling the operation of the column controller CCNT according to the burst length set in the mode register 34. The burst controller 30 has an address counter that generates a column address signal following the leading column address signal output from the address controller 32 and outputs the column address signal to the column controller CCNT.

  The address controller 32 outputs the column address signal LA0-8 from the address latch 16 to the column controller CCNT in accordance with the operation timing of the memory core 40. The address controller 32 outputs the row address signal LA9-22 from the address latch 16 to the row controller RCNT in accordance with the operation timing of the memory core 40. Further, the address controller 32 outputs an address signal LA (at least one bit of LA0-22) for setting the mode register 34 to the mode register 34.

  For example, the mode register 34 is set according to an address signal supplied together with a mode register setting command. The mode register 34 sets operation specifications of the semiconductor memory MEM such as a burst length and a read latency.

  The core controller 36 outputs a timing signal for controlling the write operation, the read operation, and the refresh operation of the memory core 40 in response to the command signal CMD. The core controller 36 activates the write enable signal WR0Z when the command signal CMD indicates a write command. The core controller 36 activates the output enable signal OE0Z when the command signal CMD indicates a read command.

  The bus controller 38 outputs read data from the read amplifier RA to the data bus CDBX during a read operation. The bus controller 38 outputs write data transferred to the data bus CDBX to the write amplifier WA during a write operation.

  The memory core 40 includes a column controller CCNT, a row controller RCNT, a read amplifier RA, a write amplifier WA, and a memory cell array ARY. For example, the memory cell array ARY includes a plurality of dynamic memory cells arranged in a matrix and a plurality of word lines and a plurality of bit lines connected to the memory cells MC. The row controller RCNT decodes the row address signal LA9-22 to select one of the word lines. The column controller CCNT decodes the column address signal LA0-8 to select the bit line. Then, the memory cell connected to the selected word line and bit line is accessed.

  FIG. 2 shows an example of the chip layout of the semiconductor device shown in FIG. Although not particularly limited, the semiconductor memory MEM includes an address terminal A0-22, a clock enable terminal CKE, a clock terminal CLK, and command terminals / CS, / RAS, / CAS, / WE arranged along the upper side of the figure. And data terminals DQ0-15 arranged along the lower side. For example, the memory core 40 is divided into four at the center of the chip. The test input circuit 22 is disposed in the peripheral circuit area PCA1 disposed between the terminal (pad) disposed on the upper side and the memory core 40. In the peripheral circuit area PCA1, a clock buffer 10, a clock enable latch 12, an address buffer 14, an address latch 16, a command buffer 18 and a command decoder 20 are also arranged. The test output circuit 24 is arranged in the peripheral circuit area PCA2 arranged between the terminal (pad) arranged on the lower side and the memory core 40. A data output buffer 26 and a data input buffer 28 are also arranged in the peripheral circuit area PCA2.

  The distance between the test input circuit 22 and the test output circuit 24 is, for example, about 10 mm, and the wiring of the test data bus TBUSX is long. In this embodiment, one test data bus TBUSX is wired in common to test data received at input terminals A0-10, 12-22, CKE, CLK, / CS, / RAS, / CAS, / WE. Thereby, the area of the test circuit including the wiring area of the test data bus TBUSX can be minimized, and the chip size can be reduced.

  FIG. 3 shows an example of the test input circuit 22 shown in FIG. The test input circuit 22 includes a test entry circuit TENT, a test input unit TIU having a plurality of AND circuits, a register reset circuit RRST, a clock driving unit CDU, a shift register SFTR, a plurality of test data selection units TDU, a clamp circuit CLMP, and a buffer circuit It has BUF1 and BUF2. Note that the latch circuit SFF in the drawing is arranged in the clock enable latch 12, the address latch 16 or the command decoder 20 shown in FIG.

  Test entry circuit TENT receives command signal ICMD and address signal IA in synchronization with clock signal ICLK. The address signal IA is at least 2 bits excluding the bit IA11. The test entry circuit TENT activates the test signal TESZ to a high level when the command signal ICMD and the address signal IA indicate the first entry command. The test entry circuit TENT activates the test output enable signal TESOEZ to a high level when the command signal ICMD and the address signal IA indicate the second entry command. The test entry circuit TENT deactivates the test signal TESZ and the test output enable signal TESOEZ to a low level when the command signal ICMD and the address signal IA indicate an exit command.

  The AND circuit of the test input unit TIU is formed corresponding to the external input terminals A0-22, CKE, CLK, / CS, / RAS, / CAS, / WE shown in FIG. In the figure, only the AND circuits corresponding to the external input terminals A3, CKE, CLK, A11, and A4 are shown for ease of explanation. In the following description, circuits corresponding to these external input terminals A3, CKE, CLK, A11, and A4 will be described.

  The AND circuit becomes effective when the test signal TESZ is at a high level, receives test data IA3 (or ICKE, ICLK, IA4) supplied from the external input terminal, and receives the received signal as test input data TA3Z (or TCKEZ, TCLKZ, TA4Z). However, the AND circuit corresponding to the terminal A11 outputs the signal IA11 supplied from the external input terminal as a clock signal. The clock driver CDU outputs the clock signal (A11) received through the buffer circuit BUF1 as the shift clock signal SCLKZ.

  The register reset circuit RRST outputs a low level register reset signal RRSTX when the test signal TESZ is low level. The register reset circuit RRST outputs a high level register reset signal RRSTX when the test signal TESZ is at a high level.

  The shift register SFTR has a plurality of registers REG0 and REG connected in series. The register REG0 or REG is formed corresponding to external input terminals (terminals arranged on the upper side in FIG. 2) excluding the address terminal A11. The register REG0 outputs a low level enable signal EN0Z when the test signal TESZ is at a low level. The register REG outputs a low level enable signal EN1Z (or EN2Z-3Z) when the register reset signal RRSTX is at a low level.

  In this state, when the test signal TESZ and the register reset signal RRSTX change to a high level, only the enable signal EN0Z changes to a high level, and the other enable signals EN1Z-3Z are maintained at a low level. Thereafter, each time the shift clock signal SCLKZ changes to a high level, the enable signal EN1Z (or EN2Z-3Z) that outputs a high level sequentially shifts. That is, during the test mode, the shift register SFTR sequentially activates only one of the enable signals EN0Z-3Z.

  The clock driver CDU that outputs the shift clock signal SCLKZ is disposed on the final register REG side that outputs the enable signal EN3Z. Thus, the direction in which the shift clock signal SCLKZ is transmitted to the registers REG and REG0 is opposite to the shift direction of the shift register SFTR. By operating the registers REG and REG0 from the end side in the shift direction (the right side in the figure), it is possible to prevent signals from being transmitted in a chain in the shift register SFTR and to prevent malfunction of the test input circuit 22.

  The test data selection unit TDU outputs test input data TA3Z (or TCKEZ, TCLKZ, TA4Z) from the AND circuit to the test data bus TBUSZ when the corresponding enable signal EN0Z (or EN1Z-3Z) is at a high level. When receiving the low level test signal TESZ, the clamp circuit CLMP clamps the test data bus TBUSZ to the ground voltage VSS (reset voltage). Thus, the test data bus TBUSX can be held at the high level (reset level) via the buffer circuit BUF2 during the normal operation mode (TESZ = low level). By fixing the voltage level of the test data bus TBUSX having a long wiring length and a large load capacity, it is possible to prevent wasteful power consumption during the normal operation mode.

  FIG. 4 shows an example of the test output circuit 24 shown in FIG. The test output circuit 24 includes an output enable generation circuit OEGEN and a data selection unit DSU0 or DSU1 corresponding to the data terminals DQ0-15.

  The output enable generation circuit OEGEN outputs the output enable signal OE0Z from the core controller 36 as the output enable signal OEZ during the normal operation mode (TESZ = low level). The output enable generation circuit OEGEN outputs the test output enable signal TESOEZ from the test entry circuit TENT as the output enable signal OEZ during the test mode (TESZ = high level).

  The data selection unit DSU0 is formed corresponding to the even-numbered data terminals DQ0, 2,. The data selection unit DSU1 is formed corresponding to the odd-numbered data terminals DQ1, 3,. The data selectors DSU0-1 receive read data transferred from the memory core 40 via the data bus CDBX (CDB0X-15X) during the normal operation mode (TESZ = low level). The data output bus DOUTX (DOUT0X-15X) Respectively. During the test mode (TESZ = high level), the data selectors DSU0-1 transfer 1-bit test data transferred from the test input circuit 22 via the test data bus TBUSX to the data output bus DOUTX (DOUT0X-15X). Output.

  However, the data selection unit DSU0 outputs the test data to the data output bus DOUTX (DOUT0X, 2X,..., 14X) without changing the logic level. The data selection unit DSU1 inverts the logic level of the test data and outputs it to the data output bus DOUTX (DOUT1X, 3X,..., 15X). Thereby, the data terminals DQ (for example, DQ1 and DQ0, 2) adjacent to each other can be set to opposite logic levels by using 1-bit common test data during the test mode. As a result, as will be described later, when the system SYS is formed by connecting the semiconductor memory chip MEM and another chip, connection failures of a plurality of external terminals can be detected simultaneously. That is, the wiring interconnection test can be efficiently performed.

  FIG. 5 shows an example of the register REG0 shown in FIG. Register REG0 has latch circuits LT1 and LT2 connected in series that operate in synchronization with shift clock signal SCLKZ, and a NOR gate connected to the output of latch circuit LT2. The voltage VII received by the latch circuit LT1 at the input terminal IN is an internal power supply voltage. The internal power supply voltage VII is generated by a voltage generation circuit formed in the semiconductor memory MEM using the external power supply voltage.

  The register REG0 outputs a low level to the output terminal OUT (EN0Z) during the normal operation mode (TESZ = low level). The register REG0 outputs a high level to the output terminal OUT when the test mode is entered (TESZ = high level). The register REG0 outputs a low level to the output terminal OUT in synchronization with the first rising edge of the shift clock signal SCLKZ after the reset is released (RRSTX = high level). Thereafter, the register REG0 continues to output a low level.

  FIG. 6 shows an example of the register REG shown in FIG. The register REG includes latch circuits LT1 and LT2 connected in series that operate in synchronization with the shift clock signal SCLKZ, and a buffer circuit BUF3 connected to the output of the latch circuit LT2. The latch circuits LT1 and LT2 are the same as the latch circuits LT1-2 of the register REG0. The buffer circuit BUF3 has a pair of inverters connected in series.

  The register REG outputs a low level to the output terminal OUT (EN1Z-3Z) during reset (RRSTX = low level). After the reset is released (RRSTX = high level), the register REG latches the level received at the input terminal IN (EN0Z-2Z) in synchronization with the rising edge of the shift clock signal SCLKZ, and the latched level is output to the output terminal OUT. Output to.

  FIG. 7 shows an example of the register reset circuit RRST shown in FIG. The register reset circuit RRST has a NOR circuit that receives the inversion level of the test signal TESZ and the starter signal STTZ. The starter signal STTZ is generated by a power-on reset circuit formed in the semiconductor memory MEM. The starter signal STTZ is set to a high level until the external power supply voltage rises to a predetermined voltage at power-on, and then set to a low level.

  The register reset circuit RRST activates the reset signal RRSTX to a low level during a period in which the test signal TESZ is at a low level or a period in which the starter signal STTZ is at a high level. The shift register SFTR shown in FIG. 3 is reset by the reset signal RRSTX at the time of power-on (STTZ = high level) or in the normal operation mode (TEZZ = low level), and the low level enable signal EN0Z from the registers REG0 and REG. -3Z is output.

  FIG. 8 shows an example of the test data selection unit TDU shown in FIG. The test data selection unit TDU has a tristate buffer TSBUF having a pMOS transistor PM1 and an nMOS transistor NM1, and a logic circuit for controlling the operation of the tristate buffer TSBUF.

  When receiving the low level enable signal EN0Z (or EN1Z-3Z), the test data selection unit TDU deactivates the tristate buffer TSBUF and sets the drains of the transistors PM1 and NM1 to the floating state. When receiving the high level enable signal EN0Z (or EN1Z-3Z), the test data selection unit TDU activates the tristate buffer TSBUF. At this time, the test data selection unit TDU outputs the logic level of the test input data TA3Z (or TCKEZ, TCLKZ, TA4Z) from the AND circuit shown in FIG. 3 to the test data bus TBUSZ.

  FIG. 9 illustrates an example of the data selection units DSU0-1 illustrated in FIG. The data selection units DSU0-1 include a switch SW1 that connects the data bus CDBX to the data output bus DOUTX, and a switch SW2 that connects the test data bus TBUSX to the data output bus DOUTX. For example, the switch SW1-2 has a CMOS transmission gate. The data selection units DSU0-1 turn on the switch SW1 during the normal operation mode (TESZ = low level), and turn on the switch SW2 during the test mode (TESZ = low level).

  During the normal operation mode, the data selection unit DSU0 outputs the read data on the data bus CDBX corresponding to the even-numbered data terminal DQ to the data output bus DOUTX. During the normal operation mode, the data selection unit DSU1 outputs read data on the data bus CDBX corresponding to the odd-numbered data terminal DQ to the data output bus DOUTX. The data selection units DSU0-1 output test data on the test data bus TBUSX to the data output bus DOUTX during the test mode.

  The data selection unit DSU0 transmits the test data on the test data bus TBUSX to the data output bus DOUTX through the two inverters and the switch SW2 without changing the logic level. The data selection unit DSU1 inverts the logic of the test data on the test data bus TBUSX via the three inverters and the switch SW2, and transmits the test data to the data output bus DOUTX. That is, one of the three inverters is provided to invert the logic level of the test data on the test data bus TBUSX. Therefore, test data obtained by inverting the logic level of the test data is transferred to the odd-numbered data output bus DOUTX.

  FIG. 10 shows an example of a system SYS on which the semiconductor memory MEM shown in FIG. 1 is mounted. The system SYS (user system) is at least a part of a computer device such as a digital television, a video recorder, or a personal computer. In the embodiments described later, the semiconductor memory MEM is mounted on the system SYS similar to that shown in FIG.

  The system SYS has the form of a system in package SiP. Alternatively, the system SYS may be in the form of a multi-chip package MCP, chip-on-chip CoC, package-on-package PoP, or a printed circuit board.

  For example, the system SYS is formed by mounting a semiconductor integrated circuit chip LOGIC and two semiconductor memory chips MEM on a substrate. The semiconductor integrated circuit chip LOGIC includes a memory controller MCNT and a direct access circuit DA for accessing the semiconductor memory MEM, in addition to a logic circuit for realizing the functions of the computer equipment. The external terminal of the semiconductor memory chip MEM is connected only to the external terminal of the semiconductor integrated circuit chip LOGIC, and is not connected to the outside of the SiP. In the following description, the semiconductor integrated circuit chip LOGIC is referred to as a logic chip LOGIC.

  The memory controller MCNT accesses the semiconductor memory MEM in response to an access request for the semiconductor memory MEM issued within the logic chip LOGIC or issued from outside the SiP. Further, the memory controller MCNT has a BIST (Built-In Self Test) circuit and an interconnection test circuit ICT. The BIST circuit performs an operation test of the semiconductor memory MEM mounted on the SiP and outputs the test result to the outside of the SiP. For example, the BIST circuit performs a final operation test (step S310) shown in FIG.

  The interconnection test circuit ICT performs an interconnection test for checking the connection between the logic chip LOGIC and the semiconductor memory chip MEM, and outputs the test result to the outside of the SiP via the external terminal of the logic chip LOGIC. The test result includes only pass / failure information, or includes information on a poorly connected terminal. For example, the interconnection test circuit ICT performs the interconnection test (step S310) shown in FIG. The interconnection test circuit ICT may be formed in the BIST circuit. Alternatively, the interconnection test circuit ICT may be formed outside the logic chip LOGIC or outside the SiP.

  The direct access circuit DA is used, for example, when analyzing a failure of the semiconductor memory MEM mounted on the SiP. With the direct access circuit DA, the semiconductor memory MEM can be directly accessed from the outside of the SiP via the logic chip LOGIC.

  FIG. 11 shows an example of a manufacturing method of the system SYS shown in FIG. In this example, the semiconductor memory chip MEM is manufactured in steps S100 to S120 (memory manufacturing process). In steps S200 to S220, a logic chip LOGIC is manufactured (logic manufacturing process). In steps S300 to S330, a SiP on which the semiconductor memory chip MEM and the logic chip LOGIC are mounted is manufactured (SiP manufacturing process). The memory manufacturing process, the logic manufacturing process, and the SiP manufacturing process may be performed by the same vendor or may be performed by different vendors.

  First, in step S100, a semiconductor memory chip MEM is manufactured on a semiconductor wafer. In step S110, a test of the semiconductor memory chip MEM is performed, and a non-defective chip and a defective chip are selected on the wafer. In step S120, the wafer on which the semiconductor memory chip MEM is formed is shipped to the SiP vendor. Alternatively, the wafer on which the semiconductor memory chip MEM is formed is carried to the SiP manufacturing process. In the memory manufacturing process, a dicing process for taking out only non-defective chips from the wafer may be performed after testing the semiconductor memory chip MEM, and only good chips may be shipped.

  On the other hand, in step S200, the logic chip LOGIC is manufactured on the semiconductor wafer. In step S210, a test of the logic chip LOGIC is performed, and a non-defective chip and a defective chip are selected on the wafer. In step S220, the wafer on which the logic chip LOGIC is formed is shipped to the SiP vendor. Alternatively, the wafer on which the logic chip LOGIC is formed is carried to the SiP manufacturing process. In the logic manufacturing process, a dicing process for extracting only non-defective chips from the wafer may be performed after the logic chip LOGIC test, and only non-defective chips may be shipped.

  In step S300, the non-defective chip MEM and the non-defective chip LOGIC are mounted on the substrate, and the SiP is assembled. When the semiconductor memory chip MEM and the logic chip LOGIC are delivered in a wafer state, step S300 includes a dicing process. The external terminals of the logic chip LOGIC are connected to the terminals on the substrate using signal wires such as bonding wires or bumps. The external terminals of the semiconductor memory chip MEM are connected to the external terminals of the logic chip LOGIC using bonding wires or bumps.

  In step S310, an interconnection test is performed to confirm that the external terminals of the semiconductor memory chip MEM are connected to the external terminals of the logic chip LOGIC. After the interconnect test, a final operation test of the SiP is performed. Specific examples of the interconnection test are shown in FIGS. Next, in step S320, the defective SiP detected by the interconnection test and the final operation test is removed. In step S330, the manufactured SiP is shipped. Alternatively, the SiP is transported to an assembly process for computer equipment on which the SiP is mounted.

  FIG. 12 shows an example of a test system TSYS that performs the interconnection test shown in FIG. The test system TSYS includes a test apparatus TEST such as an LSI tester and an evaluation boat BRD having a socket SCKT on which a plurality of SiPs are mounted.

  The test apparatus TEST supplies a test command for starting the interconnection test circuit ICT to each SiP. The test command may be simultaneously supplied to a plurality of SiPs, or may be sequentially supplied to each SiP. The SiP that has received the test command performs an interconnection test between the external terminal of the logic chip LOGIC and the external terminal of the semiconductor memory chip MEM, and outputs the test result to the test apparatus TEST.

  By performing the interconnection test using the LSI tester, the final operation test can be performed with the SiP mounted on the evaluation board BRD. Note that the test apparatus TEST may be a simple check apparatus that performs only an interconnection test. In this case, the test apparatus TEST outputs a test command for the interconnection test to the evaluation board BRD and receives a test result from the evaluation board BRD.

  FIG. 13 shows an example in which an interconnection test is performed by the test system TSYS shown in FIG. Here, in order to simplify the description, an example in which the interconnection of only the address terminals A11, A3, the clock enable terminal CKE, the clock terminal CLK, and the address terminal A4 is checked is shown. These external terminals A3, CKE, CLK, A4 are laid out in this order on the semiconductor memory MEM and the logic chip LOGIC. Then, the high level “H” and the low level “L” are alternately applied to the external terminals A3, CKE, CLK, and A4. The waveform in FIG. 13 shows one operation of the two semiconductor memories MEM in the SiP shown in FIG.

  The command signal CMD, the address signals A11, A3, A4, the clock enable signal CKE, and the clock signal CLK are output from the interconnection test circuit ICT shown in FIG. 10 to one of the two semiconductor memory chips MEM. The data signals DQ0-15 are output from one of the semiconductor memory chips MEM to the interconnection test circuit ICT in the logic chip LOGIC.

  First, the interconnection test circuit ICT outputs the test command TCMD to the command terminal CMD in synchronization with the clock signal CLK, and outputs the test code TC1 to the address terminal (a plurality of bits excluding A11). The test entry circuit TENT shown in FIG. 3 recognizes the first entry command ENT1 in response to the test code TC1 received together with the test command TCMD, and activates the test signal TESZ (FIG. 13 (a)). As the test signal TESZ is activated, the operation mode of the semiconductor memory MEM shifts from the normal operation mode to the test mode. The address terminal A11 is used to supply a shift clock signal SCLKZ for shifting the shift register SFTR. In order to prevent the shift register SFTR from malfunctioning, the address terminal A11 is not used for inputting the test code TC.

  The register reset circuit RRST deactivates the register reset signal RRSTX to a high level in synchronization with the test signal TESZ (FIG. 13 (b)). Due to the inactivation of the register reset signal RRSTX, the register REG0 of the shift register SFTR outputs a high level enable signal EN0Z (FIG. 13 (c)). The test data selection unit TDU that receives the high level enable signal EN0Z enables the tristate buffer TSBUF and outputs the test input data signal TA3Z to the test data bus TBUSZ (FIG. 13 (d)). However, the test input data A3Z at this time is the test code TC1, not the test data. When the entry command ENT1 is supplied, the output enable signal OEZ is held at a low level. For this reason, the output of the data output buffer 26 is held in a high impedance state (FIG. 13E).

  Next, the interconnection test circuit ICT outputs a test command TCMD to the command terminal CMD in synchronization with the clock signal CLK, and outputs a test code TC2 to the address terminal (a plurality of bits excluding A11). The test entry circuit TENT recognizes the second entry command ENT2 in response to the test code TC2 received together with the test command TCMD, and activates the test output enable signal TESOEZ to a high level (FIG. 13 (f)). The output enable generation circuit OEGEN shown in FIG. 4 activates the output enable signal OEZ to a high level in synchronization with the test output enable signal TESOEZ. The data output buffer 26 shown in FIG. 1 outputs indefinite data DQ0-15 in response to the high level output enable signal OEZ (FIG. 13 (g)).

  By starting the interconnection test in response to the second entry command ENT2, even when the semiconductor memory MEM is erroneously entered into the test mode due to noise or malfunction of the system SYS, the data lines DQ0-15 of the SiP It is possible to prevent data from colliding with each other. That is, by setting the data terminal DQ-15, which is the output of the data output buffer 26, to a floating state until the second entry command ENT2 is supplied, the data from the logic chip LOGIC and the data from the semiconductor memory MEM are transferred. It is possible to prevent a collision. Note that when there is no possibility that the semiconductor memory MEM is erroneously entered into the test mode, the test output enable signal TESOEZ may be activated in synchronization with the activation of the test signal TESZ. In this case, the test signal TESZ is directly supplied to one input of the OR circuit of the output enable generation circuit OEGEN shown in FIG.

  Next, the supply of the clock signal CLK is stopped while the clock enable signal CKE is held at a high level, and the clock signal CLK is fixed at a high level (FIG. 13 (h)). By fixing the clock signal CLK to a high level before changing the clock enable terminal CKE to a low level, it is possible to prevent the semiconductor memory MEM from being erroneously entered into the power-down mode, and it becomes impossible to perform an interconnection test. Can be prevented.

  Next, the high level “H” and the low level “L” are alternately applied to the external terminals A3, CKE, CLK, and A4 (FIG. 13 (i)). At this time, only the enable signal EN0Z is set to a high level. Therefore, the data output buffer 26 receives the address signal A3 (test data) via the test data bus TBUSZ. Note that test data having a logic level opposite to that of the test data bus TBUSZ is transmitted to the test data bus TBUSX.

  The data output buffer 26 outputs the address signal A3 to the even data terminals DQ0, 2,..., And outputs a low level opposite to the level of the address signal A3 to the odd data terminals DQ1, 3,. 15 (FIG. 13 (j)). The interconnection test circuit ICT shown in FIG. 10 compares the test output data DQ0-15 from the semiconductor memory MEM with the expected value. The arrows in the figure show an example of the comparison timing with the expected value by the interconnection test circuit ICT. When the test output data DQ0-15 is different from the expected value, a short circuit or disconnection of at least one of the signal lines A3 and DQ0-15 connecting the logic chip LOGIC and the semiconductor memory chip MEM is detected.

  Next, the test clock signal is sequentially supplied to the address terminal A11 (FIG. 13 (k, l, m)). In synchronization with the test clock signal, the shift clock signal SCLKZ is generated (FIG. 13 (n, o, p)), and the enable signals EN1Z, 2Z, 3Z are sequentially set to the high level for each shift clock signal SCLKZ. It changes (FIG. 13 (q, r, s)). Accordingly, the low level of the clock enable signal CKE, the high level of the clock signal CLK, and the low level of the address signal A4 are sequentially supplied to the test data bus TBUSZ (FIG. 13 (t, u, v)). .., 14 and odd data terminals DQ1, 3,..., 15 are opposite in logic to each other. Test data having a level is output (FIG. 13 (w, x, y)). The interconnection test circuit ICT sequentially compares the test output data DQ0-15 with the expected value, and detects a short circuit or disconnection of at least one of the signal lines CKE and DQ0-15. Alternatively, the interconnection test circuit ICT detects at least one of the signal lines CLK and DQ0-15, or at least one of the signal lines A4 and DQ0-15, or a disconnection. Note that the detection of a short circuit or disconnection of the signal line A11 is detected when the interconnection test is not correctly performed.

  Next, in order to prevent entry into the power down mode, the interconnection test circuit ICT starts oscillation of the clock signal CLK after changing the clock enable signal CKE to a high level (FIG. 13 (z)). The interconnection test circuit ICT outputs a test command TCMD to the command terminal CMD in synchronization with the clock signal CLK, and outputs a test code TC3 to the address terminal (a plurality of bits excluding A11). The test entry circuit TENT recognizes the exit command EXIT in response to the test code TC3 received together with the test command TCMD, and deactivates the test signal TESZ (FIG. 13 (z1)). In response to the deactivation of the test signal TESZ, the register reset signal RRSTX, the test output enable signal TESOEZ, the output enable signal OEZ, and the enable signal EN3Z are deactivated (FIG. 13 (z2, z3, z4)). . The data output buffer 26 sets the data output terminals DQ0-15 to the high impedance state in response to the inactivation of the output enable signal OEZ (FIG. 13 (z5)). Then, the interconnection test ends. After that, an inverse level is given to the external terminals A3, CKE, CLK, and A4, and an interconnection test using a reverse test pattern is performed.

  In the above interconnection test, the circuits operating in the semiconductor memory MEM during the period when the test data A3, CKE, CLK, A4 are given are the clock buffer 10, the address buffer 14, the command buffer 18, the data output buffer 26, and the test circuit. 22 and 24. Further, by supplying the test clock signal for the interconnection test from the address terminal A11 instead of the clock terminal CLK, it is possible to minimize the internal circuit that operates during the interconnection test. In other words, the operation of internal circuits other than the input buffers 10, 14, 18 and the output buffer 26 can be stopped by stopping the clock signal CLK during the interconnection test. As a result, the possibility of failure due to a defect in the internal circuit can be reduced during the interconnection test. That is, a defect in the signal line connecting the logic chip LOGIC and the semiconductor memory chip MEM can be reliably detected by the interconnection test. In particular, it is important to easily distinguish between an SiP interconnection failure and an internal circuit failure of the semiconductor memory MEM for a while after the manufacture of the semiconductor memory MEM is started.

  14 and 15 show another example in which the interconnection test is performed by the test system TSYS shown in FIG. Detailed description of the same operation as in FIG. 13 is omitted. In this example, the high level H and the low level L are sequentially supplied to the input terminals A3, CKE, CLK, and A4 of interest, and an interconnection test is performed. In FIG. 14, up to the fourth cycle in which the high level H is supplied to the address terminal A3 is the same as FIG. In FIG. 15, the last two cycles are the same as in FIG. The arrows in the figure show an example of the comparison timing with the expected value by the interconnection test circuit ICT.

  In FIG. 14, after the interconnection test is performed by the high level H test data supplied to the address terminal A3, the interconnection test circuit ICT changes the clock enable signal CKE to the high level and then changes the clock signal CLK. It changes to a low level (FIG. 14 (a)). Thereafter, the logic levels of the external terminals A3 and A4 are inverted (FIG. 14B). At this time, since the enable signal EN0Z is activated, the low level of the address terminal A3 is output from the even data terminals DQ0, 2,..., And the high level opposite to the level of the address terminal A3 is an odd number. Are output from the data terminals DQ1, 3,..., 15 (FIG. 14C). Then, the interconnection test circuit ICT compares the test output data DQ0-15 from the semiconductor memory MEM with the expected value.

  Next, the test clock signal is supplied to the address terminal A11, and the shift clock signal SCLKZ is generated (FIG. 14 (d, e)). In synchronization with the shift clock signal SCLKZ, the enable signal EN0Z changes to a low level, and the enable signal EN1Z changes to a high level (FIG. 14 (f)). As a result, test data corresponding to the high level of the clock enable signal CKE is output to the data terminals DQ0-15 via the test data bus TBUSZ, and the interconnection test is performed (FIG. 14 (g)).

  Next, in order to prevent entry into the power down mode, the clock signal CLK is changed to a high level during the clock enable signal CKE high level (FIG. 14 (h)). Thereafter, the logic levels of the external terminals A3, CKE, and A4 are inverted (FIG. 14 (i)). As a result, test data corresponding to the low level of the clock enable signal CKE is output to the data terminals DQ0-15 via the test data bus TBUSZ, and the interconnection test is performed (FIG. 14 (j)).

  Thereafter, also in FIG. 15, as in FIG. 14, the enable signals EN1Z, 2Z, and 3Z are switched by the shift clock signal SCLKZ (FIG. 15 (a, b)), and the high level and the low level for each of the input terminals CLK and A4. (1) (c, d, e, f)). In order to prevent entry into the power down mode, the logic level of the clock enable signal CKE is inverted while the clock signal CLK is held at a high level (FIG. 15 (g, h, i)). Then, the exit command EXIT is supplied, and the interconnection test ends.

  As described above, in this embodiment, by performing the interconnection test using one test data bus TBUSX, the area of the test circuit (including the wiring) can be minimized, and the chip size of the semiconductor memory MEM can be reduced. . In addition, the test data supplied to one test data bus TBUSX and the inverted data of the test data are output to the even-numbered data terminal DQ and the odd-numbered data terminal DQ, respectively, thereby reducing the number of test cycles. Many external terminal connection tests can be performed. As a result, the test circuit area can be minimized, a connection test for many terminals can be efficiently performed, and the manufacturing cost of the semiconductor device can be reduced.

  FIG. 16 shows an example of a semiconductor device in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. For example, the semiconductor device is a semiconductor memory MEM such as SDRAM. The semiconductor memory MEM operates in synchronization with the clock signal CLK, but may operate asynchronously with the clock signal CLK. The semiconductor memory MEM may be formed as a single memory chip or may be formed as a semiconductor memory device enclosed in a package.

  The semiconductor memory MEM has a test input circuit 22A and a test output circuit 24A instead of the test input circuit 22 and the test output circuit 24 of FIG. In addition, the semiconductor memory MEM newly has a test input buffer 42A. Other configurations of the semiconductor memory MEM are the same as those in FIG.

  The test input buffer 42A outputs a signal received at the external test terminal PCK as a test signal TESZ. The test input circuit 22A deletes the test entry circuit TENT from the test input circuit 22 shown in FIG. Therefore, the test input circuit 22A supplies the test signal TESZ supplied to the test terminal PCK to the register reset circuit RRST, the shift register SFTR, and the like. The test input circuit 22A does not generate the test output enable signal TESOEZ. Other configurations of the test input circuit 22A are the same as those of the test input circuit 22 shown in FIG.

  The test output circuit 24A is the same as the test output circuit 24 shown in FIG. 4 except that the output enable signal OEZ is generated in synchronization with the output enable signal OE0Z from the core controller 36 or the test signal TESZ. That is, in the test output circuit 24A, the test signal TESZ is directly supplied to one input of the OR circuit of the output enable generation circuit OEGEN shown in FIG. The other configuration of the test output circuit 24A is the same as that of the test output circuit 24 shown in FIG.

  In this embodiment, the semiconductor memory MEM is set to the normal operation mode when the test signal TESZ supplied to the external test terminal PCK is at a low level, and is set to the test mode when the test signal TESZ is at a high level. An internal circuit such as the test entry circuit TENT is not required for entry into the test mode and exit from the test mode. For this reason, in the interconnection test, it is possible to more easily distinguish between an SiP interconnection defect and a semiconductor memory MEM defect.

  When only the semiconductor memory MEM is assembled into a single package, that is, when the semiconductor memory MEM is not mounted on the SiP, the external test terminal PCK is connected to a low level line such as a ground line in the package. Alternatively, the external test terminal PCK is connected to a low level line such as a ground line by a fuse circuit or the like formed in the semiconductor memory MEM.

  FIG. 17 shows an example of a system SYS on which the semiconductor memory MEM shown in FIG. 16 is mounted. Detailed description of the same elements as those in FIG. 10 is omitted. The system SYS (user system) is at least a part of a computer device such as a digital television, a video recorder, or a personal computer. The system SYS has the form of a system in package SiP. Alternatively, the system SYS may be in the form of a multi-chip package MCP, chip-on-chip CoC, package-on-package PoP, or a printed circuit board.

  In this embodiment, the interconnection test circuit ICT in the memory controller MCNT has a function of outputting test clock signals PCK0-1 to the semiconductor memory MEM. That is, the logic chip LOGIC has test clock terminals PCK0-1. The test clock terminals PCK0-1 of the logic chip LOGIC are connected to the external test terminals PCK of the semiconductor memory MEM through signal lines in the SiP. Other configurations of the system SYS are the same as those in FIG. The manufacturing method of the system SYS is the same as that in FIG. The interconnection test between the semiconductor memory MEM and the logic chip LOGIC is performed, for example, by operating the interconnection test circuit ICT using the test system TSYS shown in FIG.

  FIG. 18 illustrates an example in which the interconnection test of the system SYS illustrated in FIG. 17 is performed. Detailed description of the same operation as in FIG. 13 is omitted. Also in this example, in order to simplify the description, an example in which the interconnection of only the address terminals A11, A3, the clock enable terminal CKE, the clock terminal CLK, and the address terminal A4 is checked is shown. These external terminals A3, CKE, CLK, A4 are laid out in this order on the semiconductor memory MEM and the logic chip LOGIC.

  In this embodiment, the semiconductor memory MEM can be entered into the test mode by changing the test signal TESZ supplied to the external test terminal PCK to a high level (FIG. 18A). The semiconductor memory MEM can be exited from the test mode by setting the test signal TESZ supplied to the external test terminal PCK to a low level (FIG. 18B). The five test cycles shown in FIG. 18 are the same operations as the five test cycles shown in FIG. Note that, after the operation of FIG. 18, an external level is given to the external terminals A3, CKE, CLK, and A4, and an interconnection test using a reverse test pattern is performed. The interconnection test may be performed by the method shown in FIGS.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Further, it is possible to reduce the internal circuit of the semiconductor memory MEM that operates for entry into the test mode and exit from the test mode. For this reason, in the interconnection test, it is possible to more easily distinguish between an SiP interconnection defect and a semiconductor memory MEM defect. Also, by providing the external test terminal PCK, the number of test cycles required for the interconnection test can be reduced, and the test time can be shortened. As a result, the manufacturing cost of the system SYS can be reduced.

  FIG. 19 shows an example of a semiconductor device in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. For example, the semiconductor device is a semiconductor memory MEM such as SDRAM. The semiconductor memory MEM operates in synchronization with the clock signal CLK, but may operate asynchronously with the clock signal CLK. The semiconductor memory MEM may be formed as a single memory chip or may be formed as a semiconductor memory device enclosed in a package.

  The semiconductor memory MEM includes a test input circuit 22B, a test output circuit 24B, a data output buffer 26B, and a data input buffer 28B instead of the test input circuit 22, the test output circuit 24, the data output buffer 26, and the data input buffer 28 of FIG. Have. The other configuration of the semiconductor memory MEM is the same as that of FIG. 1 except that the data terminal DQ is 128 bits. The external terminals of the semiconductor memory chip MEM are connected to the external terminals of the logic chip LOGIC using bonding wires or bumps.

  The chip layout of the semiconductor memory MEM is the same as that in FIG. 2 except that the data terminals DQ0-127 are laid out in a plurality of columns. For example, the data terminals DQ0-127 have 64 bits arranged in one column and two columns are formed. The layout pitch of the relatively large number of data terminals DQ0-127 is smaller than the layout pitch of the other terminals. For this reason, when the SiP is assembled using the logic chip LOGIC and the semiconductor memory chip MEM, connection failure of the data signal lines DQ0-127 is likely to occur. Specifically, the data signal lines DQ0-127 such as bonding wires and bumps are easily short-circuited with the adjacent data signal lines. For this reason, in this embodiment, the interconnection test is performed by paying attention to the data terminals DQ0-127 in which connection failure is likely to occur and the reliability is relatively low.

  The system SYS on which the semiconductor memory MEM is mounted is the same as FIG. 10 except that the number of bits of the data terminal DQ is different. The manufacturing method of the system SYS is the same as that in FIG. For example, the interconnection test between the semiconductor memory MEM and the logic chip LOGIC is performed by operating the interconnection test circuit ICT shown in FIG. 10 using the test system TSYS shown in FIG.

  During the test mode, the test input circuit 22B outputs a test signal supplied to the address terminal A11 as a test write signal TESWRZ, and outputs a test signal supplied to the address terminal A12 as a test read signal TESRDZ. The test output circuit 24B latches the test data supplied to the data terminals DQ0 to 127 and transferred via the data input bus DINX in synchronization with the test write signal TESWRZ during the test mode. The latched test data is output to the data output bus DOUTX.

  The data output buffer 26B receives read data read from the memory core 40 and inverted by the bus controller 38 through the data output bus DOUTX (DOUT0X-127X) during the normal operation mode (TESZ = low level). Then, the data output buffer 26B inverts the logic level of the received read data, and outputs the inverted data to the data terminals DQ0-127 in synchronization with the output enable signal OE0Z. The data output buffer 26B inverts the logic level of the test data received via the data output bus DOUTX (DOUT0X-127X) during the test mode (TESZ = high level). Then, the data output buffer 26B outputs the inverted data to the data terminals DQ0-127 in synchronization with the test read signal TESRDZ.

  The data input buffer 28B receives the write data supplied to the data terminal DQ0 in synchronization with the write signal WR0Z during the normal operation mode. Then, the data input buffer 28B inverts the logic level of the received write data and outputs the inverted data to the data input bus DINX (DIN0X-127X). Data input buffer 28B receives the test data supplied to data terminal DQ0 in synchronization with test write signal TESWR0Z during the test mode. Then, the data input buffer 28B inverts the logic level of the received test data and outputs the inverted data to the data input bus DINX (DIN0X-127X).

  FIG. 20 shows an example of the test input circuit 22B and the test output circuit 24B shown in FIG. The test input circuit 22B includes a test entry circuit TENT, a test input unit TIU having an AND circuit that receives an address signal IA11-12, and a buffer circuit BUF4. Note that the latch circuit SFF in the drawing is arranged in the address latch 16 shown in FIG.

  Test entry circuit TENT receives command signal ICMD and address signal IA in synchronization with clock signal ICLK. The address signal IA is at least one bit excluding the bits IA11-12. The test entry circuit TENT activates the test signal TESZ to a high level when the command signal ICMD and the address signal IA indicate an entry command. The test entry circuit TENT deactivates the test signal TESZ to a low level when the command signal ICMD and the address signal IA indicate an exit command.

  The AND circuit that receives the address signal IA11 becomes effective when the test signal TESZ is at a high level, and outputs the address signal IA11 as the test write signal TESWR0Z. The AND circuit that receives the address signal IA12 becomes effective when the test signal TESZ is at a high level, and outputs the address signal IA12 as the test read signal TESRDZ. The test write signal TESWRZ and the test read signal TESRDZ are supplied to the test output circuit 24B via the buffer circuit BUF4.

  The test output circuit 24B has an input data selection unit DISEL, a data latch DLT, and an output data selection unit DOSEL corresponding to each data terminal DQ. Here, a circuit corresponding to the data terminal DQ0 will be described.

  The input data selection unit DISEL selects the write data DIN0X supplied from the data input buffer 28B during the normal operation mode (TEESZ = low level), and outputs the selected data to the write data bus WDB0X. The input data selection unit DISEL selects the test write data DIN0X supplied from the data input buffer 28B during the test mode (TEESZ = high level), and outputs the selected data to the test write data bus TWD0X.

  The data latch DLT latches the test data supplied to the test write data bus TWD0X in synchronization with the test write signal TESWRZ, and outputs the latched test data to the test read data bus TRD0X. The test write signal TESWRZ is a signal obtained by delaying the test write signal TESWR0Z by the buffer circuit BUF5.

  The output data selection unit DOSEL selects read data from the memory core 40 supplied to the read data bus RDB0X during the normal operation mode, and outputs the selected data to the data output bus DOUT0X. The output data selection unit DOSEL selects the test data supplied to the test read data bus TRD0X during the test mode, and outputs the selected data to the data output bus DOUT0X.

  FIG. 21 illustrates an example of the input data selection unit DISEL, the data latch DLT, and the output data selection unit DOSEL illustrated in FIG. In this example, a circuit corresponding to the data terminal DQ0 is shown. The circuit corresponding to the data terminals DQ1-127 is the same as that shown in FIG. 21 except that the numerical values indicating bits are different.

  The input data selection unit DISEL includes an AND circuit that becomes valid when the test signal TEESZ is at a high level and an AND circuit that becomes valid when the test signal TESZ is at a low level. The data latch DLT is a circuit similar to the register REG0 shown in FIG. The latch DLT operates in synchronization with the test write signal TESWRZ while the test signal TESZ is at a high level. Specifically, the latch DLT latches the test write data from the input data selection unit DISEL in synchronization with the rising edge of the test write signal TESWRZ, and outputs the latched data to the test read data bus TRD0X. The output data selection unit DOSEL has a switch SW3 that is turned on while the test signal TESZ is low and a switch SW4 that is turned on when the test signal TESZ is high. For example, the switch SW1-2 has a CMOS transmission gate.

  FIG. 22 shows an example of the data output buffer 26B and the data input buffer 28B shown in FIG. In this example, a circuit corresponding to the data terminal DQ0 is shown. The circuit corresponding to the data terminals DQ1-127 is the same as that shown in FIG. 22 except that the numerical values indicating bits are different.

  Data output buffer 26B has an OR circuit that receives AND logic of test signal TESZ and test read signal TESRDZ and output enable signal OE0Z, and an output transistor OUTTR. The output transistor OUTTR inverts the logic of data supplied from the data output bus DOUT0X and outputs the inverted data to the data terminal DQ0 during a period when the output of the OR circuit is at a high level.

  Data input buffer 28B has an OR circuit that receives write signal WR0Z and test write signal TESWR0Z, and a NAND gate. The NAND gate inverts the logic level of the data supplied to the data terminal DQ0 and outputs the inverted data to the data input bus DINX while the output of the OR circuit is at a high level.

  FIG. 23 shows an example in which an interconnection test of the system SYS on which the semiconductor memory MEM shown in FIG. 19 is mounted is performed. The waveform in FIG. 23 shows one operation of the two semiconductor memories MEM in the SiP shown in FIG.

  The command signal CMD, address signals A11, A12, A4, clock enable signal CKE and clock signal CLK are output from the interconnection test circuit ICT shown in FIG. 10 to one of the two semiconductor memory chips MEM. The data signal DQ0-127 is output from the interconnection test circuit ICT to one of the semiconductor memory chips MEM or from one of the semiconductor memory chips MEM to the interconnection test circuit ICT.

  First, the interconnection test circuit ICT outputs the test command TCMD to the command terminal CMD and the test code TC4 to the address terminal (for example, A4) in synchronization with the clock signal CLK. The test entry circuit TENT shown in FIG. 20 recognizes the entry command ENT in response to the test code TC4 received together with the test command TCMD, and activates the test signal TESZ (FIG. 23 (a)). As the test signal TESZ is activated, the operation mode of the semiconductor memory MEM shifts from the normal operation mode to the test mode. Thereafter, until the exit command EXT is supplied, the clock signal CLK is stopped and held at a low level.

  Next, the interconnection test circuit ICT sets the address signal A11 to a high level for a predetermined period (FIG. 23 (b)). The high level of the address signal A11 indicates the test data input command DIN. The interconnect test circuit ICT supplies high-level “H” test data to the even-numbered data terminals DQ0, 2,..., 126 during the high level of the address signal A11, and the low-level “L” test. Data is supplied to odd-numbered data terminals DQ1, 3,... 127 (FIG. 23 (c)).

  The test input circuit 22B shown in FIG. 20 activates the test write signal TESWR0Z in response to the high level of the address signal A11 (FIG. 23 (d)). The data input buffer 28B shown in FIG. 22 receives the test data supplied to the data terminals DQ0-127 in synchronization with the test write signal TESWR0Z. The test output circuit 24B activates the test write signal TESWRZ in response to the test write signal TESWR0Z (FIG. 23 (e)).

  The data latch DLT shown in FIG. 20 latches the test data supplied to the test write data bus TWDX in synchronization with the test write signal TESWRZ (FIG. 23 (f)). In this example, a high level “H” is supplied to the even-numbered test write data buses TWD0X, 2X,. Low level “L” is supplied to the odd-numbered test write data buses TWD1X, 3X,. The test data latched in the data latch DLT is output to the test read data bus TRDX (FIG. 23 (g)).

  Next, the interconnection test circuit ICT sets the address signal A12 to the high level for a predetermined period (FIG. 23 (h)). The high level of the address signal A12 indicates the test data output command DOUT. The test input circuit 22B shown in FIG. 20 activates the test read signal TESRDZ in response to the high level of the address signal A12 (FIG. 23 (i)). The data output buffer 26B shown in FIG. 22 outputs the test data transferred from the test read data bus TRDX to the data output bus DOUTX to the data terminals DQ0-127 in synchronization with the test read signal TESRDZ (FIG. 23 (j )). Interconnect test circuit ICT compares test data DQ0-127 from semiconductor memory MEM with an expected value. The arrows in the figure show an example of comparison timing. When the test data DQ0-127 is different from the expected value, a short circuit or disconnection of one of the signal lines A11-12 and DQ0-127 connecting the logic chip LOGIC and the semiconductor memory chip MEM is detected.

  Next, in order to prevent entry into the power down mode, the interconnection test circuit ICT starts oscillation of the clock signal CLK after changing the clock enable signal CKE to a high level (FIG. 23 (k)). The interconnection test circuit ICT outputs a test command TCMD to the command terminal CMD and outputs a test code TC5 to the address terminal (for example, A4) in synchronization with the clock signal CLK. The test entry circuit TENT recognizes the exit command EXIT in response to the test code TC5 received together with the test command TCMD, and deactivates the test signal TESZ (FIG. 23 (l)). Then, the interconnection test ends.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Furthermore, the interconnection test of the external terminals D0-127, which has a small layout pitch and is likely to cause a connection failure, can be efficiently performed using a small number of test circuits.

  FIG. 24 illustrates an example of the data selection unit DSU0-1 of the semiconductor device according to another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The semiconductor device is a semiconductor memory MEM such as SDRAM. The configuration excluding the data selection units DSU0-1 is the same as that shown in FIGS. Note that the data selection units DSU0-1 shown in FIG. 24 may be applied to the semiconductor memory MEM shown in FIG.

  The data selectors DSU0-1 are obtained by adding inverting switches ISW0-1 to the data selectors DSU0-1 shown in FIG. For example, the inverting switches ISW0-1 have a fuse circuit. The state shown in FIG. 24 shows a case where the fuse circuit is not programmed. At this time, the semiconductor memory MEM is the same as that shown in FIGS. 1 to 12, and the interconnection test method is the same as that shown in FIGS. Each inversion switch ISW0-1 is switched by a fuse circuit program. At this time, the inverting switches ISW0-1 invert the logic level of the test data on the test data bus TBUSX and transmit the inverted test data to the switch circuit SW2.

  In this embodiment, for example, the semiconductor memory MEM has a control signal line wired between two data lines DQ. The logic level of the control signal transmitted on the control signal line is fixed to either the high level or the low level according to the user specification of the semiconductor memory MEM. The control signal line is connected to the logic chip LOGIC via an external control terminal arranged between the two data terminals DQ. In the interconnection test, test data having a level opposite to the logic level of the external control terminal is output from the adjacent data terminal DQ by the inverting switches ISW0-1. In the interconnection test, a connection check of external terminals including the external control terminal is performed.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Furthermore, even when control signal lines having different logic levels according to user specifications are wired between the data lines DQ, the interconnection test can be reliably performed.

  Note that the external test terminal PCK and the test input buffer 42A shown in FIG. 16 may be formed in the semiconductor memory MEM shown in FIG. At this time, the test mode can be entered by the test signal TESZ supplied to the external test terminal PCK, so that the test entry circuit TENT shown in FIG. 20 is unnecessary.

Regarding the above-described embodiment, the following additional notes are disclosed.
(Appendix 1)
An input unit for receiving data from the outside;
An output unit for outputting data transferred via the data bus;
A supply unit for supplying data input from the input unit to the data bus in response to a test signal;
A drive unit that operates the supply unit based on a clock signal supplied from a first external terminal.
(Appendix 2)
The output device outputs data to a plurality of output terminals so that adjacent data are different from each other.
(Appendix 3)
The output unit includes a plurality of first selection units provided corresponding to a plurality of output terminals,
The semiconductor device according to appendix 1 or appendix 2, wherein the plurality of first selection units include an inversion unit that inverts data transferred via the data bus alternately.
(Appendix 4)
The semiconductor device according to any one of appendices 1 to 3, wherein the first external terminal is an address terminal.
(Appendix 5)
The input unit receives data from a plurality of second external terminals,
The semiconductor device according to any one of Appendix 1 to Appendix 4, wherein the supply unit includes a plurality of second selection units provided corresponding to the plurality of second external terminals.
(Appendix 6)
A shift register including a plurality of registers provided corresponding to the plurality of second selection units;
The semiconductor device according to appendix 5, wherein the corresponding second selection unit is activated based on a control signal from the corresponding register.
(Appendix 7)
7. A semiconductor device according to appendix 6, further comprising a register reset circuit that cancels resetting of the shift register based on activation of the test signal.
The semiconductor device according to any one of appendices 1 to 7, further comprising: a clamp circuit that clamps the data bus in response to the deactivation of the test signal.
(Appendix 9)
The input unit and the supply unit are disposed on the first side of the semiconductor device chip,
The output unit is disposed on a second side facing the first side in the semiconductor device chip,
The semiconductor device according to any one of appendix 1 to appendix 8, wherein the data bus is wired from the first side to the second side.
(Appendix 10)
An input data selection unit that outputs data supplied to the input / output terminals to the internal circuit during the normal operation mode and outputs to the test circuit during the test mode;
A latch circuit included in the test circuit for latching data from the input data selection unit in synchronization with a test write signal supplied to a first input terminal;
Selecting data supplied from the internal circuit during the normal operation mode, selecting data output from the latch circuit during the test mode, and an output data selection unit at the input / output terminal;
A data output unit that outputs data from the output data selection unit to the input / output terminal in synchronization with a test read signal supplied to a second input terminal during the test mode. .
(Appendix 11)
The input data selection unit, the latch circuit, the output data selection unit, and the data output unit are provided for each of the plurality of input / output terminals,
The test write signal is commonly supplied to the latch circuit,
11. The semiconductor device according to appendix 10, wherein the test read signal is commonly supplied to the data output unit.
(Appendix 12)
Receive multiple data via multiple input terminals,
Select one data from the plurality of data in synchronization with the clock signal and supply to the common bus,
Outputting the data of the common bus from the first output terminal of the plurality of output terminals;
Inverted data obtained by inverting the data of the common bus is output from a second output terminal adjacent to the first output terminal among a plurality of output terminals,
A method of manufacturing a semiconductor device, comprising: manufacturing a semiconductor device by checking the data output from the first output terminal and the inverted data from the second output terminal.
(Appendix 13)
13. The method of manufacturing a semiconductor device according to appendix 12, wherein the clock signal is generated based on an external clock signal supplied from an address terminal.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Further, any person having ordinary knowledge in the technical field should be able to easily come up with any improvements and modifications, and there is no intention to limit the scope of the embodiments having the invention to those described above. It is also possible to rely on suitable improvements and equivalents within the scope disclosed in.

  DESCRIPTION OF SYMBOLS 10 Clock buffer; 12 Clock enable latch; 14 Address buffer; 6 Address latch; 18 Command buffer; 20 Command decoder; 22 Test input circuit; 24 Test output circuit; Data input buffer; 30 burst controller; 32 address controller; 34 mode register; 36 core controller; 38 bus controller; 40 memory core; Data selection unit; ICT, interconnection test circuit, MCNT, memory controller, MEM, semiconductor memory, OEGEN, output enable generation circuit, RRST, register reset circuit, SFTR, shift register, TDU, test Over data selection unit; TENT ‥ test entry circuit; TIU ‥ test input section

Claims (5)

An input unit for receiving data from the outside;
An output unit for outputting data transferred via the data bus;
A supply unit for supplying data input from the input unit to the data bus in response to a test signal;
A drive unit that operates the supply unit based on a clock signal supplied from a first external terminal.   The output device outputs data to a plurality of output terminals so that adjacent data are different from each other. The output unit includes a plurality of first selection units provided corresponding to a plurality of output terminals,
The semiconductor device according to claim 1, wherein the plurality of first selection units include inversion units that invert data transferred via the data bus alternately. The semiconductor device according to any one of claims 1 to 3, wherein the first external terminal is an address terminal. Receive multiple data via multiple input terminals,
Select one data from the plurality of data in synchronization with the clock signal and supply to the common bus,
Outputting the data of the common bus from the first output terminal of the plurality of output terminals;
Inverted data obtained by inverting the data of the common bus is output from a second output terminal adjacent to the first output terminal among a plurality of output terminals,
A method of manufacturing a semiconductor device, comprising: manufacturing a semiconductor device by checking the data output from the first output terminal and the inverted data from the second output terminal.

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