JP2010186194A - Image processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processing apparatus for mitigating omission of an image part upon size reduction and thickening of an image part upon enlarging and for enlarging an image with optional magnification which includes a decimal part. <P>SOLUTION: When the size of the image is reduced in writing image to a frame memory, a second image part is corrected by taking weighted average between a first image part to be eliminated by the size reduction and the second image part adjacent to the first image part. Further, when the image read out of the frame memory is enlarged, the first image part to be added by enlargement is generated by taking weighted average of two image parts present before and after the first image part. Further, when the image is enlarged, the image is enlarged according to first magnifying power in the range of 1 to 2 and, by enlarging the image according to second magnifying power which is an integer, an image enlarged by a third magnifying power which is the product of the first and second magnifying power is obtained. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an image processing apparatus having an image reduction / enlargement function.

  In an image processing apparatus, an image reduction process or an enlargement process may be performed to adjust an image to a desired size. FIG. 16 is an explanatory diagram showing the contents of a conventional vertical image reduction process. In the original image shown in FIG. 16A, lines with line numbers 1, 4, and 7 are filled with black, and the other lines are white. The reduced image shown in FIG. 16B is obtained by reducing the original image by 0.8 times.

  In the reduced image shown in FIG. 16B, the lines with the line numbers 1 and 6 of the original image are missing, and as a result, one black horizontal line disappears. As can be seen from this example, in the conventional reduction processing in the vertical direction, some lines are simply lost, and as a result, thin line segments may be lost. For example, when an original image having line segments L1 to L3 having a width of one line as shown in FIG. 16C is reduced, the original line segment L3 is lost as shown in FIG. In some cases, it disappeared. Such a problem due to the lack of the image portion also occurred at the time of horizontal reduction.

  FIG. 17 is an explanatory diagram showing the contents of a conventional vertical image enlargement process. The original image shown in FIG. 17A is the same as that shown in FIG. The enlarged image shown in FIG. 17B is an enlargement of this original image by 1.25 times. In FIG. 17B, lines with line numbers 0 and 4 of the original image are added, and as a result, the width of these lines is doubled. As can be seen from this example, in the conventional vertical enlargement process, several lines are simply added, and thus there is a problem that the width of the lines in the image becomes excessively thick. Such a problem due to the addition of the image portion also occurred at the time of horizontal enlargement.

  Furthermore, in the conventional enlargement process, it is easy to enlarge an image to an integral multiple, but it is difficult to enlarge the image at an arbitrary magnification including a decimal part.

  The present invention has been made to solve the above-described problems in the prior art, and provides a technique that can alleviate the loss of the image part at the time of reduction and the weight of the image part at the time of enlargement. The purpose.

  It is a second object of the present invention to provide a technique capable of enlarging an image at an arbitrary magnification that can include a decimal part.

In order to solve at least a part of the above-described problems, a first image processing apparatus of the present invention includes a frame memory for storing image data,
When writing the image data to the frame memory, the image represented by the image data is reduced in the vertical direction, the first line missing due to the reduction is detected, and the first line and the first line are detected. A vertical reduction unit for correcting an image of the second line by interpolating image data of a plurality of lines including a second line adjacent to the second line;
A plurality of images including the first pixel and a second pixel adjacent to the first pixel, wherein the image represented by the image data is reduced in the horizontal direction, the first pixel missing due to the reduction is detected. A horizontal reduction unit for correcting the image of the second pixel by interpolating the image data of the pixel of
Is provided.

  The vertical reduction unit in the first image processing apparatus can detect that the first line is lost due to the reduction, and can prevent the line information from being completely lost during the reduction. In addition, since interpolation processing is not performed on lines that are not adjacent to missing lines, image quality degradation due to missing lines can be alleviated without significantly degrading the sharpness of the image. Similarly, the horizontal reduction unit can prevent a pixel from being simply lost during reduction, and can alleviate a reduction in image quality due to a pixel loss without significantly degrading the sharpness of the image. Can do.

In the first image processing apparatus,
Each of the vertical reduction part and the horizontal reduction part is
A buffer for storing a given amount of given image data;
A weighted average unit that generates third image data by performing weighted averaging of the first image data read from the buffer and second image data representing an image portion following the first image data. When,
A selection unit that selects and outputs one of a plurality of image data including the given second image data and the third image data output from the weighted average unit;
A selection signal generation unit that generates a selection signal indicating an image portion that is lost due to the reduction according to a reduction ratio of the image, and supplies the selection signal to the selection unit;
It is preferable to provide.

  In each of these reduction units, the selection unit selects one image data from a plurality of image data including the given second image data and the third image data generated by the weighted average unit. Since the data is output, it is possible to generate image data with reduced omission at the time of reduction in real time.

The first image processing apparatus further includes:
It is preferable that a write address control unit that controls an increase in the write address given to the frame memory according to the selection signal is provided.

  In this way, it is possible to write the image data in which the omission at the time of reduction is reduced to an appropriate address in the frame memory.

In the first image processing apparatus,
The reduction ratios in the vertical reduction portion and the horizontal reduction portion are values in the range of 0.5 to 1, respectively. Therefore, one image portion is missing at one place due to reduction in the vertical reduction portion. In addition, it is preferable that the image portion that is lost due to the reduction in the horizontal reduction portion is one pixel at one place.

A second image processing apparatus of the present invention includes a frame memory for storing image data,
The image represented by the image data read from the frame memory is enlarged in the vertical direction, the first line added by the enlargement is detected, and the image data of a plurality of lines adjacent to the first line A vertical enlargement unit that generates image data of the first line by interpolating
The image represented by the image data is enlarged in the horizontal direction, the first pixel added by the enlargement is detected, and image data of a plurality of pixels adjacent to the first pixel and the first pixel is obtained. A horizontal enlargement unit that generates image data of the first pixel by interpolation;
Is provided.

  The vertical enlargement unit in the second image processing device has a plurality of line images including the first line and the second line adjacent to the first line when the first line is added by enlargement. A first line can be generated by interpolating the data. Accordingly, it is possible to prevent the line segment from being thickened simply by adding a line during enlargement. In addition, since the interpolation process is not performed on the lines that existed in the original image, it is possible to mitigate the deterioration of the image quality due to the enlargement of the lines without significantly degrading the sharpness of the image. Similarly, the horizontal enlargement unit can prevent the pixels from being simply fattened during enlargement, and can alleviate the deterioration of image quality due to the addition of pixels without significantly degrading the sharpness of the image. Can do.

In the second image processing apparatus, each of the vertical enlargement unit and the horizontal enlargement unit includes:
A buffer for storing a given amount of given image data;
A weighted average unit that generates third image data by performing weighted averaging of the first image data read from the buffer and second image data representing an image portion following the first image data. When,
A selection unit that selects and outputs one of a plurality of image data including the given second image data and the third image data output from the weighted average unit;
A selection signal generation unit that generates a selection signal indicating an image portion that is added along with the enlargement according to an enlargement ratio of the image, and supplies the selection signal to the selection unit;
Is provided.

  In each enlargement unit, the selection unit selects and outputs one image data from a plurality of image data including the given second image data and the third image data generated by the weighted average unit. Therefore, it is possible to generate image data in which the weighting at the time of enlargement is reduced in real time.

The second image processing apparatus further includes:
It is preferable that a read address control unit that controls an increase in the read address given to the frame memory according to the selection signal is provided.

  In this way, image data to be enlarged can be read from an appropriate address in the frame memory.

In the second image processing apparatus,
The enlargement ratios in the vertical enlargement portion and the horizontal enlargement portion are values in the range of 1 to 2, respectively. Therefore, the image portion added with enlargement in the vertical enlargement portion is one line at one place. In addition, it is preferable that the image portion added along with the enlargement in the horizontal enlargement portion is one pixel at one place.

The third image processing apparatus of the present invention
A first enlargement unit for enlarging the image according to a first enlargement factor in the range of 1 to 2,
A second enlargement unit that enlarges the image according to a second enlargement factor that is an integer,
The image is enlarged at a third enlargement ratio given by a product of the first and second enlargement ratios by enlarging the image in series with the first and second enlargement sections. Note that the order of image enlargement in the first and second enlargement portions is arbitrary, and enlargement by the second enlargement portion may be performed after enlargement by the first enlargement portion. The enlargement by the first enlargement unit may be performed after the enlargement by the enlargement unit.

  Since the enlargement of the image with the first enlargement factor that can include the fractional part and the enlargement of the image with the second enlargement factor that is an integer are performed in series, the image is enlarged at an arbitrary magnification that can contain the fractional part. be able to.

In the third image processing apparatus,
The first and second enlargement units execute image enlargement processing in series in this order,
The second enlargement unit executes the enlargement process so as to output image data at a second output speed obtained by multiplying the first output speed of the first enlargement part by the second enlargement factor. Is preferred.

  In this way, the second enlargement unit can sequentially enlarge the image data output from the first enlargement unit as it is, so that the enlargement process can be executed at high speed as a whole.

1 is a block diagram showing the overall configuration of an image processing apparatus as an embodiment of the present invention. FIG. 3 is a block diagram showing a configuration of an image writing control unit in the video processor 38. FIG. 3 is a block diagram showing a configuration of an image reading control unit in the video processor 38. Explanatory drawing which shows the outline | summary of the reduction / filtering process at the time of image writing. 2 is a block diagram showing an internal configuration of a reduction / filter circuit 66. FIG. FIG. 5 is an explanatory diagram illustrating a method for calculating various parameters related to operations in the vertical reduction / filter circuit 110. 6 is a timing chart showing the operation of the vertical reduction / filter circuit 110. FIG. 4 is an explanatory diagram showing an outline of an internal configuration and processing contents of the enlargement / filter circuit 94 shown in FIG. 3. FIG. 3 is an explanatory diagram showing an outline of vertical enlargement / interpolation processing performed by a first enlargement / interpolation circuit. FIG. 2 is a block diagram showing an internal configuration of a first expansion / interpolation circuit 150. FIG. 6 is an explanatory diagram showing a method for calculating various parameters related to the operation of the first enlargement / interpolation circuit 150 in the vertical enlargement / interpolation circuit 160. 6 is a timing chart showing the operation of the vertical enlargement / interpolation circuit 160 of the first enlargement / interpolation circuit 150; Explanatory drawing which shows the outline | summary of the expansion / interpolation process of the perpendicular direction performed by the 2nd expansion / interpolation circuit 152. FIG. The block diagram which shows the internal structure of the 2nd expansion / interpolation circuit 152. FIG. 9 is a timing chart showing the operation of the vertical enlargement / interpolation circuit 200 of the second enlargement / interpolation circuit 152; Explanatory drawing which shows the content of the image reduction process of the conventional perpendicular | vertical direction. Explanatory drawing which shows the content of the image enlargement process of the conventional perpendicular direction.

A. Overall configuration of the image processing device:
Next, embodiments of the present invention will be described based on examples. FIG. 1 is a block diagram showing the overall configuration of an image processing apparatus as an embodiment of the present invention. This image processing apparatus includes a first video selector 30, a sync separator circuit 32, n AD converters 34, a frame memory 36, a video processor 38, a second video selector 40, a liquid crystal The computer system includes a display drive circuit 42, a liquid crystal display panel 44, a menu generation circuit 46, a font ROM 48, and a CPU 50.

  The entire image processing apparatus is provided in a liquid crystal projector and is an apparatus for processing an image displayed on the liquid crystal display panel 44. The image displayed on the liquid crystal display panel 44 is projected on a projection screen using an optical system (not shown). The first video selector 30 is provided with a plurality of analog image signals V1 and V2, and one of them is selectively output according to the selection signal SEL1 provided from the video processor 38. As the plurality of analog image signals V1 and V2, for example, an image signal representing a computer screen output from a personal computer, a moving image signal output from a video recorder or a television, and the like are supplied. The synchronization separation circuit 32 separates the vertical synchronization signal VSYNC1 and the horizontal synchronization signal HSYNC1 from the analog image signal supplied from the first video selector 30, and outputs a component image signal (an image signal not including a synchronization signal). .

  The component image signal output from the sync separation circuit 32 is converted into a digital image signal by n AD converters 34. That is, n AD converters 34 are used while sequentially switching one by one, and each AD converter 34 uses an analog signal according to a sampling clock having a frequency 1 / n of the frequency of the original image signal. Is converted to a digital signal.

  The video processor 38 is a processor for writing / reading an image to / from the frame memory 36, and has a function of enlarging / reducing the image. Details of the internal configuration and functions of the video processor 38 will be described later. In addition to the digital image signal supplied from the A / D converter 34, the video processor 38 can also be supplied with a digital image signal DV3 output from another digital image output device.

  The digital image signal read from the frame memory 36 and processed by the video processor 38 is input to the second video selector 40. Another digital image signal output from the menu generation circuit 46 is also supplied to the second video selector 40. The menu generation circuit 46 generates a digital image signal representing a menu for the user to adjust the display state (brightness, contrast, synchronization, tracking, color density, hue) on the liquid crystal display panel 44. The font ROM 48 stores font data of characters used for this menu. The second video selector 40 switches and outputs the two input digital image signals in accordance with the selection signal SEL2 given from the video processor 38. As a result, the video selector 40 outputs a digital image signal DV4 representing a composite image in which the menu screen is superimposed in the image read from the frame memory 36.

  The digital image signal DV4 output from the video selector 40 is supplied to the liquid crystal display driving circuit 42. The liquid crystal display driving circuit 42 displays an image on the liquid crystal display 44 in accordance with the image signal DV4. Further, the liquid crystal display driving circuit 42 generates a vertical synchronizing signal VSYNC2 and a horizontal synchronizing signal HSYNC2 for image display and outputs them to other circuits.

  Reading of the image signal from the frame memory 36 and processing of the read image signal are performed in synchronization with the synchronization signals VSYNC2 and HSYNC2 output from the liquid crystal display driving circuit 42. On the other hand, the sampling in the A-D converter 34 and the processing for writing the image signal in the frame memory 36 are performed in synchronization with the synchronization signals VSYNC 1 and HSYNC 1 separated by the synchronization separation circuit 32. The first synchronization signals VSYNC1 and HSYNC1 and the second synchronization signals VSYNC2 and HSYNC2 are asynchronous with each other. Of course, as the first synchronization signals VSYNC1 and HSYNC1 and the second synchronization signals VSYNC2 and HSYNC2, signals synchronized with each other can be used.

  As described above, the process from receiving the image signal from the outside to writing to the frame memory 36 is performed by the first synchronization signals VSYNC1 and HSYNC1, and the process from reading the image signal from the frame memory 36 to displaying the image is performed. Since the first synchronization signal is synchronized with the second synchronization signal VSYNC2 or HSYNC2 that is synchronous or asynchronous, the frequency value of the input image signal is relatively wide regardless of the frequency of the image signal for display. Range values can be tolerated. That is, it is possible to perform a process of writing the input image signal into the frame memory 36 according to the frequency of the synchronization signals VSYNC1 and HSYNC1 of the input image signal while keeping the frequency of the output image signal for display constant. Such an advantage is particularly beneficial when the frequency range of the input image signal can be very wide.

B. Internal configuration of the video processor 38:
FIG. 2 is a block diagram showing the configuration of the image writing control unit in the video processor 38. The image writing control unit includes a color conversion circuit 60, a data selector 62, n line buffers 64, a reduction / filter circuit 66, a writing image adjustment circuit 68, a CPU writing control circuit 70, a writing An image write condition register 74, a write clock generation circuit 76, and a frame memory control circuit 80.

  The color conversion circuit 60 receives n component image signals output from the n A / D converters 34. As this component image signal, various types of signals such as YUV signals and RGB signals can be input. The color conversion circuit 60 has a function of converting YUV signals into RGB signals when they are input. When an RGB signal is input to the color conversion circuit 60, the color conversion circuit 60 outputs the RGB signal as it is.

  The data selector 62 selects and outputs one of the RGB signal output from the color conversion circuit 60 and another RGB signal DV3 (FIG. 1) given through the bus. The selection signal given to the data selector 62 is supplied from the CPU 50.

  The line buffer 64 has n buffer elements equal to the number of AD converters 34. Since a color image is represented by three color image signals of RGB, n line buffers 64 are provided for each color of RGB. The line buffer 64 is a memory for temporarily storing n parallel image signals generated by the AD converter 34.

  The reduction / filter circuit 66 reduces the image written in the frame memory 36 in the vertical and horizontal directions, and performs a filtering process for missing lines and missing pixels at the time of reduction. The internal configuration and operation of the reduction / filter circuit 66 will be further described later.

  The write control signal generation circuit 72 has a function of generating an address and a control signal for writing an image signal to the frame memory 36 and supplying the address and control signal to the frame memory control circuit 80. The frame memory control circuit 80 has a function of mediating writing and reading of image signals to and from the frame memory 36. That is, the frame memory control circuit 80 has a write address and control signal given from the write control signal generation circuit 72, and a read address and control signal given from a read control signal generation circuit of the image read control unit described later. These are supplied to the frame memory 36 in response to the control signal.

  The write image adjustment circuit 68 has a function of adjusting the vertical and horizontal sizes of the image written in the frame memory 36 and the position of the write target area in the memory space of the frame memory 36. The adjustment of the image size is realized by supplying reduction ratios in the vertical and horizontal directions of the image to the reduction / filter circuit 66 and causing the reduction / filter circuit 66 to reduce the image. Further, the position of the write target area in the frame memory 36 is realized by supplying the write start address from the write image adjustment circuit 68 to the write control signal generation circuit 72. The write control signal generation circuit 72 sequentially generates a write address in the write target area, starting from this write start address. The written image adjustment circuit 68 further generates an address to be supplied to the line buffer 64.

  The CPU write control circuit 70 is a circuit for generating an address and a control signal for writing the digital image signal DV3 given through the bus to the frame memory 36. The image writing condition register 74 is a register that stores various conditions for writing an image signal to the frame memory 36. These conditions are set by the CPU 50 via the bus. In FIG. 2, blocks marked with “*” execute their respective processes according to the conditions set in the image writing condition register 74. That is, the writing conditions registered in the image writing condition register 74 include the presence / absence of color conversion in the color conversion circuit 60, the type of color conversion, the selection in the data selector 62, the reduction rate in the reduction / filter circuit 66, and the frame memory. 36 write start positions, etc.

  The write clock generation circuit 76 generates the dot clock signal DCLK1 according to the horizontal synchronization signal HSYNC1 supplied from the synchronization separation circuit 32 (FIG. 1). The write clock generation circuit 76 has a PLL circuit (not shown). The frequency division ratio in this PLL circuit is given from the image writing condition register 74. The processing in the image writing control unit shown in FIG. 2 is executed in synchronization with the dot clock signal DCLK1 and the synchronization signals VSYNC1 and HSYNC1.

  FIG. 3 is a block diagram showing the configuration of the image reading control unit in the video processor 38. The image read control unit includes a frame memory control circuit 80, a read control signal generation circuit 90, an enlargement / filter circuit 94, a brightness / contrast adjustment circuit 96, a gradation correction circuit 98, and a CPU read line buffer 100. CPU read control circuit 102, read image adjustment circuit 104, image read condition register 106, and read clock generation circuit 108.

  The frame memory control circuit 80 shown in FIG. 3 is the same as that shown in FIG. The read control signal generation circuit 90 has a function of generating an address and a control signal for reading an image signal from the frame memory 36 and supplying the address and control signal to the frame memory control circuit 80. The enlargement / filter circuit 94 enlarges the image read from the frame memory 36 in the vertical and horizontal directions, and performs a filtering process on lines added and pixels added at the time of enlargement. The internal configuration and operation of the enlargement / filter circuit 94 will be further described later. Note that when reading out an image, the image can be reduced by thinning out the read address. Such image reduction processing is executed by the read control signal generation circuit 90.

  The brightness / contrast adjustment circuit 96 has a function of adjusting the brightness and contrast of the displayed image. The gradation correction circuit 98 performs gradation correction such as gamma correction using a look-up table.

  The CPU read line buffer 100 is a buffer used when reading an image signal from the frame memory 36 onto the bus. When reading out an image signal on the bus, the CPU read control circuit 102 generates an address and a control signal.

  The read image adjustment circuit 104 has a function of adjusting the vertical and horizontal sizes of the image read from the frame memory 36 and the position of the read target area in the memory space of the frame memory 36. The adjustment of the image size is realized by supplying the enlargement / filter circuit 94 with enlargement ratios in the vertical direction and the horizontal direction of the image and causing the enlargement / filter circuit 94 to enlarge the image. The position of the read target area in the frame memory 36 is realized by supplying a read start address from the read image adjustment circuit 104 to the read control signal generation circuit 90. The read control signal generation circuit 90 sequentially generates read addresses in the read target area, starting from this read start address.

  The image reading condition register 106 is a register that stores various conditions for reading an image signal from the frame memory 36. These conditions are set by the CPU 50 via the bus. In FIG. 3, blocks marked with “**” execute their respective processes according to the conditions set in the image reading condition register 106. That is, the reading conditions registered in the image reading condition register 106 include the reading start position of the frame memory 36, the enlargement ratio in the enlargement / filter circuit 94, the adjustment parameter in the luminance / contrast adjustment circuit 96, and the correction in the gradation correction circuit 98. Parameters, etc.

  The read clock generation circuit 108 generates the dot clock signal DCLK2 in accordance with the horizontal synchronization signal HSYNC2 supplied from the liquid crystal display drive circuit 42 (FIG. 1). The read clock generation circuit 108 has a PLL circuit (not shown) inside. The frequency division ratio in the PLL circuit is given from the image reading condition register 106. 3 is executed in synchronization with the dot clock signal DCLK2 and the synchronization signals VSYNC2 and HSYNC2.

C. Internal configuration and operation of the reduction / filter circuit 66:
FIG. 4 is an explanatory diagram showing an outline of vertical reduction / filtering processing at the time of image writing performed by the reduction / filter circuit 66. 4A shows the original image, FIG. 4B shows the reduced image reduced by the conventional method, and FIG. 4C shows the reduced image reduced by the reduction / filter circuit 66 of the embodiment. Is shown.

  On the left side of each image, the line address LAD of the original image is written. The reduced image shown in FIG. 4B is the same as the reduced image shown in FIG. 16B described in the related art. As described above, in the conventional reduction process, the lines with the original line addresses of 1 and 6 are missing. For this reason, as described in FIGS. 16C and 16D, important lines in the image may disappear.

  On the other hand, as shown in FIG. 4C, in the reduction / filtering process by the reduction / filter circuit 66 of the embodiment, the missing line addresses 1 and 6 are weighted and averaged with the adjacent lines. For example, the line at line address 1 is weighted and averaged with the immediately preceding line (line at line address 0). Therefore, the line at line address 1 does not disappear completely, and a line segment of a slightly lighter color than the original line segment remains in the reduced image. That is, the reduction / filter circuit 66 according to the embodiment can prevent the line segment having the width of one pixel from completely disappearing from the reduced image. The filtering process executed in the reduction / filter circuit 66 means a process of weighted average of image signals for two adjacent lines.

  FIG. 5 is a block diagram showing the internal configuration of the reduction / filter circuit 66. The reduction / filter circuit 66 includes a vertical reduction / filter circuit 110 and a horizontal reduction / filter circuit 112. Note that the line address generation circuit 140 and the pixel address generation circuit 142 shown in FIG. 5 are circuits included in the write control signal generation circuit 72 shown in FIG.

  The vertical reduction / filter circuit 110 includes a vertical decimation flag generation circuit 120, a FIFO buffer 122, an adder 124, a multiplier 126, and a multiplexer 128. In this specification, “decimation” means image reduction processing or thinning-out processing. The horizontal reduction / filter circuit 112 has substantially the same configuration as that of the vertical reduction / filter circuit 110, and includes a horizontal decimation flag generation circuit 130, a buffer 132, an adder 134, a multiplier 136, and a multiplexer 138. have. However, the FIFO buffer 122 of the vertical reduction / filter circuit 110 has a capacity for storing an image signal for one line, whereas the buffer 132 of the horizontal reduction / filter circuit 112 receives an image signal for one pixel. It has the capacity to store.

  The vertical decimation flag generation circuit 120 receives the line address LAD and the vertical reduction ratio Rwv at the time of writing from the write image adjustment circuit 68 (FIG. 2). The line address LAD is the same as the line address given from the write image adjustment circuit 68 to the line buffer 64 in order to read the image signal from the line buffer 64 shown in FIG. The vertical decimation flag generation circuit 120 performs a calculation described later according to the line address LAD and the vertical reduction rate Rwv to generate a vertical decimation flag Fwv. The vertical decimation flag Fwv is supplied to the FIFO buffer 122, the multiplexer 128, and the line address generation circuit 140.

  The image signal Va for one line supplied from the line buffer 64 (FIG. 2) is stored in the FIFO buffer 122. The image signal stored in the FIFO buffer 122 is read from the FIFO buffer 122 when the image signal of the next line is supplied from the line buffer 64. Accordingly, the image signal Vb read from the FIFO buffer 122 is an image signal one line before the image signal Va supplied from the line buffer 64. The adder 124 adds the image signal Va supplied from the line buffer 64 and the image signal Vb read from the FIFO buffer 122, and the added image signal is multiplied by ½ in the multiplier 126. It is done. The image signal Vab output from the multiplier 126 is an average of the image signal Va given from the line buffer 64 and the image signal Vb one line before. This averaged image signal Vab is input to the B input terminal of the multiplexer 128. The image signal Va supplied from the line buffer 64 is input to the A input terminal of the multiplexer 128 as it is. The multiplexer 128 selects and outputs one of the two input image signals Va and Vab according to the level of the vertical decimation flag Fwv.

  FIG. 6 is an explanatory diagram showing a method for calculating various parameters related to the operation of the vertical reduction / filter circuit 110. Here, Rwv represents the vertical reduction ratio, LAD represents the original line address, WLAD represents the write line address given to the frame memory 36, and Fwv represents the vertical decimation flag generated by the vertical decimation flag generation circuit 120. MPX indicates the selected state of the input terminal A / B of the multiplexer 128, and Vout1 indicates which line the image data output from the multiplexer 128 corresponds to.

  The write line address WLAD is given as an integer value obtained by multiplying the vertical reduction ratio Rwv by the original line address LAD. In the example of FIG. 6, since the vertical reduction ratio Rwv is 0.8, the write line address WLAD is 0, 0, 1, 2,. The vertical decimation flag Fwv becomes H level when the value of the write line address WLAD is repeated twice or more, and becomes L level otherwise. That is, each time the line address LAD is updated, the vertical decimation flag generation circuit 120 multiplies the line address LAD and the vertical reduction ratio Rwv, and if the multiplication result WLAD is the same as the previous multiplication result, the vertical decimation flag generation circuit 120 Raise decimation flag Fwv to H level. On the other hand, when the multiplication result WLAD is different from the previous multiplication result, the vertical decimation flag Fwv is lowered to the L level. In the example of FIG. 6, it can be seen that the vertical decimation flag Fwv is at the H level when the original line address LAD is 1 and 6. As shown in FIG. 4B, the lines with the line addresses LAD of 1 and 6 are missing lines in the conventional simple reduction process. Therefore, the vertical decimation flag Fwv is a signal indicating a line that is lost as a result of reduction.

  The selection state of the multiplexer 128 (FIG. 5) is switched according to the level of the vertical decimation flag Fwv. That is, as shown in the column “MPX” in FIG. 6, when the vertical decimation flag Fwv is at L level, the image signal Va input from the A terminal of the multiplexer 128 is selected and output. On the other hand, when the vertical decimation flag Fwv is at the H level, the image signal Vab input to the B terminal of the multiplexer 128 is selected and output. As described above, the image signal Va input to the A terminal is an image signal supplied from the line buffer 64, and the image signal Vab input to the B terminal is the image signal Va and one line before it. The image signal Vb is an averaged signal. Therefore, when the vertical decimation flag Fwv is at the H level, the multiplexer 128 selects and outputs the signal Vab obtained by averaging the image signal Va of the missing line and the image signal Vb of the previous line. For example, in the example of FIG. 6, when the image signal Va of the line whose original line address LAD is 1 is input, two lines L1 and L2 whose line addresses LAD are 0 and 1 are averaged as the output image signal Vout1. The image signal Vab is output. When the vertical decimation flag Fwv is at L level, the image signal Va supplied from the line buffer 64 is output as it is.

  As shown in FIG. 5, the vertical decimation flag Fwv is also supplied to the line address generation circuit 140. The line address generation circuit 140 is a circuit included in the write control signal generation circuit 72 (FIG. 2), and actually generates a write line address WLAD to be given to the frame memory 36. When the vertical decimation flag Fwv is at L level, the write line address is updated in synchronization with the update of the line address LAD in the line buffer 64. On the other hand, when the vertical decimation flag Fwv is at the H level, the update of the write line address WLAD is prohibited, and the write line address WLAD is kept at the same value. Accordingly, when the vertical decimation flag Fwv is at the H level, the write line address WLAD is kept the same as the previous line, so that the frame memory 36 stores the next line on the image signal of the previous line. An image signal is written. For example, in FIG. 6, an image signal obtained by averaging two lines L0 and L1 having a line address LAD of 0 and 1 is overwritten on an image signal of the line L0 having a line address LAD of 0.

  Instead of controlling the update of the write line address WLAD in the line address generation circuit 140 according to the level of the vertical decimation flag Fwv as described above, the write address of the write line address WLAD is uniquely determined in the line address generation circuit 140. It is also possible to control the update. In this case, the line address generation circuit 140 may be provided with a circuit substantially similar to the vertical decimation flag generation circuit 120 so as to generate a signal equivalent to the vertical decimation flag Fwv.

  FIG. 7 is a timing chart showing the operation of the vertical reduction / filter circuit 110. 7A shows a line address in the line buffer 64, FIG. 7B shows a write line address LAD, and FIG. 7C shows a vertical decimation flag Fwv. The write control signal FW # shown in FIG. 7D and the read control signal FR # shown in FIG. 7E are signals that permit writing and reading in the FIFO buffer 122, and are supplied from a FIFO control circuit (not shown). ing. These signals FW # and FR # are negative logic, and writing and reading of image signals are permitted only when they are at the L level. As can be seen from FIGS. 7C to 7E, when the vertical decimation flag Fwv is at the L level, writing of the image signal to the FIFO buffer 122 is permitted and reading from the FIFO buffer 122 is prohibited. Is done. On the other hand, in the line where the vertical decimation flag Fwv is at the H level, writing of the image signal to the FIFO buffer 122 is prohibited and reading from the FIFO buffer 122 is permitted.

  As shown in FIGS. 7A and 7F, the line address LAD of the image signal Va supplied from the line buffer 64 to the vertical reduction / filter circuit 110 sequentially increases one by one. Further, as shown in FIG. 7G, the image signal Vb is read from the FIFO buffer 122 only when the vertical decimation flag Fwv is at the H level. When the original line address LAD is 1, the image signal Va shown in FIG. 7 (f) and the image signal Vb shown in FIG. 7 (g) are added and averaged, and the image signal Vab shown in FIG. Created. The image signal Vab is output from the multiplexer 128 (FIG. 7 (i)).

  As described above, in the vertical reduction / filter circuit 110 shown in FIG. 5, the line missing in the conventional simple reduction process is averaged with the previous line to obtain information on these two lines. Generate one line containing. As a result, since one line is not completely lost, it is possible to prevent an important line segment of one horizontal line from being lost in the reduced image. In addition, since the filtering process (addition averaging process) is not performed on the line that is not adjacent to the line that is missing due to the reduction, the sharpness of the image is not significantly deteriorated by the filtering process.

  Further, since the vertical reduction / filter circuit 110 uses only the FIFO buffer 122 for one line as a buffer memory for temporarily storing image signals, the buffer memory capacity can be relatively small. There is. Furthermore, since the vertical reduction / filter circuit 110 can output the image signals sequentially supplied for each line while filtering in real time, the moving image signal can be processed and output at high speed.

  The horizontal reduction / filter circuit 112 shown in FIG. 5 has substantially the same configuration as the vertical reduction / filter circuit 110, and the FIFO buffer 122 of the vertical reduction / filter circuit 110 has a storage capacity of one line. On the other hand, the buffer 132 of the horizontal reduction / filter circuit 112 is different only in that it has a storage capacity for one pixel. Therefore, the contents of the reduction / filtering process are almost the same. In the description of the vertical reduction / filter circuit 110 described above, the operation can be easily understood by replacing “1 line” with “1 pixel”. That is, the horizontal reduction / filter circuit 112 performs horizontal reduction processing and filtering processing on the image signal Vout1 output from the vertical reduction / filter circuit 110 in parallel. This process is executed according to the level of the horizontal decimation flag Rwh generated by the horizontal decimation flag generation circuit 130. The pixel address generation circuit 142 controls the update of the write pixel address MPAD of the frame memory 36 according to the level of the horizontal decimation flag Rwh. As a result, one pixel including the information of these two pixels is generated by averaging the pixel missing in the conventional simple reduction process with the previous pixel. As a result, since one pixel is not completely lost, it is possible to prevent an important line segment having a width of one pixel from being lost in the reduced image. Further, since the filtering process (addition averaging process) is not performed on the pixels that are not adjacent to the pixels that are missing due to the reduction, the sharpness of the image is not significantly deteriorated by the filtering process.

  The vertical reduction ratio Rwv in the vertical reduction / filter circuit 110 and the horizontal reduction ratio Rwh in the horizontal reduction / filter circuit 112 can be set independently. Further, the effect of preventing the loss of lines and pixels due to the reduction is significant when the reduction ratios are in the range of 0.5 to 1, respectively. This is because only one line or one pixel is lost at one place in this range. Of course, the reduction ratio can be set to any value below this.

  Note that the vertical reduction / filter circuit 110 and horizontal reduction / filter circuit 112 shown in FIG. 5 use circuits (adders 124 and 134 and multipliers 126 and 136) that perform simple addition averaging of two image data, respectively. However, you may make it utilize the circuit which performs a weighted addition average (namely, weighted average).

  Also, the arrangement of the vertical reduction / filter circuit 110 and the horizontal reduction / filter circuit 112 can be reversed from that shown in FIG. That is, first, the image may be reduced in the horizontal direction by the horizontal reduction / filter circuit 112 and then reduced in the vertical direction by the vertical reduction / filter circuit 110.

D. Overview of the configuration and operation of the enlargement / filter circuit 94:
FIG. 8 is an explanatory diagram showing the outline of the internal configuration of the enlargement / filter circuit 94 for enlarging the image read from the frame memory 36 and the processing contents thereof. The expansion / filter circuit 94 includes two expansion / interpolation circuits 150 and 152 connected in series. The first enlargement / interpolation circuit 150 performs processing for enlarging the input image signal V1 by M1 and interpolating and generating an image portion added by enlargement from the image portions before and after the enlargement. The first enlargement factor M1 is a value in the range of 1 to 2. The second enlargement / interpolation circuit 152 enlarges the image signal V2 supplied from the first enlargement / interpolation circuit 150 to M2 times, and the image portion added by the enlargement is the image portion before and after the image portion. The process which interpolates and produces | generates from is performed. The second enlargement factor M2 is an integer. As shown in FIG. 8D, the enlargement ratio of the image output from the second enlargement / interpolation circuit 152 is equal to the product of the two enlargement ratios M1 and M2.

  In this way, the first enlargement / interpolation circuit 150 that enlarges the image at the first enlargement factor M1 in the range of 1 to 2 and the second enlargement of the image at the second enlargement factor M2 that is an integer. If the enlargement / interpolation circuit 152 is provided in series, appropriate processing corresponding to the range of each enlargement ratio can be performed as will be described in detail below. As a result, it is possible to enlarge an image with an arbitrary enlargement ratio (M1 × M2) including a fractional part without significantly reducing the image quality.

E. Configuration and operation of the first expansion / interpolation circuit 150:
FIG. 9 is an explanatory diagram showing an outline of the vertical enlargement / interpolation process performed by the first enlargement / interpolation circuit 150. 9A shows the original image, FIG. 9B shows the enlarged image enlarged by the conventional method, and FIG. 9C shows the first enlargement / interpolation circuit 150 of the embodiment. An enlarged image is shown.

  On the left side of each image, a read line address RLAD for reading the image from the frame memory 36 is written. The reduced image in FIG. 9B is the same as the reduced image in FIG. 17B described in the related art. As described above, in the conventional enlargement process, the lines with the original line addresses of 0 and 4 are simply added. For this reason, there has been a problem that the width of the line included in the image becomes excessively thick.

  On the other hand, as shown in FIG. 9C, in the enlargement / interpolation process by the first enlargement / interpolation circuit 150 of the embodiment, the added line exists before and after the added line. Generated by weighted average of two lines of image. For example, the lines added between line addresses 4 and 5 are generated by a weighted average of these lines. Therefore, the line at line address 4 is not simply thickened, but a slightly lighter line is added. That is, in the first enlargement / interpolation circuit 150 of the embodiment, it is possible to prevent the line segment in the image from simply becoming thick due to enlargement. The interpolation process executed in the first enlargement / interpolation circuit 150 means a process of weighted averaging image signals for two lines existing before and after the added line.

  FIG. 10 is a block diagram showing an internal configuration of the first enlargement / interpolation circuit 150. The first enlargement / interpolation circuit 150 includes a vertical enlargement / interpolation circuit 160 and a horizontal enlargement / interpolation circuit 162. The line address generation circuit 190 and the pixel address generation circuit 192 shown in FIG. 10 are circuits included in the read control signal generation circuit 90 shown in FIG.

  The vertical enlargement / interpolation circuit 160 includes a vertical interpolation flag generation circuit 170, a FIFO buffer 172, an adder 174, a multiplier 176, and a multiplexer 178. The horizontal enlargement / interpolation circuit 162 has substantially the same configuration as the vertical enlargement / interpolation circuit 160, and includes a horizontal interpolation flag generation circuit 180, a buffer 182, an adder 184, and a multiplier. 186 and multiplexer 188. However, the FIFO buffer 172 of the vertical enlargement / interpolation circuit 160 has a capacity for storing an image signal for one line, whereas the buffer 182 of the horizontal enlargement / interpolation circuit 162 has a capacity for one pixel. Have a capacity to store the image signal.

  As can be seen by comparing FIG. 10 with FIG. 5, the vertical enlargement / interpolation circuit 160 shown in FIG. 10 uses the vertical decimation flag generation circuit 120 of the vertical reduction / filter circuit 110 shown in FIG. The configuration is replaced with the generation circuit 170. Further, the horizontal enlargement / interpolation circuit 162 shown in FIG. 10 has a configuration in which the horizontal decimation flag generation circuit 130 of the horizontal reduction / filter circuit 112 shown in FIG. Yes.

  The vertical interpolation flag generation circuit 170 receives the line address LAD and the first enlargement factor Rrv in the vertical direction during reading from the read image adjustment circuit 104 (FIG. 3). The line address LAD is sequentially incremented by one every time one line is processed by the vertical enlargement / interpolation circuit 160. The line address LAD is an address different from that shown in FIG. 5, but the same reference numerals are used for convenience of illustration. The vertical interpolation flag generation circuit 170 performs a calculation described later according to the line address LAD and the vertical enlargement ratio Rrv to generate a vertical interpolation flag Frv. The vertical interpolation flag Frv is supplied to the FIFO buffer 172, the multiplexer 178, and the line address generation circuit 190.

  The image signal Ua for one line read from the frame memory 36 is stored in the FIFO buffer 172. The image signal stored in the FIFO buffer 172 is read from the FIFO buffer 172 when the image signal of the next line is supplied from the frame memory 36. Therefore, the image signal Ub read from the FIFO buffer 172 is an image signal one line before the image signal Ua read from the frame memory 36. The adder 174 adds the image signal Ua read from the frame memory 36 and the image signal Ub read from the FIFO buffer 172. The added image signal is multiplied by 1/2 in the multiplier 176. That is, the image signal Uab output from the multiplier 176 is an average of the image signal Ua read from the frame memory 36 and the image signal Ub one line before. The averaged image signal Uab is input to the B input terminal of the multiplexer 178. The image signal Ua read from the frame memory 36 is input to the A input terminal of the multiplexer 178 as it is. The multiplexer 178 selects and outputs one of the two input image signals Ua and Uab according to the level of the vertical interpolation flag Frv.

  FIG. 11 is an explanatory diagram showing a method for calculating various parameters related to the operation of the vertical enlargement / interpolation circuit 160. Here, Rrv represents a vertical enlargement ratio, LAD is a line address that is sequentially updated, LAD / Rrv is a result of dividing the line address LAD by the vertical enlargement ratio Rrv, and RLAD is given to the frame memory 36. The read line address, LFIFO is the original line of the image signal stored in the FIFO buffer 172, Frv is the vertical interpolation flag generated by the vertical interpolation flag generation circuit 170, and MPX is the input of the multiplexer 178. The selection state of the terminal A / B, and Uout1 indicate the original line address of the image data output from the multiplexer 178, respectively. Note that the line address LAD that is sequentially updated one by one can be considered to indicate the line number of the image output from the vertical enlargement / interpolation circuit 160.

  The value “LAD / Rrv” in the third column from the left in FIG. 11 is a value obtained by converting the line address LAD by the vertical enlargement ratio Rrv into an integer. In the example of FIG. 11, since the vertical enlargement ratio Rrv is 1.25, the division result LAD / Rrv is 0, 0, 1, 2,. As indicated by an arrow in FIG. 11, the vertical interpolation flag Frv becomes H level when the value of the division result LAD / Rrv is repeated twice or more, and becomes L level otherwise. That is, every time the line address LAD is updated, the vertical interpolation flag generation circuit 170 divides the line address LAD and the vertical enlargement ratio Rrv, and the division result (LAD / Rrv) is the same as the previous division result. In this case, the vertical interpolation flag Frv is raised to H level. On the other hand, when the division result is different from the previous result, the vertical interpolation flag Frv is lowered to the L level. In the example of FIG. 11, it can be seen that when the original line address LAD is 1 and 6, the vertical interpolation flag Frv is at the H level. As shown in FIG. 9B described above, the lines whose line addresses LAD are 1 and 6 are lines added by a conventional simple enlargement process. Therefore, the vertical interpolation flag Frv is a signal indicating a line to be added with enlargement.

  The selection state of the multiplexer 178 (FIG. 10) is switched according to the level of the vertical interpolation flag Frv. That is, as shown in the column “MPX” in FIG. 11, when the vertical interpolation flag Frv is at the L level, the image signal Ua input from the A terminal of the multiplexer 178 is selected and output. On the other hand, when the vertical interpolation flag Frv is at the H level, the image signal Uab input to the B terminal of the multiplexer 178 is selected and output. As described above, the image signal Ua input to the A terminal is an image signal being read from the frame memory 36, and the image signal Uab input to the B terminal is the image signal Ua and one line before it. The image signal Ub is an averaged signal. Therefore, when the vertical interpolation flag Frv is at the H level, the multiplexer 178 generates a signal Uab obtained by averaging the image signal Ua of the line read from the frame memory 36 and the image signal Ub of the previous line. Selected and output. For example, in the example of FIG. 11, when the image signal Ua of the line whose original line address LAD is 1 is input, an image obtained by averaging two lines whose line addresses LAD are 0 and 1 as the output image signal Uout1 Signal Uab is output. On the other hand, when the vertical interpolation flag Frv is at the L level, the image signal Ua read from the frame memory 36 is output as it is.

  As shown in FIG. 10, the vertical interpolation flag Frv is also supplied to the line address generation circuit 190. The line address generation circuit 190 is a circuit included in the read control signal generation circuit 90 (FIG. 3), and actually generates a read line address RLAD to be given to the frame memory 36. As shown in FIG. 11, when the vertical interpolation flag Frv is at L level, the read line address RLAD is updated in synchronization with the update of the original line address LAD in the next line. . On the other hand, when the vertical interpolation flag Frv is at the H level, as shown by an arrow in FIG. 11, the update of the read line address RLAD is prohibited in the next line, and the read line address RLAD is kept at the same value. Be drunk. Therefore, when the vertical interpolation flag Frv is at the H level, the read line address RLAD is kept the same as the previous line, so that the image signal of the same line as the previous time is read from the frame memory 36. For example, in FIG. 11, when the line address LAD is 1 and 2, the image signal of the line whose read line address RLAD is 1 is read out twice in succession.

  As shown in the column “LFIFO” in FIG. 11, the image signal of the line immediately before the line currently read from the frame memory 36 is read from the FIFO buffer 172.

  Instead of controlling the update of the read line address RLAD in the line address generation circuit 190 according to the level of the vertical interpolation flag Frv as described above, the update of the read line address RLAD in the line address generation circuit 190 is performed. It is also possible to control it independently.

  FIG. 12 is a timing chart showing the operation of the vertical enlargement / interpolation circuit 160. 12A shows the line address LAD of the output image signal, FIG. 12B shows the read line address RLAD, and FIG. 12C shows the vertical interpolation flag Frv. The write control signal FW # shown in FIG. 12D and the read control signal FR # shown in FIG. 12E are signals that permit writing and reading in the FIFO buffer 172, and are supplied from a FIFO control circuit (not shown). ing. These signals FR # and FW # are negative logic, and writing and reading of image signals are permitted only when the signals are at the L level. As can be seen from FIGS. 12C to 12E, when the vertical interpolation flag Frv is at the L level, the writing of the image signal to the FIFO buffer 172 is permitted and the reading from the FIFO buffer 172 is performed. Is prohibited. On the other hand, in the line where the vertical interpolation flag Frv is at the H level, writing of the image signal to the FIFO buffer 172 is prohibited and reading from the FIFO buffer 172 is permitted.

  As shown in FIG. 12 (f), the address of the line of the image signal Ua read from the frame memory 36 is not updated when the vertical interpolation flag Frv is at the H level, and is incremented by 1 when the vertical interpolation flag Frv is at the L level. To do. On the other hand, as shown in FIG. 12G, the image signal Ub is read from the FIFO buffer 172 only when the vertical interpolation flag Frv is at the H level. When the line address LAD of the image output from the first enlargement / interpolation circuit 150 is 1, the image signal Ua of the line R0 shown in FIG. 12F and the image of the line R1 shown in FIG. The signal Ub is added and averaged to generate the image signal Uab shown in FIG. The image signal Uab is output from the multiplexer 178 (FIG. 12 (i)).

  As described above, the vertical enlargement / interpolation circuit 160 shown in FIG. 10 generates a line that has been simply added in the conventional enlargement process by adding and averaging two lines existing before and after the line. As a result, it is possible to prevent the horizontal line in the image from becoming simply thick. In addition, since the interpolation process (addition averaging process) is not performed for lines that are not adjacent to the line added by enlargement, the sharpness of the image is not significantly deteriorated by the interpolation process.

  Further, since the vertical enlargement / interpolation circuit 160 only uses the FIFO buffer 172 for one line as a buffer memory for temporarily storing image signals, the capacity of the buffer memory can be relatively small. There is an advantage. Furthermore, since the vertical enlargement / interpolation circuit 160 can output the image signals sequentially supplied for each line while filtering in real time, the moving image signal can be processed and output at high speed.

  The horizontal enlargement / interpolation circuit 162 shown in FIG. 10 has substantially the same configuration as the vertical enlargement / interpolation circuit 160. Accordingly, the contents of the enlargement / interpolation process are almost the same. In the description of the vertical enlargement / interpolation circuit 160 described above, the operation can be easily understood by replacing “1 line” with “1 pixel”. . The horizontal enlargement / interpolation circuit 162 can prevent the lines in the image from becoming excessively thick as the image is enlarged. In addition, since the interpolation process (addition averaging process) is not performed for pixels that are not adjacent to the pixel added by enlargement, the sharpness of the image is not significantly deteriorated by the interpolation process.

  The vertical enlargement ratio Rrv in the vertical enlargement / interpolation circuit 160 and the horizontal enlargement ratio Rrh in the horizontal enlargement / interpolation circuit 162 can be set independently. Further, the effect of preventing the line segment from being enlarged due to enlargement is remarkable when these enlargement ratios are in the range of 1 to 2, respectively. This is because in this range, only one line or one pixel is added at one place.

  Note that the order of connection between the vertical enlargement / interpolation circuit 160 and the horizontal enlargement / interpolation circuit 162 can be reversed from that shown in FIG. That is, first, the horizontal enlargement / interpolation circuit 162 may enlarge in the horizontal direction, and the vertical enlargement / interpolation circuit 160 may enlarge in the vertical direction.

F. Configuration and operation of second enlargement / interpolation circuit 152:
FIG. 13 is an explanatory diagram showing an outline of the vertical enlargement / interpolation process performed by the second enlargement / interpolation circuit 152. FIG. 13A shows an image after being magnified by the first magnification / interpolation circuit 150, and FIG. 13B is a magnification magnified by the second magnification / interpolation circuit 152. An image is shown. Here, the image in FIG. 13A is referred to as an “original image”.

On the left side of each image, the line numbers L0, L1... Of the original image are shown. The second enlargement / interpolation circuit 152 executes processing for enlarging the original image Nv times in the vertical direction. The j-th line L _Nv added with the enlargement is obtained by a weighted average of the two lines L _i−1 and L _i of the original image existing before and after the added line according to the following equation (1). Straight line interpolation.

L _Nv = (1−αv) × L _i−1 + αv × L _i (1)
Here, αv = j / Nv, j = 1 to (Nv−1).

  FIG. 14 is a block diagram showing an internal configuration of the second enlargement / interpolation circuit 152. The second enlargement / interpolation circuit 152 includes a vertical enlargement / interpolation circuit 200 and a horizontal enlargement / interpolation circuit 202.

  The vertical enlargement / interpolation circuit 200 includes a weight calculation circuit 210, a multiplexer 212, two FIFO buffers 214 and 216, and an interpolation calculation circuit 218. The horizontal enlargement / interpolation circuit 202 has substantially the same configuration as the vertical enlargement / interpolation circuit 200, and includes a weight calculation circuit 220, a multiplexer 222, two buffers 224 and 226, and an interpolation calculation circuit. 228. However, the two FIFO buffers 214 and 216 of the vertical enlargement / interpolation circuit 200 each have a capacity for storing an image signal for one line, whereas the two of the horizontal enlargement / interpolation circuit 202 have two. Each of the buffers 224 and 226 has a capacity for storing an image signal for one pixel.

  The weight calculation circuit 210 receives the line address NLAD and the second vertical enlargement factor Nv during reading from the read image adjustment circuit 104 (FIG. 3). The line address NLAD is sequentially incremented by one every time one line is processed by the vertical enlargement / interpolation circuit 200. The relationship between the line address NLAD and the line address LAD in the first expansion / interpolation circuit 150 described above will be described later.

  The weight calculation circuit 210 calculates the weight αv according to the following equation (2) according to the line address NLAD and the vertical enlargement ratio Nv.

  αv = {(NLAD)% Nv} / Nv (2)

  The term in {} on the right side of Expression (2) takes a value in the range of 1 to (Nv−1) for the line added by expansion. Therefore, it can be understood that the expression (2) is equivalent to the definition of the weight αv in the above-described expression (1). The weight αv is supplied to the interpolation calculation circuit 218.

  The image signal Uout2 for one line output from the first enlargement / interpolation circuit 150 is switched by the multiplexer 212 and stored alternately in the two FIFO buffers 214 and 216. Image signals Sa and Sb read from the FIFO buffers 214 and 216, respectively, are input to the interpolation calculation circuit 218. The interpolation calculation circuit 218 executes the interpolation calculation according to the above-described equation (1) by performing a weighted average of the two image signals Sa and Sb using the weight αv given from the weight calculation circuit 210. The image signal Sout1 output from the interpolation calculation circuit 218 is a signal representing an image enlarged Nv times in the vertical direction.

  FIG. 15 is a timing chart showing the operation of the vertical enlargement / interpolation circuit 200 of the second enlargement / interpolation circuit 152. 15A shows the line address NLAD in the second enlargement / interpolation circuit 152, and FIG. 15B shows the line address of the output image of the first enlargement / interpolation circuit 150 described above. FIG. 15C shows the LAD output image signal Uout2 from the first enlargement / interpolation circuit 150. FIG. FIGS. 15D, 15E and 15F show the input image signals Sa and Sb to the interpolation calculation circuit 218 shown in FIG. 14 and the output image signal Sout1.

  As shown in FIGS. 15A and 15B, the line address NLAD in the second enlargement / interpolation circuit 152 is twice the line address LAD of the output image of the first enlargement / interpolation circuit 150. (Ie, with a period of 1/2). In general, the line address NLAD in the second enlargement / interpolation circuit 152 is updated at a speed Nv times the line address LAD of the output image of the first enlargement / interpolation circuit 150. Here, Nv is a vertical enlargement ratio in the second enlargement / interpolation circuit 152. Accordingly, the line address LAD in the second enlargement / interpolation circuit 152 is updated with (Nv−1) pause cycles as shown in FIG. In FIG. 12 described above, the pause cycle of the line address LAD is not shown for convenience of illustration, but the line address LAD is actually updated so as to sandwich the pause cycle as shown in FIG. 15B. Is done.

  The image signal Uout2 input from the first enlargement / interpolation circuit 150 is alternately written to the two FIFO buffers 214 and 216 line by line, and is read from the next cycle of the write cycle. The interpolation calculation circuit 218 performs an interpolation calculation on the two input image signals Sa and Sb shown in FIGS. 15D and 15E using the weight αv, thereby obtaining the output image signal Sout1 shown in FIG. Generate.

  As described above, the vertical enlargement / interpolation circuit 200 of the second enlargement / interpolation circuit 152 linearly interpolates two lines of the original image existing before and after the line added with the enlargement. Therefore, a smooth enlarged image can be obtained.

  The horizontal enlargement / interpolation circuit 202 shown in FIG. 14 has substantially the same configuration as the vertical enlargement / interpolation circuit 200. Therefore, the contents of the enlargement / interpolation process are almost the same. In the description of the vertical enlargement / interpolation circuit 200 described above, the operation can be easily understood by replacing “1 line” with “1 pixel”. . Note that the pixel address NPAD in the second expansion / interpolation circuit 152 is preferably updated at a period Nh times the pixel address PAD in the first expansion / interpolation circuit 150. Here, Nh is a horizontal enlargement ratio in the second enlargement / interpolation circuit 152.

  Note that the vertical enlargement ratio Nv in the vertical enlargement / interpolation circuit 200 of the second enlargement / interpolation circuit 152 and the horizontal enlargement ratio Nh in the horizontal enlargement / interpolation circuit 202 can be set independently. It is. Further, the order of connection of the vertical enlargement / interpolation circuit 200 and the horizontal enlargement / interpolation circuit 202 can be reversed from that in FIG. That is, first, the horizontal enlargement / interpolation circuit 202 may enlarge in the horizontal direction, and then the vertical enlargement / interpolation circuit 200 may enlarge in the vertical direction.

  As described above, in the above-described embodiment, the first enlargement / interpolation circuit 150 performs enlargement processing at the first enlargement ratio within the range of 1 to 2, and the second enlargement / interpolation circuit 152 Since the enlargement process is performed at the second enlargement ratio which is an integer, it is possible to enlarge the image at an arbitrary enlargement ratio including a fractional part by combining these two enlargement processes.

  The present invention is not limited to the above-described examples and embodiments, and can be implemented in various modes without departing from the gist thereof. For example, the following modifications are possible.

(1) In the above embodiment, a part of the configuration realized by hardware may be replaced with software, and conversely, a part of the configuration realized by software may be replaced with hardware. Also good.

(2) In the above-described embodiment, the reduction of the image loss phenomenon at the time of reduction and the reduction of the image fatness phenomenon at the time of enlargement are both realized by the weighted average processing of the image data. It is also possible to realize the mitigation of the image loss phenomenon and the fatness phenomenon by using the various interpolation processes. As the interpolation process, for example, various processes such as geometric average, linear interpolation, and non-linear interpolation can be used.

(3) Missing line interpolation processing at the time of reduction is not limited to the case where interpolation is performed with two lines of the missing line and one line adjacent to the missing line. Interpolation may be performed using a plurality of included lines. The same applies to the interpolation processing of missing pixels at the time of reduction. In addition, the interpolation processing of the additional line at the time of enlargement is not limited to the case where the interpolation is performed with two lines existing before and after the added line, and generally, a plurality of lines adjacent to the added line are used. Interpolation may be performed. The same applies to the interpolation processing of additional pixels at the time of enlargement.

30 ... Video selector 32 ... Sync separation circuit 34 ... D converter 36 ... Frame memory 38 ... Video processor 40 ... Video selector 42 ... Liquid crystal display drive circuit 44 ... Liquid crystal display panel 46 ... Menu generation circuit 48 ... Font ROM
50 ... CPU
60 ... Color conversion circuit 62 ... Data selector 64 ... Line buffer 66 ... Reduction / filter circuit 68 ... Write image adjustment circuit 70 ... CPU write control circuit 72 ... Book Control signal generation circuit 74 ... image write condition register 76 ... write clock generation circuit 80 ... frame memory control circuit 90 ... read control signal generation circuit 94 ... enlargement / filter circuit 96. .. Brightness / contrast adjustment circuit 98... Gradation correction circuit 100... CPU read line buffer 102... CPU read control circuit 104... Read image adjustment circuit 106. ..Read clock generation circuit 110 ... Vertical reduction / filter circuit 112 ... Horizontal reduction / filter circuit 120 ... Vertical decimation flag generation circuit 122 ... FIFO buffer 124 ... Adder 126 ... Multiplication 128 ... Multiplexer 1 0 ... Horizontal decimation flag generation circuit 132 ... Buffer 134 ... Adder 136 ... Multiplier 138 ... Multiplexer 140 ... Line address generation circuit 142 ... Pixel address generation circuit 150 .. First enlargement / interpolation circuit 152 ... Second enlargement / interpolation circuit 160 ... Vertical enlargement / interpolation circuit 162 ... Horizontal enlargement / interpolation circuit 170 ... Vertical Interpolation flag generation circuit 172 ... FIFO buffer 174 ... adder 176 ... multiplier 178 ... multiplexer 180 ... horizontal interpolation flag generation circuit 182 ... buffer 184 ... addition 186 ... Multiplier 188 ... Multiplexer 190 ... Line address generation circuit 192 ... Pixel address generation circuit 200 ... Vertical enlargement / interpolation 202. Horizontal expansion / interpolation circuit 210 ... Weight calculation circuit 212 ... Multiplexer 214, 216 ... FIFO buffer 218 ... Interpolation operation circuit 220 ... Weight calculation circuit 222 .. .Multiplexer 224,226 ... buffer 228 ... interpolation arithmetic circuit

Claims (10)

A frame memory for storing image data;
When writing the image data to the frame memory, the image represented by the image data is reduced in the vertical direction, the first line missing due to the reduction is detected, and the first line and the first line are detected. A vertical reduction unit for correcting an image of the second line by interpolating image data of a plurality of lines including a second line adjacent to the second line;
A plurality of images including the first pixel and a second pixel adjacent to the first pixel, wherein the image represented by the image data is reduced in the horizontal direction, the first pixel missing due to the reduction is detected. A horizontal reduction unit for correcting the image of the second pixel by interpolating the image data of the pixel of
An image processing apparatus comprising: The image processing apparatus according to claim 1,
Each of the vertical reduction part and the horizontal reduction part is
A buffer for storing a given amount of given image data;
A weighted average unit that generates third image data by performing weighted averaging of the first image data read from the buffer and second image data representing an image portion following the first image data. When,
A selection unit that selects and outputs one of a plurality of image data including the given second image data and the third image data output from the weighted average unit;
A selection signal generation unit that generates a selection signal indicating an image portion that is lost due to the reduction according to a reduction ratio of the image, and supplies the selection signal to the selection unit;
An image processing apparatus comprising: The image processing apparatus according to claim 2, further comprising:
An image processing apparatus comprising: a write address control unit that controls an increase in a write address given to the frame memory in response to the selection signal. The image processing apparatus according to any one of claims 1 to 3,
The reduction ratios in the vertical reduction portion and the horizontal reduction portion are values in the range of 0.5 to 1, respectively. Therefore, one image portion is missing at one place due to reduction in the vertical reduction portion. An image processing apparatus, wherein an image portion missing due to the reduction in the horizontal reduction unit is one pixel at one place. A frame memory for storing image data;
The image represented by the image data read from the frame memory is enlarged in the vertical direction, the first line added by the enlargement is detected, and the image data of a plurality of lines adjacent to the first line A vertical enlargement unit that generates image data of the first line by interpolating
The image represented by the image data is enlarged in the horizontal direction, the first pixel added by the enlargement is detected, and the image data of a plurality of pixels adjacent to the first pixel is interpolated. A horizontal enlargement unit that generates image data of one pixel;
An image processing apparatus comprising: The image processing apparatus according to claim 5, wherein
Each of the vertical enlargement portion and the horizontal enlargement portion is
A buffer for storing a given amount of given image data;
A weighted average unit that generates third image data by performing weighted averaging of the first image data read from the buffer and second image data representing an image portion following the first image data. When,
A selection unit that selects and outputs one of a plurality of image data including the given second image data and the third image data output from the weighted average unit;
A selection signal generation unit that generates a selection signal indicating an image portion that is added along with the enlargement according to an enlargement ratio of the image, and supplies the selection signal to the selection unit;
An image processing apparatus comprising: The image processing apparatus according to claim 6, further comprising:
An image processing apparatus comprising: a read address control unit that controls an increase in a read address given to the frame memory in response to the selection signal. An image processing apparatus according to any one of claims 5 to 7,
The enlargement ratios in the vertical enlargement portion and the horizontal enlargement portion are values in the range of 1 to 2, respectively. Therefore, the image portion added with enlargement in the vertical enlargement portion is one line at one place. An image processing apparatus, wherein an image portion added along with enlargement in the horizontal enlargement portion is one pixel at one place. An image processing apparatus for enlarging an image,
A first enlargement unit for enlarging the image according to a first enlargement factor in the range of 1 to 2,
A second enlargement unit that enlarges the image according to a second enlargement factor that is an integer,
The image is enlarged at a third enlargement ratio given by a product of the first and second enlargement ratios by enlarging the image in series with the first and second enlargement sections. Processing equipment. The image processing apparatus according to claim 9,
The first and second enlargement units execute image enlargement processing in series in this order,
The second enlargement unit executes the enlargement process so as to output image data at a second output speed obtained by multiplying the first output speed of the first enlargement part by the second enlargement factor. Image processing device.

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