JP2010181829A - Display driving device and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display driving device and a display device, reducing degradation in display quality, by setting a grayscale level using an FRC (Frame Rate Control) system according to grayscale of a display image. <P>SOLUTION: When a display data "Data" is input in a signal driver 30, a grayscale histogram indicating an appearance frequency of the grayscale level indicated by the display data "Data" is created in a histogram calculation section 303. A grayscale voltage setting section 304 sets a grayscale voltage setting switch in a grayscale voltage creation section 305 so as to make combination in which a grayscale voltage corresponding to a grayscale level whose appearance frequency is high according to the grayscale histogram, is created as much as possible. According to this setting and the display data, the display data "Data" (FRC) for FRC driving is created, and display is performed according to the display data "Data" (FRC). <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a display driving device and a display device that perform video display using a frame rate control (FRC) method.

  Conventionally, a frame rate control (FRC) method is known as one of methods for performing gradation display in a display device such as a liquid crystal display device (see, for example, Patent Document 1). This FRC method is a method for performing display corresponding to a larger number of gradation levels than the display of gradation voltages that can be generated in a display driving device for driving a display device. In the FRC method, one display cycle is composed of a plurality of frames, and a grayscale voltage corresponding to a different grayscale level for each frame is applied to the display pixels to obtain a desired grayscale level as an average within one display cycle. Is visible.

JP 2006-119417 A

  In general, it is known that when a gradation level that cannot be generated by a display driving apparatus is displayed using the FRC method, flickering occurs and display quality is deteriorated. Here, video display may be performed at the same gradation level for a long time, and display using the FRC method up to such a case is from the viewpoint of deterioration of display quality. However, it is not preferable.

  The present invention has been made in view of the above circumstances, and it is possible to reduce deterioration in display quality by setting a gradation level using the FRC method in accordance with the gradation of a video to be displayed. It is an object to provide a display driving device and a display device.

  In order to achieve the above object, the display driving apparatus according to the first aspect of the present invention generates a plurality of gradation voltages corresponding to a plurality of gradation levels smaller than the gradation levels that display data can take. A gradation voltage generation means; a frequency calculation means for inputting the display data and calculating an output frequency of a gradation level indicated by the display data; and the gradation voltage generation according to the appearance frequency calculated by the frequency calculation means A setting unit configured to set a gradation voltage generated by the unit; and a plurality of gradation voltages generated by the gradation voltage generation unit according to the display data are selected, and the selected gradation voltage is supplied to the display pixel. And a gradation voltage selecting means for performing display corresponding to the average gradation level of the gradation levels indicated by the supplied plurality of gradation voltages.

  In order to achieve the above object, the display device according to the second aspect of the present invention performs display by driving a display panel having a plurality of display pixels arranged in two dimensions based on display data. In the apparatus, gradation voltage generating means for generating a plurality of gradation voltages corresponding to a plurality of gradation levels lower than the gradation level that can be taken by the display data, and the display data are input and indicated by the display data Frequency calculating means for calculating the output frequency of the gradation level, setting means for setting the gradation voltage generated by the gradation voltage generating means according to the appearance frequency calculated by the frequency calculating means, and the display data The plurality of gradation voltages generated by the gradation voltage generating means are selected, and the selected gradation voltages are supplied to the display pixels, and the gradation levels indicated by the supplied gradation voltages are respectively indicated. Average Characterized by comprising a gradation voltage selection means for performing a display corresponding to the gray level.

  According to the present invention, it is possible to provide a display driving device and a display device that can reduce deterioration in display quality by setting a gradation level using the FRC method in accordance with the gradation of an image to be displayed. be able to.

It is a figure which shows the structure of the display apparatus to which the display drive device which concerns on one Embodiment of this invention is applied. It is a figure which shows the equivalent circuit of a display pixel. It is a timing chart which shows operation | movement of each block of a display apparatus at the time of performing 1 bit FRC drive. It is a block diagram which shows the outline | summary of a signal driver. It is a figure which shows a gradation histogram. It is a figure which shows the structure of a gradation voltage generation part. It is a figure for demonstrating the setting of the gradation voltage as an example of one Embodiment of this invention. It is a figure for demonstrating the setting of the gradation voltage as a modification of one Embodiment of this invention. It is a figure which shows the structure of a gradation voltage selection part.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing a configuration of a display device to which a display driving device according to an embodiment of the present invention is applied. The display device 1 shown in FIG. 1 includes a display panel 10, a scanning driver 20, a signal driver 30, a common electrode driving circuit 40, a power supply adjustment circuit 50, a video memory 60, and a control unit 70. Yes.

  The display panel 10 is configured by sandwiching liquid crystal between a pixel side substrate 11 and a counter side substrate 12. The pixel-side substrate 11 and the counter-side substrate 12 are bonded by a sealing material 13, and the sealing material 13 is sealed so that liquid crystal does not leak from between the pixel-side substrate 11 and the counter-side substrate 12.

  The pixel-side substrate 11 is a transparent substrate such as a glass substrate, and includes a plurality of scanning lines G (j) (j = 1, 2,..., N) and a plurality of signal lines S (i) (i = 1, 2,..., M) are arranged so as to intersect each other. Further, display pixels 14 are provided at positions corresponding to the intersections of the scanning lines G (j) and the signal lines S (i). In FIG. 1, only one display pixel 14 is shown.

  A common electrode 15 is formed on the opposite substrate 12, and the potential of the common electrode 15 is Vcom. Although details will be described later, the potential Vcom of the common electrode 15 is switched between the high-level side potential Vch and the low-level side potential Vcl every predetermined period.

  FIG. 2 is a diagram showing an equivalent circuit of the display pixel 14. The display pixel is configured as a capacitor Clcd having a liquid crystal sandwiched between a pixel electrode formed on the pixel side substrate 11 and a common electrode formed on the opposite side substrate 12. The pixel electrode is connected to the signal line S (i) through the thin film transistor (TFT) 141, and the gate of the TFT 141 is connected to the scanning line G (j). In addition, an auxiliary capacitor Ccs is connected in parallel with the capacitor Clcd. In a display pixel having such a configuration, when a voltage is applied between the pixel electrode and the common electrode, the alignment state of the liquid crystal filled between the pixel electrode and the common electrode is changed according to the applied voltage. As a result, the light transmittance in the liquid crystal layer changes. As a result, the transmission state of light from a light source (backlight) (not shown) arranged on the back surface of the display pixel is changed, and video display at a predetermined gradation level is performed.

  A scanning line G (j) is connected to the scanning driver 20. The scanning driver 20 receives the vertical control signal Vs from the control unit 70 and starts driving the n scanning lines G (j). At this time, each time the scanning driver 20 receives the horizontal control signal Hs from the control unit 70, the scanning driver 20 switches the scanning signal for turning on the TFTs 141 for one row from the gate-off level Vgl to the gate-on level Vgh.

  As shown in FIG. 3, the vertical control signal Vs is applied every frame, which is a period for displaying one screen of the display panel 10. Further, the horizontal control signal Hs is applied every horizontal period, which is a period for writing the gradation voltage for one row (one scanning line) of the display panel 10. In synchronization with the horizontal control signal Hs, the scanning driver 20 sequentially sets the potential to the gate-on level Vgh from the scanning line G (1). When the potential of the scanning line G (j) becomes the gate-on level Vgh, the TFT 141 connected to the scanning line is turned on. At this time, the gradation voltage applied to the signal line S (i) is applied to the pixel electrode of the display pixel 14 via the TFT 141 that is turned on.

  The signal driver 30 receives the display data data, selects a gradation voltage corresponding to the gradation level indicated by the display data data, and supplies the selected gradation voltage to the display pixel 14 via the signal line S (i). To the pixel electrode. Here, the signal driver 30 in the present embodiment is assumed to be a driver capable of driving the display panel 10 using the FRC method. Details of the signal driver 30 will be described later.

  FIG. 3 shows a timing chart when the FRC method is used. The example of FIG. 3 shows an example in which a 1-bit FRC system display is performed in the liquid crystal display device, and one display cycle is composed of four frames. Of the four frames shown in FIG. 3, the odd-numbered frame is a period in which the gradation voltage applied to the display pixel 14 is higher than the common voltage (hereinafter referred to as a positive period), and the even-numbered frame is displayed. This is a period during which the gradation voltage applied to the pixel 14 is lower than the common voltage (hereinafter referred to as a negative electrode period). In general, the liquid crystal constituting the display pixel 14 has a property that the characteristics deteriorate when a DC voltage is applied for a long time. Therefore, the polarity of the gradation voltage applied to the display pixel 14 and the common voltage (common with the gradation voltage). It is necessary to reverse the voltage magnitude relationship at regular intervals so that a long-term DC voltage is not applied to the liquid crystal. Various methods are conceivable for this purpose. In the present embodiment, as an example, the polarity of the gradation voltage and the common voltage is inverted between the positive electrode period and the negative electrode period.

  In the 1-bit FRC method in the liquid crystal display device, the positive electrode period and the negative electrode period are each composed of two frames, and display using the FRC method is performed in each period. That is, by changing the level of the gradation voltage applied to the display pixel 14 between the two frames that constitute the positive period and the negative period, the average gradation of the two frames that constitute each period is given to the human eye. It can be recognized that the level is displayed.

  The common electrode drive circuit 40 supplies the common voltage Vcom to the common electrode 15 of the counter substrate 12 based on the polarity inversion control signal Pol output from the control unit 70. As shown in FIG. 3, the polarity inversion control signal Pol is a signal applied for each frame, for example. The common electrode drive circuit 40 sets the potential of the common electrode 15 to the high-level side potential Vch when the polarity inversion control signal Pol is at the low level, and sets the potential of the common electrode 15 when the polarity inversion control signal Pol is at the high level. The low level potential Vcl is set.

  The power supply adjustment circuit 50 generates and supplies a power supply voltage required by each block of the display device 1 shown in FIG. 1 from the power supply Vcc. In the video memory 60, for example, display data input from the outside of the display device 1 is temporarily stored. The control unit 70 supplies a control signal for each block of the display device 1 shown in FIG.

  Next, the signal driver 30 will be described in detail. FIG. 4 is a configuration diagram showing an outline of the signal driver 30. For simplification of description, in the following description, it is assumed that the signal driver 30 is a driver that can generate five types of gradation voltages corresponding to five gradation levels. In addition, it is assumed that eight gradation levels (V0 to V7) can be displayed using 1-bit FRC drive. However, the method of the present embodiment can be applied to an FRC system other than 1 bit, and can also be applied to a display with more than 8 gradations.

  As shown in FIG. 4, the signal driver 30 in this embodiment includes a memory control unit 301, a display data memory 302, a histogram calculation unit 303, a gradation voltage setting unit 304, a gradation voltage generation unit 305, An FRC display data generation unit 306, a data register unit 307, a data latch unit 308, and a gradation voltage selection unit 309 are included.

  The memory control unit 301 controls the writing of the display data Data to the display data memory 302 and the reading of the display data Data from the display data memory 302 while monitoring the data storage state of the display data memory 302.

  The display data memory 302 has two memory areas A and B. Here, it is assumed that each memory area has a capacity sufficient to store display data for one frame. The memory control unit 301 writes the input display data Data into an empty memory area of the display data memory 302 every time one frame of display data Data is input from the outside. When the writing of the display data Data for one frame is completed, the memory control unit 301 reads the display data Data from the memory area where the writing is completed, and generates the display data for the FRC and the histogram calculation unit 303. Output to the unit 306.

  A histogram calculation unit 303 having a function as a frequency calculation means calculates a frequency distribution (tone gradation histogram) of gradation levels indicated by display data. FIG. 5 shows a gradation histogram. As shown in FIG. 5, the gradation histogram is obtained by determining the appearance frequency of the gradation levels V0 to V7 indicated by the display data Data. As the gradation histogram, a histogram from the time when the display device 1 is turned on until the present time may be obtained, or a histogram before a predetermined display cycle may be obtained.

  The gradation voltage setting unit 304 having a function as a setting unit is a gradation voltage for setting the gradation voltage generated by the gradation voltage generation unit 305 based on the gradation histogram calculated by the histogram calculation unit 303. The setting signal Set is supplied to the gradation voltage generation unit 305 and the FRC display data generation unit 306.

  The gradation voltage generation unit 305 generates gradation voltages applied to the pixel electrodes of the display pixels 14 using the voltages VγH and VγL supplied from the power supply adjustment circuit 50 as power sources.

  Here, the gradation voltage generation unit 305 will be described in detail. FIG. 6 is a diagram illustrating a configuration of the gradation voltage generation unit 305 in the present embodiment. As illustrated in FIG. 6, the gradation voltage generation unit 305 includes a polarity changeover switch unit 3051, a resistance unit 3052, a gradation voltage setting switch unit 3053, and a gradation amplifier unit 3054.

  The polarity changeover switch unit 3051 includes polarity changeover switches SWa and SWb. The polarity change-over switches SWa and SWb are connected to one of the power supplies VγH and VγL supplied from the power supply adjustment circuit 50 according to the level of the polarity inversion control signal Pol. The potentials of the power sources VγH and VγL are set higher for VγH. In this example, when the polarity inversion control signal Pol is at a high level, the polarity selector switch SWa is connected to the high level power source VγH, and the polarity selector switch SWb is connected to the low level side power source VγL. On the other hand, when the polarity inversion control signal Pol is at a low level, the polarity selector switch SWa is connected to the low-level power source VγL, and the polarity selector switch SWb is connected to the high-level power source VγH. By switching the polarity changeover switches SWa and SWb in this way, the polarity (level) of the gradation voltage generated in the gradation voltage generation unit 305 is inverted, for example, every frame.

  The resistor portion 3052 has (gradation level-1 that can be taken by display data-1) (seven in this example) resistors, and each resistor is connected in series. The resistor unit 3052 having such a configuration divides a voltage generated between the voltage VγH and the voltage VγL supplied from the power supply adjustment circuit 50 to generate a gradation voltage. Here, between the resistors R7 and R6, between the resistors R6 and R5, between the resistors R5 and R4, between the resistors R4 and R3, between the resistors R3 and R2, and between the resistors R2 and R1 A connection terminal connected to the gradation voltage setting switch constituting the gradation voltage setting switch section 3053 is provided therebetween. One end of each of the resistors R1 and R7 is connected to a gradation amplifier constituting the gradation amplifier unit 3054 without being connected to a gradation voltage setting switch.

  The gradation voltage setting switch unit 3053 includes (the number of gradation voltages that the gradation voltage generation unit 305 can generate−2) (three in this example) gradation voltage setting switches SWc1 to SWc3. Has been. Each gradation voltage setting switch is assigned an even number and a connection terminal provided between an odd numbered resistor and an even numbered resistor in accordance with the level of the gradation voltage setting signal Set. Connected to any one of the connection terminals provided between the resistor and the odd-numbered resistor. In this example, when the gradation voltage setting signal Set is at a high level, each gradation voltage setting switch is set between an odd-numbered resistor and an even-numbered resistor (in the example of FIG. 6, the resistor R7). And R6, between resistors R5 and R4, and between resistors R3 and R2). On the other hand, when the gradation voltage setting signal Set is at a low level, each gradation voltage setting switch is set between an even-numbered resistor and an odd-numbered resistor (resistors R6 and R5 in the example of FIG. 6). , Between the resistors R4 and R3, and between the resistors R2 and R1).

  The gradation amplifier unit 3054 has a number of gradation amplifiers (five in the example of FIG. 6) corresponding to the gradation voltages supplied via the gradation voltage setting switch unit 3053. Each gradation amplifier operates as a buffer circuit and amplifies the gradation voltage supplied via the gradation voltage setting switch unit 3053.

  With the above-described configuration, the grayscale voltage generation unit 305 generates grayscale voltages V0, V1, V3, V5, V7 and V0, V2, from the power supply voltages VγH and VγL according to the level of the grayscale voltage setting signal Set. One of V4, V6, and V7 is generated.

  Here, the level of the gradation voltage setting signal Set is set according to the gradation histogram generated by the histogram calculation unit 303. FIG. 7 is a diagram illustrating a correspondence relationship between the gradation histogram and the state of the gradation voltage setting switch (corresponding to the level of the gradation voltage setting signal Set).

In the present embodiment, the gradation voltage setting switch unit 3053 is set so that the gradation voltage corresponding to the gradation level having a high appearance frequency is generated as much as possible based on the gradation histogram generated by the histogram calculation unit 303. Do. However, in order to perform the FRC driving of k bits, the difference in gray level gradation level gray scale voltages generated by the gray voltage generator 305 correspond are adjacent and at equal intervals is (2 ^k -1) The level must not be exceeded. Considering this point, the gradation voltage setting switch unit 3053 is set.

  For example, in order to perform 1-bit FRC driving using the gradation voltage generation unit 305 having the configuration shown in FIG. 6, a group of gradation voltages V0, V1, V3, V5, and V7 having the same gradation level difference is used. Any one of the groups of the gradation voltages V0, V2, V4, V6, and V7 may be generated. Here, the gradation voltages V0 and V7 corresponding to the maximum and minimum gradation levels can be generated regardless of the state of the gradation histogram. This is because the maximum and minimum gradation levels cannot be displayed by FRC driving.

The gradation histogram determines which of the gradation levels V0, V1, V3, V5, and V7 and the group of V0, V2, V4, V6, and V7 can be generated. As this determination method, for example, the following two types of methods can be considered.
(1) A method of setting according to the maximum frequency gradation level of the gradation histogram
(2) Method of setting according to the comparison result of the sum of the appearance frequencies of the odd gradation levels and the sum of the appearance frequencies of the even gradation levels In the method of (1), the gradation level of the maximum frequency of the gradation histogram is In the case of V1, V3, and V5 (V0 and V7 are ignored because they can be generated regardless of the appearance frequency), as shown in FIG. 7A, gradation voltages V0, V1, V3, V5, The gradation voltage setting signal Set is set to the low level so that V7 is generated. On the other hand, when the gradation levels of the maximum frequency of the gradation histogram are V2, V4, and V6, the gradation voltages V0, V2, V4, V6, and V7 are generated as shown in FIG. 7B. The regulated voltage setting signal Set is set to the high level.

  In the method (2), the sum of the appearance frequencies of the gradation levels V1, V3, and V5 (V0 and V7 are ignored because they can be generated regardless of the appearance frequencies) is the gradation levels V2, V4, When the sum of the appearance frequencies of V6 is larger, the grayscale voltage setting signal Set is set to the low level so that the grayscale voltages V0, V1, V3, V5, and V7 are generated as shown in FIG. And On the other hand, the sum of the appearance frequencies of the gradation levels V1, V3 and V5 (V0 and V7 are ignored because they can be generated regardless of the appearance frequency) is greater than the sum of the appearance frequencies of the gradation levels V2, V4 and V6. Is smaller, the gradation voltage setting signal Set is set to the high level so that the gradation voltages V0, V2, V4, V6, and V7 are generated as shown in FIG.

  By determining the level of the gradation voltage setting signal Set as described above, the FRC drive can be performed correctly and the gradation level for which video display has been performed over a long period is actually generated. Since the display is based on the gradation voltage, the display quality such as flickering that occurs when the FRC method is used does not deteriorate. Furthermore, since the method (2) considers the appearance frequency of a plurality of gradation levels, the display quality is less likely to deteriorate than the method (1).

  Here, in the configuration example of FIG. 6, the gradation voltage setting switches SWc1 to SWc3 are collectively switched according to the level of one kind of gradation voltage setting signal Set. However, only one of the group of gradation levels V0, V1, V3, V5, V7 and the group of V0, V2, V4, V6, V7 can be generated. On the other hand, by making it possible to independently switch the gradation voltage setting switches SWc1 to SWc3 with the three kinds of gradation voltage setting signals Set1, Set2, and Set3, the gradation voltage generation unit according to a concept different from the above-described concept. It is also possible to set a gradation voltage that can be generated in 305.

  For example, an appearance frequency of an odd gradation level is compared with an appearance frequency of an even gradation level that is one level higher than the gradation level so that a gradation voltage corresponding to the larger one is generated. A method of setting is conceivable. In this method, for example, when a gradation histogram as shown in FIG. 8A is obtained, the appearance frequency of the gradation levels V1 and V2, the appearance frequency of the gradation levels V3 and V4, and the gradation level V5 The frequency of appearance of V6 is compared (ignore for V0 and V7). In the example of FIG. 8A, the appearance frequency of the gradation level V2 is high at the gradation levels V1 and V2, the appearance frequency of the gradation level V4 is high at the gradation levels V3 and V4, and at the gradation levels V5 and V6. The appearance frequency of the gradation level V5 is high. Therefore, as shown in FIG. 8B, the gradation voltage setting switches SWc1 to SWc3 are set so that the gradation voltages V2, V4, and V5 are generated.

  Here, in the method of comparing the appearance frequencies of the gradation levels V1 and V2, the appearance frequencies of the gradation levels V3 and V4, and the appearance frequencies of the gradation levels V5 and V6, combinations of the gradation levels V1, V4, and V5, etc. As described above, there is a possibility that the difference between adjacent gradation levels becomes 3 levels. In this case, since FRC drive cannot be performed, it is necessary to generate either V2 instead of the gradation level V1 or V3 instead of the gradation level V4.

  Hereinafter, the description will be continued returning to FIG. The FRC display data generation unit 306 in FIG. 4 generates display data Data (FRC) for FRC driving from the display data Data in synchronization with the input of the grayscale voltage setting signal Set from the grayscale voltage setting unit 304. In the present embodiment, as an example, display data Data is input only for one frame, and display data Data (FRC) for four frames for displaying one display period is generated from the display data Data for one frame. Shall.

  As described with reference to FIGS. 7 and 8, the gradation voltage that can be generated by the gradation voltage generation unit 305 can be determined from the level of the gradation voltage setting signal Set. It is not necessary to use FRC driving for the display pixels 14 that perform display of gradation levels corresponding to the gradation voltages that can be generated by the gradation voltage generation unit 305. Therefore, in this case, display data Data = display data Data (FRC). For example, in the present embodiment, the gradation voltage corresponding to the gradation level V7 can be generated regardless of the state of the gradation histogram. Therefore, when the gradation level indicated by the display data Data is the gradation level V7, as shown in FIG. 3, the gradation voltage V7 is selected for the gradation voltage in all four frames constituting one display period. Display data Data (FRC) is generated as selected by the unit 309.

  On the other hand, it is necessary to use FRC driving for the display pixels 14 that perform display of gradation levels corresponding to gradation voltages that cannot be generated by the gradation voltage generation unit 305. Therefore, in this case, display data Data (FRC) different from the display data Data is generated. For example, if the gradation voltage V3 cannot be generated, the display of the gradation level corresponding to the gradation voltage V3 can be realized as the time average of the display of the gradation level V2 and the display of the gradation level V4. For this reason, when the gradation level indicated by the display data Data is the gradation level V3, as shown in FIG. 3, the gradation voltage V2 is set to the latter 2 in the first two frames constituting one display period. Display data Data (FRC) is generated so that the gradation voltage V4 is selected by the gradation voltage selection unit 309 in the frame.

  The data register unit 307 sequentially fetches display data Data (FRC) from the FRC display data generation unit 306 in accordance with a timing signal synchronized with the horizontal synchronization signal Hs from the control unit 70.

  The data latch unit 308 simultaneously fetches the display data Data (FRC) held in the data register unit 307 in accordance with the timing signal synchronized with the horizontal synchronizing signal Hs from the control unit 70, and the fetched display data Data (FRC). Is output to the gradation voltage selection unit 309.

  As shown in FIG. 9, the gradation voltage selection unit 309 includes m DAC units 3091 and m output amplifiers 3092 corresponding to the number of signal lines S (i). Each DAC unit 3091 has the same number of switches SWd0 to SWd7 as the number of outputs of the decoder 3091a and the gradation voltage generation unit 305.

  The decoder 3091 a outputs a switching signal for turning on a switch corresponding to the display data Data (FRC) input from the data latch unit 308. The switches SWd0 to SWd7 are connected to the output of the gradation voltage generation unit 305 and open / close in response to a switching signal from the decoder 3091a. When the switches SWd0 to SWd7 are closed, the gradation voltage corresponding to the switch is supplied to the pixel electrode of the display pixel 14 via the signal line S (i). When the gradation voltage is supplied to the display pixel 14, display on the display pixel 14 is performed.

  The output amplifier 3092 operates as a buffer circuit and amplifies the gradation voltages supplied via the switches SWd0 to SWd7.

  As described above, according to the present embodiment, the grayscale voltage that cannot be generated by the grayscale voltage generation unit 305 corresponds to a grayscale voltage that has a low appearance frequency, so that it is more than simple FRC driving. Display quality is unlikely to deteriorate.

  Although the present invention has been described above based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications and applications are naturally possible within the scope of the gist of the present invention. For example, in the above-described example, the gradation histogram is created in consideration of the display data Data for the current display period input to the signal driver 30. However, a gradation histogram may be created only from the display data Data input to the signal driver 30 in the past.

  Moreover, although the above-mentioned example has shown the liquid crystal display device as a display device, it is not necessary to use a liquid crystal display device. For example, the method of this embodiment described above may be applied to an organic EL display device. Since the organic EL display device does not require AC driving as in a liquid crystal display device, one display cycle may be composed of two frames in order to perform 1-bit FRC driving.

  Further, the above-described embodiments include various stages of the invention, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some configuration requirements are deleted from all the configuration requirements shown in the embodiment, the above-described problem can be solved, and this configuration requirement is deleted when the above-described effects can be obtained. The configuration can also be extracted as an invention.

  DESCRIPTION OF SYMBOLS 10 ... Display panel, 11 ... Pixel side board | substrate, 12 ... Opposite side board | substrate, 20 ... Scan driver, 30 ... Signal driver, 40 ... Common electrode drive circuit, 50 ... Power supply adjustment circuit, 60 ... Video memory, 70 ... Control part, DESCRIPTION OF SYMBOLS 301 ... Memory control part 302 ... Display data memory 303 ... Histogram calculation part 304 ... Gradation voltage setting part 305 ... Gradation voltage generation part 306 ... Display data generation part for FRC, 307 ... Data register part, 308 ... Data latch part, 309 ... Gradation voltage selection part

Claims (6)

Gradation voltage generating means for generating a plurality of gradation voltages corresponding to a plurality of gradation levels lower than the gradation level that display data can take;
A frequency calculating means for inputting the display data and calculating an output frequency of a gradation level indicated by the display data;
Setting means for setting the gradation voltage generated by the gradation voltage generating means according to the appearance frequency calculated by the frequency calculating means;
A plurality of gradation voltages generated by the gradation voltage generation means are selected in accordance with the display data, the selected gradation voltages are supplied to display pixels, and the supplied gradation voltages are respectively indicated by the gradation voltages. Gradation voltage selection means for performing display corresponding to the average gradation level of gradation levels;
A display driving device comprising:   The setting means performs the setting so that the gradation voltages corresponding to the maximum and minimum gradation levels that the display data can take are generated regardless of the appearance frequency. The display driving device according to claim 1.   The display driving apparatus according to claim 2, wherein the setting unit performs the setting so that the plurality of gradation voltages are generated so that a difference in gradation levels is an equal interval.   The display driving apparatus according to claim 3, wherein the setting unit performs the setting based on a gradation level having a maximum appearance frequency among the appearance frequencies calculated by the frequency calculation unit. The gradation levels are divided into a plurality of groups with equal gradation level differences,
The display driving apparatus according to claim 3, wherein the setting unit performs the setting based on a gradation level belonging to a group having the largest sum of appearance frequencies calculated by the frequency calculation unit. In a display device that performs display by driving a display panel having a plurality of display pixels arranged two-dimensionally based on display data,
Gradation voltage generating means for generating a plurality of gradation voltages corresponding to a plurality of gradation levels lower than the gradation level that can be taken by the display data;
A frequency calculating means for inputting the display data and calculating an output frequency of a gradation level indicated by the display data;
Setting means for setting the gradation voltage generated by the gradation voltage generating means according to the appearance frequency calculated by the frequency calculating means;
A plurality of gradation voltages generated by the gradation voltage generation means are selected in accordance with the display data, the selected gradation voltages are supplied to display pixels, and the supplied gradation voltages are respectively indicated by the gradation voltages. Gradation voltage selection means for performing display corresponding to the average gradation level of gradation levels;
A display device comprising:

Images