JP2010171330A - Method of manufacturing epitaxial wafer, defect removing method, and the epitaxial wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing an epitaxial wafer which has an epitaxial film with a uniform thickness distribution and superior planarity and can be manufactured with simple steps, and to provide the epitaxial wafer. <P>SOLUTION: A wafer is obtained, by cutting a silicon single crystalline ingot obtained by a CZ method into thin discs (step S1). Next, a surface of the wafer is polished (lapped) to obtain a flat surface (step S2). The wafer is subjected to chemical polishing through etching (step S3), and then both surfaces of the wafer are roughly polished (step S4). After rough polishing, the wafer is subjected to vapor phase etching (step S5) to form an epitaxial film (step S6). The wafer having the epitaxial film formed therein is subjected to finish polishing (step S7) and final cleaning (step S8), at which stage all the steps have been completed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an epitaxial wafer manufacturing method, a defect removal method, and an epitaxial wafer.

  Conventionally, an epitaxial wafer is known in which an epitaxial film is vapor-phase grown on a film formation surface of a wafer obtained by cutting a silicon single crystal. When manufacturing such an epitaxial wafer, if processing distortion or particles exist in the wafer before the epitaxial film is laminated, dislocation defects are introduced when the epitaxial film is laminated, and it is difficult to normally grow a single crystal. It may become.

  Therefore, a method is known in which finish polishing is performed before forming an epitaxial film in order to remove processing distortion and particles generated in the substrate. In this case, the manufacturing process includes a slicing process for slicing a silicon single crystal ingot to obtain a thin disk-shaped wafer, a grinding (lapping) process for planarizing the wafer, a work-affected part and a work-strained part generated on the wafer. Etching is performed in the order of a chemical etching step for removing the surface, a rough polishing step for planarizing the wafer, a finish polishing step for mirror-finishing the surface of the wafer, and an epitaxial film forming step (hereinafter referred to as prior art A). There is also.) However, when manufactured in such a manufacturing process, micro-roughness called microroughness occurs on the surface of the silicon wafer after the epitaxial film forming process, and haze may deteriorate.

  Therefore, a manufacturing process is known in which a finish polishing process is performed after an epitaxial film is formed (for example, Patent Document 1). In this case, the manufacturing process is performed in the order of a slicing process, a grinding process, a chemical etching process, a rough polishing process, an epitaxial film forming process, and a final polishing process (hereinafter referred to as Conventional Technology B). There is also.) However, in this manufacturing process, scratches and processing damage may occur in the wafer after the rough polishing process, and these defects grow abnormally in the epitaxial film forming process, resulting in stacking faults (SF). . This will be specifically described with reference to FIG. In FIG. 9A, a concave work-affected portion 312 is generated in the wafer 311 after the rough polishing process. Here, the depth D1 of the work-affected portion 312 is 100 to 1000 nm. Next, as shown in FIG. 9B, when the epitaxial film 321 is formed, the work-affected portion 312 is not in a normal crystalline state, so an abnormally grown epitaxial film is formed, a transition occurs, and stacking faults occur. Part 322. As shown in FIG. 9C, when the finish polishing step is performed, the stacking fault portion 322 remains as it is.

In order to prevent such a stacking fault 322 from occurring, a manufacturing process is known in which a finish polishing process is performed before and after the formation of an epitaxial film. In this case, the manufacturing process is performed in the order of a slicing process, a grinding process, a chemical etching process, a rough polishing process, a final polishing process, an epitaxial film forming process, and a final polishing process (hereinafter referred to as conventional processes). Sometimes referred to as Technology C).
In addition, a method is known in which after the rough polishing step, a work-affected portion is removed by chemical etching by liquid phase treatment using hydrofluoric acid or nitric acid. The manufacturing process in this case is performed in the order of a slicing process, a grinding process, a chemical etching process, a rough polishing process, a liquid phase etching process, an epitaxial film forming process, and a final polishing process (hereinafter, It may be described as prior art D).

JP 2002-305202 A

  However, in the conventional technique C, it is necessary to perform the final polishing process twice, which causes a problem that the manufacturing process becomes long and the manufacturing cost increases.

  In addition, in the etching by the liquid phase as in the prior art D, the etching liquid cannot penetrate into the details of the part that has been altered by the surface tension of the liquid, so it is necessary to etch the thickness corresponding to the depth of the altered part. is there. This will be specifically described with reference to FIG. In FIG. 10A, a process-affected portion 412 occurs in the wafer 411 after the rough polishing process, and etching is performed at a depth D2 (100 to 1000 nm) by liquid phase etching. A concave recess 413 having a large opening and a shallow opening is formed, and the film formation surface of the wafer 411 is etched. Next, as shown in FIG. 10B, when the epitaxial film 421 is formed, an epitaxial recess 422 is formed on the surface of the epitaxial film 421 in accordance with the shape of the film formation surface of the wafer 411. Then, as shown in FIG. 10C, when the finish polishing step is performed, an epitaxial film 421 formed on a flat surface is obtained. As described above, when liquid phase etching is used, a wafer having excellent microroughness and high-precision flatness can be manufactured. However, since the etching amount is large, there is a problem that material cost and manufacturing cost increase. .

  Furthermore, when each process for manufacturing an epitaxial wafer is performed, there is a problem that the flatness of the wafer deteriorates or the film thickness of the epitaxial film cannot be made uniform. Specifically, the wafer after the rough polishing process has a flat surface, and after the final polishing process, the outer peripheral edge of the wafer has a sagging shape with a smaller thickness. After the epitaxial film formation process, the crystal becomes closer to the outer peripheral edge of the wafer. Since it grows easily, the epitaxial film has a truncated shape with a film thickness that increases toward the outer periphery. Therefore, there is a problem that a wafer having a uniform and flat surface of the epitaxial film cannot be stably obtained.

  An object of the present invention is to provide an epitaxial wafer manufacturing method that has a high-quality epitaxial film with a uniform film thickness distribution and no stacking faults, and that can manufacture an epitaxial wafer with excellent flatness with a simple and inexpensive process flow. A defect removal method and an epitaxial wafer are provided.

  An epitaxial wafer manufacturing method of the present invention is an epitaxial wafer manufacturing method in which an epitaxial film is vapor-phase-grown on a film formation surface of the wafer, and a rough polishing step for performing rough polishing on the film formation surface of the wafer; A vapor-phase etching process for etching defects formed by stress acting on the film-forming surface during the rough polishing and the film-forming surface by performing a gas-phase etching process on the film-forming surface of the rough-polished wafer; And an epitaxial film forming step of vapor-phase growing an epitaxial film on the film-formed surface of the vapor-etched wafer, and a final polishing step of performing final polishing on the wafer on which the epitaxial film is formed. And

When rough polishing is performed on a wafer, concave defects such as scratches and distortions may occur on the surface.
In the present invention, after the rough polishing step, vapor phase etching is performed on the surface of the wafer. Thereby, the work-affected portion of the concave portion generated on the surface of the wafer is dissolved and removed, so that it is not affected by defects generated in the rough polishing step in the formation of the epitaxial film. Therefore, generation of stacking faults after the formation of the epitaxial film can be suppressed.
In particular, according to the vapor phase etching, the etchant can be supplied to the pores of the concave defect of the wafer, so that the defect can be reliably removed with a small etching amount. Further, according to the vapor phase etching, since the particle contamination on the wafer is small, the cleaning step after the vapor phase etching can be omitted, so that the manufacturing process can be further simplified.
As described above, since the defect generated in the wafer is removed, the single crystal can be normally grown when the epitaxial film is formed thereafter. Finally, by performing final polishing, the microroughness of the epitaxial film is eliminated, and an epitaxial wafer having excellent flatness can be manufactured.
In addition, by performing processing in the order of rough polishing step, vapor phase etching step, epitaxial film formation step, and final polishing step, a product having a uniform epitaxial film thickness distribution and excellent flatness of the entire wafer is manufactured. be able to.

  The defect removal method for an epitaxial wafer according to the present invention is a defect removal method for an epitaxial wafer that removes defects generated by rough polishing applied to a film formation surface of the wafer, and performs vapor phase etching treatment on the film formation surface. Then, the defect and the film formation surface are etched.

Usually, before the epitaxial film is formed on the film formation surface of the wafer, a rough polishing process is performed.
In the present invention, a vapor phase etching process is performed to remove defects caused by the rough polishing. Thereby, the epitaxial film can be normally grown in a single crystal, and a high quality epitaxial wafer can be manufactured.

The epitaxial wafer of the present invention is an epitaxial wafer manufactured by the above-described epitaxial wafer manufacturing method, wherein the epitaxial film has two or less stacking faults caused by the defects.
In the epitaxial wafer of the present invention, it is preferable that the epitaxial film has zero stacking faults caused by the defects.

In the present invention, since the number of stacking faults generated in the epitaxial film is 2 or less, and further 0, a high-quality epitaxial wafer can be provided.
The stacking fault can be determined from an image obtained by scanning the entire surface of the epitaxial wafer using a confocal microscope and combining these data on a computer.
In the present invention, since the number of stacking faults of the epitaxial wafer is 2 or less, more preferably 0, a high-quality epitaxial wafer can be provided.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a flowchart showing an epitaxial wafer manufacturing method according to an embodiment of the present invention. FIGS. 2A and 2B are diagrams showing a process of removing a stacking fault by vapor phase etching in the embodiment, where FIG. 2A shows a state after vapor phase etching, FIG. 2B shows a state after epitaxial film lamination, and FIG. The state after finish polishing is shown. 3A and 3B are views showing the state of the wafer after each step in the embodiment, where FIG. 3A is the state after the vapor phase etching step, FIG. 3B is the state after forming the epitaxial film, and FIG. Shown later.

(Epitaxial wafer manufacturing method)
In the epitaxial wafer in this embodiment, an epitaxial film is formed on a wafer obtained by slicing a single crystal ingot into a thin disk shape. A process flow for manufacturing such an epitaxial wafer is shown in FIG.

  In FIG. 1, first, a silicon single crystal ingot obtained by the Czochralski (CZ) method is cut into a thin disk shape by a multi-wire saw or the like to obtain a wafer (step S1). Next, the wafer surface is ground and planarized (step S2). Next, chemical polishing by etching is performed (step S3), and then both surfaces of the wafer are roughly polished (step S4). After the rough polishing, a vapor phase etching process is performed (step S5), and then an epitaxial film is formed (step S6). Then, final polishing is performed on the wafer on which the epitaxial film is formed (step S7), and final cleaning is performed (step S8).

  Each of the above steps will be described in detail. The silicon single crystal ingot is pulled up by the CZ method, the silicon single crystal ingot is cut to cut out the wafer (step S1), and the grinding step to remove the unevenness of the wafer by mechanical polishing to increase the parallelism (step S2). Since the rough polishing process (step S4) and the final polishing process (step S7) are well-known techniques, description thereof is omitted.

  The chemical polishing process (step S3) is a process that uses chemical etching to remove the processing distortion caused by the slicing process (step S1) and the grinding process (step S2). As an etching solution for chemical etching, a mixed solution containing sodium hydroxide, potassium hydroxide or an alkali is diluted with water.

The vapor phase etching step (step S5) is a step of removing defects such as processing distortion and processing damage generated in the rough polishing step (step S4), and is performed by a single wafer type vapor phase etching apparatus.
First, a wafer is set in a chamber of a vapor phase etching apparatus, and a mixed gas of ozone and hydrogen fluoride is filled into the chamber as an etchant. The concentration of ozone is preferably in the range of 10 g / m ³ or more and 1000 g / m ³ or less. The higher the ozone concentration, the more the wafer damage can be removed. The concentration of hydrogen fluoride is preferably 5 g / m ³ or more and 50 g / m ³ or less. If the concentration of hydrogen fluoride is less than 5 g / m ³ , the etching process takes too much time, which is not preferable. On the other hand, if it exceeds 50 g / m ³ , it is not preferable from the viewpoint of safety.
The mixed gas is mixed with an inert gas such as N ₂ or Ar as a binder.
Here, as the gas used as the etchant, C ₂ F ₆ , CF ₄ , HCl, or the like can be used in addition to the above-described ozone and hydrogen fluoride.
Vapor phase etching is performed under conditions of normal temperature and pressure and an etching rate of 50 nm / min, and ends when the desired etching amount is reached.

  In the epitaxial film formation step (step S6), first, heat treatment is performed in the presence of hydrogen, and then an epitaxial film is formed using a normal epitaxial film growth apparatus. The method for forming the epitaxial film is not particularly limited, and various methods such as a hydrogen reduction method, a thermal decomposition method, a metal organic chemical vapor deposition method (MOCVD method), and a molecular beam epitaxial method (MBE method) can be employed.

  Here, in the manufacturing method described above, defects generated on the surface of the wafer by the rough polishing step (step S4) can be removed. In the present embodiment, the defect is described as a work-affected part. The process of removing the work-affected part will be described with reference to FIG. In FIG. 2A, a work-affected portion 111 is generated in the wafer 11 after the rough polishing process. The work-affected portion 111 is removed by vapor phase etching, and the film-formed surface is etched to form an etching recess 112 having a large opening. Here, the difference between the film formation surfaces of the wafer 11 before and after the vapor phase etching process is D, and D indicates the etching amount. The depth D is a minute etching amount within a range of 10 nm or more and 50 nm or less. This is because the etchant that is in the gas phase is likely to enter the details of the work-affected portion 111, so that the etching amount can be reduced.

  Next, as shown in FIG. 2B, when the epitaxial film 21 is formed, epitaxial growth is performed according to the shape of the film formation surface of the wafer 11, and the epitaxial film is formed to the details of the etching recess 112. At this time, an epitaxial recess 211 whose opening is large and shallow on the surface of the epitaxial film 21 according to the shape of the etching recess 112 is formed. Then, as shown in FIG. 2C, the surface of the epitaxial film 21 is formed flat by the finish polishing process.

The state of the epitaxial wafer in each process will be described with reference to FIG.
As shown in FIG. 3A, the wafer 11 after the vapor phase etching step is formed to have a uniform thickness as a whole, and minute irregularities are formed on the surface thereof. Next, as shown in FIG. 3B, when the epitaxial film 21 is formed on the wafer 11, the epitaxial film 21 becomes thicker as it approaches the outer peripheral edge portion 11A of the epitaxial wafer. This is because the epitaxial single crystal is likely to grow toward the outer peripheral side of the wafer. Then, as shown in FIG. 3C, when the final polishing step is performed, the surface of the epitaxial film 21 is polished, the film thickness distribution becomes uniform, and the surface of the epitaxial wafer is formed flat.

In the present embodiment as described above, the following operational effects can be obtained.
By using vapor phase etching, the work-affected portion 111 generated in the rough polishing step (step S4) can be removed, so that a high-quality epitaxial wafer having two or less stacking faults can be manufactured. The number of stacking faults is more preferably zero.
An epitaxial wafer having a small number of stacking faults is excellent in microroughness and flatness.
Furthermore, when vapor phase etching is used, the amount of etching is small, so that material costs and manufacturing costs can be significantly reduced.
And by implementing each process in the above-mentioned order, the epitaxial film 21 with a uniform film thickness distribution can be formed as a whole.

The aspect described above shows one aspect of the present invention, and the present invention is not limited to the above-described embodiment, and is within the scope of achieving the object and effect of the present invention. Needless to say, modifications and improvements are included in the content of the present invention.
For example, in the above embodiment, the silicon single crystal ingot is pulled up by the CZ method, but may be pulled by the MCZ method (Magnetic Field Applied Czochralski process) or the FZ method (Floating Zone process).

In the above embodiment, a mixed gas of ozone and hydrogen fluoride is used in the gas phase etching. However, the present invention is not limited to this, and the aforementioned C ₂ F ₆ , CF ₄ , HCl, or the like may be used. The temperature, pressure, etching rate, time, and the like can be adjusted as appropriate depending on the selection and concentration of the gas used in these.

EXAMPLES Next, although an Example is given and this invention is demonstrated in more detail, this invention is not restrict | limited at all to the content of description of these Examples.
Epitaxial wafers were manufactured by the manufacturing methods shown in the following examples and comparative examples.

[Example 1]
An epitaxial wafer was manufactured by the manufacturing method of the above-described embodiment. That is, a silicon single crystal ingot pulled up by the CZ method is sliced, and after a grinding process and a chemical etching process, a rough polishing process (DSP), a vapor phase etching process, an epitaxial formation process (EPI), and a final polishing process (SMP) ).
The processing conditions in the gas phase etching process are as follows.
Etchant: Mixed gas of ozone and hydrogen fluoride (at normal temperature and normal pressure, ozone gas concentration: 120 g / m ³ , hydrogen fluoride gas concentration: 23 g / m ³ )
Pressure: 106kPa
Temperature: 26 ° C
Etching rate: 50 nm / min

[Comparative Example 1]
An epitaxial wafer was manufactured by the manufacturing method of the prior art A described above. That is, after the chemical etching step, DSP, SMP, and EPI were performed in this order.

[Comparative Example 2]
An epitaxial wafer was manufactured by the manufacturing method of the prior art B described above. That is, after the chemical etching step, DSP, EPI, and SMP were performed in this order.

[Comparative Example 3]
An epitaxial wafer was manufactured by the manufacturing method of the prior art C described above. That is, after the chemical etching step, DSP, SMP, EPI, and SMP were performed in this order.

[Comparative Example 4]
An epitaxial wafer was manufactured by the manufacturing method of the conventional technique D described above. That is, after the chemical etching step, DSP, liquid phase etching, EPI, and SMP were performed in this order.
In the liquid phase etching step, etching was performed at an etching rate of 50 to 5000 nm / min.

  About the above-mentioned Example and comparative example, manufacturing cost, flatness of an epitaxial wafer, film thickness distribution of an epitaxial film, haze, and stacking fault (SF) were evaluated. The evaluation criteria are as follows.

(Evaluation of manufacturing cost)
○: Low material cost and manufacturing cost △: Slightly expensive material cost and manufacturing cost ×: High material cost and manufacturing cost

(Evaluation of flatness)
A global flatness back reference ideal range (GBIR) value, which is a standardized parameter for expressing flatness, was measured. The evaluation criteria are as follows.
○: formed flat (GBIR value <0.2 μm)
Δ: Some unevenness is formed (0.2 μm <GBIR value <0.3 μm)
X: Concavities and convexities are formed (GBIR value> 0.3 μm)

(Evaluation of film thickness distribution of epitaxial film)
The film thickness distribution of the epitaxial film was measured using QS-3000 (FTIR) manufactured by ACCENT.
○: Uniform overall △: Partially non-uniform ×: Non-uniform overall

(Evaluation criteria for haze)
Haze is extremely fine irregularities on the final polished surface of a silicon wafer. Haze was measured using Surfscan SP2 (DWO) manufactured by KLA. The evaluation criteria are as follows.
○: Haze good (haze <0.01 ppm)
Δ: Normal haze level (0.01 ppm <haze <0.05 ppm)
X: Deterioration of haze level (haze> 0.05 ppm)

(Evaluation criteria for the number of stacking faults (SF))
The number of stacking faults (SF) was confirmed by scanning the surface of the silicon wafer with a confocal microscope.
○: SF is 0 Δ: SF is 1 to 2 ×: SF is 3 or more

  As shown in Table 1, in Example 1, good results were obtained in all items. On the other hand, in Comparative Example 1, the film thickness of the epitaxial film is not uniform, and there is a problem in haze due to the macroroughness of the surface. In Comparative Example 2, a large amount of SF is generated. In Comparative Example 3, the manufacturing cost is high. Comparative Example 4 has problems in manufacturing cost, flatness, and film thickness of the epitaxial film.

Here, the state of the wafer after each process of Comparative Examples 1 to 4 will be specifically described with reference to FIGS.
FIG. 4 shows the wafer after each step of Comparative Example 1. As shown in FIG. 4A, the wafer 411 after the rough polishing step is formed to have a flat and uniform thickness. Next, as shown in FIG. 4B, when the finish polishing step is performed, the thickness decreases as the outer peripheral edge portion 411A of the wafer 411 is approached, and is not formed flat. Then, as shown in FIG. 4C, when the epitaxial film 421 is formed, the surface of the epitaxial wafer is formed flat, but the film thickness distribution of the epitaxial film 421 becomes non-uniform.

  FIG. 5 shows the wafer after each step of Comparative Example 2. As shown in FIG. 5A, the surface of the wafer 311 after the rough polishing step is formed to have a flat and uniform thickness. Next, as shown in FIG. 5B, when the epitaxial film 321 is formed, a stacking fault 322 is formed, and the film thickness increases as it approaches the outer peripheral edge 321A of the epitaxial film 321. Then, as shown in FIG. 5C, when the final polishing step is performed, the surface of the epitaxial film 321 is polished and the film thickness distribution of the epitaxial film 321 becomes uniform, and the surface of the epitaxial wafer becomes flat. As described above, the stacking fault 322 remains.

  FIG. 6 shows the wafer after each step of Comparative Example 3. As shown in FIG. 6A, the film thickness of the wafer 511 after the finish polishing step becomes smaller as it approaches the outer peripheral edge portion 511A. Next, as shown in FIG. 6B, when the epitaxial film 521 is formed, the surface of the epitaxial film 521 is formed flat, but the film thickness distribution of the epitaxial film 521 becomes non-uniform. Then, as shown in FIG. 6C, when the final polishing step is performed again, the epitaxial film 521 is polished and the film thickness distribution becomes uniform, but the film thickness is uneven as the entire epitaxial wafer, A flat surface cannot be obtained.

  FIG. 7 shows the wafer after each step of Comparative Example 4. As shown in FIG. 7A, the wafer 411 after the liquid phase etching process has a smaller film thickness as it approaches the outer peripheral edge portion 411A, and larger irregularities are formed on its surface as compared with the first embodiment. . Next, as shown in FIG. 7B, when the epitaxial film 421 is formed, the surface of the epitaxial film 421 is formed flat, but the film thickness distribution of the epitaxial film 421 becomes non-uniform. Then, as shown in FIG. 7C, when the final polishing step is performed, the surface of the epitaxial film 421 is polished and the film thickness distribution becomes uniform. However, as the entire epitaxial wafer approaches the outer peripheral edge 411A. The thickness is reduced and a flat surface cannot be obtained.

  As described above, in Comparative Example 1 to Comparative Example 4, the film thickness distribution of the epitaxial film is non-uniform, the film thickness of the outer peripheral edge of the silicon wafer is small, and it is not formed flat, or high quality. It is difficult to obtain a silicon wafer. However, in Example 1 which is the present invention, the film thickness distribution of the epitaxial film is uniform and the surface of the silicon wafer is formed flat, so that a high-quality silicon wafer can be provided.

Next, for Example 1, Comparative Example 3, and Comparative Example 4, a graph showing the relationship between the margin on the wafer surface and the number of stacking faults (SF) is shown in FIG.
As shown in FIG. 8, Example 1 can suppress the number of SFs with a small allowance (etching amount) at the time of vapor phase etching. In Comparative Example 3, since the final polishing is performed twice, it can be seen that the polishing amount is increased. Since Comparative Example 4 uses liquid phase etching, it can be seen that a larger margin (etching amount) is required than Example 1 using gas phase etching.
That is, in Example 1 using vapor phase etching, the etching amount can be reduced, so that the material cost and the manufacturing cost can be reduced.

  The present invention can be used in an epitaxial wafer manufacturing method.

The flowchart which shows the manufacturing method of the epitaxial wafer in embodiment of this invention. It is a figure which shows the process of removing a stacking fault part by the gaseous-phase etching in the said embodiment, (A) is the state after vapor-phase etching, (B) is the state after epitaxial film lamination | stacking, (C) is after finishing polishing. Indicates the state. It is a figure which shows the state of the wafer after each process in the said embodiment, (A) is the state after a gaseous-phase etching process, (B) is the state after epitaxial film formation, (C) is the state after a final polishing process. Show. It is a figure which shows the state of the wafer after each process in a prior art, (A) shows the state after a rough polishing process, (B) shows the state after a final polishing process, (C) shows the state after epitaxial film formation. Yes. It is a figure which shows the state of the wafer after each process in a prior art, (A) shows the state after a rough polishing process, (B) shows the state after epitaxial film formation, (C) shows the state after a final polishing process. Yes. It is a figure which shows the state of the wafer after each process in a prior art, (A) shows the state after a final polishing process, (B) shows the state after epitaxial film formation, (C) shows the state after a final polishing process. Yes. It is a figure which shows the state of the wafer after each process in a prior art, (A) shows the state after a liquid phase etching process, (B) shows the state after epitaxial film formation, (C) shows the state after a final polishing process. ing. The graph which shows the relationship between the margin of the wafer and the number of SF in a present Example. In the prior art, it is a figure which shows the process in which a stacking fault is formed on the surface of a wafer, (A) is the state after rough polishing, (B) is the state after epitaxial film formation, (C) is the state after the finish polishing process. Is shown. In the prior art, it is a figure which shows the process of removing a stacking fault part by liquid phase etching, (A) is the state after liquid phase etching, (B) is the state after epitaxial film lamination, (C) is the state after finish polishing Is shown.

DESCRIPTION OF SYMBOLS 11 ... Wafer 111 ... Process-affected part 112 ... Etching recessed part 21 ... Epitaxial film 211 ... Epi recessed part

Claims (4)

An epitaxial wafer manufacturing method in which an epitaxial film is vapor-phase grown on a film forming surface of a wafer,
A rough polishing step of rough polishing the film-forming surface of the wafer;
A vapor-phase etching process for etching defects formed by stress acting on the film-forming surface during the rough polishing and the film-forming surface by performing a gas-phase etching process on the film-forming surface of the rough-polished wafer; ,
An epitaxial film forming step in which an epitaxial film is vapor-grown on the film-forming surface of the vapor-etched wafer;
And a final polishing step of performing final polishing on the wafer on which the epitaxial film is formed. A method for manufacturing an epitaxial wafer, comprising: A method for removing defects of an epitaxial wafer for removing defects generated by rough polishing applied to a film forming surface of the wafer,
A defect removal method for an epitaxial wafer, wherein the defect and the film-forming surface are etched by performing a gas phase etching process on the film-forming surface. An epitaxial wafer manufactured by the epitaxial wafer manufacturing method according to claim 1,
The epitaxial wafer, wherein the number of stacking faults caused by the defects is two or less in the epitaxial film. The epitaxial wafer according to claim 3, wherein
The epitaxial wafer is characterized in that the number of stacking faults caused by the defects is zero in the epitaxial film.

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