JP2010160816A - Control method of semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a control method of a semiconductor memory device capable of performing efficient refresh processing. <P>SOLUTION: The control method of the semiconductor memory device provided with a nonvolatile memory which stores data in blocks as unit of data erasure, includes: a first process of selecting a monitoring object block from among the blocks to monitor the number of errors of the data stored in the monitoring object block; and a second process of refreshing the monitoring object block in which the number of errors of the data is equal to or more than a predetermined threshold. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for controlling a semiconductor memory device, for example, a refresh method for a semiconductor memory device provided with a NAND flash memory.

  A NAND flash memory is a non-volatile memory that can retain information even when power supply is stopped, and is widely used because it is superior in bit unit price to other non-volatile memories. However, with NAND flash memory, with the increase in capacity and integration, the influence of read disturb, which is data corruption due to aging of the written data and data read processing, has become prominent, and the stored data deteriorates. There is a problem that the possibility that the stored data cannot be correctly reproduced increases.

  The secular change is a phenomenon in which an error occurs in data due to the gradual removal of charges from the floating gate that accumulates charges over time. Read disturb is a phenomenon in which stored data has an error when a small amount of charge is stored in a floating gate of a memory cell adjacent to a memory cell from which data is read.

  The problem of aging and read disturb can be restored by using an error correcting code that corrects an error in the generated data. However, since the data on the NAND flash memory remains in error, the aging and read disturb further advance, and if an error exceeding the correction capability of the error correction code occurs, the correct data can be restored. Can not.

  Therefore, the data stored in the NAND flash memory is prevented from being completely destroyed by performing a refresh process in which the stored data is read and error correction is performed and then the data is rewritten to the NAND flash memory. The retention period can be increased.

  As a method of increasing the data retention period of the data stored on the NAND flash memory by performing such refresh processing, for example, the number of times of reading from the NAND flash memory is measured and the prescribed read amount is reached. In such a case, a method of executing the refresh process or a method of performing the refresh process when the number of errors increases can be considered (for example, see Patent Document 1).

  However, in a NAND flash memory, a data error is unlikely to occur in a memory cell with a small number of rewrites, and the data error does not increase uniformly with the passage of a fixed time. Similarly, in a NAND flash memory, data errors do not necessarily increase when a predetermined number of reads are performed. Therefore, the refresh process is performed unnecessarily, although the probability of data corruption is reduced by performing the refresh process uniformly using the number of readings without reflecting the actual data corruption situation.

  Since the NAND flash memory is a device with a limited number of rewrites, there is a problem that the life of the NAND flash memory is shortened by performing unnecessary refresh processing.

  On the other hand, when trying to perform refresh processing while monitoring the data corruption status, there is a problem that the amount of calculation and power consumption increase, for example, reading memory cells for monitoring itself requires error correction processing.

JP 2004-326867 A

  The present invention provides a method for controlling a semiconductor memory device capable of performing an efficient refresh process.

  According to one aspect of the present invention, there is provided a method for controlling a semiconductor memory device including a nonvolatile memory that stores data in a block that is a unit of data erasing, wherein a monitoring target block is selected from the blocks, and A first step of monitoring the number of errors in the data stored in the monitoring target block; and a second step of refreshing the monitoring target block in which the number of data errors is equal to or greater than a predetermined threshold. A method for controlling a semiconductor memory device is provided.

  According to the present invention, it is possible to provide a method for controlling a semiconductor memory device capable of performing an efficient refresh process.

1 is a diagram showing a schematic configuration of a semiconductor memory device according to an embodiment of the present invention. It is a figure for demonstrating the structure of the 1st table of the semiconductor memory device according to one Embodiment of this invention. It is a flowchart for demonstrating the selection process of the monitoring object block of the semiconductor memory device according to one Embodiment of this invention. It is a flowchart for demonstrating the registration process of the monitoring object block to the 1st table of the semiconductor memory device according to one Embodiment of this invention. It is a flowchart for demonstrating the registration process of the block to the 1st table of the semiconductor memory device according to one Embodiment of this invention. It is a flowchart for demonstrating the monitoring process of the number of errors with respect to the block registered into the 1st table of the semiconductor memory device according to one Embodiment of this invention. It is a flowchart for demonstrating the deletion process of the refreshed block from the 1st table of the semiconductor memory device according to one Embodiment of this invention. It is a figure for demonstrating the structure of the 2nd table of the semiconductor memory device according to one Embodiment of this invention. It is a flowchart for demonstrating the selection process of the monitoring object block of the semiconductor memory device according to one Embodiment of this invention. It is a figure for demonstrating the structure of the 3rd table of the semiconductor memory device according to one Embodiment of this invention. It is a flowchart for demonstrating the selection process of the monitoring object block of the semiconductor memory device according to one Embodiment of this invention. It is a figure for demonstrating the structure of the 4th table of the semiconductor memory device according to one Embodiment of this invention. It is a flowchart for demonstrating the selection process of the monitoring object block of the semiconductor memory device according to one Embodiment of this invention. It is a figure for demonstrating the structure of the 5th table of the semiconductor memory device according to one Embodiment of this invention. It is a flowchart for demonstrating the registration process of the monitoring object block to the 1st table of the semiconductor memory device according to one Embodiment of this invention. It is a figure for demonstrating the structure of the 6th table of the semiconductor memory device according to one Embodiment of this invention. It is a flowchart for demonstrating the process which deletes the non-monitoring target block of an error count from the 1st table of the semiconductor memory device according to one Embodiment of this invention. It is a figure for demonstrating the structure of the 7th table of the semiconductor memory device according to one Embodiment of this invention. It is a flowchart for demonstrating the monitoring process of the number of errors with respect to the monitoring object block registered into the 1st table of the semiconductor memory device according to one Embodiment of this invention. It is a figure which shows the structure of SSD concerning one Example of this invention. It is a figure which shows the structure of the drive control circuit concerning one Example of this invention. It is a figure which shows the structure of the processor concerning one Example of this invention. It is a perspective view which shows an example of the portable computer carrying SSD concerning one Example of this invention.

  Exemplary embodiments of a method for controlling a semiconductor memory device according to the present invention will be explained below in detail with reference to the accompanying drawings. In addition, this invention is not limited to the following description, In the range which does not deviate from the summary of this invention, it can change suitably.

(First embodiment)
FIG. 1 is a diagram showing a schematic configuration of a semiconductor memory device 1 according to a first embodiment of the present invention. The semiconductor memory device 1 shown in FIG. 1 is an embodiment of the present invention and is not limited to this configuration.

  The semiconductor memory device 1 according to the first embodiment includes a control unit 3 and a NAND flash memory 10. The control unit 3 is a host interface (I / I) that communicates with a central processing unit (CPU) 4 that executes programs, a RAM 5 that stores data, programs, and the like, and a host device 2 that is connected to the semiconductor storage device 1. F) 6, a timer 7, a NAND interface (I / F) 8 that controls data transfer with the NAND flash memory 10, and a bus 9 that communicably connects these components. The NAND flash memory 10 is configured by arranging a plurality of blocks which are units of data erasure.

  The semiconductor memory device 1 communicates with the host device 2 via the host I / F 6 and performs data transfer between the host device 2 and the semiconductor memory device 1 in response to a request from the host device 2. The interpretation of the request from the host device 2 and the control of the semiconductor memory device 1 itself are realized by the CPU 4 interpreting the program stored in the RAM 5 inside the control unit 3. Data supplied from the host device 2 is stored on the NAND flash memory 10, and the control unit 3 mediates data transfer between the host device 2 and the NAND flash memory 10.

  The control unit 3 inside the semiconductor memory device 1 communicates with the host device 2 via the host I / F 6 and transfers data between the RAM 5 inside the control unit 3 and the host device 2. The data transferred from the host device 2 is temporarily stored in the RAM 5 inside the control unit 3, and is written to the NAND flash memory 10 through the NAND I / F 8 at a specified timing. In response to a read request from the host device 2, the control unit 3 reads data from the NAND flash memory 10 in accordance with an instruction from the CPU 4 and stores it in the RAM 5 inside the control unit 3. Then, the control unit 3 transfers the data stored on the RAM 5 to the host device 2 through the host I / F 6.

  The NAND I / F 8 used for writing and reading data to the NAND flash memory 10 includes an error correction unit 21 and an error number detection unit 22 as error correction circuits. The error correction unit has a function of correcting an error in data read from an arbitrary block in the NAND flash memory 10. The error number detection unit 22 has a function of detecting the number of errors corrected by the error correction unit 21. The correction capability of the error correction code added by the error correction unit 21 is assumed to be 2 bits or more, and here it will be described as having an 8-bit error correction capability, but the present invention is not limited to this error correction capability. .

  When writing data on the RAM 5 to the NAND flash memory 10, the error correction unit 21 calculates an error correction code for the data to be written and writes the data together with the data on the NAND flash memory 10. Further, when reading data from the NAND flash memory 10, an error correction unit is obtained by using data read from the NAND flash memory 10 and an error correction code stored in the NAND flash memory 10 together with the data. 21 corrects an error in the read data. When error correction is performed, the error number detection unit 22 detects the number of corrected errors and stores it in the own error number detection unit 22. Here, the number of corrected errors is stored in the error number detection unit 22, but the storage location is not limited to this.

  When the error correction unit 21 performs error correction, the NAND I / F 8 interrupts the CPU 4 to notify the data stored in the NAND flash memory 10 that an error has occurred. Then, the CPU 4 accesses the error number detection unit 22 of the NAND I / F 8 and acquires the number of errors that have occurred.

  When an arbitrary time is set, the timer 7 measures the time internally, and generates an interrupt to the CPU 4 after the set time has elapsed. The CPU 4 can know from the interruption from the timer 7 that the set time has elapsed.

  The NAND flash memory 10 stores the data supplied from the host device 2 and the error correction code calculated by the error correction unit 21 from the data.

  On the RAM 5, a first table 31 (corresponding to the first table in the claims) is configured that stores information on blocks that need to be refreshed in the near future. FIG. 2 is a diagram for explaining the configuration of the first table 31. The first table 31 is composed of a plurality of entries, and a block number on the NAND flash memory 10 is registered in each entry. Access to the first table 31 is performed using the entry number, and the block stored in each entry becomes a monitoring target block (hereinafter referred to as a monitoring target block) for monitoring the number of errors in the stored data. .

  Further, on the RAM 5, a second table 32 (corresponding to the second table in the claims), a third table 33 (corresponding to the third table in the claims), a fourth table 34 (in the claims) Corresponding to the fourth table), fifth table 35 (corresponding to the fifth table of claims), sixth table 36 (corresponding to the sixth table of claims) and seventh table 37 (claim) Corresponding to the seventh table). The second table 32 to the seventh table 37 will be described later.

  In the present embodiment, when an error occurs in the data read from the NAND flash memory 10 in accordance with a request from the host device 2, the number of errors in the block in which an error has occurred in the data is monitored according to the flow shown in FIG. Decide if you want to. FIG. 3 is a flowchart for explaining monitoring target block selection processing according to the first embodiment.

  First, when the CPU 4 reads data from a block on the NAND flash memory 10, the error correction unit 21 corrects the error in the read data, and the error number detection unit 22 detects the number of corrected errors, and the own error is detected. The number is stored in the number detector 22. The CPU 4 accesses the error number detection unit 22, acquires the number of errors that occurred in the read data, and confirms it (step S101). Then, the CPU 4 confirms whether or not the number of errors is greater than or equal to the first threshold (step S102). The first threshold is an error count threshold for selecting a block to be monitored. Here, for example, the 2-bit error count is set as the first threshold (corresponding to the first threshold in the claims). .

  If the number of errors occurring in the data read from the block on the NAND flash memory 10 is greater than or equal to the first threshold (2 bits or more) (Yes at step S102), the data is further affected by aging or read disturb. There is a possibility that an error exceeding the correction capability of the error correction code may occur due to an increase in the number of errors. For this reason, the CPU 4 selects a block in which an error has occurred (a block in which data read from the NAND flash memory 10 is stored) as a monitoring target block and registers it in the first table 31 (step S103).

  If the number of errors occurring in the data read from the NAND flash memory 10 is less than the first threshold value (less than 2 bits) (No at step S102), the registration to the first table 31 is not performed. The process ends.

  The block registered in the first table 31 is in a state where the number of errors in the stored data is large, and there is a high possibility that the number of errors will further increase due to aging and read disturb. Therefore, the CPU 4 periodically reads out the data of the block registered in the first table 31 from the NAND flash memory 10 to check the number of errors, and monitors the increase in the number of data errors. Then, the CPU 4 performs a refresh process on the block in which the number of errors that have occurred in the stored data exceeds a specified number.

  Note that only the data requested by the host device 2 is read out while being stored in the NAND flash memory 10 when the number of errors is inspected each time data is read from the NAND flash memory 10. Unable to detect aging of data stored in block. For this reason, it is preferable to check the number of errors by reading data in the entire area of the first table of the NAND flash memory 10 at an arbitrary timing such as when the power is turned on or once every several months. As a result, it is possible to monitor the increase in the number of errors even for data stored in a block that is hardly read.

  FIG. 4 is a flowchart for explaining processing for checking whether or not the monitoring target block has already been registered in the first table 31. First, the CPU 4 confirms the contents recorded in the Nth entry (N is the entry number in the first table 31) of the first table 31 (step S111), and the block of the Nth entry is the block to be monitored. It is determined whether the same block as the monitoring target block is recorded in the first table 31 (step S112).

  When the block of the Nth entry is the same block as the monitoring target block (Yes at step S112), the CPU 4 ends the process. If the block of the Nth entry is not the same block as the monitoring target block (No at Step S112), the CPU 4 checks whether the Nth entry is the last entry (Step S113). If the Nth entry is not the last entry (No at Step S113), the process returns to Step S111 and increments the entry number by one. If the Nth entry is the last entry (Yes at step S113), the CPU 4 ends the process.

  Here, when the block newly selected as the monitoring target block is not registered in the first table 31, the monitoring target block is registered in the first table 31 as shown in the flowchart of FIG. FIG. 5 is a flowchart for explaining the process for registering the monitoring target block in the first table 31.

  First, the CPU 4 confirms the Nth entry (N is the entry number in the first table 31) in the first table 31 (step S121), and determines whether or not it is an empty entry (step S122). . If it is a vacant entry (Yes at step S122), the CPU 4 registers the monitoring target block in the vacant entry (step S126) and ends the process.

  If the Nth entry is not an empty entry (No at Step S122), the CPU 4 checks whether the Nth entry is the last entry (Step S123). If the Nth entry is not the last entry (No at step S123), the process returns to step S121 to increment the entry number by one. If the Nth entry is the last entry (Yes at step S123), the CPU 4 forcibly executes a refresh process on the block registered in the first table 31, An empty entry is created in the table 31 (step S124). Since the number of errors is reduced in the refreshed block data, the CPU 4 deletes the block from the first table 31. Then, the CPU 4 registers a new monitoring target block in the empty entry (step S125), and ends the process.

  Next, a method for monitoring the number of data errors for blocks registered in the first table 31 will be described. The number of errors is monitored by the method shown in the flowchart of FIG. 6 every time the CPU 4 sets a monitoring interval to the timer 7 in the control unit 3 and an interrupt from the timer 7 occurs. FIG. 6 is a flowchart for explaining the monitoring process of the number of errors for the block registered in the first table 31.

  First, the CPU 4 confirms an Nth entry (N is an entry number in the first table 31) in the first table 31 (step S131), and determines whether or not a block has been registered in the entry. (Step S132). If the block is not registered (No at Step S132), it is confirmed whether or not the entry is the last entry (Step S136). If it is not the last entry (No at Step S136), the process returns to Step S131 to increment the entry number by 1. If it is the last entry (Yes at step S136), the CPU 4 ends the error number monitoring process.

  Returning to step S132, if the block has been registered (Yes at step S132), the CPU 4 reads the data of the block registered in the Nth entry from the NAND flash memory 10 onto the RAM 5 in the control unit 3. . Next, the error of the data read by the error correction unit 21 is corrected, and the number of corrected errors is detected by the error number detection unit 22 and stored in the own error number detection unit 22. The CPU 4 accesses the error number detection unit 22 to acquire and check the number of errors that have occurred in the read data (step S133). Then, the CPU 4 determines whether or not the number of errors in the read data is equal to or greater than a second threshold (corresponding to the second threshold in the claims) (step S134). The second threshold value is a threshold value for the number of errors for selecting a block for which data is rewritten (refreshed) by a predetermined method. Here, for example, a 4-bit error number is used as the second threshold value. The second threshold is set in consideration of the correction capability of the error correction code.

  When the number of errors is less than the second threshold (less than 4 bits) (No at Step S134), the CPU 4 checks whether or not the Nth entry is the last entry (Step S136). If the Nth entry is not the last entry (No at step S136), the process returns to step S131 to increment the entry number by one. If the Nth entry is the last entry (Yes at step S136), the CPU 4 ends the error number monitoring process.

  Returning to step S134, if the number of errors is greater than or equal to the second threshold (4 bits or more) (Yes at step S134), the CPU 4 performs a refresh of the block registered in the Nth entry (step S135). . Then, the CPU 4 confirms whether or not the Nth entry is the last entry (step S136). If the Nth entry is not the last entry (No at step S136), the process returns to step S131 to increment the entry number by one. When the Nth entry is the last entry (Yes at Step S136), the CPU 4 ends the error number monitoring process.

  Further, in the present embodiment, the monitoring target block registered in the first table 31 is refreshed rather than the error count threshold (first threshold) for registering the monitoring target block in the first table 31. The threshold value (second threshold value) for the number of errors to be increased. This is because a block with a small number of errors is to be monitored, and a block with a large number of errors may be unable to restore data, so refreshing is performed.

  In order to perform the block refresh process, first, all the data of the block to be refreshed is read from the NAND flash memory 10 onto the RAM 5 in the control unit 3, and the block on the NAND flash memory 10 is erased. Then, after the block erase is completed, all the data saved in the RAM 5 is written to the erased block. Since the number of errors is reduced in the refreshed block data, the block is deleted from the first table 31 by the method shown in the flowchart of FIG. 7 and excluded from the monitoring target block. FIG. 7 is a flowchart for explaining the deletion processing of the refreshed block from the first table 31.

  First, the CPU 4 confirms the Nth entry (N is the entry number in the first table 31) in the first table 31 (step S141), and the registered block is a target block, that is, a block subjected to refresh processing. Whether or not (step S142). If it is not the target block (No at Step S142), it is confirmed whether or not the entry is the last entry (Step S144). If it is not the last entry (No at Step S144), the process returns to Step S141 to increment the entry number by 1. If it is the last entry (Yes at step S144), the CPU 4 ends the process.

  Returning to Step S142, if the registered block is the target block (Yes at Step S142), the CPU 4 deletes the block registered in the Nth entry from the first table 31 (Step S143), The process ends. Note that the data may be rewritten to another free block without rewriting the data to the block in which the data was originally written.

  As described above, according to the semiconductor memory device 1 according to the first embodiment, the data on the NAND flash memory 10 in which data that needs to be refreshed in the near future is stored due to the influence of secular change and read disturb. A block is selected based on the number of errors occurring in the data stored in the block, and is registered in the first table 31 as a monitoring target block for monitoring the number of data errors. Then, the block data registered in the first table 31 is periodically read to check the number of errors, and when the number of errors occurring in the data exceeds a specified number, refresh processing is executed. In this way, the number of times of refresh processing can be reduced by extending the period until the block refresh processing within the range of the correction capability of the error correction code, and the number of times of rewriting of the NAND flash memory 10 can be suppressed. As a result, it is possible to reliably prevent data damage caused by deterioration of stored data due to aging or read disturb by a small number of refresh processes, and to reduce the amount of processing and power consumption in the refresh process. Can be realized.

  Further, according to the semiconductor memory device 1 according to the first embodiment, the first table 31 is more than the threshold value (first threshold value) of the number of errors for registering the monitoring target block in the first table 31. The threshold value of the number of errors (second threshold value) for refreshing the monitoring target block registered in (1) is set large. As a result, it is possible to prevent data from being unable to be restored by performing a refresh process on a block having a large number of errors among the monitoring target blocks.

(Second Embodiment)
In the second embodiment, a case will be described in which the monitoring target block is selected based on the read amount of data stored in the block of the NAND flash memory 10 in the semiconductor memory device 1 of FIG. The second embodiment is different from the first embodiment in a method for registering a monitoring target block, and the other points are the same as those in the first embodiment.

  FIG. 8 is a diagram for explaining the configuration of the second table 32. The second table 32 is a management table that stores the amount of data read from the block on the NAND flash memory 10, and is configured on the RAM 5. The second table 32 stores a block number on the NAND flash memory 10 and a read amount of data read from the block.

  Each time the CPU 4 reads data from the block on the NAND flash memory 10, the CPU 4 counts the amount of data read by the number of pages, stores it in the second table 32, and updates it. The read amount stored in the second table 32 is the read amount after data is stored in the block on the NAND flash memory 10, and the value is cleared each time the data in the block is erased. It should be noted that an integrated amount of data and the number of times of reading can be used as the data reading amount.

  In the present embodiment, at the time of data read processing from the NAND flash memory 10 in accordance with a request from the host device 2, it is determined whether or not to monitor a block in which an error has occurred in accordance with the flow shown in FIG. FIG. 9 is a flowchart for explaining monitoring target block selection processing according to the second embodiment.

  First, when reading data from a block of the NAND flash memory 10 in accordance with a request from the host device 2, the CPU 4 updates the data read amount of the block in the second table 32 (step S151). Then, the CPU 4 checks whether or not the read amount of the updated data is greater than or equal to the third threshold (corresponding to the third threshold in the claims) (step S152). The third threshold value is a threshold value for the amount of data read from the block for selecting the block to be monitored. Here, for example, the read amount for 10 ^ 10 pages is set as the third threshold value.

  If the amount of data read from the block is greater than or equal to the third threshold value (Yes at step S152), the number of errors may increase due to aging or read disturb, and an error exceeding the correction capability of the error correction code may occur. There is. Therefore, the CPU 4 registers the block from which the data has been read out as a monitoring target block in the first table 31 (step S153). If the amount of data read from the block is less than the third threshold (No at step S152), the process ends without performing registration in the first table 31. Note that the monitoring of the number of errors in the block registered in the first table 31 is the same as that in the first embodiment, and a detailed description thereof will be omitted here.

  As described above, according to the semiconductor memory device 1 according to the second embodiment, the data on the NAND flash memory 10 in which data that needs to be refreshed in the near future is stored due to aging and read disturb. A block is selected based on the read amount of data stored in the block, and is registered in the first table 31 as a monitoring target block for monitoring the number of data errors. Then, the block data registered in the first table 31 is periodically read to check the number of errors, and when the number of errors occurring in the data exceeds a specified number, refresh processing is executed. In this way, the number of times of refresh processing can be reduced by extending the period until the block refresh processing within the range of the correction capability of the error correction code, and the number of times of rewriting of the NAND flash memory 10 can be suppressed. As a result, it is possible to reliably prevent data damage caused by deterioration of stored data due to aging or read disturb by a small number of refresh processes, and to reduce the amount of processing and power consumption in the refresh process. Can be realized.

(Third embodiment)
In the third embodiment, a case will be described in which the monitoring target block is selected based on the data write time to the block on the NAND flash memory 10 in the semiconductor memory device 1 of FIG. The third embodiment is different from the first embodiment in a method for registering a monitoring target block, and the other points are the same as those in the first embodiment.

  FIG. 10 is a diagram for explaining the configuration of the third table 33. The third table 33 is a management table that stores data write times to blocks on the NAND flash memory 10, and is configured on the RAM 5. The third table 33 stores the block number on the NAND flash memory 10 and the data write time to the block.

  When the CPU 4 writes data to the block on the NAND flash memory 10, the CPU 4 stores the write time in the third table 33. The value of the writing time stored in the third table 33 is cleared every time the block data on the NAND flash memory 10 is erased. Note that the write time stored in the third table 33 is the time between the time when the write is executed and the current time using the total erase count of the NAND flash memory 10 in addition to the operation time of the semiconductor memory device 1. We just need to know the difference.

  In the present embodiment, at the time of data read processing from the block of the NAND flash memory 10 according to the request of the host device 2, the elapsed time from the data write time to the block is measured along the flow shown in FIG. Then, the block for monitoring the number of errors is determined. FIG. 11 is a flowchart for explaining monitoring target block selection processing according to the third embodiment.

  First, when data is read from the NAND flash memory 10 in accordance with a request from the host device 2, the CPU 4 writes the last write time to the target block from which data is read and stored in the third table 33. The difference between the time and the current time, that is, the elapsed time from the write time to the block from which data is read is calculated (step S161). Then, the CPU 4 checks whether or not the elapsed time from the writing time to the block is equal to or greater than a fourth threshold (corresponding to the fourth threshold in the claims) (step S162). The fourth threshold value is a threshold value of the elapsed time from the writing time to the block for selecting the block to be monitored, and here, for example, one month is set as the fourth threshold value.

  If the elapsed time from the writing time to the block is equal to or greater than the fourth threshold (Yes at step S162), the number of errors increases due to aging or read disturb, and an error exceeding the correction capability of the error correction code occurs. there's a possibility that. Therefore, the CPU 4 registers the block from which the data has been read out as the monitoring target block in the first table 31 (step S163). If the elapsed time from the writing time to the block is less than the fourth threshold (No at step S162), the process ends without performing registration in the first table 31. Note that the monitoring of the number of errors in the block registered in the first table 31 is the same as that in the first embodiment, and a detailed description thereof will be omitted here.

  Note that only the data requested from the host device 2 is stored in the NAND flash memory 10 when the elapsed time from the write time to the block is checked every time the data is read from the NAND flash memory 10. However, it is impossible to detect a secular change of data stored in a block that is hardly read. For this reason, the data of the entire area of the first table of the NAND flash memory 10 is read at an arbitrary timing such as when the power is turned on or once every several months, and the elapsed time from the writing time to the block is confirmed. It is preferable to do. As a result, it is possible to monitor the increase in the number of errors even for data stored in a block that is hardly read.

  As described above, according to the semiconductor memory device 1 according to the third embodiment, the data on the NAND flash memory 10 in which data that needs to be refreshed in the near future due to the influence of secular change or read disturb is stored. A block is selected based on the elapsed time from the last write time to the block, and is registered in the first table 31 as a monitoring target block for monitoring the number of data errors. Then, the block data registered in the first table 31 is periodically read to check the number of errors, and when the number of errors occurring in the data exceeds a specified number, refresh processing is executed. In this way, the number of times of refresh processing can be reduced by extending the period until the block refresh processing within the range of the correction capability of the error correction code, and the number of times of rewriting of the NAND flash memory 10 can be suppressed. As a result, it is possible to reliably prevent data damage caused by deterioration of stored data due to aging or read disturb by a small number of refresh processes, and to reduce the amount of processing and power consumption in the refresh process. Can be realized.

(Fourth embodiment)
In the fourth embodiment, a case will be described in which the monitoring target block is selected based on the order of data writing to the block on the NAND flash memory 10 in the semiconductor memory device 1 of FIG. The fourth embodiment is different from the first embodiment in the method of registering the monitoring target block, and the other points are the same as those in the first embodiment.

  FIG. 12 is a diagram for explaining the configuration of the fourth table 34. The fourth table 34 is a management table that stores the order in which data is written to blocks on the NAND flash memory 10, and is configured on the RAM 5. The fourth table 34 stores a block number on the NAND flash memory 10 and a write order number on the NAND flash memory 10.

  When the CPU 4 writes data to a block on the NAND flash memory 10 in accordance with a request from the host device 2, the CPU 4 stores and updates the write sequence number on the NAND flash memory 10 in the fourth table 34. Note that the fourth table 34 is preferably realized by a link structure or the like so that the processing does not increase even when the write sequence number is updated for each write process. As a result, the processing load on the CPU 4 can be reduced and the processing time can be shortened.

  In the present embodiment, at the time of data write processing to the block of the NAND flash memory 10 according to the request of the host device 2, the block write order number to the NAND flash memory 10 is set according to the flow shown in FIG. Based on the write sequence number, the block for monitoring the number of errors is determined. FIG. 13 is a flowchart for explaining monitoring target block selection processing according to the fourth embodiment.

  First, when data is written into a block on the NAND flash memory 10 in accordance with a request from the host device 2, the CPU 4 stores and updates the write order number in the fourth table 34 (step S171). Then, the CPU 4 confirms the block corresponding to the Nth writing order number (N is the writing order number in the fourth table 34) of the fourth table 34 (step S172), and the writing order number is the fifth threshold value. (Corresponding to the fifth threshold value in the claims) The following is confirmed, that is, whether the block is older than the fifth threshold value (step S173). The fifth threshold value is a write order threshold value for selecting a block to be monitored. Here, for example, 10 blocks from the oldest (smaller) write order number are used as the fifth threshold value.

  If the write sequence number is less than or equal to the fifth threshold value, that is, the block is older than the fifth threshold value (Yes at step S173), the number of errors increases due to the influence of secular change or read disturb and exceeds the correction capability of the error correction code. May occur. Therefore, the CPU 4 determines whether or not the block has been registered in the first table 31 (step S174). If the block has not been registered in the first table 31 (No in step S174), the CPU 4 registers this block in the first table 31 as a monitoring target block (step S175). That is, the CPU 4 registers a block written in the past more than the fifth threshold as a monitoring target block in the first table 31, and sets it as an inspection target of the number of data errors.

  Returning to step S174, if the block has already been registered in the first table 31 (Yes at step S174), the CPU 4 checks whether or not the Nth write sequence number is the last write sequence number (step S176). If it is not the last writing order number (No at Step S176), the process returns to Step S172 and increments the writing order number by 1. If it is the last writing order number (Yes at step S176), the CPU 4 ends the process.

  Returning to step S173, if the write sequence number is not less than or equal to the fifth threshold value, that is, if the block is newer than the fifth threshold value (No at step S173), the CPU 4 determines that the Nth write sequence number is the last write sequence number. Whether or not (step S176). If it is not the last writing order number (No at Step S176), the process returns to Step S172 and increments the writing order number by 1. If it is the last writing order number (Yes at step S176), the CPU 4 ends the process. Note that the monitoring of the number of errors in the block registered in the first table 31 is the same as that in the first embodiment, and a detailed description thereof will be omitted here.

  As described above, according to the semiconductor memory device 1 of the fourth embodiment, the data on the NAND flash memory 10 in which data that needs to be refreshed in the near future due to the influence of secular change and read disturb is stored. A block is selected based on the order of data writing to the block on the NAND flash memory 10, and is registered in the first table 31 as a monitoring target block for monitoring the number of data errors. Then, the block data registered in the first table 31 is periodically read to check the number of errors, and when the number of errors occurring in the data exceeds a specified number, refresh processing is executed. In this way, the number of times of refresh processing can be reduced by extending the period until the block refresh processing within the range of the correction capability of the error correction code, and the number of times of rewriting of the NAND flash memory 10 can be suppressed. As a result, it is possible to reliably prevent data damage caused by deterioration of stored data due to aging or read disturb by a small number of refresh processes, and to reduce the amount of processing and power consumption in the refresh process. Can be realized.

(Fifth embodiment)
In the fifth embodiment, in the semiconductor memory device 1 of the first to fourth embodiments, a process when there is no empty entry when registering a monitoring target block in the first table 31 is performed. explain.

  FIG. 14 is a diagram for explaining the configuration of the fifth table 35. The fifth table 35 is a management table that stores the registration order of the monitoring target blocks registered in the first table 31, and is configured on the RAM 5. The fifth table 35 stores the number of the monitoring target block registered in the first table 31 and the order number (registration order number) in which the monitoring target block is registered in the first table 31.

  In registering the monitoring target block in the first table 31, the monitoring target blocks that are registered earlier are stored in ascending order of entry numbers in the first table 31. In this embodiment, the CPU 4 registers the number of the monitoring target block in the fifth table 35 every time the monitoring target block is registered in the first table 31. Further, in the fifth table 35, since the registration sequence number is updated every time the CPU 4 registers or deletes the monitoring target block in the first table 31, it is preferably realized by a link list or the like. As a result, the processing load on the CPU 4 can be reduced and the processing time can be shortened.

  Hereinafter, the registration processing of the monitoring target block in the first table 31 when there is no empty entry when registering the monitoring target block in the first table 31 will be described with reference to FIG. FIG. 15 is a flowchart for explaining the monitoring target block registration process in the first table 31 according to the fifth embodiment.

  First, during the process of registering the monitoring target block in the first table 31, the CPU 4 has the number of registered blocks registered in the fifth table 35 less than the sixth threshold (corresponding to the sixth threshold in the claims). It is confirmed whether or not there is (step S181). Here, the sixth threshold is the maximum number of blocks that can be registered in the first table 31 and the maximum number of blocks that can be registered in the fifth table 35. Therefore, the fact that the number of registered blocks registered in the fifth table 35 is less than the sixth threshold means that there is an empty entry in the first table 31 and is registered in the fifth table 35. That the number of registered blocks is not less than the sixth threshold means that there is no empty entry in the first table 31.

  When the number of registered blocks registered in the fifth table 35 is less than the sixth threshold, that is, when there is an empty entry in the first table 31 (Yes in step S181), the CPU 4 The monitoring target block is registered in the empty entry (step S184), and the number of the block is registered in the fifth table 35, and the process ends.

  When the number of registered blocks registered in the fifth table 35 is not less than the sixth threshold (when there is no empty entry in the first table 31) (No in step S181), the CPU 4 determines that the fifth table 35 , The refresh process is executed for the block with the registration order number in the fifth table 35 (step S182). That is, the refresh process is performed on the block with the earliest order of registration in the first table 31 and the fifth table 35.

  Then, the CPU 4 deletes the block on which the refresh process has been executed from the first table 31 and the fifth table 35 (step S183). Thereafter, a new monitoring target block is registered for the empty entry in the first table 31. Further, the CPU 4 updates the registration sequence number of the fifth table 35 and registers the monitoring target block registered in the empty entry of the first table 31 in the fifth table 35 (step S184).

  As described above, according to the semiconductor memory device 1 according to the fifth embodiment, when a new monitored block is registered in the first table 31 by managing the empty entries in the first table 31. Even when there is no empty entry, the monitoring target block can be registered, and the monitoring target block for monitoring the number of data errors can be managed.

(Sixth embodiment)
In the sixth embodiment, in the semiconductor memory device 1 according to the first to fifth embodiments, a block that is not subject to monitoring of the number of data errors is deleted from the first table 31. The process will be described.

  FIG. 16 is a diagram for explaining the configuration of the sixth table 36. The sixth table 36 is a management table that stores blocks on the NAND flash memory 10 in which data to be held is not stored, and is configured on the RAM 5. The sixth table 36 is composed of a plurality of entries, and among the numbers of blocks on the NAND flash memory 10, the numbers of blocks in which data to be held are not stored are registered in each entry. Access to the sixth table 36 is performed using the entry number.

  The CPU 4 acquires information on the number of the block in which the data to be held is not stored from the sixth table 36, so that new data can be written to the block, and there is no data to be held. The block number is registered in the sixth table 36. Note that the situation where there is no data to be stored mainly occurs when new data is written. For example, when the data X at the address A is recorded in the block 1 of the NAND flash memory 10, when the data X at the address A is rewritten from the host device 2 to the data Y, the address is transferred to another block (for example, the block 100). In the control method of performing the control of writing the data Y of A, the past data X of the address A stored in the block 1 is not data to be held.

  In the following, a process for deleting a monitoring target block that is not monitored for the number of data errors from the first table 31 will be described with reference to FIG. FIG. 17 is a flowchart for explaining processing for deleting an error count non-monitoring block from the first table 31 in the sixth embodiment.

  First, the CPU 4 checks the Nth entry (N is the entry number in the first table 31) of the first table 31 when a block in which data to be held no longer exists (step S191). ), It is determined whether or not the registered block is a target block (a non-monitoring target block in which data to be held no longer exists) (step S192). If it is not the target block (No at Step S192), it is confirmed whether or not the entry is the last entry (Step S193).

  If it is not the last entry (No at Step S193), the process returns to Step S191 and increments the entry number by one. If it is the last entry (Yes at step S193), the CPU 4 ends the process.

  Returning to step S192, if the block is the target block (Yes in step S192), the CPU 4 executes the deletion process of the block from the first table 31 and registers the block number in the sixth table 36. The process is terminated (step S194). Note that the block to be registered in the sixth table 36 does not store the data to be held, and therefore does not need to be refreshed.

  As described above, according to the semiconductor memory device 1 of the sixth embodiment, there is data to be held when writing new data to a block on the NAND flash memory 10 in which data is stored. When a non-monitoring target block that has disappeared occurs, the non-monitoring target block can be surely deleted from the first table 31 to manage empty entries in the first table 31.

(Seventh embodiment)
In the seventh embodiment, a method of monitoring a monitoring target block registered in the first table 31 in the semiconductor memory device 1 of the first to sixth embodiments will be described.

  FIG. 18 is a diagram for explaining the configuration of the seventh table 37. The seventh table 37 is a management table for storing the number of block errors on the NAND flash memory 10 registered in the first table 31, and is configured on the RAM 5. The seventh table 37 is composed of a plurality of entries. In each entry, the block number registered in the first table 31 and the number of errors detected in the data stored in the block are registered. Access to the seventh table 37 is performed using the entry number. The number of errors registered in the seventh table 37 is updated each time the number of errors is monitored.

  Hereinafter, a method for monitoring the number of data errors for the monitoring target block registered in the first table 31 will be described with reference to FIG. FIG. 19 is a flowchart for explaining the monitoring processing of the number of errors for the monitoring target block registered in the first table 31.

  The monitoring of the number of data errors for the monitoring target block registered in the first table 31 is performed each time the CPU 4 sets a monitoring interval to the timer 7 in the control unit 3 and an interrupt from the timer 7 occurs. The timer 7 measures time internally when the CPU 4 sets the monitoring interval time, and generates an interrupt to the CPU 4 after the set time has elapsed.

  When an interrupt from the timer 7 occurs, the CPU 4 confirms the Nth entry (N is the entry number in the seventh table 37) in the seventh table 37 (step S201), and the block has already been registered in the entry. It is determined whether or not (step S202). When the block is not registered (No at Step S202), it is confirmed whether or not the entry is the last entry (Step S206). If the Nth entry is not the last entry (No at Step S206), the process returns to Step S201 and increments the entry number by one. If the Nth entry is the last entry (Yes at Step S206), the CPU 4 ends the error number monitoring process.

  Returning to step S202, if the block has been registered (Yes at step S202), the CPU 4 checks the number of errors (number of bits) of the block registered in the seventh table 37 (step S203). It is determined whether or not the number of errors is equal to or greater than a seventh threshold (corresponding to a seventh threshold in claims) (step S204). The seventh threshold value is a threshold value for selecting a block to be subjected to error number detection processing from among the monitoring target blocks, and here, for example, a 4-bit error number is set as the seventh threshold value.

  When the number of errors is less than the seventh threshold (less than 4 bits) (No at Step S204), the CPU 4 checks whether or not the Nth entry is the last entry (Step S206). If the Nth entry is not the last entry (No at Step S206), the process returns to Step S201 and increments the entry number by one. When the Nth entry is the last entry (Yes at Step S206), the CPU 4 ends the error number monitoring process.

  Returning to step S204, if the number of errors is equal to or greater than the seventh threshold (4 bits or greater) (Yes in step S204), the CPU 4 transfers the data of the block from the NAND flash memory 10 to the RAM 5 in the control unit 3. The error number detection process of this data is executed (step S205), and the seventh table 37 is updated with the detected error number. Then, based on the number of errors detected here, the refresh process described with reference to FIG. 6 of the first embodiment is performed.

  Next, the CPU 4 checks whether or not the Nth entry is the last entry (step S206). If the Nth entry is not the last entry (No at Step S206), the process returns to Step S201 and increments the entry number by one. If the Nth entry is the last entry (Yes at Step S206), the CPU 4 ends the error number monitoring process.

  In addition, the seventh threshold value is set so that the set value is lowered every time the number of errors is detected, and the number of errors of a block with a small number of errors is gradually detected. Thereby, a block with a large number of errors can detect the number of errors every time with a short period, and a block with a small number of errors can detect the number of errors with a long period. Then, the seventh threshold value is returned to the original value again after being lowered to a predetermined specified value.

  As described above, according to the semiconductor memory device 1 according to the seventh embodiment, the monitoring target block registered in the first table 31 is updated based on the number of errors registered in the seventh table 37. Next, it is determined whether or not to detect the number of errors in the monitoring target block. A block with a large number of errors is detected with a short period, and a block with a small number of errors is detected with a long period. Thereby, based on the number of errors registered in the seventh table 37, the monitoring interval of the monitoring target block registered in the first table 31 is changed, and among the monitoring target blocks registered in the first table 31, The number of error monitoring can be reduced while reliably monitoring the number of data errors in blocks that are likely to require refresh processing in the near future. Consumption can be suppressed.

(Eighth embodiment)
In the eighth embodiment, the monitoring period of the number of errors in the seventh embodiment will be described. In the eighth embodiment, in monitoring the monitoring target block registered in the first table 31, an upper limit is set for the monitoring cycle (monitoring interval time set in the timer 7) of the block with a small number of errors.

  Here, the upper limit of the monitoring cycle is from when an error exceeding the first threshold occurs in the data stored in the block until the error of the data in the block reaches the upper limit of the error correction capability of the error correction unit 21. It is set shorter than the time. In addition, the monitoring period may be set to a time predicted in advance from various conditions such as an error occurrence state of the semiconductor memory device 1 and an environmental temperature range.

  As described above, by setting an upper limit for the monitoring period of a block with a small number of errors, the block registered in the first table 31 has a small number of errors, so that the number of errors is not monitored for a long period. Can be prevented from exceeding the error correction capability of the error correction unit 21 and failing to restore correct data.

  The functions in the first to eighth embodiments described above can be arbitrarily selected and used in any combination.

[Example]
An example where the semiconductor memory device 1 of each of the above embodiments is configured as an SSD (Solid State Drive) will be described. FIG. 20 is a block diagram showing the configuration of the SSD 100. As shown in FIG.

  The SSD 100 includes a plurality of NAND flash memories (NAND memories) 10 for data storage, a DRAM 101 for data transfer or work area, a drive control circuit 102 for controlling these, and a power supply circuit 103. The drive control circuit 102 outputs a control signal for controlling a status display LED provided outside the SSD 100.

  The SSD 100 transmits / receives data to / from a host device such as a personal computer via an ATA interface (ATA I / F). Further, the SSD 100 transmits / receives data to / from the debugging device via the RS232C interface (RS232C I / F).

  The power supply circuit 103 receives an external power supply and generates a plurality of internal power supplies using the external power supply. These internal power supplies are supplied to each unit in the SSD 100. Further, the power supply circuit 103 detects the rise or fall of the external power supply and generates a power-on reset signal. The power-on reset signal is sent to the drive control circuit 102.

  FIG. 21 is a block diagram showing a configuration of the drive control circuit 102. The drive control circuit 102 includes a data access bus 104, a first circuit control bus 105, and a second circuit control bus 106.

  A processor 107 that controls the entire drive control circuit 102 is connected to the first circuit control bus 105. A boot ROM 108 storing a boot program for each management program (FW: firmware) is connected to the first circuit control bus 105 via a ROM controller 109. The first circuit control bus 105 is connected to a clock controller 110 that receives a power-on reset signal from the power supply circuit 103 and supplies a reset signal and a clock signal to each unit.

  The second circuit control bus 106 is connected to the first circuit control bus 105. Connected to the second circuit control bus 106 are a parallel IO (PIO) circuit 111 that supplies a status display signal to the status display LED and a serial IO (SIO) circuit 112 that controls the RS232C interface.

  An ATA interface controller (ATA controller) 113, a first ECC (Error Check and Correct) circuit 114, a NAND controller 115, and a DRAM controller 119 are provided on both the data access bus 104 and the first circuit control bus 105. It is connected. The ATA controller 113 transmits and receives data to and from the host device via the ATA interface. An SRAM 120 used as a data work area is connected to the data access bus 104 via an SRAM controller 121.

  The NAND controller 115 includes a NAND I / F 118 that performs interface processing with the four NAND memories 10, a second ECC circuit 117, and a DMA controller for DMA transfer control 116 that performs access control between the NAND memory and the DRAM. .

  FIG. 22 is a block diagram showing the configuration of the processor 107. The processor 107 includes a data management unit 122, an ATA command processing unit 123, a security management unit 124, a boot loader 125, an initialization management unit 126, and a debug support unit 127.

  The data management unit 122 controls data transfer between the NAND memory and the DRAM and various functions related to the NAND chip via the NAND controller 115 and the first ECC circuit 114.

  The ATA command processing unit 123 performs data transfer processing in cooperation with the data management unit 122 via the ATA controller 113 and the DRAM controller 119. The security management unit 124 manages various types of security information in cooperation with the data management unit 122 and the ATA command processing unit 123. The boot loader 125 loads each management program (FW) from the NAND memory 10 to the SRAM 120 when the power is turned on.

  The initialization manager 126 initializes each controller / circuit in the drive control circuit 102. The debug support unit 127 processes debug data supplied from the outside via the RS232C interface.

  FIG. 23 is a perspective view showing an example of a portable computer 200 on which the SSD 100 is mounted. The portable computer 200 includes a main body 201 and a display unit 202. The display unit 202 includes a display housing 203 and a display device 204 accommodated in the display housing 203.

  The main body 201 includes a housing 205, a keyboard 206, and a touch pad 207 that is a pointing device. A housing 205 accommodates a main circuit board, an ODD unit (Optical Disk Device), a card slot, an SSD 100, and the like.

  The card slot is provided adjacent to the peripheral wall of the housing 205. An opening 208 facing the card slot is provided on the peripheral wall. The user can insert / remove an additional device into / from the card slot from the outside of the housing 205 through the opening 208.

  The SSD 100 may be used as a state of being mounted inside the portable computer 200 as a replacement for a conventional HDD, or may be used as an additional device while being inserted into a card slot included in the portable computer 200.

The semiconductor memory device 1 of each of the above embodiments is not limited to an SSD, and can be configured as a memory card represented by an SD ^TM card, for example. When the semiconductor memory device 1 is configured as a memory card, it is applicable not only to portable computers but also to various electronic devices such as mobile phones, PDAs, digital still cameras, and digital video cameras.

  DESCRIPTION OF SYMBOLS 1 Semiconductor memory device, 2 Host apparatus, 3 Control part, 4 CPU, 5 RAM, 6 Host interface (I / F), 7 Timer, 8 NAND interface (I / F), 9 Bus, 10 NAND flash memory, 21 Error correction unit, 22 Error number detection unit, 31 1st table, 32 2nd table, 33 3rd table, 34 4th table, 35 5th table, 36 6th table, 37 7th table table.

Claims (22)

A method for controlling a semiconductor memory device including a nonvolatile memory for storing data in a block which is a unit of data erasing,
A first step of selecting a monitoring target block from among the blocks, and monitoring the number of errors in data stored in the monitoring target block;
A second step of refreshing the monitored block in which the number of data errors is equal to or greater than a predetermined threshold;
A method for controlling a semiconductor memory device, comprising: The first step includes
An error correction step of correcting an error in data read from the block;
An error number detection step of detecting the number of errors in the data corrected in the error correction step;
A monitoring step in which a block in which the number of errors is equal to or greater than a predetermined first threshold is set as a monitoring target block for monitoring the number of data errors, and data in this block is read at a predetermined interval;
Including
The second step includes
Refreshing the monitored block whose number of errors is greater than or equal to a predetermined second threshold greater than the first threshold;
The method of controlling a semiconductor memory device according to claim 1. Registering the block number of the monitored block in the first table;
In the monitoring step, referring to the first table, detecting and monitoring the number of errors in the data of the monitoring target block;
The method of controlling a semiconductor memory device according to claim 2. Erasing the number of the monitored block that has been refreshed from the first table;
The method of controlling a semiconductor memory device according to claim 3. The first step includes
An error correction step of correcting an error in data read from the block;
An error number detection step of detecting the number of errors in the data corrected in the error correction step;
A data read amount detection step of detecting a read amount of data read from the block;
A monitoring step in which a block whose data read amount is equal to or larger than a predetermined third threshold is set as a monitoring target block for monitoring the number of data errors, and the data of this block is read at a predetermined interval;
Including
The second step includes
Refreshing the monitored block whose error count is greater than or equal to a predetermined second threshold;
The method of controlling a semiconductor memory device according to claim 1. Registering the block number of the monitored block in the first table;
In the monitoring step, referring to the first table, detecting and monitoring the number of errors in the data of the monitoring target block;
The method of controlling a semiconductor memory device according to claim 5. Erasing the number of the monitored block that has been refreshed from the first table;
The method of controlling a semiconductor memory device according to claim 6. Registering the read amount of the data in a second table;
In the monitoring step, referring to the second table, registering the block as the monitoring target block in the first table;
The method of controlling a semiconductor memory device according to claim 6. The first step includes
An error correction step of correcting an error in data read from the block;
An error number detection step of detecting the number of errors in the data corrected in the error correction step;
A write time detection step for detecting an elapsed time since data was written to the block;
A monitoring step of setting a block whose elapsed time is equal to or greater than a predetermined fourth threshold as a monitoring target block for monitoring the number of data errors, and reading data of the block at a predetermined interval;
Including
The second step includes
Refreshing the monitored block whose error count is greater than or equal to a predetermined second threshold;
The method of controlling a semiconductor memory device according to claim 1. Registering the block number of the monitored block in the first table;
In the monitoring step, referring to the first table, detecting and monitoring the number of errors in the data of the monitoring target block;
The method of controlling a semiconductor memory device according to claim 9. Erasing the number of the monitored block that has been refreshed from the first table;
The method of controlling a semiconductor memory device according to claim 10. Registering the time of writing data to the block in a third table;
In the monitoring step, referring to the third table, obtaining the elapsed time and registering the block as the monitoring target block in the first table;
The method of controlling a semiconductor memory device according to claim 10. The first step includes
An error correction step of correcting an error in data read from the block;
An error number detection step of detecting the number of errors in the data corrected by the error correction means;
A writing order detection step of detecting a writing order in which data is written to the block on the nonvolatile memory;
A monitoring step in which a block whose write order is equal to or less than a predetermined fifth threshold is a monitoring target block for monitoring the number of data errors, and data in this block is read at a predetermined interval;
Including
The second step includes
Refreshing the monitored block whose error count is greater than or equal to a predetermined second threshold;
The method of controlling a semiconductor memory device according to claim 1. Registering the block number of the monitored block in the first table;
In the monitoring step, referring to the first table, detecting and monitoring the number of errors in the data of the monitoring target block;
The method of controlling a semiconductor memory device according to claim 13. Erasing the number of the monitored block that has been refreshed from the first table;
The method of controlling a semiconductor memory device according to claim 14. Registering the writing order in a fourth table;
In the monitoring step, referring to the fourth table, registering the block as the monitoring target block in the first table;
The method of controlling a semiconductor memory device according to claim 14. Registering the monitoring target block registration order in the first table in a fifth table;
In the refresh step, when the number of registered monitoring target blocks in the fifth table reaches a predetermined sixth threshold, the monitoring target blocks in the registration order determined in advance in the fifth table are stored. Doing a refresh,
The method of controlling a semiconductor memory device according to claim 3. In the refresh step, refreshing from the monitoring target block with the oldest registration order among the monitoring target blocks,
The method of controlling a semiconductor memory device according to claim 17. Registering the number of the block in which data to be held is not stored in a sixth table;
In the monitoring step, deleting the block number registered in the sixth table from the first table;
The method of controlling a semiconductor memory device according to claim 3. Registering in the seventh table the number of the monitored block registered in the first table and the number of errors detected in the data stored in the monitored block;
In the monitoring step, based on the number of errors registered in the seventh table, changing the predetermined interval for the monitoring target block registered in the first table;
The method of controlling a semiconductor memory device according to claim 3. In the monitoring step, among the monitoring target blocks registered in the seventh table, the monitoring target block having a large number of errors is made shorter than the monitoring target block having a small number of errors,
The method of controlling a semiconductor memory device according to claim 20. The predetermined interval is the upper limit of the error correction capability of the error correction means after the error exceeding the first threshold has occurred in the data stored in the monitoring target block. Shorter than the time to reach
The method of controlling a semiconductor memory device according to claim 21.

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