JP2010160765A - System lsi and debugging method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a system LSI excellent in security function, and to obtain a debugging method thereof. <P>SOLUTION: The system LSI 10 is provided with: a main processor 11 having an operation control function; a sub-processor 13 and an IC card I/F circuit 13a having an authentication function using an IC card 20 having operation and control functions; a JTAG (Joint Test Action Group) connection control circuit 14 to be controlled by the sub-processor 13; an on-chip JTAG interface circuit 15 having an interface function of serial communication to a debugger 30; and the like. After the sub-processor 13 is started and performs authentication, the main processor 11 is started, and debugging of the system LSI is performed via the on-chip JTAG interface circuit 15 by the debugger 30. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an on-chip JTAG (Joint Test Action Group) interface circuit for realizing on-chip debugging, and a system LSI (Large) having a security function for preventing unauthorized acquisition of the behavior of an internal circuit using the JTAG interface circuit. In particular, the present invention relates to a technique for performing authentication using an IC (Integrated Circuit) card and controlling connection of an on-chip JTAG interface circuit in the system LSI.

  In recent years, system LSIs with higher security have been demanded in various fields such as electronic commerce. A system LSI is a microcontroller that forms the core of an embedded system product. In particular, the behavior of the internal circuit of the system LSI is analyzed using reverse analysis (reverse engineering), and may be abused for an unintended use by a developer of a device using the system LSI. For this reason, it is required not to abuse the analysis function of the system LSI.

  Technologies relating to such a system LSI having a security function are disclosed in, for example, the following Patent Documents 1 to 4.

  Patent Document 1 discloses that a JTAG interface circuit is invalidated by enabling the JTAG interface circuit during development and disconnecting the JTAG interface circuit by physical means such as an electronic fuse during operation. Thus, a technique for preventing a reverse analysis of an unauthorized third party is disclosed.

  Patent Document 2 discloses an IC card for authentication regarding a program of a microcomputer (hereinafter referred to as “microcomputer”) having a central processing unit (hereinafter referred to as “CPU”) and a change in contents of a memory storing the program. It is disclosed that the program in the memory is changed when the IC card is authenticated by using.

  In Patent Document 3, the SD memory card is provided with identification information so that the information in the microcomputer is not analyzed or falsified, and the program in the microcomputer is debugged when the identification information is authenticated by the read / write device. It is disclosed. Debugging is to find and fix bugs in a program by operating a microcomputer or the like connected to the debugger using the internal program and data, and this debugging tool (that is, a program that supports debugging) ) Is the debugger.

Japanese Patent No. 3760087

JP 2002-24046 A

JP 2007-72957 A

JP 2004-94451 A

  However, for example, the conventional techniques disclosed in Patent Documents 1 to 3 have the following problems (a) to (c).

(A) Patent Document 1
In the technique of Patent Document 1, the JTAG interface circuit is physically disabled during operation so that an unauthorized third party cannot analyze the system LSI. However, even when a legitimate user needs to analyze a system LSI due to a field bug or the like, it cannot be analyzed. Therefore, as an alternative method, analysis is performed using a development system LSI, but analysis is difficult due to differences from the operating environment. Further, the developer of the system LSI needs to prepare two types of physically different system LSIs, which causes a cost increase.

(B) Patent Document 2
The technique of Patent Document 2 changes a program or the like when the IC card is authenticated using the IC card. However, this technology authenticates the IC card in order to perform an action such as further upgrading the completed microcomputer product, and after this authentication, it receives data from an external device connected to the microcomputer, The contents are to be changed. Therefore, using this technique, it is impossible to debug a program for confirmation or the like before the microcomputer product is completed.

(C) Patent Document 3
In the technique of Patent Document 3, authentication is performed by the read / write device using identification information given to the SD memory card, and the authentication result is notified to the microcomputer, so that the program in the microcomputer is debugged. It is not configured to perform on-chip debugging with the approval in the microcomputer, but the authenticated data sent and received from the read / write device to the microcomputer is analyzed, and the debugging information is also analyzed based on the analysis result Probability is high.

  Therefore, it has been difficult to realize a system LSI and an on-chip debugging which is sufficiently technically satisfactory and has an excellent security function and this debugging method.

  The present invention solves such a conventional problem and makes the debug authentication technology with excellent security function using IC card authentication and the system LSI having the JTAG interface means physically the same at the time of development and operation. An object of the present invention is to realize a system LSI capable of providing a debugging function to a legitimate user while preventing analysis by an unauthorized third party, and this debugging method.

  The system LSI of the present invention includes an authentication unit using an IC card having a calculation and control function, a JTAG interface unit having an interface function of serial communication with an external debug unit, and the debug after receiving authentication by the authentication unit Control means for controlling connection of the JTAG interface means to the means.

  The system LSI debugging method of the present invention has a main processor having an arithmetic control function, a sub-processor having an authentication function using an IC card having an arithmetic and control function, and an interface function for serial communication with an external debugging means. A debugging method for a system LSI, comprising: a JTAG interface unit, wherein the main processor is started after the sub-processor is started and authenticated, and the debugging unit causes the debugging to be performed via the JTAG interface unit. The system LSI is debugged.

  According to the system LSI and the debugging method of the present invention, the authentication using the IC card is performed, and then the JTAG interface is enabled for debugging, so that the system LSI with excellent security function and the debugging method are realized. it can. As a result, the system LSI having the JTAG interface means is physically the same at the time of development and at the time of operation, and a debugging function can be provided to a legitimate user while preventing unauthorized third party analysis.

1 is a schematic configuration diagram illustrating a system LSI and an external device according to a first embodiment of the present invention. 2 is a flowchart showing an operation of an authentication process in the system LSI of FIG. It is a figure which shows the sequence operation | movement of terminal authentication step ST1 in FIG. It is a figure which shows the sequence operation | movement of card | curd authentication step ST3 in FIG. It is a figure which shows the sequence operation | movement of operation mode authentication step ST5 in FIG.

  Modes for carrying out the present invention will become apparent from the following description of the preferred embodiments when read in light of the accompanying drawings. However, the drawings are only for explanation and do not limit the scope of the present invention.

(Configuration of Example 1)
FIG. 1 is a schematic configuration diagram showing a system LSI and an external device according to the first embodiment of the present invention.

  The system LSI 10 according to the first embodiment is an integrated circuit having a security function using IC card authentication, and includes a main processor 11 having a calculation control function configured by a microcomputer, an authentication key memory 12 such as a flash memory, and the like. A sub processor 13 having an IC card interface circuit (hereinafter referred to as an “IC card I / F circuit”) 13a, which is an IC card interface means, and having an arithmetic function constituted by a microcomputer or the like, and is controlled by the sub processor 13 Control means (for example, JTAG connection control circuit) 14, JTAG interface means (for example, on-chip JTAG interface circuit) 15 controlled by the JTAG connection control circuit 14, etc. It is connected. The sub processor 13 and the IC card I / F circuit 13a constitute authentication means.

  For example, the main processor 11 is configured such that the sub processor 13 operates before the main processor 11 operates, and the main processor 11 does not operate until the authentication process is completed. The sub-processor 13 controls the authentication process, and has an authentication function based on a challenge and response method conforming to the ISO 7816-4 standard, which is one of methods used for password authentication, for example. Communication with the IC card 20 incorporating a CPU, memory, and the like is based on, for example, the ISO 7816-3 standard, and is configured to communicate with the IC card 20 through the IC card I / F circuit 13a. Further, the sub-processor 13 permits JTAG connection to the JTAG connection control circuit 14 when regular authentication is performed in the authentication process. In the case of unauthorized authentication, the sub-processor 13 sends JTAG to the JTAG connection control circuit 14. Has a function that does not allow connection.

  The main processor challenge-and-response method is a method in which authentication is performed by receiving an encryption key (challenge) sent from a server and returning data (response) combined with arithmetic processing. In this method, first, a server (eg, system LSI 10) sends a value called “challenge” to a client (eg, IC card 20). The client that has received the challenge performs a calculation process by multiplying the challenge value by the password (for example, a common key), and the hash value (for example, ciphertext) generated by the calculation process is “response”. ". The server compares the hash value returned from the client with the response generated by the server itself, and passes authentication if the two response values match. The advantage of the challenge and response method is that the value sent as a challenge is changed with a random value each time, and the value of the generated response is different every time, so if a challenge or response is illegally acquired by a third party However, there is no fatal problem in authentication.

  Main Processor In the first embodiment, for example, the system LSI 10 and the IC card 20 hold two shared keys Ka and Km for authentication by a challenge and response method. Furthermore, the serial number SDB of the accessible IC card 20 is stored in the authentication key memory 12 of the system LSI 10 in advance in a secure environment, and the IC card 20 has a data area in the internal memory. Holds a unique serial number Sn and a shared key Kb. In other words, the authentication key memory 12 on the system LSI 10 side stores two shared keys Ka and Km and the serial number SDB of the accessible IC card 20 as a database. Shared keys Ka, Kb, Km and a unique serial number Sn are held.

  For example, if the JTAG connection control circuit 14 permits the main processor on-chip JTAG interface circuit 15 to connect to the debug means (for example, a debugger) 30 after authentication, the main processor on-chip JTAG interface circuit 15 performs serial communication conforming to the IEEE1149.1 standard to the debugger 30. The function to perform between. The debugger 30 has a function of operating the main processor 11 via the on-chip JTAG interface circuit 15 and debugging the program.

Main processor (debugging method of the first embodiment)
In the debugging method in the system LSI 10 of the first embodiment, the following authentication process (authentication process operation (1), terminal authentication sequence (2), card authentication sequence (3), operation mode sequence (4)) was executed. Thereafter, program debugging processing (5) by the debugger 30 is performed.

Main Processor (1) Authentication Process Operation FIG. 2 is a flowchart showing the operation of the authentication process in the system LSI 10 of FIG.

  The authentication process in the main processor system LSI 10 is performed in accordance with the authentication program stored in the system LSI 10 according to the operation of the sub processor 13 according to the following three steps [terminal authentication (step ST1), card authentication (step ST3), operation mode authentication. (Step ST5)] is authenticated.

  When the operation is started (START), the sub processor 13 starts up, performs terminal authentication for confirming the authenticity of the system LSI 10 (step ST1), determines whether or not the terminal is authenticated (step ST2), and authenticates. If not (NG), it is determined that the authentication is unauthorized (step S8), and the authentication operation is terminated (END).

  First, if terminal authentication is performed in step S1 (OK), the sub-processor 13 next performs card authentication for confirming the authenticity of the IC card 20 (step ST3), and determines whether or not the card is authenticated. If it is not authenticated (NG), it is determined that the authentication is unauthorized, and the authentication operation is terminated (step ST8).

  If the card is authenticated in step S4, the sub-processor 13 performs the last operation mode authentication (step ST5), determines whether the operation mode is authenticated (step ST6), and if not authenticated (NG), It is determined that the authentication is successful, and the authentication operation is terminated (step ST8).

  If the operation mode authentication is regular authentication in step ST6 (OK), the sub processor 13 determines that the JTAG connection is valid (step ST7), permits the JTAG connection to the JTAG connection control circuit 14, and performs the authentication operation. finish. Since the sub processor 13 performs other operations during the actual operation of the authentication process, the sub processor 13 does not enter a dormant state after the authentication is completed.

  Thereafter, the chip-on JTAG interface circuit 15 is turned on by the JTAG connection control circuit 14 and debugging by the debugger 30 is performed.

(2) Terminal Authentication Sequence FIG. 3 is a diagram showing a sequence operation of terminal authentication step ST1 in FIG.

  In terminal authentication, the authentication key memory 12 in the system LSI 10 and the IC card 20 hold the shared key Ka, and for example, authentication is performed by a challenge and response method conforming to the ISO 7816-4 standard.

  First, the sub processor 13 in the system LSI 10 uses the IC card I / F circuit 13a, for example, the challenge S1 of the acquisition challenge command (GET CHALLENGE command) to the IC card 20 by serial communication conforming to the ISO7816-3 standard. Send.

  Upon receiving the challenge S1, the IC card 20 generates a random number Ra by the random number generation process ST1-21, and sends a response (Res (Ra)) S2 of the random number Ra as a response to the received challenge S1 in the system LSI 10. It returns to the sub processor 13 through the IC card I / F circuit 13a. The IC card 20 encrypts the generated random number Ra using the encryption algorithm F with the shared key Ka through the ciphertext generation process ST1-22, and generates a ciphertext Rac.

  The sub processor 13 in the system LSI 10 generates a ciphertext Ral by encrypting the random number Ra of the received response S2 using the encryption algorithm F with the shared key Ka by the ciphertext generation processing ST1-11. An external recognition command (EXTERNAL AUTHENTICATE command) challenge (EXTERNAL AUTHENTICATE (Ral)) S2 is sent to the IC card 20.

  The IC card 20 compares the ciphertext Ral of the received challenge S3 with the ciphertext Rac generated by the ciphertext generation means 22 by the comparison process ST1-23, and if the comparison result matches, it is OK or does not match. NG is returned to the sub processor 13 in the system LSI 10 as a response (Res (OK / NG)) S4.

  If the terminal authentication of the received response S4 is OK, the sub processor 13 in the system LSI 10 proceeds to the following card authentication.

(3) Card Authentication Sequence FIG. 4 is a diagram showing a sequence operation of the card authentication step ST3 in FIG.

  The sub-processor 13 in the system LSI 10 sends a read command (READ RECORD command) challenge S11 to the IC card 20, and receives the serial number Sn (for example, 0001) written in a specific area of the memory in the IC card 20. This is read and received in the form of a response (Res (Sn)) S12 from the IC card 20. In the system LSI 10, the serial number SDB of the permitted IC card 20 is registered in the authentication key memory 12 in an environment in which security is ensured in advance. The sub processor 13 compares the serial number Sn read from the IC card 20 with the serial number SDB of the IC card 20 registered in the database in the recognition key memory 12 through the comparison process ST3-11.

  If the read serial number Sn is the same as the serial number SDB registered in the database (OK) in the card authentication key generation process ST3-12, the sub processor 13 generates a card authentication key. In the generation of the card authentication key, the received serial number Sn is decrypted with the shared key Ka using the encryption algorithm F, and the shared key Kb composed of the decrypted text is generated. Further, the sub-processor 13 generates a random number Rb through a random number generation process ST3-13, and transmits this random number Rb to the IC card 20 by an internal recognition command (INTERNAL AUTHENTICATE command) challenge S13. At the same time, the sub processor 13 generates a ciphertext Rbl by encrypting the random number Rb with the generated shared key Kb by ciphertext generation processing ST3-14.

  The IC card 20 generates a ciphertext Rbc by encrypting the random number Rb of the challenge S13 received from the sub-processor 13 with the shared key Kb held by the ciphertext generation process ST3-21, and generates the ciphertext Rbc. A response (Res (Rbc)) S14 is returned to the sub processor 13 in the system LSI 10.

  The sub-processor 13 in the system LSI 10 compares the received ciphertext Rbc with the generated ciphertext Rbl through the comparison process ST3-15, and proceeds to the following operation mode authentication if they match.

Details of the card authentication key generation process ST3-12 will be described below.
The generation of the card authentication key (shared key Kb) of the system LSI 10 uses a serial number Sn (for example, 0001) unique to the IC card in consideration of ease of management. The serial number Sn is a value encrypted by using the encryption algorithm F with the shared key Ka.

  The card authentication key Kb is generally generated using a random number. For this reason, when registering the authorized IC card 20 key in the system LSI 10, it is necessary to register all the card authentication keys to be registered. Moreover, it is necessary to manage that the key already used is not registered, but it is difficult to manage because the key is a random number.

  If the serial number Sn is unique to the IC card, it is not necessary to register all of them because they are consecutive numbers. For example, it is possible to reduce the number of registrations by registering only the maximum value and the minimum value of the serial number Sn to be registered and allowing the consecutive numbers.

  Here, regarding the generation of the IC card authentication key (Kb) based on the serial number Sn unique to the IC card, there is a concern that there is a security problem with the analysis of an unauthorized third party. However, an unauthorized third party must first know that the card authentication key (Kb) has been generated based on the serial number Sn. 2) Since the card authentication (step ST3) in FIG. 2 is not performed after that, it seems difficult to generate a forged card, and it is necessary to specify the encryption algorithm F being used. Assuming that the encryption algorithm F can be specified, only the ciphertext Rbl can be obtained, and specifying the key (Kb) from only the ciphertext Rb1 can be performed using an encryption algorithm that is generally said to be secure. For example, it is said that it is difficult to specify a key within a realistic time range, and there is no security problem.

(4) Operation Mode Sequence FIG. 5 is a diagram showing a sequence operation of the operation mode authentication step ST5 in FIG.

  In the operation mode authentication, first, the sub processor 13 in the system LSI 10 generates a random number Rc by the random number generation processing ST5-11, and at the challenge (INTERNAL AUTHENTICATE (Rc)) S21 of the internal recognition command (INTERNAL AUTHENTICATE command), The random number Rc is transmitted to the IC card 20. At the same time, the sub processor 13 encrypts the generated random number Rc with the shared key Km held by the ciphertext generation process ST5-12 to generate a ciphertext Rcl.

  The IC card 20 generates a ciphertext Rcc by encrypting the random number Rc of the challenge S21 received from the system LSI 10 with the shared key Km held by the ciphertext generation process ST5-21, and as a response to the challenge S21 The response S22 of the ciphertext Rcc is returned to the sub processor 13 in the system LSI 10.

  The sub processor 13 in the system LSI compares the ciphertext Rcc of the received response S22 with the generated ciphertext Rcl through the comparison process ST5-13. If the comparison results match, the JTAG connection control circuit 14 validates the JTAG connection as the JTAG connectable mode, and proceeds to the debugging process described below. If the comparison result does not match, the JTAG connection is not validated as an unauthorized authentication.

(5) Debugging processing The chip-on JTAG interface circuit 15 is turned on by the JTAG connection control circuit 14, the main processor 11 is activated, the main processor 11 is operated by a test program input from the debugger 30, and the system LSI 10 Debugging is done.

(Effect of Example 1)
According to the first embodiment, there are the following effects (a) to (d).
(A) Since the JTAG connection is validated after mutual authentication between the system LSI 10 and the IC card 20 by terminal authentication and card authentication, safety can be ensured. As a result, it is possible to permit connection between the on-chip JTAG interface circuit 15 and the debug 30 in the system LSI 10 in an environment authenticated by a secure method using the IC card 20. Therefore, it is possible to realize an excellent debugging method of the security function using the IC card authentication. This makes it possible to make the system LSI having the on-chip JTAG interface circuit physically the same at the time of development and at the time of operation. It is possible to provide a debugging function to a legitimate user while preventing an analysis by a user.

  (B) Since the encrypted serial number (Sn) unique to the IC card is used as the card authentication key (Kb) of the system LSI 10, the amount of data for the card authentication key registered in the system LSI 10 can be reduced, and the card authentication key Easy management of registration.

  (C) After the sub-processor 13 starts up and performs authentication, the main processor 11 is activated and debugging is performed. At this time, since the sub processor 13 performs other operations even during the actual operation of the main processor 11, the sub processor 13 is not put into a sleep state when the authentication operation is finished, and the operation state is maintained. By providing such a sub-processor 13, it becomes possible to share processing during the actual operation of the main processor 11, and the operation of the system LSI 10 can be performed at high speed and stably.

  (D) Regarding (c), Patent Document 4 discloses an example in which two processors, a host processor and a dedicated processor, are mounted in a system LSI having an on-chip JTAG interface circuit. The authentication is not described, and the operation associated therewith is not disclosed at all. On the other hand, in the first embodiment, authentication is performed by a secure method using the IC card 20, and the sub processor 13 and the main processor 11 are skillfully used, so that the above-described remarkable effects can be obtained. It is what you play.

(Modification)
The present invention is not limited to the first embodiment, and various usage forms and modifications are possible. For example, the following forms (i) to (iv) are used as the usage form and the modification examples.

  (I) The system LSI 10 is not limited to the configuration and functions shown in FIG. 1, but can be changed to other configurations and functions, or other circuits and functions can be added.

  (Ii) In the above (i), for example, the sub-processor 13 does not need to be configured by a microcomputer, can at least identify that it has been authenticated by the IC card 20, and trigger this identification as a trigger in the on-chip JTAG interface circuit. As long as the signal can be given to the main processor 11 so as to be connected, an alternative is possible even if it does not have an arithmetic function such as a microcomputer. However, in the case of substitution, the effect of sharing the processing with the main processor 11 during actual operation, such as the effect (c) of the first embodiment, cannot be obtained.

  (Iii) In (i), for example, the sub processor 13 may be omitted, and the main processor 11 may have the function of the sub processor 13. Even with this configuration, the effects (a) and (b) of the first embodiment can be obtained.

  (Iv) The authentication method using the IC card 20 in the first embodiment can be changed to another processing procedure. For example, in the first embodiment, JTAG permission is determined by authentication after the operation mode authentication and only two operation modes are set. However, a plurality of operation modes may be determined by the operation mode. It is also possible to make a determination using, for example, the result of IC card authentication before operation mode authentication.

10 System LSI
DESCRIPTION OF SYMBOLS 11 Main processor 12 Authentication key memory 13 Sub processor 13a IC card I / F circuit 14 JTAG connection control circuit 15 On-chip JTAG interface circuit 20 IC card 30 Debugger

Claims (12)

An authentication means using an IC card having a calculation and control function;
JTAG interface means having an interface function of serial communication with external debugging means;
Control means for controlling connection of the JTAG interface means to the debug means after receiving authentication by the authentication means;
A system LSI characterized by comprising: The authentication means includes
IC card interface means having an interface function of communication with the IC card;
An arithmetic control function for program-controlling the entire system LSI, and a processor having an authentication function using the IC card via the IC card interface means;
The system LSI according to claim 1, comprising: The processor is
A main processor having the arithmetic control function;
A sub-processor having the authentication function;
The system LSI according to claim 2, comprising: The sub-processor is
4. The system LSI according to claim 3, further comprising an arithmetic function. The sub-processor is
4. The system LSI according to claim 3, wherein the system LSI has a function of identifying the authentication by the IC card and giving a signal to the main processor to connect to the JTAG interface means using the identification as a trigger. The authentication function is:
6. The mutual authentication between the system LSI and the IC card is performed by terminal authentication for confirming authenticity of the system LSI and card authentication for confirming authenticity of the IC card. The system LSI according to any one of the above.   The system LSI according to claim 1, wherein the authentication is performed using a card authentication key obtained by encrypting a serial number of the IC card. The TAG interface means includes:
The system LSI according to claim 1, wherein the system LSI is an on-chip JTAG interface circuit. A main processor having an arithmetic control function;
A sub-processor having an authentication function using an IC card having a calculation and control function;
JTAG interface means having an interface function of serial communication with external debugging means;
A system LSI debugging method comprising:
A method of debugging a system LSI, wherein the main processor is activated after the sub-processor is started and authenticated, and the debugging unit debugs the system LSI via the JTAG interface unit. In the authentication,
10. The mutual authentication between the system LSI and the IC card is performed by terminal authentication for confirming authenticity of the system LSI and card authentication for confirming authenticity of the IC card. System LSI debugging method.   11. The system LSI debugging method according to claim 9, wherein the authentication is performed using a card authentication key obtained by encrypting a serial number of the IC card. The system LSI and the IC card hold a common key,
The system LSI debugging method according to claim 9, wherein the authentication is performed by a challenge and response method using the common key.

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