JP2010152029A - Semiconductor device and patterning process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve such a problem wherein a phenomenon in which a fine pattern adjacent to a wide pattern is collapsed when an L&S pattern approaches the resolution limit is observed. <P>SOLUTION: Considering that contrast in light intensity of the fine pattern adjacent to the wide pattern is decreased, a pattern processing which reduces a decrease of the contrast in light intensity for the fine pattern is performed to obtain a semiconductor device. Specifically, the fine pattern is separated from the wide pattern, or the wide pattern is formed which is associated with the fine pattern. Further, such a pattern as to reduce the bright area of the pattern between the fine pattern and the wide pattern may be disposed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device such as a DRAM and a pattern forming method in the semiconductor device.

  Advances in semiconductor device manufacturing technology, especially in the field of microfabrication technology, are remarkable, and devices with line widths around 50 nm are being mass-produced in DRAM products.

  One of the leading technologies for miniaturization is L & S pattern transfer technology in which fine line patterns with line widths close to the resolution limit are arranged. However, as the line width becomes finer, the resist shape deteriorates significantly. Collapse and pattern defects in the etching process are serious problems.

  There is a technique described in Patent Document 1 as a countermeasure technique against pattern collapse related to a fine L & S pattern.

  Patent Document 1 discloses a technique for connecting an end of a dummy pattern and another dummy pattern with a shared dummy pattern in order to prevent pattern collapse at the end of the L & S dummy pattern inserted for pattern transfer of the fine L & S pattern. Has been.

JP 2006-235080 A

  However, as miniaturization progresses, the problem of pattern collapse at other parts of the line pattern rather than pattern collapse at the end of the line pattern has become more prominent. For example, when a wide pattern is close to a fine line pattern, it has often been confirmed that pattern collapse occurs in a portion facing the wide pattern rather than the tip portion of the line pattern.

  Such pattern collapse has a problem that a manufacturing process margin such as a focus margin in a lithography process is narrowed. In this way, the pattern arrangement associated with the L & S pattern itself rather than the fine L & S pattern itself, in particular, the wide pattern having a width wider than the line width of the L & S (line and space) pattern that is close to the resolution limit although it is fine. The layout and the pattern layout around the pattern have become a problem that affects the manufacturing process margin.

  According to the experiments by the present inventors, for example, as shown in FIG. 7, for a pattern in which a fine line pattern sandwiched between wide patterns exists, an OPC process is performed using a general technique, and exposure is performed. After optimizing the mask pattern so as to have a desired pattern size after that and performing a lithography simulation for the purpose of evaluating the manufacturing margin, a result as shown in FIG. 8 was obtained. In other words, the result was that the fine line pattern sandwiched between the wide patterns was thinned.

  In this case, the line width and interval of the fine line pattern in the L & S pattern area is 50 nm, and the simulation conditions are annular illumination, a half-tone mask with a polygon transmittance of 6% and a phase inversion of 180 degrees The light wavelength is 193 nm ArF. In lithography simulation, an image of a wafer is represented by a light intensity distribution, and contour lines defined by a certain threshold are used as shapes after lithography.

  In order to find a pattern that is likely to fall, FIG. 8 shows a simulation in which a threshold value is set in a state where the exposure amount is increased. When the pattern was actually transferred, the line pattern collapsed at the portion between the wide patterns.

  According to the study by the present inventors, when using a pattern that is close to the resolution limit, in particular, a condition for stably transferring an L & S pattern, in a region that is closely opposed to a wide pattern to a fine line pattern. Etching process caused by pattern collapse or insufficient resist residual film thickness due to significantly reduced light intensity contrast in the vicinity of line patterns where wide patterns are close to each other compared to the L & S pattern area It was found that pattern defects occurred in

  This problem has been manifested in the manufacturing process of chips having an L & S pattern with a line width of 60 nm or less, such as ArF immersion exposure, and with a line width exceeding 60 nm, there was almost no problem.

  According to the present invention, it is possible to obtain a semiconductor device that has been subjected to a process for maintaining the light intensity contrast in connection with or close to a pattern in which a decrease in light intensity contrast is predicted, in particular, a line pattern.

  Specifically, according to the first aspect of the present invention, there is provided a semiconductor device having an L & S (line and space) pattern in which a plurality of line patterns having a width L are arranged at a predetermined pitch. A first line pattern having a width L that is closely opposed to the first wide pattern having a wide width, and at least one end of the first line pattern is adjacent to a direction in which the first line pattern extends; A semiconductor device is obtained which is connected to a second wide pattern having a width wider than the arranged width L.

  According to the second aspect of the present invention, there is provided a semiconductor device having an L & S pattern in which a plurality of line patterns having a width L are arranged at a predetermined pitch, the first wide pattern having a width wider than the width L; A pattern having a first line pattern having a width L that is adjacently opposed and arranged so as to narrow a pattern bright portion region to which a first wide pattern and a pattern bright portion that separates the first line pattern are connected. Thus, a semiconductor device having the following characteristics can be obtained.

  According to the third aspect of the present invention, there is provided a semiconductor device having an L & S pattern in which a plurality of line patterns having a width L are arranged at a predetermined pitch P1, and having a width wider than L in the vicinity of the L & S pattern. Thus, the semiconductor device is obtained in which n is not 2 when P2 = nP1.

  In the present invention, since the pattern processing for maintaining the light intensity contrast in the L & S pattern is performed, the light intensity contrast can be prevented from being lowered, and the fine line pattern sandwiched between wide patterns can be prevented from collapsing. it can.

(First embodiment)
When the pattern shown in FIG. 1 is used for the pattern illustrated in FIG. 7, the manufacturing process margin can be remarkably improved. Actually, DOF = 0 nm improved to DOF = 150 nm.

  FIG. 1 is an enlarged view of an end portion of a memory cell array of a DRAM chip and shows a gate electrode pattern constituting a word line. L & S pattern regions arranged with a line width of 50 nm and an interval of 50 nm are arranged in the memory cell array region. In addition, a pattern having a width of 150 nm for connecting to another metal wiring layer, that is, a pattern wider than the line width of 50 nm is arranged at a pitch of 300 nm in a region adjacent to the memory cell array region. The pitch of the wide pattern is three times as large as the pitch of the L & S pattern region of 100 nm. That is, in the example shown in FIG. 4, the end portions of the line pattern arranged at a pitch of 100 nm are not arranged in the portion sandwiched between the wide patterns, as is apparent from the comparison with FIG. That is, a narrow line pattern that does not have a wide pattern is configured to be shorter than a line pattern that has a wide pattern. In this way, by performing the avoidance process such that the fine pattern adjacent to the wide pattern in which the decrease in the light intensity contrast is predicted is kept away from the wide pattern, the decrease in the light intensity contrast in the fine pattern can be reduced. .

  When transferring the above pattern onto a silicon substrate, annular illumination, ArF immersion, which is advantageous for fine L & S patterns, was used. As the resist, a multilayer resist including an acrylic resist is used, and a coating layer corresponding to liquid immersion is used for the top.

  When a wide pattern and a fine pattern are mixed in the vicinity of a fine L & S pattern, the light intensity contrast in the vicinity of the fine pattern is reduced, so that the wide pattern is also a repeated pattern to avoid mixing with the fine pattern. A sufficient manufacturing process margin can be ensured. Since the repetitive L & S pattern generates diffracted light only in a fixed direction, the effect of two-beam interference is large and the focus margin is wide.

  However, if the pitch is twice the pitch of the fine L & S pattern, the diffraction angle of the light after passing through the mask is halved, and higher-order diffracted light that is extra light that does not contribute much to the resolution is the lens. This is not preferable because the focus margin becomes extremely narrow. For this reason, in FIG. 1, an L & S pattern in which a plurality of line patterns having a width L are arranged at a predetermined pitch P1 is provided, and a plurality of patterns having a width wider than L are arranged at other pitches in the vicinity of the L & S pattern. When P2 is arranged, a wide pattern pitch P2 is selected so that n is not 2 when P2 = nP1 (ie, n = 3 in FIG. 1). I understand.

(Second Embodiment)
Similarly, a wide manufacturing process margin can be obtained even if the pattern shown in FIG. One end of a line pattern (first line pattern) 13 having a width of 50 nm, which is sandwiched between the first wide patterns 11 having a width of 150 nm and is opposed to each other at an interval of 50 nm, is extended and the end of the line pattern is widened. 2 wide patterns 15 are connected. The first line pattern 13 is a pattern obtained by extending the line pattern constituting the L & S pattern, and the other end of the line pattern is connected to the fine L & S pattern. The simulation result of this pattern is shown in FIG. It can be seen that the value of the minimum width of the portion that is sandwiched between the wide patterns and that are adjacent to each other is remarkably improved.

  The main cause of the decrease in the light intensity contrast in the area near the fine line pattern 13 ′ sandwiched between the first wide patterns 11 ′ is the bright part of the mask pattern adjacent to this area, that is, the pattern spacing here. It was found that the light intensity of the fine pattern dark part, that is, the pattern part, was increased by the light transmitted through the part. In particular, in the case of the embodiment, the light transmitted through the pattern bright portion adjacent to the direction in which the line pattern 13 ′ extends causes the light intensity of the line pattern dark portion to increase. It can be seen that a pattern 15 ′, that is, a dark portion is provided at the position of FIG.

  That is, it is effective to reduce transmitted light by extending one end of a fine line pattern adjacent to and facing the wide pattern and widening the pattern width of the extended end. At this time, the pattern dark portion for reducing the transmitted light is effective even if it is a pattern necessary for circuit operation. Usually, however, such a pattern usually has not so much design freedom. A dummy pattern dark part as indicated by a broken line may be provided instead of the pattern 15 ′. This dummy pattern may be connected to a pattern necessary for circuit operation or may be separated. FIG. 2 shows an example in which the dummy pattern dark part is arranged separately from other patterns. However, when separated, a bright pattern portion that can be resolved at the minimum is required, so that the transmitted light reduction effect is slightly reduced. In the embodiment of FIG. 2, wide patterns for reducing transmitted light may be connected to each other if possible in circuit operation, such as wiring driven by the same signal, power supply line or ground line. .

  FIG. 4 shows a simulation result when the wide patterns for reducing transmitted light are connected to each other.

  FIG. 5 shows another embodiment in which a pattern dark portion for reducing transmitted light is arranged in the extending direction of a fine line pattern sandwiched between wide patterns.

  From another point of view, the pattern 19 is set so that the pattern bright portion region 17 connected to the pattern bright portion separating the wide pattern 11 and the fine line pattern 13 adjacent to the wide pattern 11 is reduced. For example, it is possible to reduce the transmitted light intensity that reduces the contrast in the vicinity of the fine line pattern 13 that is adjacent to the wide pattern.

  FIG. 6 shows an example of pattern arrangement based on such a concept. On both sides of the fine line pattern 13 adjacent to and opposed to the wide pattern 11, fine L & S patterns (bright part limiting fine patterns) 21 are respectively arranged. In this configuration, the bright pattern portion that separates the wide pattern 11 and the fine line pattern 13 that is adjacent to the wide pattern 11 is limited by the bright portion limiting fine pattern 21. As a result, the bright pattern region between the wide pattern 11 and the fine line pattern 13 extends in the vertical direction at the minimum pattern interval, and the minimum necessary pattern bright part is realized in the vicinity of the line pattern 13.

  The present invention can be applied not only to DRAM but also to pattern formation of other semiconductor devices.

It is a figure for demonstrating the pattern arrangement | sequence which concerns on the 1st Embodiment of this invention. It is a figure for demonstrating the pattern arrangement | sequence which concerns on the 2nd Embodiment of this invention. It is a figure which shows the simulation result in the case of using the pattern arrangement | sequence shown by FIG. It is a figure which shows the simulation result in the case of using the modification of the pattern arrangement | sequence shown by FIG. It is a figure which shows the pattern arrangement | sequence which concerns on another Example of this invention. It is a figure which shows the simulation result at the time of using the pattern arrangement | sequence which concerns on another Example of this invention. It is a figure which shows an example of the pattern arrangement | sequence generally used. It is a figure which shows the simulation result at the time of using the pattern arrangement | sequence shown by FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 1st wide pattern 13 1st line pattern 15 2nd wide pattern 17 Pattern bright part area | region 19 Pattern 21 Bright part restriction | limiting fine pattern

Claims (9)

  A semiconductor device having an L & S (line and space) pattern in which a plurality of line patterns having a width L are arranged at a predetermined pitch, and having a width L adjacent to and opposite to a first wide pattern having a width wider than the width L A first line pattern, and at least one end of the first line pattern is disposed adjacent to the first wide pattern in a direction in which the first line pattern extends; A semiconductor device, wherein the semiconductor device is connected to a second wide pattern having a wide width.   2. The second wide pattern according to claim 1, wherein the second wide pattern is disposed at a predetermined interval from the first wide pattern, and the predetermined interval is the first line formed by the first wide pattern. A semiconductor device characterized in that the interval is capable of reducing a decrease in light intensity contrast with respect to a pattern.   A semiconductor device having an L & S pattern in which a plurality of line patterns having a width L are arranged at a predetermined pitch, and a first line pattern having a width L that is in close proximity to the first wide pattern having a width wider than the width L And a pattern arranged so as to narrow a pattern bright part region to which a first wide pattern and a pattern bright part that separates the first line pattern are connected.   A semiconductor device having an L & S pattern in which a plurality of line patterns having a width L are arranged at a predetermined pitch P1, and a plurality of patterns having a width wider than L are arranged at another pitch P2 in the vicinity of the L & S pattern. In the semiconductor device, n is not 2 when P2 = nP1.   5. The semiconductor device according to claim 4, wherein n is 3.   6. The semiconductor device according to claim 4, wherein the line pattern arranged at the pitch P1 is shorter than the pattern having the wide width.   A pattern forming method, wherein a pattern position where a decrease in light intensity contrast is predicted is specified, and a process for reducing the decrease in light intensity contrast is performed on the pattern position.   8. The pattern position at which the decrease in light intensity contrast is predicted is a line pattern narrower than the wide pattern sandwiched between wide patterns, and the narrow line pattern is sandwiched between the wide patterns. The pattern forming method is characterized in that the pattern is formed so as not to be disposed in the portion.   8. The pattern position at which the decrease in light intensity contrast is predicted is a line pattern narrower than the wide pattern sandwiched between wide patterns, and the narrow line pattern is sandwiched between the wide patterns. A pattern forming method, characterized in that the pattern is formed so as to pass through the portion and connect to a pattern wider than the narrow line pattern.

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