JP2010146102A - Arithmetic processor and storage area allocation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide memory configuration technology contributing to reduction in circuit scale. <P>SOLUTION: The processor 10 includes a plurality of arithmetic units 12a-12d performing arithmetic processing. First selection circuits 110a-110c each configure an address space to each arithmetic unit 12a-12d by use of at least one RAM 100a-100f. Each of the RAMs 100a-100f is not connected to all the arithmetic units 12a-12d, but connected only to a part thereof. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a technique for configuring a memory for arithmetic processing, and more particularly to a technique for configuring a memory in an arithmetic processing device capable of changing functions.

  In recent years, development of processing devices (processors) including an arithmetic unit having one or more basic arithmetic functions called ALU (Arithmetic Logic Unit) has been promoted (see, for example, Patent Document 1). This arithmetic unit is configured to include an ALU column including a plurality of ALUs and a connection portion provided between the ALU columns. In the processing device, by setting command data to the ALU array, the arithmetic function of the ALU circuit and the connection part connecting the preceding and succeeding ALU columns are controlled, and the expected arithmetic processing is realized as a whole. The The command data is generally created based on the data flow graph (DFG: Data Flow Graph) created from a source program written in a high-level program language such as C language.

In a processing apparatus having a plurality of arithmetic units, it is desirable that the memory configuration can be made variable because the amount of memory required for each arithmetic unit differs depending on the arithmetic processing desired to be realized. For this reason, some semiconductor devices including a memory reconfigurable circuit are proposed (see, for example, Patent Document 2).
JP 2006-40254 A Japanese Patent Laid-Open No. 2006-18452

  However, in the semiconductor device disclosed in Patent Document 2, all the arithmetic units use all the RAMs to form a memory having a necessary capacity. For this reason, more switches and wirings are required for memory reconfiguration, and the circuit scale of the entire semiconductor device is increasing.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a memory configuration technique that contributes to a reduction in circuit scale.

  In order to solve the above problems, an arithmetic processing device according to an aspect of the present invention is an arithmetic processing device capable of changing a function, and includes a plurality of arithmetic units that perform arithmetic processing, a plurality of storage areas, and each arithmetic operation. The unit includes a storage area configuration circuit that forms an address space using at least one storage area. At least one storage area is connected to only some of the plurality of arithmetic units.

  Another embodiment of the present invention is also an arithmetic processing device. This apparatus is an arithmetic processing unit capable of changing functions, and includes at least one arithmetic unit that performs a plurality of independent arithmetic processes, a plurality of storage areas, and at least one storage area for each arithmetic process. And a storage area configuration circuit that configures an address space. At least one storage area is connected to the arithmetic unit so as to be used only for a part of the plurality of arithmetic processes.

  Yet another aspect of the present invention is a storage area allocation method. In this method, a storage area for determining a storage area to be assigned to each arithmetic process is provided for an arithmetic processing apparatus having a storage area configuration circuit capable of executing a plurality of arithmetic processes and having a storage area for the arithmetic process. According to the allocation method, a storage area that can be used by each arithmetic processing is allocated according to the amount of data that each arithmetic processing must hold.

  It should be noted that any combination of the above components and the expression of the present invention expressed as a method, apparatus, system, and computer program are also effective as an aspect of the present invention.

  According to the present invention, an efficient memory configuration technique can be provided.

  FIG. 1 is a basic configuration diagram of a processing apparatus 10 according to an embodiment. The processing device 10 includes an integrated circuit device 26, a compilation unit 30, a data flow graph processing unit 31, a setting data generation unit 32, and a storage unit 34. The processing device 10 is configured as an arithmetic processing device capable of changing functions.

  The integrated circuit device 26 is configured as one chip, and includes an arithmetic unit 12, a setting unit 14, a control unit 18, an internal state holding circuit 20, a first feedback path 24, a main memory 27, and a second feedback path 29. The arithmetic unit 12 is a reconfigurable circuit that includes a plurality of arithmetic units and that can change the function by changing the setting. The arithmetic unit 12 is configured as a logic circuit such as a combinational circuit or a sequential circuit. The first feedback path 24 and the second feedback path 29 function as a feedback path, and connect the output of the arithmetic unit 12 to the input of the arithmetic unit 12.

  The arithmetic unit 12 includes a multi-stage array of logic circuits each capable of selectively executing a plurality of arithmetic functions, and a connection unit capable of setting a connection relationship between the output of the preceding logic circuit and the input of the succeeding logic circuit. . Structurally, a connection part for setting connection lines between logic circuit strings is provided between the plurality of logic circuit strings. The arithmetic unit 12 can change the function by arbitrarily setting the function of each logic circuit arranged in a plurality of stages and the connection between the logic circuits.

  The arithmetic unit 12 has a pipeline configuration and can execute a plurality of threads simultaneously. A thread is a processing unit to be executed by the arithmetic unit 12, and the processing of each thread is completed by itself. The plurality of threads may be executed independently of each other, and there may be data passing between the threads. The processing apparatus 10 can simultaneously implement a plurality of types of circuit configurations on the arithmetic unit 12.

  The setting unit 14 includes a first circuit setting unit 14a, a second circuit setting unit 14b, a third circuit setting unit 14c, and a fourth circuit setting unit 14d, and is used to configure an expected circuit in the arithmetic unit 12. Setting data 40 is supplied. Each of the circuit setting units 14a to 14d may be configured as a command memory that outputs data to be held based on the count value of the program counter. In this case, the control unit 18 functions as a sequencer to control the output of the program counter, and the setting data 40 becomes command data output from the command memory.

  Here, it is assumed that the arithmetic unit 12 is an ALU array composed of four stages of ALU columns. Specifically, the first circuit setting unit 14a, the second circuit setting unit 14b, the third circuit setting unit 14c, and the fourth circuit setting unit 14d receive setting data 40 for executing different threads, respectively. In the pipeline, the data is supplied in a predetermined order to a reconfigurable unit composed of a connection portion and an ALU row in each stage. As a result, a part of a different type of circuit is configured in each stage of the ALU array, and a multithread processing function is realized.

  The internal state holding circuit 20 is configured as a sequential circuit such as a data flip-flop (DFF), for example, and receives the output of the arithmetic unit 12. The internal state holding circuit 20 is connected to the first feedback path 24 and feeds back the output of the arithmetic unit 12 directly to the input of the arithmetic unit 12. Note that the first feedback path 24 may be configured to input only the lowermost output of the arithmetic unit 12 to the uppermost stage.

  The main memory 27 is configured by a RAM for storing output data output from the arithmetic unit 12. The main memory 27 has a function of temporarily holding output data of the arithmetic unit 12 and returning it to the arithmetic unit 12. The main memory 27 writes / reads data based on a chip enable (CE) signal and an address signal from the control unit 18. The main memory 27 is connected to the second feedback path 29 and feeds back data to the input of the arithmetic unit 12 at a predetermined timing based on a read instruction from the control unit 18. When the setting unit 14 is configured as a command memory, the data in the main memory 27 may be written / read using command data supplied from the command memory.

  In the processing apparatus 10, there are two paths for feeding back the output of the arithmetic unit 12 to the input of the arithmetic unit 12, a first feedback path 24 and a second feedback path 29. Since the first feedback path 24 does not go through the main memory 27, the output data of the arithmetic unit 12 can be fed back at high speed. On the other hand, the second feedback path 29 can supply a data signal to the arithmetic unit 12 at an expected timing according to an instruction from the control unit 18. As described above, the first feedback path 24 or the second feedback path 29 is appropriately used depending on the circuit to be reconfigured on the arithmetic unit 12.

  The arithmetic unit 12 includes a logic circuit whose function can be changed. The plurality of logic circuits may have a structure arranged in a matrix. The function of each logic circuit and the connection relationship between the logic circuits are set based on setting data 40 supplied by the setting unit 14. In the logic circuit, the combination connection for connecting the basic arithmetic elements to each other is also set based on the setting data 40. The setting data 40 is generated by the following procedure.

  A program 36 to be realized by the integrated circuit device 26 is held in the storage unit 34. The program 36 shows an operation description describing the operation of processing in the circuit, and describes a signal processing circuit or a signal processing algorithm in a high-level language such as C language. The compiling unit 30 compiles the program 36 stored in the storage unit 34, converts it into a data flow graph (DFG) 38, and stores it in the storage unit 34. The data flow graph 38 expresses the dependency of execution order between operations in a circuit, and shows the flow of operations of input variables and constants in a graph structure. In general, the data flow graph 38 is created so that the calculation proceeds from top to bottom.

  The data flow graph processing unit 31 searches the data flow graph 38 generated by the compiling unit 30 for a group of data flows having a predetermined rule. A group of data flows is a set of nodes having a predetermined connection relationship between operation nodes, and is registered in the storage unit 34 in advance. The data flow graph processing unit 31 searches for a group of predetermined data flows and replaces them with a number of nodes smaller than the number of nodes constituting the group.

  The node replaced from the group of data flows needs to be a node that can be processed by the logic circuit of the arithmetic unit 12. Correspondingly, the logic circuit is configured to have a combination connection for combining a plurality of basic arithmetic elements of its own in a predetermined order in order to process the replaced node. As a result, the logic circuit can have a new arithmetic function executed by a plurality of basic arithmetic elements by having the combination connection without increasing the number of basic arithmetic elements. In other words, a group of data flows having a predetermined rule is registered in advance according to possible combinations of a plurality of basic arithmetic elements in the logic circuit, and the data flow graph processing unit 31 can execute data in one logic circuit. A group of flows can be searched and replaced with one node.

  The setting data generation unit 32 generates setting data 40 from the data flow graph 38 processed by the data flow graph processing unit 31. The setting data 40 is data for mapping the data flow graph 38 to the arithmetic unit 12 and defines the function of the logic circuit in the arithmetic unit 12 and the connection relationship between the logic circuits.

  Note that the setting data generating unit 32 is based on the relationship between the memory (RAM) generated by the compiling unit 30 and the arithmetic processing unit such as the arithmetic unit 12 or the thread, and the connection relationship between the memory and the arithmetic unit 12 and the memory. Setting data 40 that defines control related to access is also generated. This setting data 40 is used for reconfiguration of the main memory 27.

  FIG. 2 shows the configuration of the arithmetic unit 12. The arithmetic unit 12 is provided with a plurality of logic circuit arrays each including a logic circuit 50 that can selectively execute a plurality of arithmetic functions. Specifically, the arithmetic unit 12 includes a multi-stage arrangement of logic circuit arrays and a connection unit 52 provided at each stage. The connection unit 52 can set an arbitrary connection relationship between the output of the preceding logic circuit and the input of the subsequent logic circuit, or a connection relationship selected from a predetermined combination of connection relationships. The connection unit 52 can hold the output signal of the preceding logic circuit. In the arithmetic unit 12, the operation proceeds from the upper stage to the lower stage due to the multi-stage arrangement structure of the logic circuits.

  The arithmetic unit 12 has an ALU (Arithmetic Logic Unit) as the logic circuit 50. The ALU is an arithmetic logic circuit capable of selectively executing a plurality of types of multi-bit operations, and can selectively execute a plurality of types of multi-bit operations such as logical sum, logical product, and bit shift by setting. Each ALU has a selector for setting a plurality of arithmetic functions. In the illustrated example, the ALU is configured to have two input terminals and one output terminal. The ALU may have three or more input terminals, and may have two or more output terminals.

  As shown in the figure, the arithmetic unit 12 is configured as an ALU array of X stages and Y columns in which X ALUs in the vertical direction and Y ALUs in the horizontal direction are arranged. FIG. 2 shows an ALU array having four stages of ALU columns 53. The connection unit 52a, the ALU column 53a, the connection unit 52b, the ALU column 53b, the connection unit 52c, the ALU column 53c, the connection unit 52d, the ALU column 53d, and the connection The parts 52e are connected in this order. The connection unit 52 and the subsequent ALU column 53 constitute a reconfigurable unit. In the reconfigurable unit, the connection unit 52 supplies variables and constants input from the outside to the intended ALU in the subsequent ALU column 53. It has a function to do. The connection unit 52 can also directly output the calculation result of the preceding ALU to the outside. In the ALU array, the physical arrangement of the plurality of ALUs does not need to be in an array, and the connection relationship between the ALUs may be configured in an array.

  Variables and constants are input to the first-stage ALU column 53a composed of ALU11, ALU12,..., ALU1Y via the connection unit 52a, and a predetermined calculation is performed. The output of the calculation result is input to the second-stage ALU column 53b composed of the ALU 21, ALU 22,..., ALU 2Y according to the connection set in the connection unit 52b. In the connection unit 52b, the connection is configured so that an arbitrary connection relationship between the output of the ALU column 53a and the input of the ALU column 53b or a connection relationship selected from a predetermined combination of connection relationships can be realized. The desired connection is enabled by setting. Hereinafter, the configuration is the same up to the connection portion 52e which is the final stage. Each connection unit 52 may function as a DFF circuit, and the final-stage connection unit 52e may function as the internal state holding circuit 20 illustrated in FIG.

  Circuit configuration is performed in one clock. Specifically, the setting unit 14 maps the setting data to the arithmetic unit 12 every clock. In FIG. 1, the setting unit 14 includes four first circuit setting units 14 a to 14 d. However, as illustrated in FIG. 2, the arithmetic unit 12 includes five connection units 52 and four circuit setting units 14. When configured with the ALU column 53, the setting unit 14 may include nine circuit setting units in order to supply the setting data 40 to each connection unit 52 and each ALU column 53.

  The output of each ALU column 53 is held in the subsequent connection unit 52. During the execution of a plurality of threads, the DFF circuit of the connection unit 52 holds the data output from the preceding logic circuit and executes the same thread as the thread executed by the preceding logic circuit at the next clock. The held data is supplied to the logic circuit. As described above, the processing of one thread is executed in the ALU row 53 at the next stage for each clock. When processing is performed in the final stage, it is lowered one stage at a time from the uppermost ALU column. Thereby, multi-thread processing can be executed, and an efficient circuit configuration can be realized.

  FIG. 3 is an explanatory diagram for explaining multithread processing. At the T-th clock, the ALU column 53a processes the thread 1, the ALU column 53b processes the thread 4, the ALU column 53c processes the thread 3, and the ALU column 53d processes the thread 2. At the next (T + 1) th clock, the ALU column 53a processes the thread 2, the ALU column 53b processes the thread 1, the ALU column 53c processes the thread 4, and the ALU column 53d processes the thread 3. In this way, each thread is processed by the ALU row 53 in the subsequent stage for each clock, whereby multithread processing is executed.

  Returning to FIG. 1, when the circuit is configured, the control unit 18 selects and reads the setting data 40 from the storage unit 34 and supplies the setting data 40 to the setting unit 14. The setting unit 14 stores each setting data 40. When the setting unit 14 is configured as a command memory, the control unit 18 gives a program counter value to the setting unit 14, and the setting unit 14 calculates setting data stored according to the counter value as command data. Set to unit 12. The setting unit 14 may include a cache memory and other types of memory. In this example, a configuration in which the control unit 18 receives the setting data 40 from the storage unit 34 and supplies the setting data to the setting unit 14 will be described. However, the setting unit 14 is not provided via the control unit 18 in advance. The setting data may be stored in the.

  The setting unit 14 sets the setting data 40 in the arithmetic unit 12 and causes the arithmetic unit 12 to sequentially reconfigure the circuit. Thereby, the arithmetic unit 12 can perform an intended calculation. The arithmetic unit 12 uses an ALU having high-performance arithmetic capability as a basic cell, and the arithmetic unit 12 and the setting unit 14 are configured on one chip, so that the configuration can be realized at a high speed with one clock. Can do. The control unit 18 has a clock function, and the clock signal is supplied to the main memory 27. The control unit 18 may include a quaternary counter and supply a count signal to the setting unit 14.

  FIG. 1 shows a basic configuration of a processing apparatus 10 including one arithmetic unit 12. In the following, the processing apparatus 10 has a plurality of arithmetic units 12, and each arithmetic unit 12 constitutes a main memory 27. Therefore, the overall circuit scale is reduced by limiting the usable storage area (RAM). Specifically, by restricting the connection between the arithmetic unit 12 and the RAM on hardware, the RAM is efficiently allocated to the arithmetic unit 12 while the connection is restricted while reducing the circuit scale. In the following, an example in which the processing device 10 has the configuration function of the main memory 27 of the plurality of arithmetic units 12 will be described. However, the reconfiguration function of the main memory 27 is realized in units of threads in addition to the units of arithmetic units. Also good.

  FIG. 4 shows an example of the configuration of the processing apparatus 10 of the present embodiment. The processing apparatus 10 shown in FIG. 4 includes a plurality of arithmetic units 12a, 12b, 12c, and 12d, and has a memory configuration function capable of reconfiguring the memory for each arithmetic unit 12. As a memory group, a common memory circuit 60, an individual memory circuit 70, and an individual memory circuit 80 are provided. Each of the common memory circuit 60 and the individual memory circuits 70 and 80 includes a first selection circuit 110 and two RAMs 100. The Note that each memory circuit may include three or more RAMs 100, or may include only one RAM 100. The processing apparatus 10 may include a plurality of integrated circuit devices 26 (see FIG. 1) and a memory having a reconfiguration function that can be used by the plurality of integrated circuit devices 26. In this case, there may be an arithmetic unit 12 that does not use a memory having a reconfiguration function.

  Specifically, the common memory circuit 60 can be used by the arithmetic units 12a, 12b, and 12d, and includes a first selection circuit 110a and RAMs 100e and 100f. The individual memory circuit 70 can be used only by the arithmetic units 12a and 12b, and includes a first selection circuit 110b and RAMs 100a and 100b. The individual memory circuit 80 can be used only by the arithmetic units 12c and 12d, and includes a first selection circuit 110c and RAMs 100c and 100d. Here, it is assumed that the capacity of the RAM 100a is 2048 bytes, and the capacity of the other RAMs 100b to 100f is 1024 bytes, and the memory that holds the calculation results and intermediate data in each calculation unit 12 is used as the RAM 100 of the memory group. An example of configuration is shown below.

  A second selection circuit 120 that selects connection with the memory group is provided for the arithmetic unit 12. The second selection circuit 120a is provided for the arithmetic unit 12a, and connects either the common memory circuit 60 or the individual memory circuit 70 to the arithmetic unit 12a. The second selection circuit 120b is provided for the arithmetic unit 12b, and connects either the common memory circuit 60 or the individual memory circuit 70 to the arithmetic unit 12b. Although the second selection circuit 120c is provided for the arithmetic unit 12c, since the arithmetic unit 12c does not use the common memory circuit 60, the second selection circuit 120c may not exist in this example. The second selection circuit 120d is provided for the arithmetic unit 12d, and connects either the common memory circuit 60 or the individual memory circuit 80 to the arithmetic unit 12d.

  In the processing device 10, the first selection circuit 110 and the second selection circuit 120 have a storage area configuration that forms an address space using at least one storage area (RAM 100) when a storage area is required for the arithmetic unit. Form a circuit. In the processing apparatus 10, at least one RAM 100 is connected to only a part of the plurality of arithmetic units, thereby reducing the circuit scale. For example, the RAMs 100c and 100d are connected only to the arithmetic units 12c and 12d, and are not connected to the arithmetic units 12a and 12b.

  FIG. 5 shows a modification of the configuration of the processing apparatus 10 of the present embodiment. In the processing apparatus 10 illustrated in FIG. 5, one arithmetic unit 12 processes a plurality of threads. In the illustrated example, the arithmetic unit 12 a executes threads 1 and 2, and the arithmetic unit 12 b executes threads 3 and 4. The processing apparatus 10 shown in FIG. 5 has a memory configuration function that can reconfigure the memory for each thread. 4 and FIG. 5, the arrangement of the first selection circuits 110a to 110c and the second selection circuits 120a to 120d for constituting the memory is the same, and the following processing is shown in FIG. In relation to the device 10, the memory configuration functions will be described.

  FIG. 6 shows an example in which the main memory 27 is configured using the RAM 100 for each arithmetic unit 12. The configuration method of the main memory 27 will be described in detail with reference to FIGS. 16 (a) to 16 (c). In this example, the arithmetic unit 12a requires a memory with a capacity of 3072 bytes, the arithmetic unit 12b requires a memory with a capacity of 1024 bytes, the arithmetic unit 12c requires a memory with a capacity of 1024 bytes, and the arithmetic unit 12d requires a memory with a capacity of 2048 bytes. .

  In the memory configuration example shown in FIG. 6, for the arithmetic unit 12a, the RAM 100e (capacity: 1024 bytes) of the common memory circuit 60 and the RAM 100a (capacity: 2048 bytes) of the individual memory circuit 70, one main having a capacity of 3072 bytes. A memory 27a is configured. For the arithmetic unit 12b, the RAM 100b of the individual memory circuit 70 constitutes a main memory 27b having a capacity of 1024 bytes. For the arithmetic unit 12c, the RAM 100c of the individual memory circuit 80 provides a main memory 27c having a capacity of 1024 bytes. For the main memory 27d, the RAM 100d of the individual memory circuit 80 and the RAM 100f of the common memory circuit 60 constitute one main memory 27d having a capacity of 2048 bytes. In the figure, addr indicates an address in the main memory 27.

  FIG. 7 shows the configuration of the common memory circuit 60. The common memory circuit 60 includes a first selection circuit 110a and RAMs 100e and 100f. The first selection circuit 110a includes memory control circuits 130e and 130f and a read control circuit 150a. Since the memory control circuits 130e and 130f have the same configuration, the memory control circuit 130f is not shown. The read control circuit 150a is a circuit for supplying read data to the second selection circuit 120a provided in the arithmetic unit 12a. In the present embodiment, the common memory circuit 60 includes the arithmetic unit 12a in addition to the arithmetic unit 12a. Since it is connected to the arithmetic units 12b and 12d, a read control circuit (not shown) for supplying read data to the second selection circuits 120b and 120d is further provided. The memory control circuit 130 is provided for each RAM 100, and the read control circuit 150 is provided for each arithmetic unit 12. FIG. 7 shows a circuit configuration in which the RAM 100 is assigned to the arithmetic unit 12 as an example of assigning the RAM 100 to the arithmetic processing. However, as described above, the RAM 100 can also be assigned to the thread.

  Although FIG. 7 shows the configuration of the common memory circuit 60, the individual memory circuits 70 and 80 can also be configured in the same manner as the common memory circuit 60.

  The memory control circuit 130 is a circuit for determining whether the access is to the RAM 100 controlled by the memory control circuit 130 and controlling the RAM 100 accordingly. Hereinafter, the memory control circuit 130e of the RAM 100e will be described as an example.

  set_a and set_b are memory configuration information. Specifically, set_a is information indicating which of the arithmetic units 12 the RAM 100e constitutes, and set_b is information indicating where in the address space of the configured memory it corresponds. Note that set_a and set_b may have information that they are not used by any arithmetic unit 12. Multiplexers (MUX) 132, 134, and 136 store the RAM 100 e from write data (w_data), address signal (addr), and write determination signal (w_en) supplied from the arithmetic units 12 a, 12 b, and 12 d to be connected. This circuit selects one of the usable arithmetic units 12 and is controlled by set_a. For example, in the memory configuration example of FIG. 6, since the RAM 100e is configured as a part of the main memory 27a of the arithmetic unit 12a, set_a is a signal indicating the arithmetic unit 12a, and the MUXs 132, 134, and 136 are respectively Select w_data, addr, and w_en for the arithmetic unit 12a.

  The access determination circuit 138 determines whether addr is in the address range indicated by set_b using a specific bit of addr (hereinafter referred to as a determination bit signal). Here, when there are a plurality of types of RAMs 100 having capacities of 1024 bytes and 2048 bytes, if a smaller address value is assigned in the descending order of the number of RAMs having the smaller capacity or the same capacity, the higher order of the addr The access determination circuit 138 can efficiently determine the bit by looking at the bit. For example, in the memory configuration example shown in FIG. 6, since the arithmetic unit 12a uses the RAM 100a and the RAM 100e, the RAM 100e that meets the condition that the number of RAMs having a small capacity or the same capacity is large is assigned to address values 0 to 1023, The RAM 100a is assigned to address values 1024 to 3071. Then, the eleventh bit or more from the lower order of addr is used as a determination bit signal. If the determination bit signal is 0, it is determined that the access is to the RAM 100e. In this case, set_b is a signal indicating 0, and the access determination circuit 138 determines whether the determination bit signal is 0, and outputs the result as active if 0 and negative if not.

  The CE generation circuit 142 generates a control signal for the RAM 100e from the output of the access determination circuit 138 and the selected w_en. For example, if the output of the access determination circuit 138 and the selected w_en are both active, a signal for writing to the RAM 100e is output. If the output of the access determination circuit 138 is active and the w_en is not active, the RAM 100e is read. Output a signal.

  The read control circuit 150a selects read data to be passed to the arithmetic unit 12a from the data (r_data) read from the RAMs 100e and 100f of the memory group. Read control circuit 150 a is formed of read data conversion circuits 152, 154 and read data selection circuit 156. Hereinafter, the read data conversion circuit 152 provided for the RAM 100e will be described as an example. The read data conversion circuit 152 outputs r_data if it is r_data of the arithmetic unit 12a, otherwise converts it to 0 (all bits 0) and outputs it. Whether r_data is r_data of the arithmetic unit 12a is determined by using set_a and data (select) obtained by delaying the output of the access determination circuit 138 of the memory control circuit 130e by the delay circuit 140 by the time required for RAM reading. Judgment. That is, if set_a is a signal indicating the arithmetic unit 12a, and the select that is the output of the access determination circuit 138 is active, it is determined that r_data of the arithmetic unit 12a. The read data selection circuit 156 selects r_data of the arithmetic unit 12a among the outputs from the read data conversion circuits 152 and 154 of the RAMs 100e and 100f. This selection is realized by taking the logical sum (OR) of the outputs of the read data conversion circuits 152 and 154. Therefore, the read data selection circuit 156 outputs the data value when the data read from the RAM 100e or RAM 100f of the memory group is r_data of the arithmetic unit 12a, and outputs 0 when it is not r_data of the arithmetic unit 12a. The

  Note that the read data conversion circuits 152 and 154 convert all the bits to 0 when each r_data is not r_data of the arithmetic unit 12a. However, the read data conversion circuits 152 and 154 may convert other signal values such as all bits to be output. Good. At this time, the read data selection circuit 156 outputs 0 when the outputs from both of the read data conversion circuits 152 and 154 are all 1s, otherwise, the logic of the output of the read data conversion circuits 152 and 154 Take product (AND) and output.

  The above is the description of the memory control circuit 130e of the RAM 100e, but the memory control circuits 130 of the other RAMs 100 have the same configuration.

  FIG. 8 shows a circuit configuration of the second selection circuit 120. The second selection circuit 120 selects one of r_data from a plurality of memory groups. The circuit configuration is the same as that of the read data selection circuit 156 of the read control circuit 150a, and includes a read data selection circuit 158 that takes a logical sum (OR) of data from each memory group. The second selection circuit 120a has a read data selection circuit 158. In the memory configuration example shown in FIG. 6, one read data of the RAM 100a and RAM 100e constituting the main memory 27a of the arithmetic unit 12a is supplied to the arithmetic unit 12a. To do. Similarly, the second selection circuit 120d supplies one read data of the RAM 100d and RAM 100f constituting the main memory 27d of the arithmetic unit 12d to the arithmetic unit 12d. The second selection circuit 120b supplies read data from the RAM 100b to the arithmetic unit 12b, and the second selection circuit 120c supplies read data from the RAM 100c to the arithmetic unit 12c.

  As described above, by limiting the memory group that can be used by the arithmetic unit 12, it is possible to reduce selection circuits and connection lines, thereby increasing the degree of freedom of placement and routing and reducing the circuit scale. This improves the operating speed and shortens the processing time.

  Further, the read control circuit 150a and the second selection circuit 120a are provided with the read data selection circuit 156 and the read data selection circuit 158, respectively, so that the number of wirings between the memory group and the arithmetic unit 12 can be reduced. Further, when the read data conversion circuits 152 and 154 do not have the desired data, the read data is converted into a zero value so that only the desired data can be output by performing a logical sum. The control signal at 156 is unnecessary. As a result, the degree of freedom of placement and routing is increased, the circuit scale is reduced, the operation speed is improved, and the processing time is shortened.

  The memory configuration information set_a and set_b of the common memory circuit 60 may be supplied from the setting unit 14 or the control unit 18 and may be set when the arithmetic unit 12 that is a reconfigurable circuit is configured. In the former case, since the memory configuration can be dynamically changed during the operation of the processor, the processing variations of the arithmetic unit 12 can be increased. In the latter case, the degree of freedom of placement and routing is increased, for example, the memory configuration information can be placed independently for each RAM. As a result, the circuit scale is reduced, and the processing time is shortened by further improving the operation speed.

  Further, by limiting the assignment of address values by the RAM 100, the bit width of the address addr supplied to the memory configuration information and the memory group can be reduced, and the circuit scale is reduced. Thereby, the operation speed can be improved and the processing time can be shortened. Specifically, as a method for limiting the assignment of address values, specifically, when an address space is constituted by the RAMs 100 having different storage capacities, smaller address values are assigned to the address spaces in order from the RAM 100 having a smaller storage capacity. Alternatively, if there are RAMs 100 having the same storage capacity, smaller address values may be assigned in order from the largest number of RAMs 100 having the same storage capacity. Also, a small address value may be assigned to the RAM 100 that can be used for the plurality of arithmetic units 12.

  For example, in the example of the processing apparatus 10 shown in FIG. 4, the determination bit signals of the RAMs 100e and 100f of the common memory circuit 60 are only 0 or 1, the determination bit signal of the RAM 100a of the individual memory circuit 70 is 0 to 5, and the determination bits of the RAM 100b The signal can be limited to 0 to 3, and the determination bit signals of the RAMs 100c and 100d of the individual memory circuit 80 can be limited to 0 to 3. In this case, the set_b of the RAMs 100e and 100f of the common memory circuit 60 may be 1 bit, and the set_b of the RAMs 100b, 100c, and 100d may be 2 bits. If the address value assignment is not limited, the set_b requires 3 bits in all cases. Therefore, the limitation of the address value assignment has an advantage that the circuit scale can be reduced. In addition, the bit width of the address addr to be sent to the common memory circuit 60 is 13 bits when there is no restriction. However, if this restriction is used, the address addr to be sent to the common memory circuit 60 at the time of output of the arithmetic units 12a and 12b. If the 12th bit is converted into the logical sum (OR value) of the 12th and 13th bits, 12 bits are sufficient.

  FIG. 9 shows a further modification of the configuration of the processing apparatus 10 of the present embodiment. The processing apparatus 10 illustrated in FIG. 9 includes one arithmetic unit 12a, and the arithmetic unit 12a executes threads 1, 2, 3, and 4. The processing apparatus 10 illustrated in FIG. 9 has a memory configuration function that can reconfigure the memory for each thread. The second selection circuits 120 a to 120 d are provided for the threads 1 to 4, respectively, to enable data transmission / reception between the respective threads and the RAM 100.

  As described above, when the arithmetic unit 12 is configured by a reconfigurable circuit capable of executing a plurality of independent processes (threads), it is possible to set the use restriction of the memory group for each thread. Compared with FIG. 4, it can be seen that the arithmetic unit 12 and the thread are simply replaced. This is because the processing unit is the arithmetic unit 12 in FIG. 4 but only the difference in FIG. 9 is that the processing unit is a thread. Therefore, the memory configuration technique of this embodiment is as follows. It can be seen that it can be executed for each processing unit.

  Note that the processing device 10 may include a plurality of arithmetic units 12, an individual memory circuit may be provided for each arithmetic unit 12, and all the arithmetic units 12 may access the common memory circuit. According to this configuration, since the individual memory circuit can be a memory dedicated to the arithmetic unit, the circuit scale can be reduced, and the common memory circuit is shared by all the arithmetic units, so that the flexibility of the memory configuration is maintained. It is also possible.

  The hardware configuration of the processing device 10 has been described above. In the following, a technique for sharing a memory address space in order to further effectively use the memory in multithread processing will be described. The multi-thread processing may be executed in the plurality of arithmetic units 12, but for the sake of simplicity, the address space sharing technique will be described below according to the configuration of the processing device 10 shown in FIG.

  FIG. 10 shows an example of the configuration of the arithmetic unit 12. The arithmetic unit 12 constitutes an address space sharing circuit in which a plurality of threads share the memory address space. In this address space sharing circuit, the thread 3 can share the memory 1 address space while the memory is allocated to each of the threads 1 to 4. The address space sharing circuit is realized by the output selection circuit 170 and the input selection circuits 180 and 182.

  The MUXs 160 a, 160 b, 160 c, and 160 d are provided on the input side of the connection unit 52, and select and output read data from the RAM 100 assigned to threads that are processed by the lower ALU column 53 of the connection unit 52. Specifically, the MUX 160a selects the data of the thread processed by the first-stage ALU column 53a from the read data from the RAM 100 of each thread and supplies the selected data to the connection unit 52a. The MUXs 160e, 160f, 160g, and 160h are provided on the output side of the connection unit 52, and the lower connection unit 52 of the ALU column 53 that processes a specific thread among data that accesses (writes or reads) the RAM 100. Select and output data from. Specifically, the MUX 160 e selects the processed thread 4 data from the thread data processed in each ALU column 53 and outputs the selected data to the RAM 100 allocated to the thread 4. These MUXs 160 may be controlled by a control signal output from a quaternary counter (not shown).

  FIG. 11 shows the operation of the output selection circuit 170 when the thread 1 and the thread 3 share the address space. When the memory address space is not shared by a plurality of threads, the desired memory can be accessed from the ALU column 53 of each stage by selecting the MUXs 160e, 160f, 160g, and 160h. On the other hand, as shown in FIG. 11, when the memory address space is shared between the thread 1 and the thread 3, the memory can be accessed only from the first-stage ALU column 53a and the second-stage ALU column 53b. Input of read data is limited to the third-stage ALU column 53c and the fourth-stage ALU column 53d. Here, limiting the level means that the input of read data is limited to a specific level.

  The output selection circuit 170 always selects the memory access data of the thread 1 when the thread 3 does not use the memory for the thread 1. On the other hand, when the thread 3 uses the memory for the thread 1, the output selection circuit 170 determines that the thread 1 is processed when the thread 1 is processed by the first-stage ALU column 53a or the second-stage ALU column 53b. At other times, that is, when the thread 3 is processed by the first-stage ALU column 53a or the second-stage ALU column 53b, the memory access data of the thread 3 is selected. In other words, the output selection circuit 170 at the time of sharing operates so as to always select the input indicated by the solid line among the two inputs to the output selection circuit 170 in FIG. In this example, the output data of the thread 1 processed in the ALU column 53a at the Tth clock, the output data of the thread 1 processed in the ALU column 53b at the (T + 1) clock, and the ALU at the (T + 2) clock. The output data of the thread 3 processed in the column 53a and the output data of the thread 3 processed in the ALU column 53b are selected at the (T + 3) th clock.

  The input selection circuits 180 and 182 are circuits that convert a control signal from a quaternary counter supplied to the MUXs 160c and 160d. When the memory address space is not shared, the MUX 160c always selects the thread data to be processed by the ALU column 53c from the read data from the memory of each thread. This is the same as when the input selection circuit 180 is not provided. When the memory address space is shared, when the third-stage ALU column 53c processes the thread 3, the data from the thread 1 memory is selected. Otherwise, the third-stage ALU column 53c is selected. Selects thread memory data to process.

  Similarly, when the memory address space is not shared, the MUX 160d always selects the thread data to be processed by the ALU column 53d from the read data from the memory of each thread. This is the same as when the input selection circuit 182 is not provided. When the memory address space is shared, the data from the thread 1 memory is selected when the fourth-stage ALU column 53d processes the thread 3, and otherwise the fourth-stage ALU column 53d. Selects thread memory data to process. That is, the data from the thread 1 memory is input to the third-stage ALU column 53c or the fourth-stage ALU column 53d in which the thread 1 or thread 3 is operating as shown in FIG.

  As described above, when the memory address space is shared by a plurality of threads, a plurality of accessible reconfigurable circuit stages are limited, and the access timing is controlled so as not to access the shared address space at the same time. Threads are prevented from accessing memory at the same time.

  FIG. 12 shows a memory configuration example when the thread 1 and the thread 3 share the memory address space in the processing apparatus 10 shown in FIG. By using the memory of the thread 1, the thread 3 can use a capacity larger than the capacity of the memory that the thread 3 can use when the memory address space is not shared. For example, when the memory capacity required by the thread 3 is 2500 bytes, referring to FIG. 9, when the memory space is not shared, only 2048 bytes of the RAMs 100c and 100d can be used at the maximum. Can't configure memory that can. Therefore, it is necessary to increase the number or capacity of the RAM 100 of the individual memory circuit 80. However, if the memory address space can be shared with the thread 1 as in this embodiment, the thread 3 may use a 2500-byte memory. It becomes possible.

  At this time, if the capacity of the memory required for the processing of the thread 1 is 500 bytes, if one RAM having a capacity of 1024 bytes is used when the memory address space is not shared, the capacity of 524 bytes remains, but 2500 By sharing the memory address space of 3072 bytes with the thread 3 that requires bytes, the remainder of the capacity is only 72 bytes, and the memory can be used effectively. As described above, since the shared function enables efficient use of the memory, the number of RAMs 100 and the capacity of the RAM 100 can be reduced, and the circuit scale can be reduced. Furthermore, since the thread 3 shares the memory with the thread 1, the thread 4 can use all the RAMs 100c and 100d of the individual memory circuit 80, and variations of processing executed by the thread 4 can be increased.

  Further, by sharing the memory address space among a plurality of threads, data can be transferred via the memory, so that the processing efficiency can be improved and the processing time can be shortened. Here, an example of a configuration in which a memory address space is shared by restricting memory access between threads of one arithmetic unit 12a at the stage of the reconfigurable circuit is shown. The address space may be shared with each other, and the address space may be shared between the arithmetic units 12. Further, the address space may be shared between a thread of a certain arithmetic unit 12 and another arithmetic unit 12. Furthermore, the address space may be shared by three or more arithmetic units 12 or threads.

  FIG. 13 shows a configuration example of the two arithmetic units 12. In this example, the RAM 100 is allocated to the threads of the arithmetic units 12a and 12b. The arithmetic units 12a and 12b constitute an address space sharing circuit in which threads executed by the respective arithmetic units 12a and 12b share the address space of the memory. In this address space shared circuit, a memory is allocated to each of the threads 1 to 4 executed by the arithmetic unit 12a, and a memory is allocated to each of the threads 5 to 8 executed by the arithmetic unit 12b. Among them, the thread 7 shares the address space of the memory with the thread 1, and the thread 7 and the thread 1 are processed by different arithmetic units 12b and 12a, respectively. The address space sharing circuit is realized by the output selection circuit 170a and the input selection circuits 180a and 182a. The operations of the output selection circuit 170a and the input selection circuits 180a and 182a are the same as those described with reference to FIG.

  FIG. 14 shows another configuration example of the two arithmetic units 12. Here, the RAM 100 is allocated to each of the arithmetic units 12a and 12b. The arithmetic units 12a and 12b constitute an address space sharing circuit that shares the address space of the memory. The output selection circuit 170b operates so as to always select the output of the arithmetic unit 12a when the address space of the memory is not shared, and when it is shared, the output unit 170b operates according to a control signal from a quaternary counter (not shown). 12a or the output of the arithmetic unit 12b is selected. For example, the output selection circuit 170b selects the output of the arithmetic unit 12a for the first two count values of the quaternary counter, and selects the output of the arithmetic unit 12b for the latter two count values. May work. Further, the input selection circuit 180b always outputs the data from the arithmetic unit 12b memory from the MUX 160 when the address space of the memory is not shared, and when shared, from the memory for the arithmetic unit 12a or the arithmetic unit 12b Select data. In this example, when sharing is performed, for example, the memory access of the arithmetic unit 12a is restricted to the first stage and the second stage, the input is restricted to the third stage and the fourth stage, and the memory access of the arithmetic unit 12b is restricted to the third stage and the fourth stage. Stages and inputs are limited to the first and second stages.

  When the arithmetic unit 12 does not have a multi-stage configuration, for example, if the memory address space is shared by the two arithmetic units 12a and 12b, the access timing may be controlled so that the memory is accessed alternately. . As described above, the memory address space can be shared between threads, between arithmetic units, or between threads and arithmetic units, so that the circuit scale can be reduced and the processing time can be reduced. It is possible to realize reduction and improvement in processing performance of the processing apparatus 10.

  Hereinafter, a method for efficiently allocating memory to the arithmetic unit 12 or the thread in the processing device 10 in which connection with the memory is limited will be described. Hereinafter, the target to which the memory is allocated is referred to as “target processing”. Here, when the processing unit is a thread in the processing device 10, the thread is a target process, and in the processing device 10 that does not perform multi-thread processing, the arithmetic unit 12 executes one process. Unit 12 is the target process.

  FIG. 15 shows a configuration of the processing apparatus 10 in which the connection between the memory and the target process is restricted on hardware. The common memory circuit 210 includes RAMs 200e, 200f, and 200g, the individual memory circuit 220 includes RAMs 200a, 200b, and 200c, and the individual memory circuit 230 includes a RAM 200d. The target process 250 and the target process 260 can use the common memory circuit 210 and the individual memory circuit 220, and the target process 270 can use the common memory circuit 210 and the individual memory circuit 230. In FIG. 15, the numbers given to each RAM 200 indicate the memory capacity (no unit). For example, the RAM 200a has a memory capacity of 128, and the RAM 200c has a memory capacity of 32. The number given to each target process indicates the amount of data that needs to be stored in the memory. For example, the target process 250 needs to store 190 data amounts in the memory, and the target process 260 needs to store 60 data amounts in the memory. Hereinafter, a technique for allocating memory to each of the target processes 250, 260, and 270 will be described.

  FIGS. 16A, 16B, and 16C are flowcharts of the memory allocation process. In the following, an example in which memory is allocated to each target process when the memory and the target process are connected as shown in FIG. 15 will be described. In this memory allocation process, the amount of data handled in each target process is sequentially allocated to the RAM 200. In this flowchart, “unallocated data” means data not yet allocated to the RAM 200. For example, if the RAM 200a is already allocated to the target process 250, the unallocated data is 62 (= 190-128). The memory allocation process is executed by the compiling unit 30 shown in FIG. The compiling unit 30 acquires the amount of data that each target process must hold before performing the memory allocation process. Also, the available memory capacity is acquired in advance.

  First, it is determined whether there is a target process with unallocated data (S10). If memory is allocated to all target processes (N in S10), this flow ends. At the start of the memory allocation process, since no memory has been allocated to the target process (Y in S10), the process proceeds to S12.

  In S12, among the target processes having unallocated data, the target process having the smallest total usable memory capacity is set as the process group a. The total memory capacity that can be used means the total memory capacity that can be accessed by each target process. Referring to FIG. 15, the target process 270 is set in the processing group a because the target process having the smallest total available memory capacity is the target process 270 due to memory access restrictions. Subsequently, among the target processes included in the processing group a, the target process having the largest unallocated data amount is set as the process x (S14). In this case, since the target process included in the processing group a is only the target process 270, the target process 270 is specified as the process x. Subsequently, all the RAMs that can be used by the process x are set as candidate memories b (S16). Referring to FIG. 15, RAMs 200d, 200e, 200f, and 200g that can be used by the target process 270 are identified as candidate memories b. These candidate memories b constitute a candidate memory group.

  When the candidate memory b can be set in the target process 270 as described above (Y in S18), the candidate memories b are sorted in descending order of capacity, and the order is retained (S20). When the memory capacities are the same, sorting is performed in ascending order of the number of target processes that may be used. Regarding the RAMs 200d, 200e, 200f, and 200g, which are candidate memories b, they all have the same capacity of 32, but the RAM 200d may be used only by the target process 270, whereas the common memory circuit There is a possibility that 200e, 200f, and 200g included in 210 are used by three target processes 250, 260, and 270. Therefore, these are sorted in the order of the RAMs 200d, 200e, 200f, and 200g, and the order is maintained. By determining the order in which the RAM 200 is tried in accordance with S20, the possibility of memory allocation can be increased, and the total memory capacity after allocation can be kept small.

  First, i indicating the order of the stored RAM 200 is set to 1 (S22), and the i-th RAM 200 in the candidate memory group is set as a candidate memory c (S24). Here, the RAM 200d is set as the candidate memory c. Subsequently, it is determined whether the capacity of the candidate memory c is equal to or less than the unallocated data amount of the process x (S26). Here, the capacity of the candidate memory c (RAM 200d) is 32, the unallocated data amount of the process x (target process 270) is 30, and the capacity of the candidate memory c is larger than the unallocated data amount of the process x (N in S26). .

  Subsequently, in the processing group a, a target process whose usable memory is the same as that of the processing x is a processing group d (including the processing x), and the unallocated data amount of the processing group d is set to a minimum memory capacity larger than that. The sum of the values expressed in multiples of e is set as e (S28). Here, since the processing group a is only the target processing 270, the processing group d is the target processing 270, and the unallocated data amount is 30. At this time, the minimum capacity of the memory is 32, which is a multiple of 32 and larger than 30, and the minimum value is 32. Therefore, e = 32 is specified. Here, it is examined how many memories with the minimum capacity can be used to allocate the unallocated data amount, and the unallocated data amount is expressed in units of the minimum capacity of the memory. This is for checking whether all unallocated data can be allocated using a memory having a capacity smaller than that of the candidate memory c from S28 to S32 below. At that time, for example, when there are two processes with unallocated data amounts of 10 and 20, a memory with a capacity of 32 is originally allocated to each process. Since the total amount of allocated data is 30, there is a risk that it can be determined that one memory with a capacity of 32 can be allocated. Next, in S30, the sum of the capacities of memories having a capacity smaller than that of the candidate memory c in the candidate memory group is defined as f. Here, since there is no memory having a smaller capacity than the candidate memory c (RAM 200d) among the RAMs 200d to 200g, f = 0.

  Here, e and f are compared (S32), and in this case, e (= 32)> f (= 0) (Y in S32), so that the candidate memory c is assigned to the unallocated data of the process x (S34). ). As a result, the RAM 200d is allocated to the target process 270. At this time, all the data of the process x (target process 270) is allocated, and therefore there is no unallocated data in the process x (N in S36), and the process returns to S10.

  At this time, there are target processes 250 and 260 as target processes having unallocated data (Y in S10). In S12, the target process having the smallest total available memory capacity is selected as the process group a. Here, since the total available memory capacity of the target processes 250 and 260 is the same, both the target processes 250 and 260 are set as the processing group a. Subsequently, in S14, the target process 250 having a large amount of unallocated data is set as the process x, and in S16, the RAMs 200a, 200b, 200c, 200e, 200f, and 200g, which are memories usable by the target process 250, are stored in the candidate memory b. Set as These candidate memories b constitute a candidate memory group.

  Since the candidate memory b exists (Y in S18), the candidate memory b is sorted in descending order of capacity in S20, and the order is maintained. When the memory capacities are the same, sorting is performed in ascending order of the number of target processes that may be used. Regarding the RAMs 200a, 200b, 200c, 200e, 200f, and 200g, which are candidate memories b, the candidate memories b are sorted in the order of the RAMs 200a, 200b, 200c, 200e, 200f, and 200g, and the order is maintained.

  I indicating the order of the stored RAMs 200 is set to 1 (S22), and the i-th RAM 200 in the candidate memory group is set as a candidate memory c (S24). Here, the RAM 200a is set as the candidate memory c. Subsequently, it is determined whether the capacity of the candidate memory c is equal to or less than the unallocated data amount of the process x (S26). Here, the capacity of the candidate memory c (RAM 200a) is 128, the unallocated data amount of the process x (target process 250) is 190, and the capacity of the candidate memory c is smaller than the unallocated data amount of the process x (Y in S26). . Therefore, the candidate memory c is allocated to the unallocated data of the process x (S34), whereby the RAM 200a is allocated to the target process 250. At this time, since there is unallocated data in the process x (target process 250) (Y in S36), the process returns to S12. At this time, the unallocated data amount of the target process 250 is 62 (= 192-128).

  Subsequently, in S12, the target process 250 (unallocated data amount 62) and the target process 260 (unallocated data amount 60) are selected as the processing group a. In S14, the target process 250 having a large unallocated data amount in the process group a is set as the process x. In S16, the RAMs 200b, 200c, 200e, 200f, and 200g that can use the process x are set as the candidate memory b. Since there is a candidate memory (Y in S18), in S20, the candidate memory b is sorted and the order of the RAMs 200b, 200c, 200e, 200f, and 200g is maintained. Then, i = 1 (S22), and in S24, the RAM 200b is first set as the candidate memory c.

  Subsequently, it is determined whether the capacity of the candidate memory c is equal to or less than the unallocated data amount of the process x (S26). Here, the capacity of the candidate memory c (RAM 200b) is 128, and the unallocated data of the process x (target process 250). The amount is 62 (N in S26). In S28, among the processing groups a, the target processing whose usable memory is the same as the processing x is the processing group d (including the processing x), and the unallocated data amount of the processing group d is set to the minimum memory capacity larger than that. The sum of the values expressed in multiples of e is set as e (S28). Here, since the process group a is the target processes 250 and 260 and the target processes 250 and 260 have the same usable memory, the process group d is the target processes 250 and 260. At this time, the unallocated data amounts of the target processes 250 and 260 are 62 and 60, respectively. At this time, the minimum capacity of the memory is 32, which is a multiple of 32 and larger than 62 and 60, and the minimum values are 64 and 64, respectively. Therefore, e = 128 (= 64 + 64) is specified.

  Next, in S30, let f be the total memory capacity of the candidate memory group that is smaller than the candidate memory c (RAM 200b). Here, since the capacity of the RAMs 200c, 200e, 200f, and 200g is smaller than that of the candidate memory c (RAM 200b), f = 128 (= 32 + 32 + 32 + 32. At this time, e = f (N in S32), and i is incremented by 1. (S38), it is determined whether the capacities of the i-th memory and the (i-1) -th memory in the candidate memory group are the same (S40) At this time, the second memory (RAM 200c) and the first memory (RAM 200b) Since the capacity is different (N in S40), the process returns to S24, where the RAM 200c, which is the second memory, is set as the candidate memory c.

  In S26, since the capacity (32) of the candidate memory c is equal to or less than the unallocated data amount (62) of the process x (Y in S26), the candidate memory c is allocated to the unallocated data of the process x (S34). Thus, the RAM 200c is allocated to the target process 250. At this time, since there is unallocated data in the process x (target process 250) (Y in S36), the process returns to S12. At this time, the unallocated data amount of the target process 250 is 30 (= 62−32).

  Subsequently, in S12, the target process 250 (unallocated data amount 30) and the target process 260 (unallocated data amount 60) are selected as the processing group a. In S14, the target process 260 having a large unallocated data amount is set as the process x in the process group a. In S16, the RAMs 200b, 200e, 200f, and 200g that can use the process x are set as the candidate memory b. Since there is a candidate memory (Y in S18), in S20, the candidate memory b is sorted and the order of the RAMs 200b, 200e, 200f, and 200g is maintained. Then, i = 1 (S22), and in S24, the RAM 200b is first set as the candidate memory c.

  Subsequently, it is determined whether the capacity of the candidate memory c is equal to or less than the unallocated data amount of the process x (S26). Here, the capacity of the candidate memory c (RAM 200b) is 128, and the unallocated data of the process x (target process 260). The amount is 60 (N in S26). In S28, among the processing groups a, the target processing whose usable memory is the same as the processing x is the processing group d (including the processing x), and the unallocated data amount of the processing group d is set to the minimum memory capacity larger than that. The sum of the values expressed in multiples of e is set as e (S28). Here, since the process group a is the target processes 250 and 260 and the target processes 250 and 260 have the same usable memory, the process group d is the target processes 250 and 260. At this time, the unallocated data amounts of the target processes 250 and 260 are 30 and 60, respectively. At this time, the minimum capacity of the memory is 32, which is a multiple of 32 and larger than 30, 60, and the minimum values are 32, 64, respectively. Therefore, e = 96 (= 32 + 64) is specified.

  Next, in S30, let f be the total memory capacity of the candidate memory group that is smaller than the candidate memory c (RAM 200b). Here, since the capacity of the RAMs 200e, 200f, and 200g is smaller than that of the candidate memory c (RAM 200b), f = 96 (= 32 + 32 + 32. At this time, e = f (N of S32) and i is incremented by 1 (S38). It is determined whether the i-th memory and the (i-1) -th memory in the candidate memory group have the same capacity (S40), where the second memory (RAM 200e) and the first memory (RAM 200b) are Since the capacities are different (N in S40), the process returns to S24, where the RAM 200e as the second memory is set as the candidate memory c.

  In S26, since the capacity (32) of the candidate memory c is equal to or less than the unallocated data amount (60) of the process x (Y in S26), the candidate memory c is allocated to the unallocated data of the process x (S34). Thus, the RAM 200e is allocated to the target process 260. At this time, since unallocated data exists in the process x (target process 260) (Y in S36), the process returns to S12. At this time, the unallocated data amount of the target process 260 is 28 (= 60−32).

  Subsequently, in S12, the target process 250 (unallocated data amount 30) and the target process 260 (unallocated data amount 28) are selected as the processing group a. In S14, the target process 250 having a large unallocated data amount in the process group a is set as the process x. In S16, the RAMs 200b, 200f, and 200g that can use the process x are set as the candidate memory b. Since there is a candidate memory (Y in S18), in S20, the candidate memory b is sorted and the order of the RAMs 200b, 200f, and 200g is maintained. Then, i = 1 (S22), and in S24, the RAM 200b is first set as the candidate memory c.

  Subsequently, it is determined whether the capacity of the candidate memory c is equal to or less than the unallocated data amount of the process x (S26). Here, the capacity of the candidate memory c (RAM 200b) is 128, and the unallocated data of the process x (target process 250). The amount is 30 (N in S26). In S28, among the processing groups a, the target processing whose usable memory is the same as the processing x is the processing group d (including the processing x), and the unallocated data amount of the processing group d is set to the minimum memory capacity larger than that. The sum of the values expressed in multiples of e is set as e (S28). Here, since the process group a is the target processes 250 and 260 and the target processes 250 and 260 have the same usable memory, the process group d is the target processes 250 and 260. At this time, the unallocated data amounts of the target processes 250 and 260 are 30 and 28, respectively. At this time, the minimum memory capacity is 32, which is a multiple of 32 and larger than 30, 28, and the minimum values are 32, 32, respectively. Therefore, e = 64 (= 32 + 32) is specified.

  Next, in S30, let f be the total memory capacity of the candidate memory group that is smaller than the candidate memory c (RAM 200b). Here, since the RAMs 200f and 200g have a smaller capacity than the candidate memory c (RAM 200b), f = 64 (= 32 + 32). At this time, e = f (N in S32), i is incremented by 1 (S38), and it is determined whether the capacities of the i-th memory and the (i-1) -th memory in the candidate memory group are the same (S40). . At this time, since the second memory (RAM 200f) and the first memory (RAM 200b) have different capacities (N in S40), the process returns to S24. In S24, the second memory RAM 200f is set as the candidate memory c.

  In S26, since the capacity (32) of the candidate memory c is equal to or larger than the unallocated data amount (30) of the process x (Y in S26), the candidate memory c is allocated to the unallocated data of the process x (S34). Thus, the RAM 200f is allocated to the target process 250. At this time, there is no unallocated data in the process x (target process 260) (N in S36), and the process returns to S10.

  At this time, there is a target process 260 with unallocated data (Y in S10), and in S12, the target process 260 is selected as the process group a. Subsequently, in S14, the target process 260 is set as the process x, and in S16, the RAMs 200b and 200g, which are memories that can be used by the target process 260, are set as the candidate memory b.

  Since the candidate memory b exists (Y in S18), the candidate memory b is sorted in descending order of capacity in S20, and the order is maintained. At this time, the candidate memory b is sorted in the order of the RAMs 200b and 200g, and the order is retained.

  I indicating the order of the stored RAMs 200 is set to 1 (S22), and the i-th RAM 200 in the candidate memory group is set as a candidate memory c (S24). Here, the RAM 200b is set as the candidate memory c. Subsequently, it is determined whether the capacity of the candidate memory c is equal to or less than the unallocated data amount of the process x (S26). Here, the capacity of the candidate memory c (RAM 200b) is 128, the unallocated data amount of the process x (target process 260) is 28, and the capacity of the candidate memory c is larger than the unallocated data amount of the process x (N in S26). .

  Subsequently, in the processing group a, a target process whose usable memory is the same as that of the processing x is a processing group d (including the processing x), and the unallocated data amount of the processing group d is set to a minimum memory capacity larger than that. The sum of the values expressed in multiples of e is set as e (S28). Here, since the process group a is only the target process 260, the process group d is the target process 260, and the amount of unallocated data is 28. At this time, the minimum capacity of the memory is 32, which is a multiple of 32 and greater than 28, and the minimum value is 32. Therefore, e = 32 is specified. Next, in S30, the sum of the capacities of memories having a capacity smaller than that of the candidate memory c in the candidate memory group is defined as f. Here, of the RAMs 200b and 200g, the memory having a smaller capacity than the candidate memory c (RAM 200b) is the RAM 200g, and f = 32.

  At this time, e = f (N in S32), i is incremented by 1 (S38), and it is determined whether the capacities of the i-th memory and the (i-1) -th memory in the candidate memory group are the same (S40). . At this time, since the second memory (RAM 200g) and the first memory (RAM 200b) have different capacities (N in S40), the process returns to S24. In S24, the second memory RAM 200g is set as the candidate memory c.

  At this time, the capacity of the candidate memory c (RAM 200g) is 32, the unallocated data amount of the process x (target process 260) is 28, and the capacity of the candidate memory c is larger than the unallocated data amount of the process x (N in S26). .

  Subsequently, in the processing group a, a target process whose usable memory is the same as that of the processing x is a processing group d (including the processing x), and the unallocated data amount of the processing group d is set to a minimum memory capacity larger than that. The sum of the values expressed in multiples of e is set as e (S28). Here, since the process group a is only the target process 260, the process group d is the target process 260, and the amount of unallocated data is 28. At this time, the minimum capacity of the memory is 32, which is a multiple of 32 and greater than 28, and the minimum value is 32. Therefore, e = 32 is specified. Next, in S30, the sum of the capacities of memories having a capacity smaller than that of the candidate memory c in the candidate memory group is defined as f. Here, since there is no memory having a smaller capacity than the candidate memory c (RAM 200g) among the RAMs 200b and 200g, f = 0.

  Here, e and f are compared (S32), and in this case, e (= 32)> f (= 0) (Y in S32), so that the candidate memory c is assigned to the unallocated data of the process x (S34). ). As a result, the RAM 200g is allocated to the target process 260. At this time, all the data of the process x (target process 260) has been allocated, and therefore there is no unallocated data in the process x (N in S36), and the process returns to S10. In S10, since the memory allocation has been completed for all target processes (N in S10), this flow ends.

  If the candidate memory b does not exist in S18 (N in S18), the memory x can be used for the process x, and the memory x that can be reassigned to another memory among the already allocated memories. It is determined whether there is (S42). If such a memory x does not exist (N in S42), allocation cannot be performed, and this flow ends. On the other hand, when such a memory x exists (Y of S42), in the process of the allocation destination of the memory x, the allocation of the memory x is changed to another memory (S44), and the memory x is not allocated to the process x. Data is assigned (S46), and the process proceeds to S36. As described above, when the candidate memory b does not exist, the memory allocation process is executed again by changing the already allocated memory.

FIG. 17 shows the RAM allocated to the target process.
As described above, the compiling unit 30 can automatically allocate memory to each target process, and can improve the development efficiency of the user. Also, by executing this allocation process, the total capacity of the memory to be used can be minimized. Since the memory generally increases in power consumption as its capacity increases, the power consumption of the memory can be reduced by reducing the total capacity of the memory used. For example, in FIG. 15, when the usable RAM 200 is assigned in the alphabetical order given as a reference in order from the target process 250 without using this method, the target process 250 is assigned to the RAMs 200 a and 200 b and the target process 260. Are allocated to the RAMs 200c and 200e, and the target processing 270 is the RAMs 200d and 200f. Accordingly, the total capacity of the allocated RAM 200 in this case is 384, which is larger than the total capacity (320) of the allocated RAM 200 in FIG.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a basic configuration diagram of a processing apparatus according to an embodiment. It is a figure which shows the structure of an arithmetic unit. It is explanatory drawing for demonstrating multithread processing. It is a figure which shows an example of a structure of the processing apparatus of this embodiment. It is a figure which shows the modification of the structure of the processing apparatus of this embodiment. It is a figure which shows the example which comprised the main memory using RAM with respect to each arithmetic unit. It is a figure which shows the structure of a common memory circuit. It is a figure which shows the circuit structure of a 2nd selection circuit. It is a figure which shows the further modification of the structure of the processing apparatus of this embodiment. It is a figure which shows an example of a structure of an arithmetic unit. FIG. 10 is a diagram illustrating an operation of the output selection circuit when the thread 1 and the thread 3 share an address space. FIG. 10 is a diagram illustrating a memory configuration example when a thread 1 and a thread 3 share a memory address space in the processing device illustrated in FIG. 9. It is a figure which shows the structural example of two arithmetic units. It is a figure which shows another structural example of two arithmetic units. It is a figure which shows the structure of the processing apparatus with which the connection of a memory and an object process was restrict | limited on hardware. It is a figure which shows the flowchart of a memory allocation process. It is a figure which shows the flowchart of a memory allocation process. It is a figure which shows the flowchart of a memory allocation process. It is a figure which shows RAM allocated to the object process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Processing apparatus, 12 ... Arithmetic unit, 14 ... Setting part, 18 ... Control part, 20 ... Internal state holding circuit, 24 ... First feedback path, 26 ... Integrated circuit device, 27 ... main memory, 29 ... second feedback path, 30 ... compiling unit, 31 ... data flow graph processing unit, 32 ... setting data generating unit, 34 ... Storage unit 36 ... program 38 ... data flow graph 40 ... setting data 50 ... logic circuit 60 ... common memory circuit 70,80 ... individual memory circuit 100 ... RAM, 110 ... first selection circuit, 120 ... second selection circuit, 130 ... memory control circuit, 138 ... access determination circuit, 140 ... delay circuit, 142 ... CE generation circuit, 150 ..Read control circuit, 152,154 ... Read data conversion circuit, 156,158 ... Read data selection circuit, 170 ... Output selection circuit, 180,182 ... Input selection circuit, 200 ... RAM, 210 ... common memory circuit, 220, 230 ... individual memory circuit.

Claims (12)

An arithmetic processing device capable of changing functions,
A plurality of arithmetic units for performing arithmetic processing;
Multiple storage areas;
A storage area configuration circuit that forms an address space using at least one storage area for each arithmetic unit, and
At least one storage area is connected to only a part of a plurality of arithmetic units. An arithmetic processing device capable of changing functions,
At least one arithmetic unit for performing a plurality of independent arithmetic processes;
Multiple storage areas;
A storage area configuration circuit that forms an address space using at least one storage area for each arithmetic processing, and
At least one storage area is connected to an arithmetic unit so as to be used only for a part of a plurality of arithmetic processes. The storage area configuration circuit includes:
Based on some bits of the address signal supplied,
A control circuit for selecting a storage area to which data is written or read out of at least one storage area constituting the address space;
A read data selection circuit for selecting one of data read from at least one storage area,
The arithmetic processing apparatus according to claim 1, wherein the control circuit is provided for each storage area.   4. The address space is configured in such a manner that, in the case where the address space is constituted by storage areas having different storage capacities, the address space is assigned a smaller address value in order from the storage area having the smaller storage capacity. Arithmetic processing device.   The address space is configured by a plurality of storage areas, and when there are storage areas having the same storage capacity, a smaller address value is assigned in order from the largest number of storage areas having the same storage capacity. The arithmetic processing device according to any one of 1 to 3.   6. The arithmetic processing apparatus according to claim 1, wherein a single address space can be shared by a plurality of arithmetic processes.   7. The access timing is controlled so that the plurality of arithmetic processes do not access the shared address space at the same time when an address space constituted by the same storage area is shared by the plurality of arithmetic processes. The arithmetic processing unit described. The arithmetic unit has a multistage arrangement structure of logic circuits,
When the first arithmetic processing enables the use of the address space configured for the second arithmetic processing, the first arithmetic processing and the second arithmetic processing do not access the shared address space at the same time. The arithmetic processing apparatus according to claim 7, wherein output stages to the address space or input stages are limited.   9. The storage area according to claim 1, wherein a storage area where all the arithmetic processes can be used and a storage area where only a part of the plurality of arithmetic processes can be used exist. The arithmetic processing unit described in 1. A storage area allocating method for determining a storage area to be assigned to each arithmetic process for an arithmetic processing apparatus having a storage area configuration circuit capable of executing a plurality of arithmetic processes and configuring a storage area for the arithmetic process. And
Obtaining the amount of data that each arithmetic process must hold;
Obtaining the amount of storage space available;
Allocating a storage area that can be used by each arithmetic processing according to the amount of data that each arithmetic processing must hold;
A storage area allocating method comprising: A step of selecting a calculation process in which the total capacity of the usable storage area is the smallest among the calculation processes for which storage area allocation has not been completed;
The storage area allocation method according to claim 10, wherein the storage area is allocated from the selected arithmetic processing.   The arithmetic processing device according to any one of claims 1 to 9, wherein the storage area configuration circuit includes a storage area allocated to each arithmetic processing by the storage area allocation method according to any one of claims 10 to 11. An arithmetic processing apparatus comprising an address space using a relationship.

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